Exposure alignment method for wafer back photoetching process

Abstract

The invention provides an exposure alignment method for a wafer back photoetching process, which comprises the following steps of: dividing a doping layer in a doping process into a doping region and a non-doping region by changing the doping process before a semiconductor wafer back photoetching patterning process, the non-doped region is arranged to be an outer contour surrounding region covering the region where the alignment mark on the front side of the semiconductor wafer is located, so that infrared light emitted by exposure alignment can smoothly pass through the non-doped region to the alignment mark on the front side of the semiconductor wafer when the exposure process of the back side photoetching patterning process of the semiconductor wafer is subsequently carried out; it is ensured that the intensity of the reflected alignment Mark light signal meets the identification requirement, so that exposure alignment failure or overlay deviation increase between different layers is avoided, and the product yield is improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor photolithography technology, and in particular to an exposure alignment method for wafer backside photolithography technology. Background Art

[0002] In the exposure process of the photolithography process, the wafer needs to be aligned with the exposure equipment before the exposure process to measure the exposure position of the wafer, so as to ensure that the pattern formed after the wafer is exposed has the required overlay accuracy. At present, the common alignment equipment illuminates the wafer to be exposed through an infrared light source, and then receives the light wave reflected by the wafer to be exposed through a sensor, and judges whether the wafer to be exposed is aligned with the exposure equipment through the reflected light wave signal.

[0003] For some power devices, the wafer back process needs to be performed after the wafer front process is completed. When performing the photolithography process on the back of the wafer, the alignment mark (Mark) on the front of the wafer needs to be aligned with the exposure equipment. However, during the alignment process, the alignment Mark light signal reflected from the back of the wafer to be exposed after the infrared spectrum is irradiated is often insufficient or even the reflected alignment Mark light signal cannot be received, resulting in exposure alignment failure or increased overlay deviation between different layers, which reduces the product yield. Summary of the invention

[0004] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide an exposure alignment method for wafer back side lithography process, which is used to solve the problem in the prior art that in the exposure process of wafer back side lithography for patterning, the intensity of the alignment Mark light signal reflected after the infrared spectrum is irradiated from the back side of the wafer to be exposed is insufficient or even the reflected alignment Mark light signal cannot be received, resulting in exposure alignment failure or increased overlay deviation between different layers, thereby reducing product yield.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides an exposure alignment method for a wafer backside photolithography process, the exposure alignment method comprising the following steps:

[0006] Providing a semiconductor wafer, wherein an alignment mark is formed on the front side of the semiconductor wafer;

[0007] Forming a patterned photoresist layer on the back side of the semiconductor wafer, wherein the patterned photoresist layer at least covers the back side area of ​​the semiconductor wafer corresponding to the outer contour of the area where the alignment mark is located;

[0008] Based on the patterned photoresist layer, ion implantation and annealing are performed on the semiconductor wafer to form a back doping layer, wherein the back doping layer includes a doping area and a non-doping area, and the area where the non-doping area is located at least covers the outer contour area of ​​the area where the alignment mark is located;

[0009] Placing the semiconductor wafer with the back doped layer formed thereon with the back side facing upward in an exposure machine equipped with infrared light technology;

[0010] Based on the infrared light technology in the exposure machine, the reflected light signal of the alignment mark on the front side of the semiconductor wafer is identified to achieve exposure alignment.

[0011] Optionally, the semiconductor wafer is a silicon wafer.

[0012] Optionally, the semiconductor wafer is used to prepare an IGBT power device or a VDMOS power device.

[0013] Optionally, the doping region in the back doping layer is an N-type doping region or a P-type doping region or a doping region formed by stacking an N-type doping layer and a P-type doping layer.

[0014] Optionally, the alignment mark on the front side of the semiconductor wafer is formed in a cell area of ​​the semiconductor wafer or a cutting path of the semiconductor wafer.

[0015] Furthermore, the alignment mark on the front side of the semiconductor wafer is formed on a cutting path of the semiconductor wafer; and the patterned photoresist layer covers a back side area of ​​the semiconductor wafer corresponding to an area encompassed by an outer contour of the cutting path.

[0016] Optionally, the patterned photoresist layer is a positive photoresist.

[0017] Optionally, the light shielding layer material of the photomask used to form the patterned photoresist layer is Cr.

[0018] Optionally, the alignment mark is identified by receiving reflected light of infrared light from the exposure machine.

[0019] Optionally, the wavelength of the infrared wave emitted by the infrared technology of the exposure machine is 760nm to 1500nm.

[0020] As described above, the exposure alignment method of the wafer back side photolithography process of the present invention divides the doping layer in the doping process into a doping area and a non-doping area by changing the doping process before the semiconductor wafer back side photolithography patterning process, wherein the doping area is the doping layer required for the semiconductor device structure, and the non-doping area is set to cover the outer contour of the area where the alignment mark on the front side of the semiconductor wafer is located. Therefore, when the exposure process of the semiconductor wafer back side photolithography patterning process is subsequently performed, the infrared light emitted by the exposure alignment can smoothly pass through the non-doping area to the alignment mark on the front side of the semiconductor wafer, ensuring that the reflected alignment Mark light signal intensity meets the recognition requirements, thereby avoiding exposure alignment failure or increasing overlay deviation between different layers, thereby improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic cross-sectional structure diagram showing failure of exposure alignment during exposure alignment in a wafer backside photolithography process in the prior art.

[0022] Figures 2 to 5 It is a schematic cross-sectional structure diagram of each step in the exposure alignment method of the wafer backside photolithography process of the present invention.

[0023] Component number description

[0024] 10 Semiconductor Wafer

[0025] 100 Front structure

[0026] 101 Alignment mark

[0027] 102 Alignment mark area outline

[0028] 103 Photoresist layer

[0029] 104 Patterned photoresist layer

[0030] 105 Back doping layer

[0031] 106 Doping region

[0032] 107 Undoped region

[0033] 11. Substrate layer

[0034] 12 Infrared light

[0035] 20 Semiconductor Wafer

[0036] 200 doping layer

[0037] 201 Alignment mark

[0038] 202 photoresist layer

[0039] 21 Infrared light DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] See also Figures 1 to 5It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0042] As described in the background technology, for some semiconductor devices, such as vertically conductive power devices, after completing the wafer front process, some wafer backside photolithography patterning processes are required. When performing the wafer backside photolithography patterning process, the exposure process needs to be aligned with the alignment mark on the front side of the wafer. However, during the exposure alignment process, it often happens that the infrared light emitted by the exposure machine irradiates from the back side of the wafer into the wafer, and the sensor cannot receive the reflected alignment mark light signal or the received alignment mark light signal is very weak, resulting in the alignment failure of the exposure process or the increase of the overlay deviation between different layers. In response to this phenomenon, the inventor conducted in-depth research and found that, Figure 1 As shown, before the back-side photolithography process of the semiconductor wafer 20 is carried out, the semiconductor devices need to firstly form a doping layer 200 with the required doping concentration by ion implantation on the back side of the semiconductor wafer 20, and then carry out the subsequent back-side photolithography process on the basis of the doping layer 200. After the photoresist layer 202 is formed on the doping layer 200, it needs to enter the exposure machine for the exposure process. During this process, it is necessary to realize the alignment process of the wafer in the exposure machine. For the alignment process of the exposure machine with infrared technology, the infrared light 21 emitted by the exposure machine is generally emitted vertically from the back side of the semiconductor wafer 20 to the front side of the semiconductor wafer 20. The mark 201 generates reflected light, and the alignment mark 201 is identified by collecting the reflected light signal of the alignment mark 201 to achieve exposure alignment. However, after the infrared light 21 enters the semiconductor wafer 20, it needs to penetrate the doping layer 200 to reach the alignment mark 201 on the front side of the semiconductor wafer 20. The doping layer 200 has a blocking effect on the infrared light 21, which causes the intensity of the infrared light 21 entering the semiconductor wafer 20 to gradually weaken or even be completely absorbed, thereby making the reflected light intensity of the alignment mark 201 weak or even zero, making it impossible to accurately identify the alignment mark 201, resulting in exposure alignment failure or causing problems such as film ejection.

[0043] Based on this, the present invention proposes an exposure alignment method for a wafer backside photolithography process, the exposure alignment method comprising the following steps:

[0044] S1, providing a semiconductor wafer, wherein an alignment mark is formed on the front side of the semiconductor wafer;

[0045] S2, forming a patterned photoresist layer on the back side of the semiconductor wafer, wherein the patterned photoresist layer at least covers the back side area of ​​the semiconductor wafer corresponding to the outer contour of the area where the alignment mark is located;

[0046] S3, performing ion implantation and annealing on the semiconductor wafer based on the patterned photoresist layer to form a back doping layer, wherein the back doping layer includes a doping area and a non-doping area, and the area where the non-doping area is located at least covers the outer contour area of ​​the area where the alignment mark is located;

[0047] S4, placing the semiconductor wafer with the back doping layer formed thereon with the back side facing upward in an exposure machine equipped with infrared light technology;

[0048] S5, identifying the reflected light signal of the alignment mark on the front side of the semiconductor wafer based on the infrared light technology in the exposure machine to achieve exposure alignment.

[0049] The exposure alignment method of the wafer back side photolithography process of the present invention divides the doping layer in the doping process into a doping area and a non-doping area by changing the doping process before the semiconductor wafer back side photolithography patterning process, wherein the doping area is the doping layer required for the semiconductor device structure, and the non-doping area is set to cover the outer contour of the area where the alignment mark on the front side of the semiconductor wafer is located. Therefore, when the exposure process of the semiconductor wafer back side photolithography patterning process is subsequently performed, the infrared light emitted by the exposure alignment can smoothly pass through the non-doping area to the alignment mark on the front side of the semiconductor wafer, ensuring that the reflected alignment Mark light signal intensity meets the recognition requirements, thereby avoiding exposure alignment failure or increasing overlay deviation between different layers, and improving product yield.

[0050] The exposure alignment method of the wafer backside photolithography process of the present invention is described in detail below with reference to the accompanying drawings.

[0051] like Figure 2 As shown, step S1 is first performed to provide a semiconductor wafer 10 , wherein an alignment mark 101 is formed on the front surface of the semiconductor wafer 10 .

[0052] The orientation of the drawings in this embodiment is based on the placement of the drawings. Since the exposure alignment method of this embodiment is mainly aimed at the back side process of the semiconductor wafer 10, the drawings all place the semiconductor wafer 10 with the back side facing upwards. Figure 2 In the embodiment, the back side of the semiconductor wafer 10 faces upward, and the front side of the semiconductor wafer 10 faces downward.

[0053] As an example, the material of the semiconductor wafer 10 can be any semiconductor material known in the art that is suitable for preparing vertical conductive devices and allows infrared light to penetrate. For example, the semiconductor wafer 10 is used to prepare IGBT power devices or VDMOS power devices. The semiconductor wafer 10 can be at least one of the following materials: silicon, germanium, red phosphorus, germanium silicon, silicon carbide, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or other III / V compound semiconductors, and can also include a multilayer structure formed by these semiconductors. In this embodiment, the semiconductor wafer 10 is selected as a silicon wafer.

[0054] It should be noted here that this embodiment focuses on describing the back process of the semiconductor wafer 10, so other structures and processes related to the vertical conductive device on the semiconductor wafer 10 are not described in detail here, and can all be implemented using existing conventional structures and corresponding processes. Based on this, before the exposure alignment process of this embodiment is performed, the semiconductor wafer 10 may have a corresponding front structure formed in the semiconductor wafer 10 according to the structure of different vertical conductive devices, and after the exposure alignment of this embodiment is implemented, other structures of the vertical conductive device will be prepared.

[0055] As an example, the number, shape, size and other parameters of the alignment mark 101 are set according to actual conditions. Generally, the alignment mark 101 includes a pre-alignment mark and a fine alignment mark. The pre-alignment mark is used in the pre-alignment process of the semiconductor wafer 10, and the fine alignment mark is used in the fine alignment process of the semiconductor wafer 10. The shapes of the alignment marks used in different alignment processes are different, and no excessive restrictions are made here.

[0056] like Figure 3 As shown, step S2 is then performed to form a patterned photoresist layer 104 on the back side of the semiconductor wafer 10 , wherein the patterned photoresist layer 104 at least covers the back side area of ​​the semiconductor wafer 10 corresponding to the area encompassed by the outer contour 102 of the area where the alignment mark is located.

[0057] The purpose of this step is to shield the semiconductor wafer 10 in the area enclosed by the outer contour 102 of the alignment mark area during the subsequent ion implantation process to ensure that the area is not implanted with ions, while ensuring that the area that requires ion implantation (i.e., the area where the patterned photoresist layer 104 is exposed) achieves the required doping.

[0058] As an example, the alignment mark can be set in the cell area of ​​the semiconductor wafer according to different design principles and requirements; it can also be set in the cutting road of the semiconductor wafer 10, also known as the scribing area. The cutting road refers to the gap on the wafer used to separate each independent chip. After the structure preparation of the chip on the wafer is completed, it will be cut along the cutting road to make it an independent chip. In this embodiment, the alignment mark 101 is formed on the cutting road in the semiconductor wafer 10. Since the cutting road is an invalid area for the relatively independent chip, when forming the patterned photoresist layer 104, it can be selected to make the patterned photoresist layer 104 cover the back area of ​​the semiconductor wafer corresponding to the area enclosed by the outer contour of the cutting road. At this time, the alignment mark 101 formed on the cutting road is completely covered, and the mask used for the patterned photoresist layer 104 has a low preparation accuracy requirement. For example, for positive photoresist, it is only necessary to use light shielding treatment on the mask corresponding to the cutting road to make it a non-light-transmitting area. Since the size of the cutting road is much larger than the size of the alignment mark, the preparation of the mask is easier.

[0059] As a specific example, the method of forming the patterned photoresist layer 104 includes: Figure 2 As shown, a photoresist layer 103 is first coated on the back of the semiconductor wafer 10, and the thickness of the photoresist layer 103 is selected according to actual needs; Figure 3 As shown, the photoresist layer 103 is then exposed and developed to obtain the patterned photoresist layer 104. The photomask used in the exposure process selects a laminated structure in which a light-shielding layer is attached to a light-transmitting layer. The material of the light-shielding layer is an opaque material such as Cr.

[0060] like Figure 4 As shown, step S3 is then performed, in which ion implantation and annealing are performed on the semiconductor wafer 10 based on the patterned photoresist layer 104 to form a back doping layer 105, wherein the back doping layer 105 includes a doping region 106 and a non-doping region 107, and the area where the non-doping region 107 is located at least covers the area included in the outer contour 102 of the area where the alignment mark is located.

[0061] As an example, the doping type of the doping region 106 is set according to the device structure requirements to be formed, for example, it can be a single N-type doping or a single P-type doping, or it can be a stack composed of an N-type doping layer and a P-type doping layer. The doping concentration and doping ions of the doping region 106 are also set according to the device structure requirements to be formed, for example, the P-type doping ions can be boron ions, aluminum ions or gallium ions, etc., and the N-type doping ions can be nitrogen ions, phosphorus ions or hydrogen ions, etc. According to actual needs, there can also be other auxiliary doping ions in the doping region 106, which are specifically set according to actual conditions and are not overly restricted here.

[0062] like Figure 5 As shown, the next step is to perform step S4, placing the semiconductor wafer 10 with the back doping layer 105 formed thereon with its back side facing upward in an exposure machine with infrared light technology.

[0063] As an example, the purpose of this step is to perform a photolithography patterning process on the back side of the semiconductor wafer 10, so the back side of the back doping layer 105 is coated with a photoresist layer 103, and the photoresist layer 103 needs to be exposed on an exposure machine later. Before exposure, the photomask and the wafer to be exposed (i.e., the semiconductor wafer 10) need to be aligned with the exposure machine to achieve exposure alignment between the two.

[0064] like Figure 5 As shown, step S5 is finally performed to identify the reflected light signal of the alignment mark 101 on the front side of the semiconductor wafer 10 based on the infrared light technology in the exposure machine to achieve exposure alignment.

[0065] As described above, before exposure, the photomask and the wafer to be exposed (i.e., the semiconductor wafer 10) need to be aligned with respect to the exposure machine, including aligning the photomask with respect to the exposure machine and aligning the wafer to be exposed with respect to the exposure machine. This step is to align the semiconductor wafer 10 with respect to the exposure machine, and the infrared light is emitted by the infrared device carried by the exposure machine itself and enters the semiconductor wafer 10 through the photoresist layer 103. Since the infrared light is not absorbed by the non-doped area 107, it can reach the alignment mark 101 on the front of the semiconductor wafer 10, thereby receiving the reflected light intensity that can accurately distinguish the alignment mark 101.

[0066] As an example, the wavelength of infrared light used in the exposure machine is selected to be 760nm to 1500nm.

[0067] In summary, the present invention provides an exposure alignment method for a wafer backside photolithography process, by changing the doping process before the semiconductor wafer backside photolithography patterning process, the doping layer in the doping process is divided into a doping area and a non-doping area, wherein the doping area is the doping layer required for the semiconductor device structure, and the non-doping area is set to cover the outer contour of the alignment mark area on the front of the semiconductor wafer. Therefore, when the exposure process of the semiconductor wafer backside photolithography patterning process is subsequently performed, the infrared light emitted by the exposure alignment can smoothly pass through the non-doping area to the alignment mark on the front of the semiconductor wafer, ensuring that the reflected alignment Mark light signal intensity meets the recognition requirements, thereby avoiding exposure alignment failure or increasing the overlay deviation between different layers, and improving the product yield. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0068] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An exposure alignment method for wafer backside photolithography process, characterized in that: The exposure alignment method comprises the following steps: Providing a semiconductor wafer, wherein an alignment mark is formed on the front side of the semiconductor wafer; Forming a patterned photoresist layer on the back side of the semiconductor wafer, wherein the patterned photoresist layer at least covers the back side area of ​​the semiconductor wafer corresponding to the outer contour of the area where the alignment mark is located; Based on the patterned photoresist layer, ion implantation and annealing are performed on the semiconductor wafer to form a back doping layer, wherein the back doping layer includes a doping area and a non-doping area, and the area where the non-doping area is located at least covers the outer contour area of ​​the area where the alignment mark is located; Placing the semiconductor wafer with the back doped layer formed thereon with the back side facing upward in an exposure machine equipped with infrared light technology; Based on the infrared light technology in the exposure machine, the reflected light signal of the alignment mark on the front side of the semiconductor wafer is identified to achieve exposure alignment.

2. The exposure alignment method for wafer backside photolithography process according to claim 1, characterized in that: The semiconductor wafer is a silicon wafer.

3. The exposure alignment method for wafer backside photolithography process according to claim 1, characterized in that: The semiconductor wafer is used for preparing IGBT power devices or VDMOS power devices.

4. The exposure alignment method for wafer backside photolithography process according to claim 1, characterized in that: The doping region in the back doping layer is an N-type doping region or a P-type doping region or a doping region formed by stacking an N-type doping layer and a P-type doping layer.

5. The exposure alignment method for wafer backside photolithography process according to claim 1, characterized in that: The alignment mark on the front side of the semiconductor wafer is formed in a cell area of ​​the semiconductor wafer or a dicing street of the semiconductor wafer.

6. The exposure alignment method for wafer backside photolithography process according to claim 5, characterized in that: The alignment mark on the front side of the semiconductor wafer is formed on a cutting path of the semiconductor wafer; the patterned photoresist layer covers a back side area of ​​the semiconductor wafer corresponding to an area enclosed by an outer contour of the cutting path.

7. The exposure alignment method for wafer backside photolithography process according to claim 1, characterized in that: The patterned photoresist layer is a positive photoresist.

8. The exposure alignment method for wafer backside photolithography process according to claim 1, characterized in that: The light shielding layer material of the photomask used to form the patterned photoresist layer is Cr.

9. The exposure alignment method for wafer backside photolithography process according to claim 1, characterized in that: The alignment mark is identified by receiving reflected light of the infrared light in the exposure machine.

10. The exposure alignment method for wafer backside photolithography process according to claim 1, characterized in that: The wavelength of the infrared wave emitted by the infrared technology of the exposure machine is 760nm to 1500nm.

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