Packaging and stacking structure of SOC and storage chip

Abstract

The invention discloses a packaging and stacking structure of an SOC (system on chip) and a memory chip, which improves the speed capacity, reduces the volume and realizes lightening, thinning, high density and high speed. The device comprises a PCB (Printed Circuit Board); the SOC chip module comprises a plurality of SOC chips and a first plastic package body; the LPDDR chip module comprises a plurality of memory chips, an adapter plate and a second plastic package body; the UFS chip module comprises a main control chip, a plurality of stacked flash memory chips, a flash memory chip substrate and a third plastic package body; and a sealing substrate.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a packaging stacking structure of a SOC and a storage chip. Background Art

[0002] As mobile terminal products such as mobile phones are becoming thinner, higher-density and higher-capacity, the demand for high speed is getting higher and higher. The existing mobile phone S0C chip and Memory chip are both independent products. These chips are soldered on the PCB board through the SMT process, which will cause delays and impacts on the response speed of mobile terminals such as mobile phones. Therefore, it is urgent to develop a new packaging structure to reduce the size and make it thinner while increasing the speed capacity to make it have high density and high speed. Summary of the invention

[0003] In view of the above problems, the present invention provides a packaging stacking structure of a SOC and a memory chip, which improves the speed capacity, reduces the volume, and achieves lightness, high density and high speed.

[0004] A package stacking structure of a SOC and a memory chip, characterized in that it comprises:

[0005] PCB board;

[0006] A SOC chip module, comprising a plurality of SOC chips and a first plastic package;

[0007] The LPDDR chip module includes a plurality of memory chips, an adapter board, and a second plastic package;

[0008] The UFS chip module includes a main control chip, a plurality of stacked flash memory chips, a flash memory chip substrate, and a third plastic package;

[0009] and a sealing substrate;

[0010] A plurality of memory chips are connected to one surface of the closed substrate through the second plastic package body, and the adapter board is provided on the other surface formed by the combination of the plurality of memory chips. The central area of ​​the other surface of the closed substrate is connected to the corresponding SOC chip Bump of the SOC chip, and the periphery of the other surface of the closed substrate is connected to the raised first solder ball of the PCB board. A raised second solder ball is provided on the surface of the adapter board away from the memory chip, and the exposed surface of the flash memory chip substrate is connected to the raised second solder ball. A main control chip and a plurality of stacked flash memory chips are encapsulated in the third plastic package body of the flash memory chip substrate.

[0011] It is further characterized by:

[0012] The sealing substrate is preliminarily provided with a first opening through the TMV process, and then the SOC chip module and the memory chip module are plastic-sealed through the sealing substrate by double-sided plastic sealing, and then the double-sided openings of the entire mechanism are opened through the TMV process to form second openings and third openings, so that the entire mechanism has a channel or line connected to the PCB board and the flash memory chip substrate, and the chips in the SOC chip module and the memory chip module are interconnected, thereby improving the response speed of the mobile terminal;

[0013] The plurality of memory chips include stacked memory chip groups arranged in two columns, the two stacked memory chip groups have the same height, and the memory chips of each stacked memory chip group are stacked in staggered layers and connected by gold wires;

[0014] The main control chip is arranged on one side of the surface area of ​​the flash memory chip substrate, and a plurality of stacked flash memory chips are arranged on the other side of the surface area of ​​the flash memory chip substrate. The flash memory chips of the stacked flash memory chips are stacked in staggered layers and connected by gold wires.

[0015] The adapter board is supported on the equal height surface formed by two groups of stacked memory chips, the adapter board is connected to one group of stacked memory chips through gold wires, the flash memory chip substrate is provided with a fourth opening through the TMV process, the circuit in the fourth opening is connected to the raised second solder ball of the adapter board, and the main control chip and the plurality of stacked flash memory chips are indirectly connected to the PCB board;

[0016] Preferably, the second solder ball is provided with a second opening at a corresponding position of the second plastic package body, so as to ensure reliable connection between the second solder ball and the corresponding circuit of the flash memory chip substrate;

[0017] The sealing substrate connects the SOC chip module and the memory chip module to the raised first solder balls of the PCB board through the lines arranged in the first opening and the third opening, ensuring the interconnection of the two groups of chips.

[0018] After adopting the present invention, the memory chips of the SOC chip and the LPDDR chip module are plastic-sealed in a double-sided plastic-sealing manner, and after plastic-sealing, double-sided TMV holes are opened, and then the UFS chip module is SMT-welded from the adapter board of the LPDDR chip module, and then the entire mechanism is welded on the PCB board through SMT, so as to realize the PoP structure of SOC and Memory products, improve the product operation speed, and reduce the volume; and the memory chips in several SOC chips and LPDDR chip modules are plastic-sealed on both sides of the sealing substrate in a double-sided plastic-sealing manner, and the chips in the SOC chip module and the memory chip module are interconnected, thereby improving the response speed of the mobile terminal; in summary, it improves the speed capacity, reduces the volume, and realizes lightness, high density and high speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the packaging structure corresponding to the present invention;

[0020] The names corresponding to the serial numbers in the figure are as follows:

[0021] PCB board 10, raised first solder ball 11, SOC chip module 20, SOC chip 21, first plastic package 22, SOC chip Bump23, LPDDR chip module 30, stacked memory chipset 301, first gold wire 302, third gold wire 303, memory chip 31, adapter board 32, second plastic package 33, raised second solder ball 34, UFS chip module 40, second gold wire 401, fourth opening 402, main control chip 41, flash memory chip 42, flash memory chip substrate 43, third plastic package 44, closed substrate 50, first opening 51, second opening 52, third opening 53. DETAILED DESCRIPTION

[0022] A packaging stacking structure of SOC and memory chip, see Figure 1 : It includes a PCB board 10, a SOC chip module 20, a LPDDR chip module 30, a UFS chip module 40, and a sealing substrate 50;

[0023] A raised first solder ball 11 is provided on the outer periphery of the upper surface of the PCB board 10;

[0024] The SOC chip module 20 includes a plurality of SOC chips 21 and a first plastic package 22. Each group of SOC chips 21 is provided with a SOC chip Bump 23.

[0025] The LPDDR chip module 30 includes a plurality of memory chips 31, an adapter board 32, and a second plastic package 33;

[0026] The UFS chip module 40 includes a main control chip 41, a plurality of stacked flash memory chips 42, a flash memory chip substrate 43, and a third plastic package 44;

[0027] The closed-package substrate 50 is provided with a first opening 51 in advance through the TMV process before packaging, and corresponding circuits and plating layers are arranged in the first opening 51. A surface of the closed-package substrate 50 is packaged and connected with a plurality of memory chips 31 through the second plastic packaging body 33, and the second plastic packaging body is also packaged with an adapter board 32. The other surface formed by the combination of the plurality of memory chips 31 is provided with an adapter board 32. The central area of ​​the other surface of the closed-package substrate 50 is packaged with a plurality of SOC chips through the first plastic packaging body, and each group of SOC chips corresponds to the corresponding circuit or plating layer of the closed-package substrate 50 connected to the SOC chip Bump23. The periphery of the other surface of the closed-package substrate 50 is connected to the raised first solder ball 11 of the PCB board 10, and the surface of the adapter board 32 facing away from the memory chip 31 is provided with a raised second solder ball 34. The exposed surface of the flash memory chip substrate 43 is connected to the raised second solder ball 34, and a main control chip 41 and a plurality of stacked flash memory chips 42 are packaged in the third plastic packaging body 44 of the flash memory chip substrate 43.

[0028] In a specific implementation, a first opening 51 is pre-arranged on the sealing substrate 50 by the TMV process, and then the SOC chip module 20 and the memory chip module 30 are sealed by double-sided plastic sealing through the sealing substrate 50, and then the second opening 52 and the third opening 53 are formed by opening holes on both sides of the entire mechanism by the TMV process, so that the entire mechanism has a channel or line connected to the PCB board 10 and the flash memory chip substrate 43, and the chips in the SOC chip module 20 and the memory chip module 30 are interconnected, thereby improving the response speed of the mobile terminal;

[0029] The plurality of memory chips 31 include stacked memory chipsets 301 arranged in two columns, the two stacked memory chipsets 301 have the same height, and the memory chips 31 of each stacked memory chipset 301 are stacked in staggered layers and connected by first gold wires 302;

[0030] The main control chip 41 is arranged on one side of the surface of the flash memory chip substrate 43, and a plurality of stacked flash memory chips 42 are arranged on the other side of the surface of the flash memory chip substrate 43. The flash memory chips of the plurality of stacked flash memory chips 42 are stacked in staggered layers and connected by a second gold wire 401.

[0031] The adapter board 32 is supported on the isotropic surface formed by two groups of stacked memory chipsets 301. The adapter board 32 is connected to one group of stacked memory chipsets 301 through a third gold wire 303. The flash memory chip substrate 43 is provided with a fourth opening 402 through the TMV process. The circuit in the fourth opening 402 is connected to the raised second solder ball 34 of the adapter board 42, so as to indirectly connect the main control chip 41 and several stacked flash memory chips 42 to the PCB board 10.

[0032] In a specific implementation, the second opening 52 corresponds to the corresponding position of the protruding second solder ball 34 corresponding to the second plastic package body, ensuring that the protruding second solder ball 52 and the corresponding circuit of the flash memory chip substrate 43 are reliably connected;

[0033] The sealing substrate 50 connects the SOC chip module 20 and the memory chip module 30 to the raised first solder balls 11 of the PCB board 10 through the lines set by the first openings 51 and the third openings 53, ensuring the interconnection of the two groups of chips.

[0034] Its production principle: through a multi-layer sealing substrate, the memory chip and SOC chip of the LPDDR chip module are interconnected, and the first plastic sealing body and the second plastic sealing body are formed by a double-sided plastic sealing process, so that the two form an integrated structure, and then the surfaces of the sealing substrate and the second plastic sealing body are opened by the TMV process, so that the integrated structure has a channel or line connected to the PCB board and the flash memory chip substrate;

[0035] The UFS chip module is also packaged independently. A hole is opened on the flash chip substrate through the TMV process, and then the UFS chip module 40 is SMT welded on the exposed raised second solder ball of the adapter board. Then, the overall structure formed by the combination of the SOC chip module 20, the LPDDR chip module 30, the UFS chip module 40, and the sealed substrate 50 is SMT welded on the raised first solder ball 11 of the PCB board to realize the PoP structure of the SOC and Memory products.

[0036] The memory chips of the SOC chip and LPDDR chip module are encapsulated by double-sided plastic encapsulation, and double-sided TMV holes are opened after plastic encapsulation. Then, the UFS chip module is SMT welded on the adapter board of the LPDDR chip module, and then the entire structure is SMT welded on the PCB board to realize the PoP structure of SOC and Memory products, improve the product operation speed and reduce the volume;

[0037] The memory chips in the SOC chips and LPDDR chip modules are sealed on both sides of the sealing substrate by double-sided plastic sealing, and the chips in the SOC chip module and the memory chip module are interconnected, thereby improving the response speed of the mobile terminal;

[0038] In addition, the LPDDR chip module and the UFS chip module are packaged independently, with a higher packaging and testing yield. The two products are combined into a finished product with a higher yield. At the same time, the UFS particles corresponding to the UFS chip module will not be lost. The two modules are independently packaged and tested and then mixed packaged, which makes the packaging yield higher and thus reduces costs.

[0039] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0040] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A package stacking structure of a SOC and a memory chip, characterized in that: It includes: PCB board; A SOC chip module, comprising a plurality of SOC chips and a first plastic package; The LPDDR chip module includes a plurality of memory chips, an adapter board, and a second plastic package; The UFS chip module includes a main control chip, a plurality of stacked flash memory chips, a flash memory chip substrate, and a third plastic package; and a sealing substrate; A plurality of memory chips are connected to one surface of the closed substrate through the second plastic package body, and the adapter board is provided on the other surface formed by the combination of the plurality of memory chips. The central area of ​​the other surface of the closed substrate is connected to the corresponding SOC chip Bump of the SOC chip, and the periphery of the other surface of the closed substrate is connected to the raised first solder ball of the PCB board. A raised second solder ball is provided on the surface of the adapter board away from the memory chip, and the exposed surface of the flash memory chip substrate is connected to the raised second solder ball. A main control chip and a plurality of stacked flash memory chips are encapsulated in the third plastic package body of the flash memory chip substrate.

2. The package stacking structure of a SOC and a memory chip according to claim 1, characterized in that: The sealing substrate is pre-arranged with a first opening through the TMV process, and then the SOC chip module and the memory chip module are plastic-sealed through the sealing substrate by double-sided plastic sealing. Then, holes are opened on both sides of the entire structure through the TMV process to form second openings and third openings, so that the entire structure has channels or lines connected to the PCB board and the flash memory chip substrate, and the chips in the SOC chip module and the memory chip module are interconnected.

3. The package stacking structure of a SOC and a memory chip according to claim 1, characterized in that: The plurality of memory chips include stacked memory chip groups arranged in two columns. The two stacked memory chip groups have the same height, and the memory chips of each stacked memory chip group are stacked in staggered layers and connected by gold wires.

4. The package stacking structure of a SOC and a memory chip according to claim 3, characterized in that: The main control chip is arranged on one side of the surface area of ​​the flash memory chip substrate, and a plurality of stacked flash memory chips are arranged on the other side of the surface area of ​​the flash memory chip substrate. The flash memory chips of the stacked flash memory chips are stacked in staggered layers and connected by gold wires.

5. The package stacking structure of a SOC and a memory chip according to claim 4, characterized in that: The adapter board is supported on an isotropic surface formed by two groups of stacked memory chips. The adapter board is connected to one group of stacked memory chips through a gold wire. The flash memory chip substrate is provided with a fourth opening through the TMV process. The circuit in the fourth opening is connected to the raised second solder ball of the adapter board, so that the main control chip and several stacked flash memory chips are indirectly connected to the PCB board.

6. The package stacking structure of a SOC and a memory chip according to claim 2, characterized in that: The raised second solder ball is provided with a second opening at a position corresponding to the second plastic packaging body.

7. The package stacking structure of a SOC and a memory chip according to claim 1, characterized in that: The sealing substrate connects the SOC chip module and the memory chip module to the raised first solder balls of the PCB board through the lines arranged in the first opening and the third opening.

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