Manufacturing method of package substrate and package substrate

Abstract

The present specification relates to a method for manufacturing a package substrate and a package substrate. A package substrate according to the present specification includes: a core layer; and an upper layer on the core layer, the core layer comprising a glass core comprising a first surface and a second surface opposite each other, the upper layer comprising: a first distribution layer formed on the core layer; and a dummy layer formed on the first distribution layer, the dummy layer including a material having a thermal expansion coefficient lower than a thermal expansion coefficient of an insulating material of the first distribution layer. Thereby, a dummy layer without curing shrinkage is provided between the distribution layers, thereby achieving an effect that curing shrinkage of the distribution layers located between the dummy layer and the core layer can be relieved and stress concentrated on the core layer can be dispersed.

Description

Technical Field

[0001] The present application relates to a packaging substrate, a semiconductor package, a method for manufacturing the packaging substrate, a method for manufacturing the semiconductor package, and the like. Background Art

[0002] When manufacturing electronic components, realizing circuits on semiconductor wafers is called the front-end (FE) process, and assembling the wafers in a state that can be used in actual products is called the back-end (BE) process. The back-end process includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have recently enabled the rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology and software technology.

[0004] Semiconductor technology is developing in various forms, such as line widths of nanometer units below micrometers, more than 10 million cells, high-speed operation, and release of large amounts of heat, but there is still a lack of technical support for relatively complete packaging of the above semiconductors.

[0005] Therefore, the electrical performance of a semiconductor sometimes depends on the packaging technology and the corresponding electrical connections, rather than on the performance of the semiconductor technology itself.

[0006] As the material of the packaging substrate, ceramic or resin is used. In the case of a ceramic substrate such as a silicon substrate, it is difficult to mount a high-performance high-frequency semiconductor element due to the high resistance value or high dielectric constant. In the case of a resin substrate, although relatively high-performance high-frequency semiconductor elements can be mounted, there are limitations in reducing the spacing of wiring.

[0007] Recently, silicon or glass can be used for high-end package substrates. By forming a through hole on the silicon or glass substrate and applying a conductive material to the through hole, the wiring length between the component and the motherboard can be shortened, and excellent electrical characteristics can be obtained.

[0008] In addition, the semiconductor package generates heat when in operation, and sometimes additionally includes a heat sink for releasing the heat. Related prior art includes US patent US11694974 B2 and US patent publication US2022-0367311 A1.

[0009] Summary of the invention

[0010] Problem that the invention aims to solve

[0011] The purpose of this embodiment is to provide a packaging substrate, which has a virtual layer between the distribution layers and shrinks negligibly during heat treatment or the like, thereby alleviating the stress on the core layer caused by the curing shrinkage of the distribution layer located between the virtual layer and the core layer and dispersing the stress concentrated on the core layer.

[0012] In addition, the present embodiment aims to provide a packaging substrate which has the effect of preventing peeling between the distribution layer and the core layer that may occur during heat treatment or cracking and damage of the core layer due to warping of the distribution layer through a dummy layer formed between the distribution layers.

[0013] Means used to solve problems

[0014] In order to achieve the above objective, one embodiment relates to a method for manufacturing a packaging substrate and a packaging substrate using the same.

[0015] The packaging substrate according to the present specification includes: a core layer; and an upper layer located on the core layer, the core layer includes a glass core, the glass core includes a first surface and a second surface opposite to each other, and the upper layer includes: a first distribution layer formed on the core layer; and a virtual layer formed on the first distribution layer, the virtual layer includes a material with a coefficient of thermal expansion (CTE) lower than the coefficient of thermal expansion of an insulating material of the first distribution layer.

[0016] The upper layer may further include a second distribution layer formed on the dummy layer.

[0017] The dummy layer may be located between the first distribution layer and the second distribution layer and in direct contact with the first distribution layer.

[0018] When the difference (absolute value) between the thermal expansion coefficient of the glass core and the thermal expansion coefficient of the first distribution layer is defined as D_C and the difference (absolute value) between the thermal expansion coefficient of the first distribution layer and the thermal expansion coefficient of the virtual layer is defined as D_D, D_D may be smaller than D_C.

[0019] The dummy layer may include 80 wt % or more of inorganic matter.

[0020] The virtual layer may be an inorganic layer.

[0021] The dummy layer may include polysilicon, SiO 2 or a metal layer.

[0022] The thermal expansion coefficient of the dummy layer may be 20 ppm / ° C. or less.

[0023] The upper layer may further include a fine distribution layer formed on the second distribution layer.

[0024] The second distribution layer may include polymer resin A and inorganic particles A, and the fine distribution layer may include polymer resin B and inorganic particles B.

[0025] The average size of the inorganic particles A may be smaller than the average size of the inorganic particles B.

[0026] The package substrate may further include a lower layer located below the core layer.

[0027] The lower layer may include: a third distribution layer formed below the core layer; a lower dummy layer formed below the third distribution layer; and a fourth distribution layer formed below the dummy layer.

[0028] On the other hand, in order to achieve the above-mentioned purpose, a manufacturing method of a packaging substrate according to one embodiment includes the following steps: preparing a core layer including a glass core; arranging a first insulating material, a first conductive pattern or a combination thereof on the core layer to form a first distribution layer; and forming a virtual layer on the first distribution layer, the virtual layer including a material having a thermal expansion coefficient lower than the thermal expansion coefficient of the first insulating material.

[0029] The method for manufacturing the package substrate may further include the following step: disposing a second insulating material, a second conductive pattern or a combination thereof on the dummy layer to form a second distribution layer.

[0030] The thermal expansion coefficient of the dummy layer may be smaller than the thermal expansion coefficient of the second insulating material.

[0031] The method for manufacturing the package substrate may further include the following step: disposing a third insulating material and a third conductive pattern below the core layer to form a third distribution layer.

[0032] The dummy layer includes a material having a thermal expansion coefficient lower than a thermal expansion coefficient of the third insulating material.

[0033] The manufacturing method of the packaging substrate may also include the following steps: arranging a third insulating material and a third conductive pattern below the core layer to form a third distribution layer; forming a lower dummy layer below the third distribution layer; and arranging a fourth insulating material and a fourth conductive pattern below the lower dummy layer to form a fourth distribution layer.

[0034] Effects of the Invention

[0035] The manufacturing method of the packaging substrate of this embodiment and the packaging substrate using the same can have the following effects: by arranging a virtual layer whose shrinkage is negligible during heat treatment or the like between the distribution layers, the stress of the core layer caused by the curing shrinkage of the distribution layer located between the virtual layer and the core layer is alleviated, and the stress concentrated on the core layer is dispersed.

[0036] In addition, due to the dummy layer formed between the distribution layers, it is possible to prevent the peeling between the distribution layer and the core layer or the cracking and breaking of the core layer due to the warpage of the distribution layer which may occur during the heat treatment process. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram for explaining the cross-sectional structure of a package substrate according to the present embodiment.

[0038] Figure 2 FIG. 1 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment.

[0039] Figure 3A and Figure 3B Each of them is a schematic diagram illustrating a portion of a package substrate according to the present embodiment in cross section.

[0040] FIG. 4A to FIG. 4E The flowchart is a cross-sectional view of a process for producing a core distribution layer in a process for manufacturing a package substrate according to the present embodiment.

[0041] FIG. 5A to FIG. 5E The flowchart is a cross-sectional view of a process for generating an insulating layer in a process for manufacturing a package substrate according to the present embodiment.

[0042] FIG. 6A to FIG. 6C Each of them is a schematic diagram illustrating in cross section the problems occurring during a heat treatment of a package substrate including a core layer and a plurality of distribution layers.

[0043] 7A to 7C Each of the diagrams is a schematic diagram illustrating in cross section a heat treatment process of a package substrate including a dummy layer formed between distribution layers according to each embodiment.

[0044] Description of Reference Numerals

[0045] 100: Semiconductor devices

[0046] 10: Motherboard

[0047] 30: Semiconductor Components

[0048] 32: First semiconductor element

[0049] 34: Second semiconductor element

[0050] 36: The third semiconductor element

[0051] 20: Package substrate

[0052] 21, 21a: Glass core

[0053] 22: Core layer

[0054] 223: Core insulation

[0055] 213: First Surface

[0056] 214: Second Surface

[0057] 23: Core through hole

[0058] 24: Core distribution layer

[0059] 241: Core distribution pattern

[0060] 26: Upper layer

[0061] 25: Upper distribution layer

[0062] 251: Upper distribution pattern

[0063] 253: Upper insulation layer

[0064] 27: Top connection layer

[0065] 271: Electrode connected above

[0066] 272: Connection pattern above

[0067] 28: Cavity

[0068] 281: Interior Space

[0069] 282: Cavity distribution layer

[0070] 40: Electronic components

[0071] 50: Connection

[0072] 51: Component connection

[0073] 52: Plate connection

[0074] 61: First distribution layer

[0075] 62: Second distribution layer

[0076] 63: Third distribution layer

[0077] 64: Fourth distribution layer

[0078] 70: Virtual layer DETAILED DESCRIPTION

[0079] The following detailed description is provided to help fully understand the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be apparent. For example, the sequence of actions described herein is merely an example and is not limited to those set forth herein. Except for the steps that must be performed in a specific order, the sequence of actions can be changed according to the understanding of the disclosure of the application. In addition, after understanding the disclosure of the application, the description of known features can be omitted to increase clarity and simplicity. However, the omission of features and their descriptions is not intended to admit that they are common sense.

[0080] The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0081] Although terms such as "first", "second", and "third" may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are only used to distinguish one component, part, region, layer, or section from another component, part, region, layer, or section. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section.

[0082] Throughout the specification, when an element such as a layer, a region or a substrate is described as being “on another element,” “connected to another element,” or “coupled to another element,” it may be directly “on another element,” “connected to another element,” or “coupled to another element,” or one or more other elements may be interposed therebetween. On the contrary, when an element is described as being “directly on another element,” “directly connected to another element,” or “directly coupled to another element,” no other elements may be interposed therebetween. Similarly, expressions such as “between” and “directly between” and “contacting” and “directly contacting” may also be interpreted as described above.

[0083] The terms used herein are only used for the purpose of describing specific examples and are not used to limit the present disclosure. As used herein, the singular form is intended to also include the plural form, unless the context clearly states otherwise. As used herein, the term "and / or" includes any one of the items listed in the relevant list and a combination of more than two items. As used herein, the terms "include", "comprise" and "have" specify the existence of stated features, numbers, actions, elements, parts and / or their combinations, but do not exclude the existence or addition of more than one other features, numbers, actions, elements, parts and / or their combinations. The use of the term "may" herein about examples or embodiments (for example, about the content that can be included or implemented in examples or embodiments) means that there is at least one example or embodiment in which such features are included or implemented, and all examples are not limited thereto.

[0084] In the present application, “B is disposed on A” means that B is disposed in direct contact with A or is disposed on A with another layer or structure interposed therebetween, and thus should not be construed as being limited to B being disposed in direct contact with A.

[0085] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs consistent with and after understanding the present disclosure. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless explicitly defined herein.

[0086] In one or more examples, the description of "A and / or B" means "A, B, or A and B."

[0087] In one or more examples, terms such as "first," "second," "A," or "B" are used to distinguish the same terms.

[0088] In one or more examples, unless otherwise specified, the expression singular is interpreted as including the meaning of the singular or plural as interpreted in the context.

[0089] Figure 1 Schematic diagram for explaining the cross-sectional structure of a package substrate according to the present embodiment. Figure 2 FIG. 1 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment. Figure 3A and Figure 3B Each of them is a schematic diagram illustrating a portion of a package substrate according to the present embodiment in cross section.

[0090] In order to achieve the above-mentioned purpose, the semiconductor device 100 according to the present embodiment includes: a semiconductor element part 30, in which one or more semiconductor elements 32, 34, 36 are located; a packaging substrate 20, which is electrically connected to the semiconductor element; and a motherboard 10, which is electrically connected to the packaging substrate 20, and is connected to the semiconductor elements 32, 34, 36 and transmits external electrical signals.

[0091] The package substrate 20 according to an embodiment includes: a core layer 22 ; an upper layer 26 located on one surface of the core layer 22 ; and a cavity portion 28 in which an electronic component 40 may be located.

[0092] The semiconductor element section 30 refers to an element mounted on a semiconductor device, and is mounted on the package substrate 20 via connection electrodes, etc. Specifically, as the semiconductor element section 30, for example, a computing element such as a CPU, a GPU (a first semiconductor element 32, a second semiconductor element 34), a storage element such as a memory chip (a third semiconductor element 36), etc. can be used, but any semiconductor element mounted on a semiconductor device can be used without limitation.

[0093] The motherboard 10 may be a motherboard of a printed circuit board, a printed wiring board, or the like.

[0094] The packaging substrate 20 may selectively further include a lower layer (not shown in the figure) located below the core layer.

[0095] The core layer 22 may include: a glass core 21, including a first region 221 and a second region 222, the first region 221 having a first thickness 211, the second region 222 being adjacent to the first region 221 and having a second thickness 212 thinner than the first thickness; a plurality of core through holes 23, penetrating the glass core 21 in the thickness direction; and a core distribution layer 24, located on the surface of the glass core 21 or the core through holes 23, and electrically connecting the first surface 213 of the glass core 21 and the second surface 214 opposite to the first surface through the core through holes 23.

[0096] The second region 222 of the core layer 22 may function as a cavity structure.

[0097] In the same region, the glass core 21 has a first surface 213 and a second surface 214 opposite to each other, and the two surfaces are substantially parallel to each other, so that the glass core 21 has a constant thickness as a whole.

[0098] The inner space 281 formed by the thickness difference between the first region 221 and the second region 222 plays a role of accommodating a part or all of the electronic component 40 .

[0099] The glass core 21 may include a core through hole 23 penetrating the first surface 213 and the second surface 214. The core through hole 23 may be formed in both the first region 221 and the second region 222, and may be formed at an intended pitch and pattern.

[0100] As a packaging substrate for semiconductor devices, a stacked form of silicon substrate and organic substrate has been used in the past. Due to the characteristics of semiconductors, silicon substrates may produce parasitic elements when used in high-speed circuits, and have the disadvantage of relatively large power loss. In addition, organic substrates need to be large in area in order to form more complex distribution patterns, but this does not conform to the trend of manufacturing ultra-miniaturized electronic devices. In order to form a complex distribution pattern within a predetermined size, the pattern needs to be miniaturized, but due to the characteristics of materials such as polymers used for organic substrates, there are actually limitations to pattern miniaturization.

[0101] In this embodiment, as a method for solving the above-mentioned problem, the glass core 21 is used as a support body of the core layer 22. In addition, together with the glass core 21, a core through hole 23 formed through the glass core 21 is also used, thereby providing a package substrate 20 having a shorter current length, more miniaturization, faster response, and less loss characteristics.

[0102] The glass core 21 is preferably a glass substrate suitable for semiconductors, for example, a borosilicate glass substrate, an alkali-free glass substrate, etc., but the present invention is not limited thereto.

[0103] The core through hole 23 penetrates the glass core 21. The core through hole 23 may be formed by removing a predetermined region of the glass core 21, and more specifically, may be formed by etching a plate-shaped glass using a physical and / or chemical method.

[0104] Specifically, when forming the core through hole 23, a method of forming a defect (stain) on the surface of the glass core by laser or the like and then performing chemical etching, laser etching, or the like may be used, but the present invention is not limited thereto.

[0105] Based on the unit area (1 cm×1 cm) of the glass core 21, 100 to 3000 core through holes 23 may be provided, or 100 to 2500 core through holes 23 may be provided, or 225 to 1024 core through holes 23 may be provided. When the spacing condition is met, it is more conducive to forming a conductive layer, etc., and the performance of the package substrate may be improved.

[0106] The core distribution layer 24 includes a core distribution pattern 241 and a core insulation layer 223, wherein the core distribution pattern 241 is a conductive layer that electrically connects the first surface and the second surface of the glass core through a through hole, and the core insulation layer 223 surrounds the core distribution pattern. The interior of the core layer 22 is formed with a conductive layer through a core through hole, so that it can be used as an electrical passage through the glass core 21. In addition, the core layer 22 connects the upper and lower parts of the glass core at a relatively short distance, thereby achieving faster electrical signal transmission and lower loss characteristics. For example, the conductive layer can be a copper plating layer, but the present invention is not limited thereto.

[0107] The cavity 28 is basically circular, triangular, quadrilateral, hexagonal, octagonal, cross-shaped, etc., and its shape is not limited.

[0108] The shape of the electronic component 40 can be roughly cylindrical, rectangular or polygonal.

[0109] The cavity portion 28 may include a cavity distribution pattern as a conductive layer electrically connecting the electronic component 40 and the core distribution layer 24 and an insulating layer surrounding the cavity distribution pattern.

[0110] On the other hand, the cavity portion according to another embodiment may be implemented in the form of penetrating the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion may be formed according to the same process as the core through hole 23, and the area and shape of the penetrating glass core 21 may be different from those of the core through hole 23.

[0111] In this embodiment, the insulating layer may be formed after the electronic components 40 are arranged in the cavity portion. That is, the insulating layer may also be formed in the cavity portion through the process of forming the core insulating layer 223 .

[0112] The core allocation pattern 241 may be formed as a pattern capable of being electrically connected to the electronic component 40 .

[0113] The electronic component 40 may include an active component such as a transistor or a power transmission component such as a multi-layer ceramic capacitor (MLCC), that is, a passive component.

[0114] As the electronic component 40, a component such as a transistor for converting an electrical signal between a motherboard and a semiconductor element portion to an appropriate level can be used. In this case, a transistor or the like is applied to the junction of the package substrate 20, so that a more efficient and faster semiconductor device 100 can be provided.

[0115] In addition, power transmission elements such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor elements. There are generally at least 200 types of power transmission elements as passive elements applied to semiconductor elements. When transmitting power, the characteristics of the conductive layer around the element affect the performance of the element. In one embodiment, a non-circular core via that is not a circular core via can be applied to places where a low-resistance conductive layer is required, such as the power transmission element.

[0116] On the other hand, as the electronic component 40, a passive component such as a capacitor can be inserted and used alone. In addition, a plurality of passive components can be embedded between insulator layers (electronic component insulating layers), and the component group can be formed so that the electrodes are exposed and then can be inserted into the electronic component 40. In the latter case, the workability of manufacturing the package substrate can be improved more smoothly, and the insulating layer can be more advantageously sufficiently and reliably arranged in the space between the complex components.

[0117] The glass core 21 plays an intermediate role, that is, an intermediary role, in connecting the semiconductor element part 30 and the motherboard 10 to the upper part and the lower part respectively, and the core through hole 23 is used as a path for transmitting their electrical signals, thereby achieving smooth signal transmission. In order to distinguish it from the core through hole of the second area 222 described below, the core through hole set in the first area 221 is called the first area core through hole.

[0118] The upper layer 26 is located on the first surface 213 .

[0119] The upper layer 26 includes an upper distribution layer 25 and an upper connection layer 27 located on the upper distribution layer 25 . The uppermost surface of the upper layer 26 may be protected by a cap layer 60 having an opening that allows direct contact between the connection electrodes of the semiconductor element.

[0120] The upper distribution layer 25 includes: an upper insulating layer 253 located on the first surface; and an upper distribution pattern 251, which is a conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24, and the upper distribution pattern 251 is built into the upper insulating layer 253. The upper distribution layers 25 disposed above and below each other may be connected to each other through blind vias.

[0121] As the upper insulating layer 253 , any material as long as it is applied to a semiconductor element or a package substrate as an insulating layer may be used. For example, epoxy resin including a filler may be used, but the present invention is not limited thereto.

[0122] The insulator layer may be formed by forming a coating and curing it, or may be formed by laminating an insulator film formed in an uncured or semi-cured state on the core layer 22 and curing it. At this time, if a reduced pressure lamination method or the like is adopted, the insulator is embedded in the space inside the core through hole 23, so that the process can be performed efficiently.

[0123] According to one embodiment, even if multiple insulator layers are stacked for use, it may be substantially difficult to distinguish between the insulator layers, and the multiple insulator layers are collectively referred to as upper insulating layers. In addition, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case, their boundaries may be substantially indistinguishable. Alternatively, according to another embodiment, the boundaries of the insulator layers may be created by setting the pressure and temperature for curing the multiple insulator layers differently.

[0124] The upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a predetermined shape, and can be formed, for example, by a build-up method. Specifically, the conductive layer can be formed by forming an insulator layer, removing unnecessary portions of the insulator layer, and then copper plating. Then, the method of selectively removing unnecessary portions of the conductive layer, forming an insulator layer again on the conductive layer, removing unnecessary portions again, and then forming a conductive layer by plating, etc. can be repeated. Thus, an upper distribution pattern 251 having a conductive layer formed in a vertical or horizontal direction according to a desired pattern can be formed.

[0125] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, and is therefore formed to include a fine pattern in at least a portion thereof, so as to smoothly transmit electrical signals with the semiconductor element portion 30 and fully accommodate the required complex pattern. At this time, the fine pattern refers to a pattern whose width and interval are less than 4 μm, or a pattern whose width and interval are less than 3.5 μm, or a pattern whose width and interval are less than 3 μm, or a pattern whose width and interval are less than 2.5 μm, or a pattern whose width and interval are 1 μm to 2.3 μm (hereinafter, the description of the fine pattern is the same).

[0126] The upper connection layer 27 includes: an upper connection pattern 272 located on the upper insulating layer 253 and at least a portion of which is electrically connected to the upper distribution pattern 251 ; and an upper connection electrode 271 that electrically connects the semiconductor element portion 30 and the upper connection pattern 272 .

[0127] The upper connection pattern 272 may be located on one side of the upper insulating layer 253, or may be embedded in a manner that at least a portion thereof is exposed on the upper insulating layer. For example, in the case where the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and in the case where the upper connection pattern is embedded in a manner that a portion thereof is exposed on the upper insulating layer, after forming a copper plating layer or the like, a portion of the insulating layer or the conductive layer may be removed by surface polishing, surface etching or the like.

[0128] Similar to the upper distribution pattern 251 described above, at least a portion of the upper connection pattern 272 may include a fine pattern. The upper connection pattern 272 including the fine pattern as described above allows more components to be electrically connected even in a narrow area, thereby making the electrical signal connection between components or with the outside smoother and enabling a more integrated package.

[0129] The upper surface connection electrode 271 may be directly connected to the semiconductor element portion 30 through a terminal or the like, or may be connected via an element connection portion 51 such as a solder ball or the like.

[0130] The cavity portion 28 includes a cavity allocation layer 282 located above and / or below the second region 222 and electrically connected to the core allocation pattern 241, and an inner space 281 for disposing the electronic component 40. The cavity allocation layer 282 may be formed by a second region core through hole.

[0131] Specifically, the thickness of the glass core 21 in the second region 222 is thinner than that in the first region 221, and the electronic component 40 can be located in the inner space 281 formed due to the difference in thickness. In addition, the core through hole 23 and the core distribution layer 24 formed in the glass core 21 function as an electrical connection structure connecting the electronic component 40 and external components.

[0132] In addition, as described above, a cavity portion in the form of penetrating the first region 221 (rather than the second region 222 ), ie, penetrating the first surface 213 and the second surface 214 of the glass core 21 may be formed, and the electronic element 40 may be arranged in the cavity portion.

[0133] The package substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 can be directly connected to the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, and the motherboard 10 can be electrically connected via a board connection portion 52 such as a solder ball. In addition, the core distribution pattern 241 connected to the motherboard 10 can be connected to the motherboard 10 via a lower layer (not shown in the figure) located at the lower part of the core layer 22. The element connection portion 51 and the board connection portion 52 are collectively referred to as a connection portion 50.

[0134] According to one example, except for the glass core 21 , the package substrate 20 between the semiconductor element portion 30 and the motherboard 10 may not substantially use an additional substrate.

[0135] In the past, the interposer and the organic substrate were stacked together and used to connect the components to the motherboard. It is understood that this multi-level structure is adopted for at least two reasons: one is that there are scale issues when directly bonding the fine patterns of the components to the motherboard, and the other is that during the bonding process or the driving process of the semiconductor device, the difference in thermal expansion coefficient may cause wiring damage.

[0136] In this embodiment, the above problem is solved by using a glass core having a thermal expansion coefficient similar to that of a semiconductor element and forming a fine pattern having a fine scale enough for mounting the element on the first surface of the glass core and its upper layer.

[0137] A method of manufacturing a package substrate according to an embodiment of the present invention will be described below.

[0138] FIG. 4A to FIG. 4E as well as FIG. 5A to FIG. 5E FIG. 1 is a flow chart illustrating a manufacturing process of a package substrate according to the present embodiment in cross section.

[0139] First, if Figure 4A As shown, a glass core 21a having a flat first surface and a flat second surface is prepared, and a defect (groove 21b) is formed at a predetermined position on the glass surface in order to form a core through hole. The glass core may be a glass core suitable for a substrate of an electronic device, for example, an alkali-free glass core may be used, but is not limited thereto. As a commercial product, products manufactured by manufacturers such as Corning, Schott, and AGC may be used. The defect (groove) may be formed by mechanical etching, laser irradiation, or the like.

[0140] like Figure 4B As shown, an etching step is performed to form a core through hole 23 in the glass core 21a formed with a defect (groove 21b) by a physical or chemical etching process. During the etching process, while a through hole is formed in the defective portion of the glass core, the surface of the glass core 21a may be etched. In order to prevent such etching of the glass surface, a masking film or the like may be used, but considering the cumbersomeness of the process of using and removing the masking film, etc., the glass core itself with the defect may be etched, in which case the thickness of the glass core having the core through hole may be slightly thinner than the thickness of the original glass core.

[0141] Then, if Figure 4C and Figure 4DAs shown, the core layer preparation step may be performed by forming a conductive layer 21d on the glass core. Representatively, the conductive layer may be a metal layer including copper metal, but the present invention is not limited thereto.

[0142] The surface of the glass (including the surface of the glass core and the surface of the core through hole) and the surface of the copper metal have different properties, so the adhesion is poor. In this embodiment, the adhesion between the glass surface and the metal is improved by two methods, a dry method and a wet method.

[0143] The dry method is a method using sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core through hole by metal sputtering. When forming the seed layer, a dissimilar metal such as titanium, chromium, nickel, etc. can be sputtered together with copper, etc. In this case, it is believed that the adhesion between glass and metal is improved by the surface morphology of the glass and the anchoring effect of the interaction of metal particles.

[0144] Wet method is the method for carrying out primer treatment, is the method for forming primer layer 21c by pre-treating with the compound substance with the functional group such as amine etc. According to the required degree of adhesion, after pre-treating with silane coupling agent, primer treatment can be carried out with the compound or particle with amine functional group.As mentioned above, the support substrate of the present embodiment needs to have the high performance of the degree that is enough to form fine pattern, even after primer treatment, also need to keep this state.Therefore, when this primer comprises nanoparticle, it is preferred to use the nanoparticle with average diameter below 150nm, for example, the particle with amine group is preferably used as nanoparticle.For example, the primer layer can be formed by using the bonding force improving agent manufactured by CZ series etc. of MEC company.

[0145] In the seed layer / primer layer 21c, the conductive layer can selectively form a metal layer with or without removing the portion where the conductive layer is not required to be formed. In addition, the seed layer / primer layer 21c selectively processes the portion where the conductive layer is required to be formed or the portion where the conductive layer is not required to be formed into an activated state or an inactivated state for metal plating to carry out subsequent processes. For example, the activation or inactivation treatment can use a light irradiation treatment with a laser having a specified wavelength or a drug treatment. When forming the metal layer, a copper plating method suitable for manufacturing semiconductor elements can be used, but the present invention is not limited to this.

[0146] like Figure 4E As shown, when a portion of the core distribution layer is not needed, it can be removed, or after partially removing or inactivating the seed layer, metal plating is performed to form a conductive layer in a predetermined pattern, thereby forming an etching layer 21e of the core distribution layer.

[0147] FIG. 5A to FIG. 5EA preparation step of forming an insulating layer and an upper distribution pattern according to an embodiment is described.

[0148] like Figure 5A As shown, after forming the core distribution layer as the conductive layer, the core through hole may be subjected to an insulating layer forming step of filling the empty space with an insulating layer. At this time, the insulating layer used may be an insulating layer prepared in the form of a film, for example, a method of reducing pressure laminating an insulating layer in the form of a film, etc. When reducing pressure lamination is performed in this way, the insulating layer is fully embedded in the empty space inside the core through hole to form a core insulating layer without void formation.

[0149] FIG. 5B to FIG. 5E The steps for preparing the upper layer are described.

[0150] The upper layer preparation step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming the insulating layer 23a or by stacking insulating films. Simply, it is preferred to stack insulating films. The stacking of insulating films can be performed by laminating insulating films and curing. At this time, if a reduced pressure lamination method is adopted, the insulating resin can be fully embedded in a layer in which no conductive layer is formed inside the core through hole, etc. At least a portion of the upper insulating layer is also in direct contact with the glass core, so a layer with sufficient adhesion is used. Specifically, the glass core and the upper insulating layer preferably have a property that meets 4B or above according to the adhesion test value of ASTM D3359.

[0151] The upper distribution pattern can be formed by repeatedly forming the insulating layer 23a, forming the conductive layer 23c in a predetermined pattern, and etching unnecessary parts to form an etching layer 23d of the conductive layer. The conductive layers formed adjacent to each other through the insulating layer are formed by performing a plating process after forming blind holes 23b in the insulating layer. The blind holes can be formed by dry etching methods such as laser etching and plasma etching, wet etching methods using a mask layer and an etching solution, etc.

[0152] Thereafter, although not shown in the drawings, an upper connection layer and a capping layer may be formed.

[0153] The upper connection pattern and the upper connection electrode can also be formed by a process similar to the process of forming the upper distribution layer. Specifically, it can be formed by forming an etching layer of an insulating layer on the insulating layer 23e, forming a conductive layer thereon again, and then forming an etching layer of the conductive layer. In addition, a method of selectively forming only the conductive layer without using an etching method can also be adopted. An opening portion (not shown in the figure) is formed at a position of the cover layer corresponding to the upper connection electrode, and can be formed so that the upper connection electrode is exposed and directly connected to the element connection portion or the terminal of the element.

[0154] After the upper layer is generated, the process of forming the lower layer by forming the lower connection layer and the cap layer can be carried out. The lower distribution layer and / or the lower connection layer can be formed in a manner similar to the upper connection layer and the cap layer formation steps described above, and optionally, a cap layer (not shown in the figure) can also be formed.

[0155] On the other hand, as described above, the core layer may include a glass core, and the glass core may be a glass substrate having a first surface and a second surface opposite to each other. In addition, as described above, the encapsulation substrate may include a distribution layer located above and / or below the core layer.

[0156] In the packaging substrate, the upper layer may be located on the upper part of the core layer, and the upper layer may include a plurality of distribution layers. In addition, optionally, in the packaging substrate, the lower layer may be located on the lower part of the core layer, and the lower layer may include a plurality of distribution layers. The plurality of distribution layers may be more than 2 layers, more than 3 layers, more than 4 layers, more than 5 layers, or more than 6 layers. In addition, the plurality of distribution layers may be less than 30 layers, less than 26 layers, less than 22 layers, less than 18 layers, or less than 15 layers. However, the total number of distribution layers provided in the upper layer or the lower layer is not limited thereto.

[0157] The distribution layer may be formed by disposing an insulating film above or below the core layer and curing it. Exemplarily, the insulating film may include inorganic particles such as Ajinomoto Build-up Film (ABF) and a polymer resin. Exemplarily, the distribution layer may be formed by disposing an insulating material such as an insulating film above or below the core layer and a conductive pattern patterned with copper or the like.

[0158] The distribution layer may be configured as a structure in which multiple layers are stacked according to the design of a redistributed layer (RDL). When the distribution layer is stacked without a conductive pattern, the first insulating layer is regarded as the distribution layer. In addition, when the distribution layer includes a conductive pattern and is stacked, the conductive pattern layer and the insulating layer are stacked based on the conductive pattern (or metal layer) and the pad, and the layers are regarded as the distribution layer.

[0159] The package substrate generally includes a plurality of distribution layers. At this time, multiple heat treatments are performed to cure (pre-cure) the insulating film. During this process, problems such as warpage of the glass core bending or strong stress concentration on the core layer may occur. The inventors have noticed that one of the reasons for these phenomena is the difference in the coefficient of thermal expansion (CTE) between the insulating film and the glass core.

[0160] In order to solve the problem of cracks or breakage of the glass core during the manufacturing process and the problem of delamination between the core layer and the distribution layer, the following embodiments are proposed.

[0161] FIG. 6A to FIG. 6C FIG. 1 is a schematic diagram illustrating in cross section the problems occurring during a heat treatment of a package substrate including a core layer and a plurality of distribution layers.

[0162] Reference Fig. 6A , the package substrate may include a plurality of distribution layers located on the core layer. For example, the package substrate may include an upper layer located on the core layer. The upper layer may include a first distribution layer 61. The upper layer may include a first distribution layer 61 and a second distribution layer 62 disposed on the first distribution layer 61.

[0163] For example, the first distribution layer 61 may be formed by disposing a first insulating material on a core layer and curing it, and the second distribution layer 62 may be formed by disposing a second insulating material on the first distribution layer 61 and curing it.

[0164] Alternatively, for example, the insulating layer may be formed by placing the first insulating material on the core layer and curing it, removing the insulating layer of the portion where the conductive pattern is to be formed, and then filling the portion where the insulating layer is removed by plating with a metal such as copper to form the first conductive pattern. As above, the first distribution layer 61 including the first insulating material and the first conductive pattern may be formed.

[0165] The second distribution layer 62 may be formed by disposing and curing a second insulating material on the first distribution layer 61. Alternatively, the second distribution layer 62 including a second insulating material and a second conductive pattern may be formed on the first distribution layer 61.

[0166] The heat treatment process may be performed several times in the manufacturing process of curing the first distribution layer 61 and the second distribution layer 62, etc. For example, the temperature of the substrate is increased / maintained / lowered to about 60°C or above or 80°C or above, and the process may be repeated. In addition to the stress caused by heat itself, various stresses are applied to the substrate, such as stress caused by the difference in thermal expansion coefficients between the distribution layer and the core layer, and stress applied to the substrate by reducing its volume while inducing chemical bonding of an insulating material including a polymer resin, etc. For example, in the case of a glass core using an amorphous glass plate as a support, problems of core layer damage such as delamination of the boundary between the glass core and the upper layer or cracks in the glass core may occur.

[0167] In addition, refer to Figure 6B, the package substrate may include a plurality of distribution layers below the core layer. For example, the package substrate may include a lower layer below the core layer, and the lower layer may include a third distribution layer 63 and a fourth distribution layer 64. As with the first distribution layer 61 and the second distribution layer 62 described above, the third distribution layer 63 and the fourth distribution layer 64 may each include an insulating material or an insulating material and a conductive pattern. As described above, damage to the core layer may also occur during the manufacturing process of the lower layer.

[0168] In addition, refer to Figure 6C The package substrate includes an upper layer located above the core layer and a lower layer located below the core layer, the upper layer may include a first distribution layer 61 and a second distribution layer 62, and the lower layer may include a third distribution layer 63 and a fourth distribution layer 64. Each distribution layer may include an insulating material. In addition, each distribution layer may optionally include both an insulating material and a conductive pattern.

[0169] The manufacturing process of each distribution layer includes a multi-stage process such as heat treatment. During this process, as mentioned above, various stresses may be applied to the core layer. When the upper layer and the lower layer are formed on both sides of the core layer, the core layer may be damaged. For example, delamination occurs at the boundary between the glass core and the upper layer, or cracks appear on the glass core.

[0170] Therefore, the present specification proposes embodiments for solving problems such as warpage and stress caused by the difference in thermal expansion coefficients of the core layer and the distribution layer.

[0171] As an example, an embodiment can be proposed in which a dummy layer is added to the upper layer and / or the lower layer to disperse the stress accumulated due to temperature change, etc. For example, the dummy layer can be a layer that shrinks less than the first distribution layer or the third distribution layer under temperature change.

[0172] The dummy layer includes a material having a thermal expansion coefficient lower than that of the insulating material of the first distribution layer. Alternatively, the dummy layer includes a material having a thermal expansion coefficient lower than that of the insulating material of the third distribution layer.

[0173] 7A to 7C The schematic diagrams are cross-sectional views respectively illustrating a heat treatment process of a package substrate including a dummy layer formed between distribution layers according to each embodiment. As an embodiment, the present specification proposes a solution of constructing a dummy layer between distribution layers that shrinks less with temperature changes.

[0174] In one or more embodiments, Fig. 7A and Figure 7BThe example of directly setting the first distribution layer on the core layer and directly setting the virtual layer thereon is given, but an additional layer (e.g., distribution layer) may be set between the core layer and the first distribution layer and / or between the first distribution layer and the virtual layer. In addition, in an embodiment, an additional layer (e.g., distribution layer) may be set between the virtual layer and the second distribution layer and / or on the second distribution layer.

[0175] Additionally, in one or more embodiments, Figure 7B and Figure 7C The example shows that the third distribution layer is directly disposed below the core layer and the virtual layer is directly disposed below the third distribution layer, but an additional layer (e.g., a distribution layer) may be disposed between the core layer and the third distribution layer and / or between the third distribution layer and the virtual layer. In addition, in an embodiment, an additional layer (e.g., a distribution layer) may be disposed between the virtual layer and the fourth distribution layer and / or below the fourth distribution layer.

[0176] Reference Fig. 7A The package substrate includes a core layer and an upper layer located on the core layer. The core layer may include a glass core including a first surface and a second surface opposite to each other. Although not shown, the core layer may have Figures 1 to 5E The core through hole, cavity, core insulating layer, core distribution pattern, etc. shown in FIG. In addition, although not shown in the figure, a cap layer, a connection electrode, etc. may be arranged above the upper layer, below the lower layer, etc. (hereinafter, the same applies to Figure 7B and Figure 7C for example).

[0177] The upper layer includes a first distribution layer 61 formed on the core layer, a dummy layer 70 formed on the first distribution layer 61, and a second distribution layer 62 formed on the dummy layer 70. A fine distribution layer (not shown) may be further included on the second distribution layer 62.

[0178] Compared with the thickness of the conductive pattern provided on the second distribution layer 62 , the conductive pattern may be provided on the fine distribution layer with a thinner thickness.

[0179] In addition, when inorganic particles are applied to the second distribution layer 62 and the fine distribution layer, respectively, the average size of the inorganic particles (inorganic particles B) of the fine distribution layer is different from the average size of the inorganic particles (inorganic particles A) of the second distribution layer 62. Specifically, the average size of the inorganic particles A may be smaller than the average size of the inorganic particles B. In this case, the setting of the fine distribution pattern may be more facilitated.

[0180] The dummy layer 70 may be located between the first distribution layer 61 and the second distribution layer 62 and directly contact the first distribution layer 61 .

[0181] The dummy layer 70 may include a material with a thermal expansion coefficient lower than a thermal expansion coefficient of the insulating material of the first distribution layer 61 .

[0182] The dummy layer 70 may include a material with a thermal expansion coefficient lower than that of the insulating material of the first distribution layer 61 and the second distribution layer 62 .

[0183] The thermal expansion coefficient of the dummy layer 70 may be smaller than the thermal expansion coefficient of the first insulating material of the first distribution layer.

[0184] When the difference (absolute value) between the thermal expansion coefficient of the glass core and the thermal expansion coefficient of the first distribution layer is defined as D_C, and the difference (absolute value) between the thermal expansion coefficient of the first distribution layer and the thermal expansion coefficient of the virtual layer is defined as D_D, D_D may be smaller than D_C.

[0185] The dummy layer can substantially suppress damage to the core layer due to stress during a manufacturing process of the package substrate such as heat treatment and during a driving process of a device with components mounted on the package substrate accompanied by heat generation.

[0186] The thermal expansion coefficient of the virtual layer may be 20 ppm / °C or less. The thermal expansion coefficient of the virtual layer may be 20 ppm / °C or less, 18 ppm / °C or less, 16 ppm / °C or less, 14 ppm / °C or less, 12 ppm / °C or less, or 10 ppm / °C or less. The thermal expansion coefficient of the virtual layer may be 3 ppm / °C or more, 5 ppm / °C or more, or 8 ppm / °C or more.

[0187] The thickness of the dummy layer 70 may be thinner than that of the first distribution layer.

[0188] The difference between the thickness of the dummy layer 70 and the thickness of the first distribution layer may be 5 μm or more, 7 μm or more, 10 μm or more, 13 μm or more, or 15 μm or less, and the difference may be 20 μm or less, or 17 μm or less.

[0189] The inorganic content of the virtual layer 70 may be 80 wt % or more, 85 wt % or more, 90 wt % or more, 95 wt % or more, 97 wt % or more, or 99 wt % or more. The inorganic content of the virtual layer may be 100 wt % or less.

[0190] The dummy layer 70 may include an inorganic layer.

[0191] The virtual layer 70 may be an inorganic layer.

[0192] The inorganic layer may include polysilicon, SiO2 and / or a metal layer.

[0193] The inorganic layer may be composed of polysilicon, SiO2 and / or a metal layer.

[0194] The metal layer may be a metal plating layer. The metal layer may include copper. A metal layer including copper may be used as the dummy layer.

[0195] When the dummy layer includes a layer having a conductive property, the layer is not connected to the conductive layer and the electrode (through electrode) of the allocation layer.

[0196] For example, after forming the first distribution layer 61 on the core layer and forming the dummy layer 70 on the first distribution layer 61, the second distribution layer 62 may be formed on the dummy layer 70. Since the formation process of the first distribution layer 61 and the second distribution layer 62 is repeated as described above, detailed description is omitted.

[0197] like Fig. 7A In the embodiment shown, when a virtual layer 70 is formed between the distribution layers, even if multiple thermal processes are performed, the shrinkage / expansion degree of the distribution layer located between the virtual layer 70 and the core layer can be reduced during the manufacturing or driving process of the packaging substrate because the virtual layer 70 has a negligible shrinkage degree with temperature changes.

[0198] For example, Fig. 7A As shown, if solidification shrinkage occurs after solidification of the first distribution layer, stress may be applied to the glass core disposed adjacently. In one embodiment, a virtual layer whose shrinkage is negligible compared to the shrinkage of the first distribution layer and whose volume change with temperature is small is provided to disperse the stress applied to the core layer due to solidification shrinkage of the first distribution layer, so as to prevent cracks and damage to the core layer.

[0199] In other words, the present embodiment can achieve the effect of dispersing the stress concentrated in the core layer. As a result, the effect of preventing cracks and damage to the core layer caused by peeling between the distribution layer and the core layer or warping of the distribution layer can be obtained.

[0200] Optionally, when the dummy layer 70 is made of a metal layer with high thermal conductivity, the heat generated by the packaging substrate can also be dissipated.

[0201] On the other hand, the dummy layer 70 may be disposed to face the glass core via the first distribution layer.

[0202] Exemplarily, the virtual layer 70 may be arranged to correspond to the front surface of the glass core. Exemplarily, the virtual layer 70 may be arranged in an area other than a portion toward the inner side of the edge of the glass core (not shown in the figure). That is, the virtual layer 70 may be arranged to correspond to an area smaller than the front surface of the glass core. Exemplarily, the virtual layer 70 may be arranged in an area other than a virtual area (not shown in the figure). When the core layer (or encapsulation substrate) is observed from above, a plurality of unit encapsulation substrates may be arranged. The virtual area refers to an area on the core layer other than a portion where a unit encapsulation substrate is arranged.

[0203] like Fig. 7A As shown, one virtual layer can be set in the upper layer. In addition, more than two virtual layers can be set in the upper layer as needed. The number or range of use of the virtual layers can be adjusted according to possible locations.

[0204] Or, refer to Figure 7B The package substrate may include a core layer and a lower layer located below the core layer. Since the specific description of the core layer and the like is repeated with the above description, the detailed description thereof will be omitted.

[0205] The lower layer may include: a third distribution layer 63 formed below the core layer; a dummy layer 70 formed below the third distribution layer 63 ; and a fourth distribution layer 64 formed below the dummy layer 70 .

[0206] The dummy layer 70 may be located between the third distribution layer 63 and the fourth distribution layer 64 and directly contact the third distribution layer 63 .

[0207] The dummy layer 70 may include a material having a thermal expansion coefficient lower than that of the insulating material of the third distribution layer 63 .

[0208] The thermal expansion coefficient of the dummy layer 70 may be smaller than the thermal expansion coefficient of the third insulating material of the third distribution layer.

[0209] When the difference (absolute value) between the thermal expansion coefficient of the glass core and the thermal expansion coefficient of the third distribution layer is defined as D_C, and the difference (absolute value) between the thermal expansion coefficient of the third distribution layer and the thermal expansion coefficient of the virtual layer is defined as D_D, D_D can be smaller than D_C.

[0210] Since the specific description of the virtual layer overlaps with the above description, its detailed description will be omitted.

[0211] For example, the third distribution layer 63 may be formed by disposing and curing the third distribution layer 63 under the core layer. Thereafter, the dummy layer 70 may be formed under the third distribution layer 63, and the fourth distribution layer 64 may be formed by disposing and curing the fourth distribution layer 64 under the dummy layer 70.

[0212] For example, after forming the third distribution layer 63 under the core layer and forming the dummy layer 70 under the third distribution layer 63, the fourth distribution layer 64 may be formed under the dummy layer 70. Since the formation process of the third distribution layer 63 and the fourth distribution layer 64 is repeated in the above description, the detailed description thereof is omitted.

[0213] If Figure 7B The embodiment shown forms a dummy layer 70 between the distribution layers, which can substantially suppress damage to the core layer. In addition, if the dummy layer 70 selectively uses a metal layer with high thermal conductivity, the heat generated by the package substrate can also be dissipated.

[0214] On the other hand, the dummy layer 70 can be arranged to face the glass core through the third distribution layer. The detailed description such as the area where the dummy layer is arranged and the application of one or more dummy layers to the lower layer corresponds to the description of the dummy layer arranged in the upper layer described above, so the detailed description is omitted.

[0215] The thickness of the dummy layer 70 may be thinner than that of the third distribution layer.

[0216] The difference between the thickness of the dummy layer 70 and the thickness of the third distribution layer may be 5 μm or more, 7 μm or more, 10 μm or more, 13 μm or more, or 15 μm or more, and may be 20 μm or less or 17 μm or less.

[0217] The virtual layer 70 may include an inorganic layer. Since the description of the composition, structure, etc. of the virtual layer overlaps with the above description, the detailed description thereof will be omitted.

[0218] Or, refer to Figure 7C, the encapsulation substrate may include a core layer, an upper layer located on the core layer, and a lower layer located below the core layer. The core layer may include a glass core having a first surface and a second surface opposite to each other, the upper layer may include a first distribution layer 61 formed on the core layer, a virtual layer 70 formed on the first distribution layer 61, and a second distribution layer 62 formed on the virtual layer 70, and the lower layer may include a third distribution layer 63 formed below the core layer, a virtual layer 70 of the lower layer formed below the third distribution layer 63, and a fourth distribution layer 64 formed below the virtual layer 70 of the lower layer. A fine distribution layer (not shown in the figure) may also be included on the second distribution layer 62. Since the specific description of the fine distribution layer is repeated in the above description, its detailed description will be omitted.

[0219] The upper layer of the package substrate may include a dummy layer 70 between the first distribution layer 61 and the second distribution layer 62 , and the lower layer of the package substrate may include a dummy layer 70 between the third distribution layer 63 and the fourth distribution layer 64 .

[0220] The upper virtual layer 70 may directly contact the first distribution layer 61, and the lower virtual layer 70 may directly contact the third distribution layer 63. In this case, by respectively arranging the glass core and the virtual layer on both sides of the first distribution layer (or the third distribution layer), the stress applied to the boundary of the glass core or the upper layer (or the lower layer) can be relieved by the first distribution layer (or the third distribution layer), etc., and the occurrence of defects of the packaging substrate can be reduced.

[0221] The specific description of the virtual layer is the same as the above description.

[0222] For example, in a package substrate according to an embodiment, as an upper layer, a distribution layer A, a distribution layer B, a virtual layer 70, a distribution layer C, and a distribution layer D can be sequentially arranged on the core layer 22. In this case, the distribution layer B can be regarded as the first distribution layer 61, and the distribution layer C can be regarded as the second distribution layer 62. The distribution layer D can be a fine distribution layer. In addition, in the package substrate, as a lower layer, a distribution layer E, a distribution layer F, a solder resist, and a bump layer can be sequentially arranged below the core layer 22.

[0223] For example, in a package substrate according to an embodiment, as upper layers, a distribution layer A, a virtual layer 70, a distribution layer B, and a distribution layer C are sequentially arranged above the core layer 22. At this time, the distribution layer A can be regarded as the first distribution layer 61, and the distribution layer B can be regarded as the second distribution layer 62. The distribution layer C can be a fine distribution layer. In addition, in the package substrate, as lower layers, a distribution layer E, a distribution layer F, a solder resist, and a bump layer can be sequentially arranged below the core layer 22. The distribution layer E can be regarded as the third distribution layer 63, and the distribution layer F can be regarded as the fourth distribution layer 64.

[0224] For example, in a package substrate according to an embodiment, as an upper layer, a distribution layer A, a virtual layer, a distribution layer B, and a distribution layer C may be sequentially arranged above the core layer 22. In this case, the distribution layer A may be regarded as a first distribution layer 61, and the distribution layer B may be regarded as a second distribution layer 62. The distribution layer C may be a fine distribution layer. In addition, in the package substrate, as a lower layer, a distribution layer E, a virtual layer 70, a distribution layer F, a solder resist, and a bump layer may be sequentially arranged below the core layer 22. The distribution layer E may be regarded as a third distribution layer 63, and the distribution layer F may be regarded as a fourth distribution layer 64.

[0225] In addition, this specification proposes a method for manufacturing a package substrate according to the present embodiment. For example, the method for manufacturing a package substrate according to the embodiment of this specification is as follows.

[0226] For example, the core layer 22 including the glass core 21 may be prepared. As described above, the core layer 22 may include the glass core 21 having the first surface and the second surface opposite to each other.

[0227] Thereafter, an insulating material may be disposed on the core layer 22 and cured to form a first distribution layer 61. The first distribution layer 61 may include an insulating material.

[0228] Exemplarily, the insulating material may be a polymer resin, a mixed material of a polymer resin and a filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.), etc. Exemplarily, the polymer resin may be an acrylic resin, an epoxy resin or a modified resin thereof, etc., and a material applicable to electronic devices for the purpose of molding, etc. may be used. For example, a liquid crystal polymer (LCP) may be used.

[0229] Exemplarily, the mixed material may be a mixture of acrylic resin and filler, a mixture of acrylic resin and epoxy resin and filler, a mixture of epoxy resin and filler, etc. The filler may be inorganic particles, for example, silica particles. As a commercial product, Ajinomoto built-up film (ABF), epoxy molding compound (EMC), etc. may be used, but the present invention is not limited thereto.

[0230] In addition, when the first distribution layer 61 includes both the first insulating material and the first conductive pattern, a process of forming a redistribution layer may be adopted. Exemplarily, after the first insulating material is disposed on the core layer 22 and cured, a portion of the first insulating material is removed in consideration of the form of the first conductive pattern, and then the first conductive pattern is formed by a method such as plating to form the first distribution layer.

[0231] Next, a dummy layer 70 may be formed on the first distribution layer 61. For example, the dummy layer 70 may be made of the above-mentioned materials.

[0232] When the virtual layer is a metal layer, methods such as metal plating and metal deposition can be used. When the virtual layer is an inorganic layer, methods such as sputtering and deposition can be used.

[0233] Next, the insulating material may be disposed on the dummy layer 70 and cured to form the second distribution layer 62. The manufacturing process of the second distribution layer may be similar to the manufacturing process of the first distribution layer.

[0234] The first insulating material and the second insulating material may have the same thermal expansion coefficient as each other. In this case, process efficiency can be further improved.

[0235] The first insulating material and the second insulating material may have different thermal expansion coefficients. In this case, different materials refer to materials containing different components or materials containing the same components but having different physical properties due to different contents.

[0236] The manufacturing method of the packaging substrate may further include the following steps: arranging the third insulating material and the third conductive pattern below the core layer to form a third distribution layer; forming a lower dummy layer below the third distribution layer; and arranging a fourth insulating material and a fourth conductive pattern below the lower dummy layer to form a fourth distribution layer.

[0237] Since the manufacturing process of the third distribution layer, the dummy layer, and the fourth distribution layer corresponds to the manufacturing process of the first distribution layer, the dummy layer, and the second distribution layer described above, a detailed description is omitted.

[0238] In the method for manufacturing the package substrate, the upper layer may be manufactured in the order of the first distribution layer, the dummy layer, and the second distribution layer.

[0239] In the method for manufacturing the package substrate, the lower layer may be manufactured in the order of the third distribution layer, the dummy layer, and the fourth distribution layer.

[0240] In the method for manufacturing the package substrate, the upper layer and the lower layer may be manufactured in the order of a first distribution layer, a third distribution layer, a dummy layer (an upper dummy layer and a lower dummy layer), a second distribution layer, and a fourth distribution layer.

[0241] The manufacturing method of the packaging substrate according to the embodiment described above and the packaging substrate using the same can achieve the following effect: by arranging a virtual layer without curing shrinkage between the distribution layers, the curing shrinkage of the distribution layer between the virtual layer and the core layer is alleviated, thereby dispersing the stress concentrated on the core layer.

[0242] Furthermore, due to the dummy layer formed between the distribution layers, it is possible to prevent peeling between the distribution layer and the core layer or cracking and breakage of the core layer due to warping of the distribution layer, which may occur during the heat treatment process.

[0243] Above, this specification is described with reference to the embodiments illustrated in the accompanying drawings, but this is only an example. As long as a person skilled in the art will understand, various modifications and equivalent other embodiments can be derived from this. In other words, the scope of this specification is not limited to the above-mentioned embodiments, but various changes or modifications of the basic concepts of the embodiments defined in the attached claims by those skilled in the art belong to the scope of the embodiments. Therefore, the true technical protection scope of this specification should be determined according to the technical ideas of the attached claims.

Claims

1. A packaging substrate, wherein: include: Core layer; as well as an upper layer located on the core layer, The core layer includes a glass core, the glass core includes a first surface and a second surface opposite to each other, The upper layer comprises: a first distribution layer formed on the core layer; as well as a virtual layer formed on the first distribution layer, The dummy layer includes a material with a lower thermal expansion coefficient than a thermal expansion coefficient of an insulating material of the first distribution layer.

2. The packaging substrate according to claim 1, wherein: The upper layer further includes a second distribution layer formed on the dummy layer, The dummy layer is located between the first distribution layer and the second distribution layer and is in direct contact with the first distribution layer.

3. The packaging substrate according to claim 1, wherein: When the absolute value of the difference between the thermal expansion coefficient of the glass core and the thermal expansion coefficient of the first distribution layer is defined as D_C and the absolute value of the difference between the thermal expansion coefficient of the first distribution layer and the thermal expansion coefficient of the dummy layer is defined as D_D, D_D is smaller than D_C.

4. The packaging substrate according to claim 1, wherein: The virtual layer includes more than 80% by weight of inorganic matter.

5. The packaging substrate according to claim 1, wherein: The thermal expansion coefficient of the dummy layer is less than 20 ppm / °C.

6. The packaging substrate according to claim 1, wherein: The upper layer further includes a second distribution layer formed on the dummy layer and a fine distribution layer formed on the second distribution layer. The second distribution layer comprises a polymer resin A and inorganic particles A, The fine distribution layer includes a polymer resin B and inorganic particles B, The average size of the inorganic particles A is smaller than the average size of the inorganic particles B.

7. A method for manufacturing a packaging substrate, wherein: The steps include: preparing a core layer including a glass core; disposing a first insulating material, a first conductive pattern, or a combination thereof on the core layer to form a first distribution layer; and forming a dummy layer on the first distribution layer, The dummy layer includes a material with a thermal expansion coefficient lower than a thermal expansion coefficient of the first insulating material.

8. The method for manufacturing a packaging substrate according to claim 7, wherein: The method further comprises the following steps: providing a second insulating material, a second conductive pattern or a combination thereof on the virtual layer to form a second distribution layer, The thermal expansion coefficient of the dummy layer is smaller than the thermal expansion coefficient of the second insulating material.

9. The method for manufacturing a packaging substrate according to claim 7, wherein: The method further comprises the following steps: providing a third insulating material and a third conductive pattern below the core layer to form a third distribution layer, The dummy layer includes a material having a thermal expansion coefficient lower than a thermal expansion coefficient of the third insulating material.

10. The method for manufacturing a packaging substrate according to claim 7, wherein: The following steps are also included: Disposing a third insulating material and a third conductive pattern below the core layer to form a third distribution layer; forming a lower dummy layer below the third distribution layer; as well as A fourth insulating material and a fourth conductive pattern are disposed below the lower dummy layer to form a fourth distribution layer.

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