Semiconductor device, method for manufacturing the same, and method for determining offset of semiconductor device

Abstract

Embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and a method for determining the offset of a semiconductor device; the semiconductor device includes a first semiconductor structure in which a first alignment mark is provided; a second semiconductor structure stacked with the first semiconductor structure in a first direction; a second alignment mark is provided in the second semiconductor structure; the relative position of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; both the first alignment mark and the second alignment mark include a first image, a second image, a third image, and a fourth image; the second image is located on at least one side of the first image in a second direction; the third image is located on at least one side of the first image in a third direction; the fourth image is located on at least one side of the first image in a fourth direction; thus, the alignment efficiency and alignment accuracy of the first and second semiconductor structures can be improved, as well as the reliability and yield of the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor device, a manufacturing method thereof, and a method for determining the offset of a semiconductor device. Background Art

[0002] With the increasing demand for efficiency in big data analysis and miniaturization in fields such as the Internet of Things (IoT), artificial intelligence (AI), and three-dimensional imaging (3D), the bonding method of chips plays a crucial role in semiconductor manufacturing. Hybrid bonding has higher interconnect density and interconnect accuracy compared to flip-chip bonding, wire bonding, etc., and is widely used in the semiconductor field. Hybrid bonding can achieve an interconnect pitch of less than 10 micrometers (um). After directly interconnecting the metals between chips, it can reduce parasitic capacitance and resistance. At the same time, direct bonding allows for better heat dissipation, can eliminate solder bumps, and reduce the thermal stress of the interconnecting metals.

[0003] However, under the requirements of high-density and high-precision technologies, how to determine the alignment between chips has become an urgent problem to be solved. Summary of the Invention

[0004] In view of this, to solve one or more of the existing technical problems, an embodiment of the present disclosure provides a semiconductor device, including: a first semiconductor structure; a first alignment mark is provided in the first semiconductor structure; a second semiconductor structure, stacked with the first semiconductor structure in a first direction; a second alignment mark is provided in the second semiconductor structure; the relative position of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; wherein, both the first alignment mark and the second alignment mark include a first image, a second image, a third image, and a fourth image; the second image is located on at least one side of the first image in a second direction; the third image is located on at least one side of the first image in a third direction; the fourth image is located on at least one side of the first image in a fourth direction; the first direction, the second direction, and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects both the second direction and the third direction.

[0005] In some embodiments, the outer boundary size of the first image in the third direction of the first alignment mark is the same as the outer boundary size of the second image in the third direction of the first alignment mark; the outer boundary size of the first image in the second direction of the first alignment mark is the same as the outer boundary size of the third image in the second direction of the first alignment mark.

[0006] In some embodiments, the outer boundary dimension of the second image in the first alignment mark in the third direction is the same as the outer boundary dimension of the second image in the second alignment mark in the third direction; the outer boundary dimension of the third image in the first alignment mark in the second direction is the same as the outer boundary dimension of the third image in the second alignment mark in the second direction.

[0007] In some embodiments, the first image includes a circular shape, an annular shape, a square shape, a matrix pattern, or a cross-shaped pattern; the second image includes a plurality of elongated patterns arranged uniformly in the third direction; the third image includes a plurality of elongated patterns arranged uniformly in the second direction; the fourth image includes an elongated pattern extending in the fourth direction, and / or a plurality of circular patterns arranged linearly or in an arc uniformly in a direction perpendicular to the fourth direction.

[0008] In some embodiments, the number of elongated patterns in the second image of the first alignment mark is the same as the number of elongated patterns in the second image of the second alignment mark; and / or the number of elongated patterns in the third image of the first alignment mark is the same as the number of elongated patterns in the third image of the second alignment mark.

[0009] In some embodiments, the plurality of elongated patterns in the second image and / or the third image have different dimensions in their extending directions.

[0010] In some embodiments, among the plurality of elongated patterns of the second image or the third image, a part of the elongated patterns have a first dimension in their extending directions, and another part of the elongated patterns have a second dimension in their extending directions; wherein, the elongated patterns having the first dimension and the elongated patterns having the second dimension are arranged alternately at intervals.

[0011] In some embodiments, the first image in the first alignment mark and the first image in the second alignment mark overlap at least partially in the first direction.

[0012] In some embodiments, when the first alignment mark and the second alignment mark overlap completely in the first direction, the plurality of elongated patterns in the second image of the first alignment mark are aligned one by one with the plurality of elongated patterns in the second image of the second alignment mark in the second direction; and the plurality of elongated patterns in the third image of the first alignment mark are aligned one by one with the plurality of elongated patterns in the third image of the second alignment mark in the third direction.

[0013] An embodiment of the present disclosure also provides a method for determining the offset of a semiconductor device. The semiconductor device is the semiconductor device described in the above embodiments of the present disclosure. The determination method includes: obtaining a layer image of the semiconductor device on a first plane; the layer image includes a first alignment mark and a second alignment mark; the semiconductor device includes a first semiconductor structure and a second semiconductor structure stacked in a first direction. The first alignment mark is disposed in the first semiconductor structure, and the second alignment mark is disposed in the second semiconductor structure; the first plane is perpendicular to the first direction; determining the offset between the first semiconductor structure and the second semiconductor structure through the relative positions of the first alignment mark and the second alignment mark; wherein, both the first alignment mark and the second alignment mark include a first image, a second image, a third image, and a fourth image; the second image is located on at least one side of the first image in a second direction; the third image is located on at least one side of the first image in a third direction; the fourth image is located on at least one side of the first image in a fourth direction; the first direction, the second direction, and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects both the second direction and the third direction.

[0014] In some embodiments, the determining the offset between the first semiconductor structure and the second semiconductor structure through the relative positions of the first alignment mark and the second alignment mark includes: determining the offset between the first semiconductor structure and the second semiconductor structure in the third direction through the relative positions of the second images of the first alignment mark and the second alignment mark; determining the offset between the first semiconductor structure and the second semiconductor structure in the second direction through the relative positions of the third images of the first alignment mark and the second alignment mark; determining the rotational offset of the first semiconductor structure and the second semiconductor structure in the first plane in the clockwise / counterclockwise direction through the relative positions of the fourth images of the first alignment mark and the second alignment mark.

[0015] An embodiment of the present disclosure also provides a method for manufacturing a semiconductor device, the method comprising: forming a first semiconductor structure; a first alignment mark is provided in the first semiconductor structure; forming a second semiconductor structure; a second alignment mark is provided in the second semiconductor structure; bonding the first semiconductor structure and the second semiconductor structure in a first direction; wherein, the relative positions of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; both the first alignment mark and the second alignment mark include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in a second direction; the third image is located on at least one side of the first image in a third direction; the fourth image is located on at least one side of the first image in a fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects both the second direction and the third direction.

[0016] In an embodiment of the present disclosure, by providing a first alignment mark in the first semiconductor structure and a second alignment mark in the second semiconductor structure, and both the first alignment mark and the second alignment mark include a first image, a second image, a third image and a fourth image; after stacking and bonding the first semiconductor structure and the second semiconductor structure, the offset between the first semiconductor structure and the second semiconductor structure in multiple orientations is determined by the alignment of the first image, the second image, the third image and the fourth image in the first alignment mark with the first image, the second image, the third image and the fourth image in the second alignment mark. In this way, on the one hand, the offset between the first semiconductor structure and the second semiconductor structure can be directly determined by manual visual inspection without additional equipment, improving the alignment efficiency; on the other hand, through the alignment results of multiple groups of images, the specific misaligned positions can be more accurately reflected, and the alignment accuracy can be improved by comparing the alignment results of multiple groups. Thus, the reliability and yield of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the alignment of four groups of alignment marks in the related art provided by the present disclosure;

[0018] Figure 2 Schematic diagram of the first semiconductor structure and the second semiconductor structure provided by an embodiment of the present disclosure;

[0019] Figure 3 Schematic diagram of the first alignment mark provided by an embodiment of the present disclosure;

[0020] Figure 4 Schematic diagram of the first alignment mark provided by another embodiment of the present disclosure;

[0021] Figure 5 Schematic diagram of the second alignment mark provided by an embodiment of the present disclosure;

[0022] Figure 6 Schematic diagram of the second alignment mark provided by another embodiment of the present disclosure;

[0023] Figure 7 Schematic diagram of the specific shapes of three first alignment marks provided by an embodiment of the present disclosure;

[0024] Figure 8 Schematic diagram of the specific shapes of three second alignment marks provided by an embodiment of the present disclosure;

[0025] Figure 9 Schematic diagram of the complete alignment of three groups of first alignment marks and second alignment marks provided by an embodiment of the present disclosure;

[0026] Figure 10 Schematic diagram of the offset of three groups of first alignment marks and second alignment marks provided by an embodiment of the present disclosure;

[0027] Figure 11 Schematic diagram of the flow of the method for determining the offset of a semiconductor device provided by an embodiment of the present disclosure;

[0028] Figure 12 Schematic diagram of the manufacturing method flow of a semiconductor device provided by an embodiment of the present disclosure.

[0029] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The figures generally illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed implementation manners

[0030] The exemplary embodiments disclosed in the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0031] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of actual embodiments are described herein, and well-known functions and structures are not described in detail.

[0032] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Throughout the drawings, like reference numerals denote like elements.

[0033] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the present disclosure. And when a second element, component, region, layer, or section is discussed, it does not necessarily imply that a first element, component, region, layer, or section exists in the present disclosure.

[0034] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0036] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not used to limit the embodiments of the present disclosure.

[0037] There are mainly two process methods for hybrid bonding: wafer-to-wafer hybrid bonding technology (Wafer-to-Wafer Hybrid Bonding) and chip-to-wafer hybrid bonding (Chip-to-Wafer Hybrid Bonding). Under the requirements of high-density and high-precision technologies, whether the positions between wafers (die) are accurately aligned after bonding can be determined by the alignment of alignment marks in the wafers (die), or can be determined by electrical measurement.

[0038] On the one hand, referring to Figure 1 , Figure 1 shows the alignment of four groups of alignment marks; among them, the first mark 101 is located in the first wafer, and the second mark 102 is located in the second wafer; from Figure 1 , it can be seen that through the alignment of the first mark 101 and the second mark 102, the offset amount of the first wafer and the second wafer in the X-axis direction and / or Y-axis direction can be roughly determined, but it cannot be determined whether the first wafer and the second wafer have rotation.

[0039] On the other hand, when using the electrical test results to judge the alignment situation, when no electrical information is detected during the electrical test (or called in-line test, Inline), it will cause a deviation between the electrical test data and the predicted value of the offset amount, and cannot effectively reflect the alignment situation. In addition, the alignment situation reflected by the electrical test results is relatively rough and not accurate enough, resulting in signal delay in some semiconductor devices that pass the electrical test due to inaccurate alignment.

[0040] Based on one or more of the above problems, embodiments of the present disclosure propose a semiconductor device. The semiconductor device includes a first semiconductor structure; a first alignment mark is provided in the first semiconductor structure; a second semiconductor structure, stacked and arranged with the first semiconductor structure in a first direction; a second alignment mark is provided in the second semiconductor structure; the relative positions of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; wherein, both the first alignment mark and the second alignment mark include a first image, a second image, a third image, and a fourth image; the second image is located on at least one side of the first image in a second direction; the third image is located on at least one side of the first image in a third direction; the fourth image is located on at least one side of the first image in a fourth direction; the first direction, the second direction, and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects both the second direction and the third direction.

[0041] In this way, by providing a first alignment mark in the first semiconductor structure, a second alignment mark in the second semiconductor structure, and making both the first alignment mark and the second alignment mark include a first image, a second image, a third image, and a fourth image; after stacking and bonding the first semiconductor structure and the second semiconductor structure, the offset between the first semiconductor structure and the second semiconductor structure in multiple orientations can be determined by the alignment of the first image, the second image, the third image, and the fourth image in the first alignment mark with the first image, the second image, the third image, and the fourth image in the second alignment mark. In this way, on the one hand, the offset between the first semiconductor structure and the second semiconductor structure can be directly determined by manual visual inspection without additional equipment, improving the alignment efficiency; on the other hand, through the alignment results of multiple groups of images, the specific misaligned positions can be more accurately reflected, and the alignment accuracy can be improved by comparing the alignment results of multiple groups. In this way, the reliability and yield of the semiconductor device can be improved.

[0042] Before introducing in detail the semiconductor device proposed by the present disclosure, each direction that may be used in the following description is defined first. In the present disclosure, the stacking direction of the first semiconductor structure and the second semiconductor structure is defined as the first direction (such as the Z-axis direction). In a plane perpendicular to the Z-axis direction, an intersecting second direction (such as the X-axis direction), a third direction (such as the Y-axis direction), and a fourth direction (such as the P-direction) are defined. Here, the first direction, the second direction, and the third direction are perpendicular to each other, that is, the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other in pairs. The fourth direction is perpendicular to the first direction and intersects both the second direction and the third direction, that is, the P-direction is perpendicular to the Z-axis direction and intersects both the X-axis direction and the Y-axis direction. It should be noted that based on the different extension directions of the X-axis and the Y-axis, the P-direction can include two directions.

[0043] Refer to Figure 2, the first semiconductor structure 201 and the second semiconductor structure 202 are stacked in the Z-axis direction. A storage unit (not shown in the figure) and a first alignment mark 203 may be provided in the first semiconductor structure 201, and a logic circuit (not shown in the figure) and a second alignment mark 204 may be provided in the second semiconductor structure 202. From the material level, both the first semiconductor structure 201 and the second semiconductor structure 202 include a silicon substrate and a metal layer, and the silicon substrate may include a silicon dioxide layer and a silicon dielectric layer.

[0044] Here, the first semiconductor structure 201 and the second semiconductor structure 202 can be face-to-face bonded by a hybrid bonding method, and the alignment of the first semiconductor structure 201 and the second semiconductor structure 202 can be determined by the overlapping situation of the first alignment mark 203 and the second alignment mark 204 in the Z-axis direction. Among them, refer to Figure 2 , when the first alignment mark 203 and the second alignment mark 204 completely overlap in the Z-axis direction, it indicates that the first semiconductor structure 201 and the second semiconductor structure 202 are completely aligned. When the first alignment mark 203 and the second alignment mark 204 partially overlap in the Z-axis direction, it indicates that the first semiconductor structure 201 and the second semiconductor structure 202 are partially aligned, that is, there is an offset between them. When the first alignment mark 203 and the second alignment mark 204 do not overlap at all in the Z-axis direction, it indicates that the first semiconductor structure 201 and the second semiconductor structure 202 are completely misaligned.

[0045] The first alignment mark and the second alignment mark will be described in detail below with reference to the accompanying drawings.

[0046] The pattern of the first alignment mark and the pattern of the second alignment mark may be the same or different. In the embodiments of the present disclosure, both the first alignment mark and the second alignment mark include a first image, a second image, a third image, and a fourth image; the second image is located on at least one side of the first image in the X-axis direction; the third image is located on at least one side of the first image in the Y-axis direction; the fourth image is located on at least one side of the first image in the P direction. In other words, the second image, the third image, and the fourth image surround the first image.

[0047] Refer to Figure 3 and Figure 4 , the first alignment mark 203 includes a first image 301, a second image 302, a third image 303, and a fourth image 304, where Figure 3 In the first alignment mark 203 shown, the second image 302, the third image 303, and the fourth image 304 are only located on one side of the first image 301 respectively; Figure 4In the first alignment mark 203 shown, the second image 302 is located on opposite sides of the first image 301 in the X-axis direction; the third image 303 is located on opposite sides of the first image 301 in the Y-axis direction; the fourth image 304 is located on opposite sides of the first image 301 in the P direction (it should be understood that the P direction includes two directions, here, the fourth image 304 is located on all four sides of the first image 301).

[0048] In some embodiments, referring to Figure 3 , the outer boundary dimension L1 of the first image 301 in the Y-axis direction in the first alignment mark 203 is the same as the outer boundary dimension L2 of the second image 302 in the Y-axis direction in the first alignment mark, that is, L1 = L2; the outer boundary dimension L3 of the first image 301 in the X-axis direction in the first alignment mark is the same as the outer boundary dimension L4 of the third image 303 in the X-axis direction in the first alignment mark, that is, L3 = L4. It should be understood that the outer boundary dimension is the dimension of the outermost edge of the image.

[0049] Referring to Figure 5 and Figure 6 , the second alignment mark 204 includes a first image 501, a second image 502, a third image 503, and a fourth image 504, wherein Figure 5 In the second alignment mark 204 shown, the second image 502, the third image 503, and the fourth image 504 are only located on one side of the first image 501 respectively; Figure 6 In the second alignment mark 204 shown, the second image 502 is located on opposite sides of the first image 501 in the X-axis direction; the third image 503 is located on opposite sides of the first image 501 in the Y-axis direction; the fourth image 504 is located on opposite sides of the first image 501 in the P direction (it should be understood that the P direction includes two directions, here, the fourth image 504 is located on all four sides of the first image 501).

[0050] In some embodiments, referring to Figure 3 and Figure 5 , the outer boundary dimension L2 of the second image 302 in the Y-axis direction in the first alignment mark 203 is the same as the outer boundary dimension R2 of the second image 502 in the Y-axis direction in the second alignment mark 204; that is, L2 = R2. The outer boundary dimension L4 of the third image 303 in the X-axis direction in the first alignment mark 203 is the same as the outer boundary dimension R4 of the third image 503 in the X-axis direction in the second alignment mark 204, that is, L4 = R4.

[0051] In this way, during the alignment of the first alignment mark 203 and the second alignment mark 204, the offset of the first semiconductor structure and the second semiconductor structure in the Y-axis direction can be more intuitively determined by comparing two second images with the same outer boundary dimensions; and the offset of the first semiconductor structure and the second semiconductor structure in the X-axis direction can be more intuitively determined by comparing two third images with the same outer boundary dimensions.

[0052] In some embodiments, with reference to Figure 4 and Figure 6 , the distance L5 in the X-axis direction between the second image 302 and the third image 303 in the first alignment mark 203 is less than the distance R5 in the X-axis direction between the second image 502 and the third image 503 in the second alignment mark 204, that is, L5 < R5. Also, the distance L6 in the Y-axis direction between the second image 302 and the third image 303 in the first alignment mark 203 is less than the distance R6 in the Y-axis direction between the second image 502 and the third image 503 in the second alignment mark 204, that is, L6 < R6. In this way, during the alignment process, the second image 302 in the first alignment mark 203 can be compared with the second image 502 in the second alignment mark 204 with a dislocation, and the third image 303 in the first alignment mark 203 can be compared with the third image 503 in the second alignment mark 204 with a dislocation. Thus, the offset between the first alignment mark and the second alignment mark can be more intuitively determined.

[0053] In some embodiments, the outer boundary dimension of the first image in the second alignment mark in the Y-axis direction may be the same as or different from the outer boundary dimension of the second image in the second alignment mark in the Y-axis direction. The outer boundary dimension of the first image in the second alignment mark in the X-axis direction may be the same as or different from the outer boundary dimension of the third image in the second alignment mark in the X-axis direction. Among them, when the dimensions of the two are different, it indicates that the dimensions of the first image in the first alignment mark and the first image in the second alignment mark are different. At this time, it is beneficial to compare the first image in the first alignment mark with the first image in the second alignment mark.

[0054] Exemplarily, with reference to Figure 5, the outer boundary dimension R1 of the first image 501 in the second alignment mark in the Y-axis direction is smaller than the outer boundary dimension R2 of the second image 502 in the second alignment mark in the Y-axis direction, that is, R1 < R2; the outer boundary dimension R3 of the first image 501 in the second alignment mark in the X-axis direction is smaller than the outer boundary dimension R4 of the third image 503 in the second alignment mark in the X-axis direction, that is, R3 < R4. In other words, in this embodiment, the outer boundary dimension R1 of the first image 501 in the second alignment mark 204 in the Y-axis direction is smaller than the outer boundary dimension L1 of the first image 301 in the first alignment mark in the Y-axis direction, that is, R1 < L1. The outer boundary dimension R3 of the first image 501 in the second alignment mark in the X-axis direction is smaller than the outer boundary dimension L3 of the first image 301 in the first alignment mark in the X-axis direction, that is, R3 < L3. In this way, during the alignment process of the first alignment mark 203 and the second alignment mark 204, the first image 301 in the first alignment mark and the first image 501 in the second alignment mark do not completely overlap (i.e., there is a misalignment), which can more intuitively determine the offset position between the two and reduce the difficulty of discrimination.

[0055] It should be noted that the fourth image in the first alignment mark and the fourth image in the second alignment mark can be used to determine the offset amount of the first semiconductor structure and the second semiconductor structure in the clockwise / counterclockwise direction in the XY plane, that is, the rotational offset amount of the first semiconductor structure and the second semiconductor structure in the XY plane. The following will be described in detail in combination with the specific graphics of the images.

[0056] In some embodiments, the first image includes a circular shape, a circular ring shape, a square shape, a matrix pattern or a cross-shaped pattern; the second image includes a plurality of long strip-shaped patterns arranged uniformly in the Y-axis direction; the third image includes a plurality of long strip-shaped patterns arranged uniformly in the X-axis direction; the fourth image includes a long strip-shaped pattern extending in the P direction, and / or a plurality of circular patterns arranged linearly or in an arc uniformly in a direction perpendicular to the P direction.

[0057] Here, the plurality of long strip-shaped patterns in the second image and the third image are arranged uniformly, indicating that the plurality of long strip-shaped patterns divide the sizes of the second image and the third image evenly, and the size occupied by each long strip-shaped pattern in the plurality of long strip-shaped patterns is the same. It should be understood that in combination with reference Figure 3 and Figure 5 , when the shapes of the second image 302 in the first alignment mark 203 and the second image 502 in the second alignment mark 204 are the same, the offset amount in the Y-axis direction between the two can be quickly determined by the number of offset long strip-shaped patterns. Similarly, when the shapes of the third image 303 in the first alignment mark 203 and the third image 503 in the second alignment mark 204 are the same, the offset amount in the X-axis direction between the two can be quickly determined by the number of offset long strip-shaped patterns.

[0058] It should be understood that the shapes of the first image in the first alignment mark and the first image in the second alignment mark may be the same or different; the shapes of the fourth image in the first alignment mark and the fourth image in the second alignment mark may be the same or different.

[0059] Exemplarily, referring to Figure 7 , Figure 7 , there are schematic diagrams showing the specific shapes of three first alignment marks 203; among them, Figure 7 in (1), the first image 301 is in a circular ring shape, the second image 302 is a plurality of long strip-shaped graphics evenly arranged along the Y-axis direction, the third image 303 is a plurality of long strip-shaped graphics evenly arranged along the X-axis direction, and the fourth image 304 is a long strip-shaped graphic extending along the P direction. Figure 7 in (2), the first image 301 is in a circular ring shape, the second image 302 is a plurality of long strip-shaped graphics evenly arranged along the Y-axis direction, the third image 303 is a plurality of long strip-shaped graphics evenly arranged along the X-axis direction, and the fourth image 304 is a plurality of circular graphics evenly arranged in an arc in a direction perpendicular to the P direction. Figure 7 in (3), the first image 301 is in a circular ring shape, the second image 302 is a plurality of long strip-shaped graphics evenly arranged along the Y-axis direction, the third image 303 is a plurality of long strip-shaped graphics evenly arranged along the X-axis direction, and the fourth image 304 is a combination of a long strip-shaped graphic extending along the P direction and a plurality of circular graphics evenly arranged in an arc in a direction perpendicular to the P direction.

[0060] It should be noted that when the fourth image is a combination of a long strip-shaped graphic and a plurality of circular graphics, circles may not be provided at the positions where the long strip-shaped graphic overlaps with the circular graphics in the extending direction, so that image overlap can be avoided, the discrimination difficulty can be reduced, and the alignment efficiency can be improved.

[0061] Exemplarily, referring to Figure 8 , Figure 8 , there are schematic diagrams showing the specific shapes of three second alignment marks 204; among them, Figure 8 in (1), the first image 501 is in a circular ring shape, the second image 502 is a plurality of long strip-shaped graphics evenly arranged along the Y-axis direction, the third image 503 is a plurality of long strip-shaped graphics evenly arranged along the X-axis direction, and the fourth image 504 is a long strip-shaped graphic extending along the P direction. Figure 8 in (2), the first image 501 is in a circular ring shape, the second image 502 is a plurality of long strip-shaped graphics evenly arranged along the Y-axis direction, the third image 503 is a plurality of long strip-shaped graphics evenly arranged along the X-axis direction, and the fourth image 504 is a plurality of circular graphics evenly arranged in an arc in a direction perpendicular to the P direction. Figure 8In (3), the first image 501 is circular, the second image 502 is a plurality of elongated figures arranged uniformly in the Y-axis direction, the third image 503 is a plurality of elongated figures arranged uniformly in the X-axis direction, and the fourth image 504 is a combination of an elongated figure extending in the P direction and a plurality of circular figures arranged uniformly in an arc in a direction perpendicular to the P direction.

[0062] In other embodiments, the shapes of the first image, the second image, the third image, and the fourth image in the first alignment mark, and the shapes of the first image, the second image, the third image, and the fourth image in the second alignment mark may also be any other suitable shapes, and the present disclosure does not limit this.

[0063] Reference Figure 7 and Figure 8 , the number of elongated figures in the second image 302 of the first alignment mark 203 is the same as the number of elongated figures in the second image 502 of the second alignment mark 204; and / or, the number of elongated figures in the third image 303 of the first alignment mark 203 is the same as the number of elongated figures in the third image 503 of the second alignment mark 204. In this way, for the plurality of elongated figures in the second image 302 of the first alignment mark 203, the size occupied by each elongated shape can be made the same as the size occupied by each elongated shape among the plurality of elongated figures in the second image 502 of the second alignment mark 204. When comparing the alignment of the two, the offset in the Y-axis direction between the two can be determined by the number of elongated figures that differ between the two. Similarly, for the plurality of elongated figures in the third image 303 of the first alignment mark 203, the size occupied by each elongated shape can be made the same as the size occupied by each elongated shape among the plurality of elongated figures in the third image 503 of the second alignment mark 204. When comparing the alignment of the two, the offset in the X-axis direction between the two can be determined by the number of elongated figures that differ between the two.

[0064] On this basis, the offset in the X-axis direction and the Y-axis direction between the first semiconductor structure and the second semiconductor structure can be quickly determined by visually inspecting the difference in the number of elongated figures in the second image or the third image of the first alignment mark and the second alignment mark, thereby improving the alignment efficiency and alignment accuracy.

[0065] In some embodiments, the sizes of the plurality of elongated figures in the second image and / or the third image are different in their extending directions.

[0066] In some embodiments, among the plurality of strip-shaped patterns of the second image or the third image, the dimensions of a part of the strip-shaped patterns in their extending direction are the first dimension, and the dimensions of another part of the strip-shaped patterns in their extending direction are the second dimension; wherein, the strip-shaped patterns with the first dimension and the strip-shaped patterns with the second dimension are arranged alternately at intervals.

[0067] Exemplarily, referring to Figure 7 , in the first alignment mark 203, the dimensions of the plurality of strip-shaped patterns in the third image 303 in the Y-axis direction are different. Among them, the dimensions of a part of the strip-shaped patterns (such as 701) in the Y-axis direction are the first dimension, and the dimensions of another part of the strip-shaped patterns (such as 702) in the Y-axis direction are the second dimension. Here, the first dimension is greater than the second dimension, and the strip-shaped patterns with the first dimension and the strip-shaped patterns with the second dimension are arranged alternately at intervals. In this way, the dimension between every two adjacent strip-shaped patterns with a specific first dimension (or second dimension) is a fixed value. When performing alignment comparison, the recognition rate of the strip-shaped patterns can be improved, the specific difference between the two images can be determined more quickly, and the alignment efficiency is improved. In some other embodiments, the first dimension can also be less than the second dimension. In addition, the ratio of the number of strip-shaped patterns with the first dimension to the number of strip-shaped patterns with the second dimension arranged alternately at intervals can be selected and set according to actual needs, and the present disclosure does not limit this.

[0068] It should be noted that in the second image in the first alignment mark, the second image in the second alignment mark, and the third image in the second alignment mark, the above-mentioned arrangement of alternately arranging strip-shaped patterns with different dimensions can be adopted to further improve the alignment efficiency.

[0069] In some specific embodiments, referring to Figure 7 and Figure 8 , the width of a strip-shaped pattern in the second image is S1, and the width of a strip-shaped pattern in the third image is S2. Here, S1 can be equal to S2. Exemplarily, S1 = S2 = 1um. In some specific embodiments, the spacing width between every two adjacent strip-shaped patterns in the second image is S3, and the spacing width between every two adjacent strip-shaped patterns in the third image is S4. Here, S3 can be equal to S4. Exemplarily, S3 = S4 = 1um. In this way, the specific offset between two second images or two third images can be determined by the number of strip-shaped patterns and the number of spacings.

[0070] It should be noted that, in order to obtain the offset between the first alignment mark and the second alignment mark more intuitively, in practical applications, the first image in the first alignment mark should at least partially overlap with the first image 501 in the second alignment mark 204 in the Z-axis direction. In other words, if the first semiconductor structure and the second semiconductor structure are bonded face to face, the position of the first alignment mark in the first semiconductor structure, the position of the second alignment mark in the second semiconductor structure, and the relative position between the first alignment mark and the second alignment mark after bonding should be considered.

[0071] In some embodiments, when the first alignment mark and the second alignment mark completely overlap in the Z-axis direction, a plurality of elongated patterns in the second image of the first alignment mark are aligned one by one with a plurality of elongated patterns in the second image of the second alignment mark in the X-axis direction; and a plurality of elongated patterns in the third image of the first alignment mark are aligned one by one with a plurality of elongated patterns in the third image of the second alignment mark in the Y-axis direction.

[0072] Exemplarily, referring to Figure 9 , Figure 9 shows schematic diagrams of three sets of complete alignment (complete overlap) of the first alignment mark 203 and the second alignment mark 204. In the three schematic diagrams, the fourth image 304 in the first alignment mark 203 is different from the fourth image 504 of the second alignment mark 204. Among them, a plurality of elongated patterns in the second image 302 of the first alignment mark 203 are aligned one by one with a plurality of elongated patterns in the second image 502 of the second alignment mark 204 in the X-axis direction. A plurality of elongated patterns in the third image 303 of the first alignment mark 203 are aligned one by one with a plurality of elongated patterns in the third image 503 of the second alignment mark 204 in the X-axis direction.

[0073] Referring to Figure 9 , the first image 301 in the first alignment mark 203 and the first image 501 in the second alignment mark 204 are both circular rings; and the first image 301 in the first alignment mark 203 and the first image 501 in the second alignment mark 204 are concentric circles. The diameter of the first image 301 in the first alignment mark 203 is M1. Exemplarily, M1 = 80um, and the diameter of the first image 501 in the second alignment mark 204 is M2. Exemplarily, M2 = 40um.

[0074] As Figure 9As shown, the width of the first alignment mark 203 in the X-axis direction (or Y-axis direction) is smaller than the width of the second alignment mark 204 in the X-axis direction (or Y-axis direction); in some specific embodiments, the width of the second alignment mark 204 in the X-axis direction (or Y-axis direction) is M3, and for example, M3=120um or 200um. The width of the first alignment mark 203 in the X-axis direction (or Y-axis direction) can be set according to actual needs, and the present disclosure does not limit this.

[0075] It should be understood that Figure 9 The three groups of fourth image graphics are only exemplarily shown. In other embodiments, the fourth image 304 in the first alignment mark 203 and the fourth image 504 in the second alignment mark 204 may also be other graphics, which is not limited in the present disclosure.

[0076] It should be noted that when the angles between the P direction and the X-axis direction and the Y-axis direction are all 45°, only one long strip-shaped pattern extending along the P direction may be provided in the fourth image. At this time, the angle between the long strip-shaped pattern and the second image is 45°, and the angle between the long strip-shaped pattern and the third image is also 45°. The rotation offset between the first semiconductor structure and the second semiconductor structure is determined by judging the long strip-shaped pattern of the fourth image 304 in the first alignment mark 203 and the long strip-shaped pattern of the fourth image 504 in the second alignment mark 204.

[0077] When multiple circular graphics are set in the fourth image, the multiple circular graphics and the second image and the third image form a right-angle sector, and the multiple circular graphics divide the right angle equally; in some embodiments, 319, 318, 200, 100, 35, 19, etc. circular graphics can be set in the fourth image. At this time, the 319, 318, 200, 100, 36, 20 circular graphics divide the right angle (90°) into 320, 319, 201, 101, 36, 20 equal parts. Exemplarily, when the right angle (90°) is divided into 320 equal parts, the angle of each equal part is 0.28125°. On this basis, by comparing the two corresponding fourth images in the first alignment mark and the second alignment mark, the rotation angle of the two alignment marks on the XY plane, that is, the rotation offset, can be determined.

[0078] Among them, when the fourth image 304 in the first alignment mark 203 includes 318 circular patterns (i.e., 90° is divided into 319 equal parts), and the fourth image 504 in the second alignment mark 204 includes 319 circular patterns (i.e., 90° is divided into 320 equal parts), by comparing the fourth image 304 in the first alignment mark 203 with the fourth image 504 in the second alignment mark 204, the accuracy can reach about 0.00088° (90° / 319 / 320 ≈ 0.00088°). In this way, the measurement accuracy can be improved, and the accuracy of alignment measurement can be improved.

[0079] It should be understood that the more circular patterns there are in the fourth image, the higher the accuracy and the higher the accuracy of the determined rotation offset. In some specific embodiments, the diameter of the circular pattern can be 1um.

[0080] In some embodiments, when the first alignment mark and the second alignment mark do not completely overlap (i.e., there is an offset between them), the patterns in at least one set of images in the first alignment mark and the second alignment mark are not aligned.

[0081] Exemplarily, referring to Figure 10 , Figure 10 FIG. (1) shows a schematic diagram of the offset between the second image 1001 of the first alignment mark and the second image 1002 of the second alignment mark. Exemplarily, the second image 1001 of the first alignment mark is offset by the width distance S1 of a long strip pattern, such as 1um, on the X-axis compared to the second image 1002 of the second alignment mark. Figure 10 FIG. (2) shows a schematic diagram of the offset between the third image 1003 of the first alignment mark and the third image 1004 of the second alignment mark. Exemplarily, the third image 1003 of the first alignment mark is offset by the width distance S2 of a long strip pattern and a spacing S4, such as 2um, on the Y-axis compared to the third image 1004 of the second alignment mark. Figure 10 FIG. (3) shows a schematic diagram of the offset between the fourth images of two sets of first alignment marks and the fourth image of the second alignment mark.

[0082] Figure 10 In one of the diagrams in FIG. (3), the fourth image of the first alignment mark includes a long strip pattern 1005 and a plurality of circular patterns 1006 arranged uniformly in an arc, and the fourth image of the second alignment mark includes a long strip pattern 1007. Among them, the long strip pattern 1005 of the first alignment mark is rotated by an angle α compared to the long strip pattern 1007 of the second alignment mark, that is, the rotation offset is an angle α. Figure 10In another set of views of (3), the fourth image of the first alignment mark includes a plurality of circular patterns 1008 evenly arranged in an arc, and the fourth image of the second alignment mark includes a plurality of circular patterns 1009 evenly arranged in an arc. Among them, the plurality of circular patterns 1008 of the first alignment mark are rotated by an angle corresponding to one circular pattern compared with the plurality of circular patterns 1009 of the second alignment mark. Thus, the rotational offset between the two can be determined according to the angle corresponding to two adjacent circular patterns.

[0083] Based on this, in the embodiments of the present disclosure, the offset between the first semiconductor structure and the second semiconductor structure in the Y-axis direction can be determined by the relative position between the second image in the first alignment mark and the second image in the second alignment mark; the offset between the first semiconductor structure and the second semiconductor structure in the X direction can be determined by the relative position between the third image of the first alignment mark and the third image of the second alignment mark; the rotational offset of the first semiconductor structure and the second semiconductor structure in the clockwise / counterclockwise direction in the XY plane can be determined by the relative position between the fourth image of the first alignment mark and the fourth image of the second alignment mark; thereby improving the alignment accuracy between the first semiconductor structure and the second semiconductor structure and enhancing the reliability of the semiconductor device.

[0084] Furthermore, by setting the patterns of the first alignment mark and the second alignment mark, the offset between the first semiconductor structure and the second semiconductor structure can be directly determined by manual visual inspection without the need for additional equipment, improving the alignment efficiency; on the other hand, the specific misaligned position can be more accurately reflected through the alignment results of multiple groups of images, and the alignment accuracy can be improved by comparing the alignment results of multiple groups. Thus, the reliability and yield of the semiconductor device can be further enhanced.

[0085] Based on the above semiconductor device, the embodiments of the present disclosure further provide a method for determining the offset of a semiconductor device. The semiconductor device is the semiconductor device described in the above embodiments of the present disclosure. Refer to Figure 11 , Figure 11 FIG. shows a schematic flow chart of a method for determining the offset of a semiconductor device. The method includes:

[0086] Step S1101, obtain the layer image of the semiconductor device on the first plane; the layer image includes the first alignment mark and the second alignment mark; the semiconductor device includes a first semiconductor structure and a second semiconductor structure stacked and arranged in a first direction. The first alignment mark is disposed in the first semiconductor structure, and the second alignment mark is disposed in the second semiconductor structure; the first plane is perpendicular to the first direction.

[0087] Step S1102: Determine the offset between the first semiconductor structure and the second semiconductor structure based on the relative positions of the first alignment mark and the second alignment mark. The first alignment mark and the second alignment mark each include a first image, a second image, a third image, and a fourth image. The second image is located on at least one side of the first image in the second direction. The third image is located on at least one side of the first image in the third direction. The fourth image is located on at least one side of the first image in the fourth direction. The first direction, the second direction, and the third direction are perpendicular to each other. The fourth direction is perpendicular to the first direction and intersects both the second direction and the third direction.

[0088] In some embodiments, determining the offset between the first semiconductor structure and the second semiconductor structure based on the relative positions of the first alignment mark and the second alignment mark includes: determining the offset between the first semiconductor structure and the second semiconductor structure in the third direction based on the relative positions of the second images of the first alignment mark and the second alignment mark.

[0089] Determine the offset between the first semiconductor structure and the second semiconductor structure in the second direction based on the relative positions of the third images of the first alignment mark and the second alignment mark.

[0090] Determine the rotational offset between the first semiconductor structure and the second semiconductor structure in the clockwise / counterclockwise direction on the first plane based on the relative positions of the fourth images of the first alignment mark and the second alignment mark.

[0091] Based on the above semiconductor device, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor device. Refer to Figure 12 , Figure 12 for a schematic flowchart of a method for manufacturing a semiconductor device. The method includes: Step S1201: Form a first semiconductor structure; a first alignment mark is provided in the first semiconductor structure.

[0092] Step S1202: Form a second semiconductor structure; a second alignment mark is provided in the second semiconductor structure.

[0093] Step S1203: Bond the first semiconductor structure and the second semiconductor structure in a first direction; wherein, the relative positions of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; both the first alignment mark and the second alignment mark include a first image, a second image, a third image, and a fourth image; the second image is located on at least one side of the first image in a second direction; the third image is located on at least one side of the first image in a third direction; the fourth image is located on at least one side of the first image in a fourth direction; the first direction, the second direction, and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects both the second direction and the third direction.

[0094] It should be noted that: "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. Additionally, the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0095] The above is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a first semiconductor structure; A first alignment mark is disposed in the first semiconductor structure; A second semiconductor structure, stacked and arranged with the first semiconductor structure in a first direction; A second alignment mark is disposed in the second semiconductor structure; The relative position of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; Among them, the first alignment mark and the second alignment mark both include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the second image includes a plurality of long strip graphics uniformly arranged along the third direction; the third image includes a plurality of long strip graphics uniformly arranged along the second direction; the fourth image includes a long strip graphics extending along the fourth direction, and / or a plurality of circular graphics uniformly arranged in a straight line or arc in a direction perpendicular to the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction, and intersects with both the second direction and the third direction.

2. The semiconductor device according to claim 1, wherein: The outer boundary size of the first image in the first alignment mark in the third direction is the same as the outer boundary size of the second image in the first alignment mark in the third direction; An outer boundary size of the first image in the first alignment mark in the second direction is the same as an outer boundary size of the third image in the first alignment mark in the second direction.

3. The semiconductor device according to claim 2, characterized in that The outer boundary size of the second image in the first alignment mark in the third direction is the same as the outer boundary size of the second image in the second alignment mark in the third direction; An outer boundary size of the third image in the first alignment mark in the second direction is the same as an outer boundary size of the third image in the second alignment mark in the second direction.

4. The semiconductor device according to claim 3, characterized in that The first image includes a circle, a ring, a square, a matrix or a cross.

5. The semiconductor device according to claim 4, characterized in that The number of long strip graphics in the second image of the first alignment mark is the same as the number of long strip graphics in the second image of the second alignment mark; and / or the number of long strip graphics in the third image of the first alignment mark is the same as the number of long strip graphics in the third image of the second alignment mark.

6. The semiconductor device according to claim 5, characterized in that The multiple long strip-shaped graphics in the second image and / or the third image have different sizes in their extending directions.

7. The semiconductor device according to claim 6, characterized in that Among the plurality of long strip-shaped graphics in the second image or the third image, the size of a portion of the long strip-shaped graphics in the extending direction thereof is a first size, and the size of another portion of the long strip-shaped graphics in the extending direction thereof is a second size; The long strip-shaped figures having the first size and the long strip-shaped figures having the second size are arranged alternately.

8. The semiconductor device according to claim 7, characterized in that The first image in the first alignment mark at least partially overlaps the first image in the second alignment mark in the first direction.

9. The semiconductor device according to claim 8, characterized in that When the first alignment mark and the second alignment mark completely overlap in the first direction, a plurality of long strip patterns in the second image of the first alignment mark are aligned one by one with a plurality of long strip patterns in the second image of the second alignment mark in the second direction; Furthermore, the plurality of long strip-shaped patterns in the third image of the first alignment mark and the plurality of long strip-shaped patterns in the third image of the second alignment mark are aligned one by one in the third direction.

10. A method for determining an offset of a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 9, characterized in that: The determination method comprises: Acquire a layer image of the semiconductor device on a first plane; the layer image includes a first alignment mark and a second alignment mark; the semiconductor device includes a first semiconductor structure and a second semiconductor structure stacked and arranged in a first direction, the first semiconductor structure is provided with the first alignment mark, and the second semiconductor structure is provided with the second alignment mark; the first plane is perpendicular to the first direction; Determining an offset between the first semiconductor structure and the second semiconductor structure according to a relative position of the first alignment mark and the second alignment mark; Among them, the first alignment mark and the second alignment mark both include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the second image includes a plurality of long strip graphics uniformly arranged along the third direction; the third image includes a plurality of long strip graphics uniformly arranged along the second direction; the fourth image includes a long strip graphics extending along the fourth direction, and / or a plurality of circular graphics uniformly arranged in a straight line or arc in a direction perpendicular to the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction, and intersects with both the second direction and the third direction.

11. The determination method according to claim 10, characterized in that: The step of determining the offset between the first semiconductor structure and the second semiconductor structure by the relative position of the first alignment mark and the second alignment mark comprises: determining an offset between the first semiconductor structure and the second semiconductor structure in the third direction according to a relative position between the second image of the first alignment mark and the second image of the second alignment mark; determining an offset between the first semiconductor structure and the second semiconductor structure in the second direction according to a relative position between the third image of the first alignment mark and the third image of the second alignment mark; The rotation offset of the first semiconductor structure and the second semiconductor structure along the clockwise / counterclockwise direction on the first plane is determined according to the relative position between the fourth image of the first alignment mark and the fourth image of the second alignment mark.

12. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a first semiconductor structure; a first alignment mark is disposed in the first semiconductor structure; forming a second semiconductor structure; a second alignment mark is disposed in the second semiconductor structure; bonding the first semiconductor structure and the second semiconductor structure in a first direction; Among them, the first alignment mark and the second alignment mark both include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the second image includes a plurality of long strip graphics uniformly arranged along the third direction; the third image includes a plurality of long strip graphics uniformly arranged along the second direction; the fourth image includes a long strip graphics extending along the fourth direction, and / or a plurality of circular graphics uniformly arranged in a straight line or arc in a direction perpendicular to the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction, and intersects with both the second direction and the third direction.

Images