Simplified one-way energy flow five-level frequency converter capacitor voltage balance control strategy

Abstract

The invention discloses a simplified one-way energy flow five-level frequency converter capacitor voltage balance control strategy, relates to a one-way energy flow direct connection type five-level middle-high voltage frequency converter, and comprises five parts of inverter level unbalance degree calculation, direct current side voltage calculation, a rectifier level control strategy, a rectifier level modulation method and an inverter level modulation method. The objective of the invention is to solve the problems of difficult direct-current side capacitor voltage balance control and poor output voltage waveform quality of a five-level frequency converter. Compared with the prior art, the direct current side capacitor voltage balance control method has the remarkable advantages that the degree of unbalance generated to the direct current side capacitor voltage when the inverter works is reduced by improving an inverter stage modulation method, and direct current side capacitor voltage balance control is further realized through rectifier stage control, so that the direct current side capacitor voltage balance control is realized; and the waveform quality of the output voltage of the inverter stage is ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of medium and high voltage variable frequency speed regulation, and more specifically, relates to a simplified capacitor voltage balance control strategy for a transformerless isolated unidirectional energy flow three-phase five-level medium and high voltage inverter. Background Art

[0002] In recent years, multilevel power converters have been successfully applied more and more in the fields of high voltage and high power variable frequency speed regulation, active power filtering, high voltage direct current (HVDC) transmission and reactive power compensation of power systems. The basic circuit topology of multilevel converters can be roughly divided into two categories: clamped type and unit cascade type. The unidirectional energy flow diode clamped three-level medium and high voltage inverters that are currently most widely used in industry, and the unidirectional energy flow cascade H-bridge medium and high voltage inverters are typical representatives of these two types of products. In both types of medium and high voltage inverters, in order to use low withstand voltage power electronic devices to complete high voltage power conversion and suppress the harmonics of input current, a bulky, complex wiring and expensive power frequency phase shifting transformer is required on the input side of the rectifier. This limits its application in many industrial occasions. In order to eliminate the power frequency phase shifting transformer, academia and industry have tried to use high-frequency isolation DC-DC converters to connect the cascade rectifier stage and the cascade inverter stage to form a new type of medium and high voltage inverter. Compared with traditional medium and high voltage inverters, the rectifier stage implementation scheme of this new type of medium and high voltage inverter eliminates the bulky, complex wiring, and expensive power frequency phase-shifting transformer, thereby effectively reducing the system volume, weight, and manufacturing cost. However, this type of new type of medium and high voltage inverter also has obvious disadvantages, mainly manifested in: high power density, high efficiency, high power high frequency isolation DC / DC converter is very difficult to design and implement, which has become the main bottleneck for this type of new type of medium and high voltage inverter to truly become practical. For this reason, in recent years, a new generation of medium and high voltage inverters that use cascade rectifier stages and cascade inverter stages to connect directly have received more and more attention in the field of power electronics technology. Among them, a new generation of direct-connected medium and high voltage inverters composed of a Y-connected three-single-phase diode cascade Boost rectifier circuit + a three-single-phase multi-level inverter circuit and an open winding connection with the motor is one of the typical solutions. This new type of topology does not require power frequency transformer isolation, nor does it require the use of a high-frequency isolation DC conversion unit, thereby greatly reducing its volume, structure, cost, and control complexity, showing great practical advantages.

[0003] Although the new generation of direct-connected medium and high voltage inverters have shown obvious advantages, there are still some problems that must be solved in practical engineering applications. For example, the DC side capacitor voltage balance control of the five-level inverter is an inherent control difficulty of the five-level NPC converter. The imbalance of the DC side capacitor voltage will not only lead to the deterioration of the inverter output waveform quality, but also cause equipment damage, seriously affecting production safety. The existing five-level converter midpoint potential balance control method mostly uses the inverter stage for independent control. The disadvantage of this method is that the output voltage has a high harmonic content. For the inverter, its rectifier stage still has the ability to balance the DC side capacitor voltage. Therefore, through the cooperation of the rectifier stage and the inverter stage, it can not only achieve the DC side capacitor voltage balance control, but also ensure the inverter stage output voltage waveform quality. Summary of the invention

[0004] In view of the defects of the prior art, the purpose of the present invention is to provide a capacitor voltage balance control strategy for the above-mentioned direct-connected new generation five-level medium and high voltage inverter, aiming to solve the problems of difficult DC side capacitor voltage balance control and poor output voltage waveform quality of the five-level inverter.

[0005] To achieve the above-mentioned object, the present invention provides a simplified unidirectional energy flow five-level inverter capacitor voltage balance control strategy, which relates to a unidirectional energy flow direct-connected five-level medium and high voltage inverter, characterized in that it includes five parts: inverter stage imbalance calculation, rectifier stage maximum controllable imbalance calculation, rectifier stage control strategy, rectifier stage modulation method, and inverter stage modulation method;

[0006] Calculation of inverter level imbalance:

[0007] Define h i is the unbalance degree generated by the inverter stage, m i is the inverter modulation ratio, and the unbalance degree generated by the inverter is calculated using the following formula, and h is taken i The maximum value of h imax ;

[0008]

[0009] Calculation of the maximum controllable imbalance of the rectifier stage:

[0010] Define V s is the phase voltage amplitude on the grid side, V dc is the rated value of DC side voltage, m r is the rectifier stage modulation ratio, and the rectifier stage modulation ratio is calculated using the following formula;

[0011]

[0012] Define h ris the controllable imbalance of the rectifier stage, and the controllable imbalance of the rectifier stage is calculated using the following formula;

[0013]

[0014] Compare r and h i size, and ensure that h r ≥h i , if h r <h i , then further modify the DC side voltage rating until h r and h i Satisfy h r ≥h i ;

[0015] Rectification stage control strategy:

[0016] Step 1: Sample the voltage of the three-phase DC side capacitors A, B, and C to obtain the voltage signal v of each DC side capacitor of the three-phase A, B, and C dca1 、v dca2 、v dca3 、v dca4 、v dcb1 、v dcb2 、v dcb3 、v dcb4 、v dcc1 、v dcc2 、v dcc3 、v dcc4 And the three-phase DC side total voltage signal v dca 、v dcb 、v dcc , average the total voltage of the three-phase DC side to get the average value of the total voltage of the DC side, and compare the average value of the total voltage of the DC side with the expected value of the DC side voltage V * dc The difference is sent to the PI regulator to obtain the expected current i required to maintain the DC side voltage stability. * dc ;

[0017] Step 2: Sample the current on the input side of the three-phase grid A, B, and C to obtain the current i on the input side of the three-phase grid a 、i b 、i c , use the following formula to calculate the A, B, C three-phase modulation wave signal u sa 、u sb 、u sc ;

[0018]

[0019] Step 3: v dca1 and vdca2 Summing to get u a1 , v dca3 and v dca4 Summing to get u a2 ,u a1 and u a2 The difference is sent to the PI regulator to get u ab1 , v dca1 and v dca2 The difference is sent to the PI regulator to get u ab2 , v dca4 and v dca3 The difference is sent to the PI regulator to get u ab3 , use the following formula to calculate the A-phase rectifier stage fully controlled device S a1 , S a2 , S a3 , S a4 The modulated wave signal u sa1 、u sa2 、u sa3 、u sa4 ;

[0020]

[0021] v dcb1 and v dcb2 Summing to get u b1 , v dcb3 and v dcb4 Summing to get u b2 ,u b1 and u b2 The difference is sent to the PI regulator to get u bb1 , v dcb1 and v dcb2 The difference is sent to the PI regulator to get u bb2 , v dcb4 and v dcb3 The difference is sent to the PI regulator to get u bb3 , use the following formula to calculate the B-phase rectifier stage fully controlled device S b1 , S b2 , S b3 , S b4 The modulated wave signal u sb1 、u sb2 、u sb3 、u s b4;

[0022]

[0023] v dcc1 and v dcc2 Summing to get u c1 , v dcc3 and vdcc4 Summing to get u c2 ,u c1 and u c2 The difference is sent to the PI regulator to get u cb1 , v dcc1 and v dcc2 The difference is sent to the PI regulator to get u cb2 , v dcc4 and v dcc3 The difference is sent to the PI regulator to get u cb3 , the C-phase rectifier stage fully controlled device S is calculated using the following formula c1 , S c2 , S c3 , S c4 The modulated wave signal u sc1 、u sc2 、u sc3 、u sc4 ;

[0024]

[0025] Rectification stage modulation method:

[0026] The three-phase rectifier stage adopts the modulation method of carrier phase shift, and defines the rectifier stage to use four carrier signals of 0°, 90°, 180° and 270°, and defines the rectifier stage fully controlled device S a1 , S a2 , S a3 , S a4 , S b1 , S b2 , S b3 , S b4 , S c1 , S c2 , S c3 , S c4 The driving signals are G sa1 , G sa2 , G sa3 , G sa4 , G sb1 , G sb2 , G sb3 , G sb4 , G sc1 , G sc2 , G sc3 , G sc4 , when u sa1 When the carrier signal is greater than 0°, the drive signal G sa1 Output high level, output low level in other cases; when u sa2 When the carrier signal is greater than 90°, the drive signal G sa2 Output high level, output low level in other cases; when u sa3When the carrier signal is greater than 180°, the drive signal G sa3 Output high level, output low level in other cases; when u sa4 When the carrier signal is greater than 270°, the drive signal G sa4 Output high level, output low level in other cases; when u sb1 When the carrier signal is greater than 0°, the drive signal G sb1 Output high level, output low level in other cases; when u sb2 When the carrier signal is greater than 90°, the drive signal G sb2 Output high level, output low level in other cases; when u sb3 When the carrier signal is greater than 180°, the drive signal G sb3 Output high level, output low level in other cases; when u sb4 When the carrier signal is greater than 270°, the drive signal G sb4 Output high level, output low level in other cases; when u sc1 When the carrier signal is greater than 0°, the drive signal G sc1 Output high level, output low level in other cases; when u sc2 When the carrier signal is greater than 90°, the drive signal G sc2 Output high level, output low level in other cases; when u sc3 When the carrier signal is greater than 180°, the drive signal G sc3 Output high level, output low level in other cases; when u sc4 When the carrier signal is greater than 270°, the drive signal G sc4 Output high level, and output low level in other cases;

[0027] Inverter level modulation method:

[0028] Step 1: Define the modulation wave signal of the inverter U-phase bridge arm 1 as u su , the fully controlled devices are S from top to bottom u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' ; The modulation wave signal of U phase bridge arm 2 is u su' , the fully controlled devices are S from top to bottom u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' ; The modulation wave signal of the V-phase bridge arm 1 is usv , the fully controlled devices are S from top to bottom v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' ; The modulation wave signal of the V-phase bridge arm 2 is u sv' , the fully controlled devices are S from top to bottom v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' ; The modulation wave signal of W phase bridge arm 1 is u sw , the fully controlled devices are S from top to bottom w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' ; The modulation wave signal of W phase bridge arm 2 is u sw' , the fully controlled devices are S from top to bottom w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' ; ω is the angular frequency of the inverter modulation signal, and the modulation wave signals of the six bridge arms of the inverter are calculated using the following formula;

[0029]

[0030] Step 2: Define the fully controlled device S u1 , S u2 , S u3 , S u4 , S u'1 , S u'2 , S u'3 , S u'4 , S v1 , S v2 , S v3 , S v4 , S v'1 , S v'2 , S v'3 , S v'4 , S w1 , S w2, S w3 , S w4 , S w'1 , S w'2 , S w'3 , S w'4 The corresponding modulation signals are u su1 、u su2 、u su3 、u su4 、u su '1, u su '2, u su '3.u su '4.u sv1 、u sv2 、u sv3 、u sv4 、u sv '1, u sv '2, u sv '3.u sv '4.u sw1 、u sw2 、u sw3 、u sw4 、u sw'1 、u sw'2 、u sw'3 、u sw'4 Each modulated signal is calculated using the following formula:

[0031]

[0032] Step 3: Define the fully controlled device S u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' , S u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' , S v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' , S v'1 , S v'2 , S v'3 , S v'4 , S v'1' , Sv'2' , S v'3' , S v'4' , S w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' , S w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' The corresponding drive signals are G su1 , G su2 , G su3 , G su4 , G su1' , G su2' , G su3' , G su4' , G su'1 , G su'2 , G su'3 , G su'4 , G su'1' , G su'2' , G su'3' , G su'4' , G sv1 , G sv2 , G sv3 , G sv4 , G sv1' , G sv2' , G sv3' , G sv4' , G sv'1 , G sv'2 , G sv'3 , G sv'4 , G sv'1' , G sv'2' , G sv'3' , G sv'4' , G sw1 , G sw2 , G sw3 , G sw4 , G sw1' , G sw2' , G sw3' , G sw4' , G sw'1 , G sw'2 , G sw'3 , G sw'4 , G sw'1' , G sw'2' , G sw'3' , Gsw'4' , all fully controlled devices at the inverter stage share the same carrier signal. su1 When the drive signal G is greater than the inverter-level carrier signal, su1 Output high level, output low level in other cases; drive signal G su1' With G su1 On the contrary; when u su2 When the drive signal G is greater than the inverter-level carrier signal, su2 Output high level, output low level in other cases; drive signal G su2' With G su2 On the contrary; when u su3 When the drive signal G is greater than the inverter-level carrier signal, su3 Output high level, output low level in other cases; drive signal G su3' With G su3 On the contrary; when u su4 When the drive signal G is greater than the inverter-level carrier signal, su3 Output high level, output low level in other cases; drive signal G su4' With G su4 On the contrary; when u su'1 When the drive signal G is greater than the inverter-level carrier signal, su'1 Output high level, output low level in other cases; drive signal G su'1' With G su'1 On the contrary; when u su'2 When the drive signal G is greater than the inverter-level carrier signal, su'2 Output high level, output low level in other cases; drive signal G su'2' With G su'2 On the contrary; when u su'3 When the drive signal G is greater than the inverter-level carrier signal, su'3 Output high level, output low level in other cases; drive signal G su'3' With G su'3 On the contrary; when u su'4 When the drive signal G is greater than the inverter-level carrier signal, su'3 Output high level, output low level in other cases; drive signal G su'4' With G su'4 On the contrary; when u sv1 When the drive signal G is greater than the inverter-level carrier signal, sv1 Output high level, output low level in other cases; drive signal G sv1' With G sv1 On the contrary; when u sv2 When the drive signal G is greater than the inverter-level carrier signal, sv2 Output high level, output low level in other cases; drive signal G sv2' With G sv2On the contrary; when u sv3 When the drive signal G is greater than the inverter-level carrier signal, sv3 Output high level, output low level in other cases; drive signal G sv3' With G sv3 On the contrary; when u sv4 When the drive signal G is greater than the inverter-level carrier signal, sv3 Output high level, output low level in other cases; drive signal G sv4' With G sv4 On the contrary; when u sv'1 When the drive signal G is greater than the inverter-level carrier signal, sv'1 Output high level, output low level in other cases; drive signal G sv'1' With G sv'1 On the contrary; when u sv'2 When the drive signal G is greater than the inverter-level carrier signal, sv'2 Output high level, output low level in other cases; drive signal G sv'2' With G sv'2 On the contrary; when u sv'3 When the drive signal G is greater than the inverter-level carrier signal, sv'3 Output high level, output low level in other cases; drive signal G sv'3' With G sv'3 On the contrary; when u sv'4 When the drive signal G is greater than the inverter-level carrier signal, sv'3 Output high level, output low level in other cases; drive signal G sv'4' With G sv'4 On the contrary; when u sw1 When the drive signal G is greater than the inverter-level carrier signal, sw1 Output high level, output low level in other cases; drive signal G sw1' With G sw1 On the contrary; when u sw2 When the drive signal G is greater than the inverter-level carrier signal, sw2 Output high level, output low level in other cases; drive signal G sw2' With G sw2 On the contrary; when u sw3 When the drive signal G is greater than the inverter-level carrier signal, sw3 Output high level, output low level in other cases; drive signal G sw3' With G sw3 On the contrary; when u sw4 When the drive signal G is greater than the inverter-level carrier signal, sw3 Output high level, output low level in other cases; drive signal G sw4' With G sw4 On the contrary; when u sw'1When the drive signal G is greater than the inverter-level carrier signal, sw'1 Output high level, output low level in other cases; drive signal G sw'1' With G sw'1 On the contrary; when u sw'2 When the drive signal G is greater than the inverter-level carrier signal, sw'2 Output high level, output low level in other cases; drive signal G sw'2' With G sw'2 On the contrary; when u sw'3 When the drive signal G is greater than the inverter-level carrier signal, sw'3 Output high level, output low level in other cases; drive signal G sw'3' With G sw'3 On the contrary; when u sw'4 When the drive signal G is greater than the inverter-level carrier signal, sw'3 Output high level, output low level in other cases; drive signal G sw'4' With G sw'4 on the contrary.

[0033] The above technical scheme conceived by the present invention has the following significant advantages compared with the prior art: the present invention first reduces the imbalance of the DC side capacitor voltage when the inverter is working by improving the inverter stage modulation method, and further realizes the DC side capacitor voltage balance control through the rectification stage control, which not only realizes the DC side capacitor voltage balance control, but also ensures the inverter stage output voltage waveform quality.

[0034] The following is a detailed description with reference to the accompanying drawings in conjunction with examples. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of a direct-connected five-level medium- and high-voltage frequency conversion system in an embodiment of the present invention;

[0036] Figure 2 It is the rectifier stage control strategy provided by the present invention;

[0037] Figure 3 The present invention provides a rectifier stage modulation method;

[0038] Figure 4 The inverter level modulation method provided by the present invention;

[0039] Figure 5 It is the equivalent carrier of the inverter-level modulation method provided by the present invention within different modulation ratio ranges;

[0040] Figure 6 It is the total voltage of the A-phase DC side, the voltage of each split capacitor on the DC side and the U-phase output current when the inverter stage constant voltage-frequency ratio is started provided by the present invention;

[0041] Figure 7 It is a multi-level voltage output by the U phase of the inverter stage when the inverter stage modulation ratio provided by the present invention is 1;

[0042] Figure 8 It is the multi-level voltage output by the U phase of the inverter stage when the inverter stage modulation ratio provided by the present invention is 0.8;

[0043] Fig. 9 It is the multi-level voltage output by the U phase of the inverter stage when the inverter stage modulation ratio provided by the present invention is 0.6;

[0044] Fig.10 It is the multi-level voltage output by the U phase of the inverter stage when the inverter stage modulation ratio provided by the present invention is 0.3;

[0045] Fig.11 It is the multi-level voltage output by the U-phase of the inverter stage when the inverter stage modulation ratio provided by the present invention is 0.2. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not limited to the present invention.

[0047] like Figure 1 As shown, the embodiment provides a schematic diagram of a direct-connected five-level medium- and high-voltage frequency conversion system, in which the rectifier input side adopts a star connection and the inverter output side adopts an open winding connection.

[0048] The present invention provides a simplified unidirectional energy flow five-level inverter capacitor voltage balance control strategy, including five parts: inverter stage imbalance calculation, rectifier stage maximum controllable imbalance calculation, rectifier stage control strategy, rectifier stage modulation method, inverter stage modulation method;

[0049] Calculation of inverter level imbalance:

[0050] Define h i is the unbalance degree generated by the inverter stage, m i is the inverter modulation ratio, and the unbalance degree generated by the inverter is calculated using the following formula, and h is taken i The maximum value of h imax ;

[0051]

[0052] Calculation of the maximum controllable imbalance of the rectifier stage:

[0053] Define V s is the phase voltage amplitude on the grid side, V dc is the rated value of DC side voltage, m ris the rectifier stage modulation ratio, and the rectifier stage modulation ratio is calculated using the following formula;

[0054]

[0055] Define h r is the controllable imbalance of the rectifier stage, and the controllable imbalance of the rectifier stage is calculated using the following formula;

[0056]

[0057] Compare r and h i size, and ensure that h r ≥h i , if h r <h i , then further modify the DC side voltage rating until h r and h i Satisfy h r ≥h i .

[0058] Figure 2 The rectifier stage control strategy provided by the present invention comprises the following steps:

[0059] Step 1: Sample the voltage of the three-phase DC side capacitors A, B, and C to obtain the voltage signal v of each DC side capacitor of the three-phase A, B, and C dca1 、v dca2 、v dca3 、v dca4 、v dcb1 、v dcb2 、v dcb3 、v dcb4 、v dcc1 、v dcc2 、v dcc3 、v dcc4 And the three-phase DC side total voltage signal v dca 、v dcb 、v dcc , average the total voltage of the three-phase DC side to get the average value of the total voltage of the DC side, and compare the average value of the total voltage of the DC side with the expected value of the DC side voltage V * dc The difference is sent to the PI regulator to obtain the expected current i required to maintain the DC side voltage stability. * dc ;

[0060] Step 2: Sample the current on the input side of the three-phase grid A, B, and C to obtain the current i on the input side of the three-phase grid a 、i b 、i c , use the following formula to calculate the A, B, C three-phase modulation wave signal usa 、u sb 、u sc ;

[0061]

[0062] Step 3: v dca1 and v dca2 Summing to get u a1 , v dca3 and v dca4 Summing to get u a2 ,u a1 and u a2 The difference is sent to the PI regulator to get u ab1 , v dca1 and v dca2 The difference is sent to the PI regulator to get u ab2 , v dca4 and v dca3 The difference is sent to the PI regulator to get u ab3 , use the following formula to calculate the A-phase rectifier stage fully controlled device S a1 , S a2 , S a3 , S a4 The modulated wave signal u sa1 、u sa2 、u sa3 、u sa4 ;

[0063]

[0064] v dcb1 and v dcb2 Summing to get u b1 , v dcb3 and v dcb4 Summing to get u b2 ,u b1 and u b2 The difference is sent to the PI regulator to get u bb1 , v dcb1 and v dcb2 The difference is sent to the PI regulator to get u bb2 , v dcb4 and v dcb3 The difference is sent to the PI regulator to get u bb3 , use the following formula to calculate the B-phase rectifier stage fully controlled device S b1 , S b2 , S b3 , S b4 The modulated wave signal u sb1 、u sb2 、u sb3 、u sb4 ;

[0065]

[0066] v dcc1 and v dcc2 Summing to get u c1 , v dcc3 and v dcc4 Summing to get u c2 ,u c1 and u c2 The difference is sent to the PI regulator to get u cb1 , v dcc1 and v dcc2 The difference is sent to the PI regulator to get u cb2 , v dcc4 and v dcc3 The difference is sent to the PI regulator to get u cb3 , the C-phase rectifier stage fully controlled device S is calculated using the following formula c1 , S c2 , S c3 , S c4 The modulated wave signal u sc1 、u sc2 、u sc3 、u sc4 .

[0067]

[0068] Figure 3 The present invention provides a rectifier stage modulation method, wherein the three-phase rectifier stage adopts a carrier phase shift modulation method, defines the rectifier stage to adopt four carrier signals of 0°, 90°, 180° and 270°, and defines the rectifier stage fully controlled device S a1 , S a2 , S a3 , S a4 , S b1 , S b2 , S b3 , S b4 , S c1 , S c2 , S c3 , S c4 The driving signals are G sa1 , G sa2 , G sa3 , G sa4 , G sb1 , G sb2 , G sb3 , G sb4 , G sc1 , G sc2 , G sc3 , G sc4 , when u sa1When the carrier signal is greater than 0°, the drive signal G sa1 Output high level, output low level in other cases; when u sa2 When the carrier signal is greater than 90°, the drive signal G sa2 Output high level, output low level in other cases; when u sa3 When the carrier signal is greater than 180°, the drive signal G sa3 Output high level, output low level in other cases; when u sa4 When the carrier signal is greater than 270°, the drive signal G sa4 Output high level, output low level in other cases; when u sb1 When the carrier signal is greater than 0°, the drive signal G sb1 Output high level, output low level in other cases; when u sb2 When the carrier signal is greater than 90°, the drive signal G sb2 Output high level, output low level in other cases; when u sb3 When the carrier signal is greater than 180°, the drive signal G sb3 Output high level, output low level in other cases; when u sb4 When the carrier signal is greater than 270°, the drive signal G sb4 Output high level, output low level in other cases; when u sc1 When the carrier signal is greater than 0°, the drive signal G sc1 Output high level, output low level in other cases; when u sc2 When the carrier signal is greater than 90°, the drive signal G sc2 Output high level, output low level in other cases; when u sc3 When the carrier signal is greater than 180°, the drive signal G sc3 Output high level, output low level in other cases; when u sc4 When the carrier signal is greater than 270°, the drive signal G sc4 Output high level in the other cases, output low level.

[0069] Figure 4 The inverter level modulation method provided by the present invention comprises the following steps:

[0070] Step 1: Define the modulation wave signal of the inverter U-phase bridge arm 1 as u su , the fully controlled devices are S from top to bottom u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' ; The modulation wave signal of U phase bridge arm 2 is u su', the fully controlled devices are S from top to bottom u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' ; The modulation wave signal of the V-phase bridge arm 1 is u sv , the fully controlled devices are S from top to bottom v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' ; The modulation wave signal of the V-phase bridge arm 2 is u sv' , the fully controlled devices are S from top to bottom v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' ; The modulation wave signal of W phase bridge arm 1 is u sw , the fully controlled devices are S from top to bottom w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' ; The modulation wave signal of W phase bridge arm 2 is u sw' , the fully controlled devices are S from top to bottom w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' ; ω is the angular frequency of the inverter modulation signal, and the modulation wave signals of the six bridge arms of the inverter are calculated using the following formula;

[0071]

[0072] Step 2: Define the fully controlled device S u1 , S u2 , S u3 , S u4 , S u'1 , S u'2 , S u'3 , S u'4 , Sv1 , S v2 , S v3 , S v4 , S v'1 , S v'2 , S v'3 , S v'4 , S w1 , S w2 , S w3 , S w4 , S w'1 , S w'2 , S w'3 , S w'4 The corresponding modulation signals are u su1 、u su2 、u su3 、u su4 、u su '1, u su '2, u su '3.u su '4.u sv1 、u sv2 、u sv3 、u sv4 、u sv '1, u sv '2, u sv '3.u sv '4.u sw1 、u sw2 、u sw3 、u sw4 、u sw'1 、u sw'2 、u sw'3 、u sw'4 Each modulated signal is calculated using the following formula:

[0073]

[0074]

[0075] Step 3: Define the fully controlled device S u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' , S u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' , Sv1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' , S v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' , S w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' , S w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' The corresponding drive signals are G su1 , G su2 , G su3 , G su4 , G su1' , G su2' , G su3' , G su4' , G su'1 , G su'2 , G su'3 , G su'4 , G su'1' , G su'2' , G su'3' , G su'4' , G sv1 , G sv2 , G sv3 , G sv4 , G sv1' , G sv2' , G sv3' , G sv4' , G sv'1 , G sv'2 , G sv'3 , G sv'4 , G sv'1' , G sv'2' , G sv'3' , G sv'4' , G sw1 , G sw2 , Gsw3 , G sw4 , G sw1' , G sw2' , G sw3' , G sw4' , G sw'1 , G sw'2 , G sw'3 , G sw'4 , G sw'1' , G sw'2' , G sw'3' , G sw'4' , all fully controlled devices at the inverter stage share the same carrier signal. su1 When the drive signal G is greater than the inverter-level carrier signal, su1 Output high level, output low level in other cases; drive signal G su1' With G su1 On the contrary; when u su2 When the drive signal G is greater than the inverter-level carrier signal, su2 Output high level, output low level in other cases; drive signal G su2' With G su2 On the contrary; when u su3 When the drive signal G is greater than the inverter-level carrier signal, su3 Output high level, output low level in other cases; drive signal G su3' With G su3 On the contrary; when u su4 When the drive signal G is greater than the inverter-level carrier signal, su3 Output high level, output low level in other cases; drive signal G su4' With G su4 On the contrary; when u su'1 When the drive signal G is greater than the inverter-level carrier signal, su'1 Output high level, output low level in other cases; drive signal G su'1' With G su'1 On the contrary; when u su'2 When the drive signal G is greater than the inverter-level carrier signal, su'2 Output high level, output low level in other cases; drive signal G su'2' With G su'2 On the contrary; when u su'3 When the drive signal G is greater than the inverter-level carrier signal, su'3 Output high level, output low level in other cases; drive signal G su'3' With G su'3 On the contrary; when u su'4 When the drive signal G is greater than the inverter-level carrier signal, su'3 Output high level, output low level in other cases; drive signal G su'4' With G su'4On the contrary; when u sv1 When the drive signal G is greater than the inverter-level carrier signal, sv1 Output high level, output low level in other cases; drive signal G sv1' With G sv1 On the contrary; when u sv2 When the drive signal G is greater than the inverter-level carrier signal, sv2 Output high level, output low level in other cases; drive signal G sv2' With G sv2 On the contrary; when u sv3 When the drive signal G is greater than the inverter-level carrier signal, sv3 Output high level, output low level in other cases; drive signal G sv3' With G sv3 On the contrary; when u sv4 When the drive signal G is greater than the inverter-level carrier signal, sv3 Output high level, output low level in other cases; drive signal G sv4' With G sv4 On the contrary; when u sv'1 When the drive signal G is greater than the inverter-level carrier signal, sv'1 Output high level, output low level in other cases; drive signal G sv'1' With G sv'1 On the contrary; when u sv'2 When the drive signal G is greater than the inverter-level carrier signal, sv'2 Output high level, output low level in other cases; drive signal G sv'2' With G sv'2 On the contrary; when u sv'3 When the drive signal G is greater than the inverter-level carrier signal, sv'3 Output high level, output low level in other cases; drive signal G sv'3' With G sv'3 On the contrary; when u sv'4 When the drive signal G is greater than the inverter-level carrier signal, sv'3 Output high level, output low level in other cases; drive signal G sv'4' With G sv'4 On the contrary; when u sw1 When the drive signal G is greater than the inverter-level carrier signal, sw1 Output high level, output low level in other cases; drive signal G sw1' With G sw1 On the contrary; when u sw2 When the drive signal G is greater than the inverter-level carrier signal, sw2 Output high level, output low level in other cases; drive signal G sw2' With G sw2 On the contrary; when u sw3When the drive signal G is greater than the inverter-level carrier signal, sw3 Output high level, output low level in other cases; drive signal G sw3' With G sw3 On the contrary; when u sw4 When the drive signal G is greater than the inverter-level carrier signal, sw3 Output high level, output low level in other cases; drive signal G sw4' With G sw4 On the contrary; when u sw'1 When the drive signal G is greater than the inverter-level carrier signal, sw'1 Output high level, output low level in other cases; drive signal G sw'1' With G sw'1 On the contrary; when u sw'2 When the drive signal G is greater than the inverter-level carrier signal, sw'2 Output high level, output low level in other cases; drive signal G sw'2' With G sw'2 On the contrary; when u sw'3 When the drive signal G is greater than the inverter-level carrier signal, sw'3 Output high level, output low level in other cases; drive signal G sw'3' With G sw'3 On the contrary; when u sw'4 When the drive signal G is greater than the inverter-level carrier signal, sw'3 Output high level, output low level in other cases; drive signal G sw'4' With G sw'4 on the contrary.

[0076] Figure 5 It is the equivalent carrier of the inverter level modulation method provided by the present invention in different modulation ratio ranges, including a carrier in a high modulation ratio range, a carrier in a medium modulation ratio range and a carrier in a low modulation ratio range.

[0077] Figure 6 It is the total voltage on the DC side of phase A, the voltage of each split capacitor on the DC side and the output current of phase U when the inverter stage constant voltage-frequency ratio is started provided by the present invention. It can be seen that when the inverter stage constant voltage-frequency ratio is started, the total voltage on the DC side of phase A and the voltage of each split capacitor on the DC side are kept balanced, and the proposed control strategy can maintain balance within the full modulation ratio range of the inverter stage.

[0078] Figure 7 This is the multi-level voltage output by the U-phase of the inverter stage when the inverter stage modulation ratio provided by the present invention is 1. It can be clearly seen that the output voltage has 9 levels in total.

[0079] Figure 8 This is the multi-level voltage output by the inverter stage U phase when the inverter stage modulation ratio provided by the present invention is 0.8. It can be clearly seen that the output voltage has 9 levels in total.

[0080] Fig. 9 This is the multi-level voltage output by the U-phase of the inverter stage when the inverter stage modulation ratio provided by the present invention is 0.6. It can be clearly seen that the output voltage has 7 levels in total.

[0081] Fig.10 This is the multi-level voltage output by the U-phase of the inverter stage when the inverter stage modulation ratio provided by the present invention is 0.3. It can be clearly seen that the output voltage has 5 levels in total.

[0082] Fig.11 This is the multi-level voltage output by the U-phase of the inverter stage when the inverter stage modulation ratio provided by the present invention is 0.2. It can be clearly seen that the output voltage has three levels in total.

[0083] pass Figure 7-Figure 11 It can be seen that the proposed control strategy can maintain the inverter output voltage at a lower THD while ensuring the balanced control of the DC side capacitor voltage.

[0084] It is easy for those skilled in the art to understand that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. The scope of use of each modulation wave of the inverter stage is not limited to the scope shown in the embodiment. Through corresponding modifications, the control strategy provided by the invention is also applicable. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. The present invention provides a simplified unidirectional energy flow five-level inverter capacitor voltage balance control strategy, which relates to a unidirectional energy flow direct-connected five-level medium and high voltage inverter, characterized in that: It includes five parts: calculation of inverter-level imbalance, calculation of maximum controllable imbalance of rectifier-level, rectifier-level control strategy, rectifier-level modulation method, and inverter-level modulation method; Calculation of inverter level imbalance: Define h i is the unbalance degree generated by the inverter stage, m i is the inverter modulation ratio, and the unbalance degree generated by the inverter is calculated using the following formula, and h is taken i The maximum value of h imax ; Calculation of the maximum controllable imbalance of the rectifier stage: Define V s is the phase voltage amplitude on the grid side, V dc is the rated value of DC side voltage, m r is the rectifier stage modulation ratio, and the rectifier stage modulation ratio is calculated using the following formula; Define h r is the controllable imbalance of the rectifier stage, and the controllable imbalance of the rectifier stage is calculated using the following formula; Compare r and h i size, and ensure that h r ≥h i , if h r <h i , then further modify the DC side voltage rating until h r and h i Satisfy h r ≥h i ; Rectification stage control strategy: Step 1: Sample the voltage of the three-phase DC side capacitors A, B, and C to obtain the voltage signal v of each DC side capacitor of the three-phase A, B, and C dca1 、v dca2 、v dca3 、v dca4 、v dcb1 、v dcb2 、v dcb3 、v dcb4 、v dcc1 、v dcc2 、v dcc3 、v dcc4 And the three-phase DC side total voltage signal v dca 、v dcb 、v dcc , average the total voltage of the three-phase DC side to get the average value of the total voltage of the DC side, and compare the average value of the total voltage of the DC side with the expected value of the DC side voltage V * dc The difference is sent to the PI regulator to obtain the expected current i required to maintain the DC side voltage stability. * dc ; Step 2: Sample the current on the input side of the three-phase grid A, B, and C to obtain the current i on the input side of the three-phase grid a 、i b 、i c , use the following formula to calculate the A, B, C three-phase modulation wave signal u sa 、u sb 、u sc ; Step 3: v dca1 and v dca2 Summing to get u a1 , v dca3 and v dca4 Summing to get u a2 ,u a1 and u a2 The difference is sent to the PI regulator to get u ab1 , v dca1 and v dca2 The difference is sent to the PI regulator to get u ab2 , v dca4 and v dca3 The difference is sent to the PI regulator to get u ab3 , use the following formula to calculate the A-phase rectifier stage fully controlled device S a1 , S a2 , S a3 , S a4 The modulated wave signal u sa1 、u sa2 、u sa3 、u sa4 ; v dcb1 and v dcb2 Summing to get u b1 , v dcb3 and v dcb4 Summing to get u b2 ,u b1 and u b2 The difference is sent to the PI regulator to get u bb1 , v dcb1 and v dcb2 The difference is sent to the PI regulator to get u bb2 , v dcb4 and v dcb3 The difference is sent to the PI regulator to get u bb3 , use the following formula to calculate the B-phase rectifier stage fully controlled device S b1 , S b2 , S b3 , S b4 The modulated wave signal u sb1 、u sb2 、u sb3 、u sb4 ; v dcc1 and v dcc2 Summing to get u c1 , v dcc3 and v dcc4 Summing to get u c2 ,u c1 and u c2 The difference is sent to the PI regulator to get u cb1 , v dcc1 and v dcc2 The difference is sent to the PI regulator to get u cb2 , v dcc4 and v dcc3 The difference is sent to the PI regulator to get u cb3 , the C-phase rectifier stage fully controlled device S is calculated using the following formula c1 , S c2 , S c3 , S c4 The modulated wave signal u sc1 、u sc2 、u sc3 、u sc4 ; Rectification stage modulation method: The three-phase rectifier stage adopts the modulation method of carrier phase shift, and defines the rectifier stage to use four carrier signals of 0°, 90°, 180° and 270°, and defines the rectifier stage fully controlled device S a1 , S a2 , S a3 , S a4 , S b1 , S b2 , S b3 , S b4 , S c1 , S c2 , S c3 , S c4 The driving signals are G sa1 , G sa2 , G sa3 , G sa4 , G sb1 , G sb2 , G sb3 , G sb4 , G sc1 , G sc2 , G sc3 , G sc4 , when u sa1 When the carrier signal is greater than 0°, the drive signal G sa1 Output high level, output low level in other cases; when u sa2 When the carrier signal is greater than 90°, the drive signal G sa2 Output high level, output low level in other cases; when u sa3 When the carrier signal is greater than 180°, the drive signal G sa3 Output high level, output low level in other cases; when u sa4 When the carrier signal is greater than 270°, the drive signal G sa4 Output high level, output low level in other cases; when u sb1 When the carrier signal is greater than 0°, the drive signal G sb1 Output high level, output low level in other cases; when u sb2 When the carrier signal is greater than 90°, the drive signal G sb2 Output high level, output low level in other cases; when u sb3 When the carrier signal is greater than 180°, the drive signal G sb3 Output high level, output low level in other cases; when u sb4 When the carrier signal is greater than 270°, the drive signal G sb4 Output high level, output low level in other cases; when u sc1 When the carrier signal is greater than 0°, the drive signal G sc1 Output high level, output low level in other cases; when u sc2 When the carrier signal is greater than 90°, the drive signal G sc2 Output high level, output low level in other cases; when u sc3 When the carrier signal is greater than 180°, the drive signal G sc3 Output high level, output low level in other cases; when u sc4 When the carrier signal is greater than 270°, the drive signal G sc4 Output high level, and output low level in other cases; Inverter level modulation method: Step 1: Define the modulation wave signal of the inverter U-phase bridge arm 1 as u su , the fully controlled devices are S from top to bottom u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' ; The modulation wave signal of U phase bridge arm 2 is u su' , the fully controlled devices are S from top to bottom u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' ; The modulation wave signal of the V-phase bridge arm 1 is u sv , the fully controlled devices are S from top to bottom v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' ; The modulation wave signal of the V-phase bridge arm 2 is u sv' , the fully controlled devices are S from top to bottom v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' ; The modulation wave signal of W phase bridge arm 1 is u sw , the fully controlled devices are S from top to bottom w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' ; The modulation wave signal of W phase bridge arm 2 is u sw' , the fully controlled devices are S from top to bottom w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' ; ω is the angular frequency of the inverter modulation signal, and the modulation wave signals of the six bridge arms of the inverter are calculated using the following formula; Step 2: Define the fully controlled device S u1 , S u2 , S u3 , S u4 , S u'1 , S u'2 , S u'3 , S u'4 , S v1 , S v2 , S v3 , S v4 , S v'1 , S v'2 , S v'3 , S v'4 , S w1 , S w2 , S w3 , S w4 , S w'1 , S w'2 , S w'3 , S w'4 The corresponding modulation signals are u su1 、u su2 、u su3 、u su4 、u su '1, u su '2, u su '3.u su '4.u sv1 、u sv2 、u sv3 、u sv4 、u sv '1, u sv '2, u sv '3.u sv '4.u sw1 、u sw2 、u sw3 、u sw4 、u sw'1 、u sw'2 、u sw'3 、u sw'4 Each modulated signal is calculated using the following formula: Step 3: Define the fully controlled device S u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' , S u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' , S v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' , S v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' , S w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' , S w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' The corresponding driving signals are G su1 , G su2 , G su3 , G su4 , G su1' , G su2' , G su3' , G su4' , G su'1 , G su'2 , G su'3 , G su'4 , G su'1' , G su'2' , G su'3' , G su'4' , G sv1 , G sv2 , G sv3 , G sv4 , G sv1' , G sv2' , G sv3' , G sv4' , G sv'1 , G sv'2 , G sv'3 , G sv'4 , G sv'1' , G sv'2' , G sv'3' , G sv'4' , G sw1 , G sw2 , G sw3 , G sw4 , G sw1' , G sw2' , G sw3' , G sw4' , G sw'1 , G sw'2 , G sw'3 , G sw'4 , G sw'1' , G sw'2' , G sw'3' , G sw'4' , all fully controlled devices at the inverter stage share the same carrier signal. su1 When the drive signal G is greater than the inverter-level carrier signal, su1 Output high level, output low level in other cases; drive signal G su1' With G su1 On the contrary; when u su2 When the drive signal G is greater than the inverter-level carrier signal, su2 Output high level, output low level in other cases; drive signal G su2' With G su2 On the contrary; when u su3 When the drive signal G is greater than the inverter-level carrier signal, su3 Output high level, output low level in other cases; drive signal G su3' With G su3 On the contrary; when u su4 When the drive signal G is greater than the inverter-level carrier signal, su3 Output high level, output low level in other cases; drive signal G su4' With G su4 On the contrary; when u su'1 When the drive signal G is greater than the inverter-level carrier signal, su'1 Output high level, output low level in other cases; drive signal G su'1' With G su'1 On the contrary; when u su'2 When the drive signal G is greater than the inverter-level carrier signal, su'2 Output high level, output low level in other cases; drive signal G su'2' With G su'2 On the contrary; when u su'3 When the drive signal G is greater than the inverter-level carrier signal, su'3 Output high level, output low level in other cases; drive signal G su'3' With G su'3 On the contrary; when u su'4 When the drive signal G is greater than the inverter-level carrier signal, su'3 Output high level, output low level in other cases; drive signal G su'4' With G su'4 On the contrary; when u sv1 When the drive signal G is greater than the inverter-level carrier signal, sv1 Output high level, output low level in other cases; drive signal G sv1' With G sv1 On the contrary; when u sv2 When the drive signal G is greater than the inverter-level carrier signal, sv2 Output high level, output low level in other cases; drive signal G sv2' With G sv2 On the contrary; when u sv3 When the drive signal G is greater than the inverter-level carrier signal, sv3 Output high level, output low level in other cases; drive signal G sv3' With G sv3 On the contrary; when u sv4 When the drive signal G is greater than the inverter-level carrier signal, sv3 Output high level, output low level in other cases; drive signal G sv4' With G sv4 On the contrary; when u sv'1 When the drive signal G is greater than the inverter-level carrier signal, sv'1 Output high level, output low level in other cases; drive signal G sv'1' With G sv'1 On the contrary; when u sv'2 When the drive signal G is greater than the inverter-level carrier signal, sv'2 Output high level, output low level in other cases; drive signal G sv'2' With G sv'2 On the contrary; when u sv'3 When the drive signal G is greater than the inverter-level carrier signal, sv'3 Output high level, output low level in other cases; drive signal G sv'3' With G sv'3 On the contrary; when u sv'4 When the drive signal G is greater than the inverter-level carrier signal, sv'3 Output high level, output low level in other cases; drive signal G sv'4' With G sv'4 On the contrary; when u sw1 When the drive signal G is greater than the inverter-level carrier signal, sw1 Output high level, output low level in other cases; drive signal G sw1' With G sw1 On the contrary; when u sw2 When the drive signal G is greater than the inverter-level carrier signal, sw2 Output high level, output low level in other cases; drive signal G sw2' With G sw2 On the contrary; when u sw3 When the drive signal G is greater than the inverter-level carrier signal, sw3 Output high level, output low level in other cases; drive signal G sw3' With G sw3 On the contrary; when u sw4 When the drive signal G is greater than the inverter-level carrier signal, sw3 Output high level, output low level in other cases; drive signal G sw4' With G sw4 On the contrary; when u sw'1 When the drive signal G is greater than the inverter-level carrier signal, sw'1 Output high level, output low level in other cases; drive signal G sw'1' With G sw'1 On the contrary; when u sw'2 When the drive signal G is greater than the inverter-level carrier signal, sw'2 Output high level, output low level in other cases; drive signal G sw'2' With G sw'2 On the contrary; when u sw'3 When the drive signal G is greater than the inverter-level carrier signal, sw'3 Output high level, output low level in other cases; drive signal G sw'3' With G sw'3 On the contrary; when u sw'4 When the drive signal G is greater than the inverter-level carrier signal, sw'3 Output high level, output low level in other cases; drive signal G sw'4' With G sw'4 on the contrary.

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