A Simplified Control Strategy for Capacitor Voltage Balancing of Unidirectional Energy-Flow Five-Level Inverters

Abstract

The present invention discloses a simplified control strategy for capacitor voltage balance of a unidirectional energy flow five-level frequency converter, which relates to a unidirectional energy flow direct-connected type medium-voltage and high-voltage five-level frequency converter, and includes five parts: calculation of the imbalance degree of the inverter stage, calculation of the DC side voltage, control strategy of the rectifier stage, modulation method of the rectifier stage, and modulation method of the inverter stage. The purpose is to solve the problems of difficult capacitor voltage balance control on the DC side of the five-level frequency converter and poor quality of the output voltage waveform. Compared with the prior art, the remarkable advantages of the present invention are as follows: Firstly, the present invention reduces the imbalance degree generated by the inverter on the DC side capacitor voltage during operation by improving the modulation method of the inverter stage, and further realizes the capacitor voltage balance control on the DC side through the control of the rectifier stage, which not only realizes the capacitor voltage balance control on the DC side, but also ensures the quality of the output voltage waveform of the inverter stage.

Description

Technical Field

[0001] The present invention belongs to the technical field of medium and high voltage variable frequency speed regulation, and more specifically, relates to a simplified capacitor voltage balance control strategy for a transformerless isolated unidirectional energy flow three-phase five-level medium and high voltage inverter. Background Art

[0002] In recent years, multilevel converters have been increasingly successfully applied in fields such as high voltage and high power variable frequency speed regulation, active power filtering, high voltage direct current (HVDC) transmission, and reactive power compensation in power systems. The basic circuit topologies of multilevel converters can be roughly divided into two categories: clamped type and cascaded cell type. Currently, the most widely used unidirectional energy flow diode clamped three-level medium and high voltage inverter in industry, as well as the unidirectional energy flow cascaded H-bridge medium and high voltage inverter, are typical representatives of these two types of products. In these two types of medium and high voltage inverters, no matter which type, in order to use low-voltage withstand power electronic devices to complete high-voltage power conversion and suppress the harmonics of the input current, a large-sized, complex-wired, and expensive industrial frequency phase-shifting transformer is required on the input side of the rectifier. This limits its application in many industrial scenarios. In order to eliminate the industrial frequency phase-shifting transformer, the academic and industrial communities have tried to use high-frequency isolation DC-DC converters to connect the cascaded rectifier stage and the cascaded inverter stage to form a new type of medium and high voltage inverter. Compared with traditional medium and high voltage inverters, the rectifier stage implementation scheme of this new type of medium and high voltage inverter eliminates the large-sized, complex-wired, and expensive industrial frequency phase-shifting transformer, thus effectively reducing the system volume, weight, and manufacturing cost. However, this new type of medium and high voltage inverter also has obvious disadvantages, mainly manifested in that it is very difficult to design and implement a high-power density and high-efficiency high-frequency isolation DC / DC converter, which has become the main bottleneck for this new type of medium and high voltage inverter to truly enter practical use. For this reason, in recent years, a new generation of medium and high voltage inverters with direct connection between the cascaded rectifier stage and the cascaded inverter stage has received increasing attention in the field of power electronics technology. Among them, a new generation of direct-connected medium and high voltage inverter composed of a Y-connected three single-phase diode cascaded Boost rectifier circuit + a three single-phase multilevel inverter circuit connected to the motor in an open winding is one of the typical solutions. This new type of topology neither requires industrial frequency transformer isolation nor high-frequency isolation DC conversion units, thus greatly reducing its volume, structure, cost, and control complexity, showing great practical advantages.

[0003] Although the direct-connected new generation medium-voltage frequency converter shows obvious advantages, there are still some problems that must be solved in practical engineering applications. For example, the DC-side capacitor voltage balance control of the five-level frequency converter is an inherent control difficulty of the five-level NPC converter. The imbalance of the DC-side capacitor voltage will not only cause the output waveform quality of the frequency converter to deteriorate, but also cause equipment damage, seriously affecting production safety. Most of the existing neutral point potential balance control methods for the five-level converter adopt independent control at the inverter stage. The disadvantage of such methods is that the harmonic content of the output voltage is relatively high. For the frequency converter, its rectifier stage still has the ability to control the DC-side capacitor voltage balance. Therefore, through the cooperation of the rectifier stage and the inverter stage, the DC-side capacitor voltage balance control can be achieved, and the output voltage waveform quality of the inverter stage can be guaranteed. Summary of the Invention

[0004] Aiming at the defects of the existing technology, the purpose of the present invention is to provide a capacitor voltage balance control strategy for the above-mentioned direct-connected new generation five-level medium-voltage frequency converter, aiming to solve the problems of difficult DC-side capacitor voltage balance control and poor output voltage waveform quality of the five-level frequency converter.

[0005] To achieve the above purpose, the present invention provides a simplified unidirectional power flow five-level frequency converter capacitor voltage balance control strategy, which relates to a unidirectional power flow direct-connected five-level medium-voltage frequency converter, and is characterized in that it includes five parts: inverter stage imbalance calculation, rectifier stage maximum controllable imbalance calculation, rectifier stage control strategy, rectifier stage modulation method, and inverter stage modulation method;

[0006] Inverter stage imbalance calculation:

[0007] Define h i as the imbalance generated by the inverter stage, and m i as the modulation ratio of the inverter stage. The imbalance generated by the inverter stage is calculated using the following formula, and the maximum value of h i is taken as h imax ;

[0008]

[0009] Rectifier stage maximum controllable imbalance calculation:

[0010] Define V s as the amplitude of the grid-side phase voltage, V dc as the rated value of the DC-side voltage, and m r as the modulation ratio of the rectifier stage. The modulation ratio of the rectifier stage is calculated using the following formula;

[0011]

[0012] Define h rThe unbalance degree that can be controlled by the rectifier stage is calculated using the following formula;

[0013]

[0014] Compare h r and h i and ensure that h r ≥h i . If h r <h i , then further modify the DC-side voltage rating until h r and h i satisfy h r ≥h i ;

[0015] Rectifier stage control strategy:

[0016] Step 1: Sample the DC-side capacitor voltages of phases A, B, and C to obtain the DC-side capacitor voltage signals v dca1 , v dca2 , v dca3 , v dca4 , v dcb1 , v dcb2 , v dcb3 , v dcb4 , v dcc1 , v dcc2 , v dcc3 , v dcc4 and the total DC-side voltage signals v dca , v dcb , v dcc . Calculate the average value of the total DC-side voltage by averaging the total DC-side voltages of the three phases, and send the difference between the average value of the total DC-side voltage and the expected DC-side voltage V * dc to a PI regulator to obtain the desired current i * dc ;

[0017] Step 2: Sample the grid input currents of phases A, B, and C to obtain the grid input currents i a , i b , i c , and calculate the modulation wave signals u sa , u sb , u sc of phases A, B, and C using the following formula;

[0018]

[0019] Step 3: v dca1 and vdca2 Sum to obtain u a1 , v dca3 and v dca4 Sum to obtain u a2 , u a1 and u a2 Take the difference and send it to the PI regulator to obtain u ab1 , v dca1 and v dca2 Take the difference and send it to the PI regulator to obtain u ab2 , v dca4 and v dca3 Take the difference and send it to the PI regulator to obtain u ab3 , and calculate the modulation wave signals u a1 、S a2 、S a3 、S a4 、S sa1 、u sa2 、u sa3 、u sa4 ;

[0020]

[0021] v dcb1 and v dcb2 Sum to obtain u b1 , v dcb3 and v dcb4 Sum to obtain u b2 , u b1 and u b2 Take the difference and send it to the PI regulator to obtain u bb1 , v dcb1 and v dcb2 Take the difference and send it to the PI regulator to obtain u bb2 , v dcb4 and v dcb3 Take the difference and send it to the PI regulator to obtain u bb3 , and calculate the modulation wave signals u b1 、S b2 、S b3 、S b4 、S sb1 、u sb2 、u sb3 、u sb4 ;

[0022]

[0023] v dcc1 and v dcc2 Sum to obtain u c1 , v dcc3 and v dcc4Sum to obtain u c2 , u c1 and u c2 Take the difference and send it to the PI regulator to obtain u cb1 , v dcc1 and v dcc2 Take the difference and send it to the PI regulator to obtain u cb2 , v dcc4 and v dcc3 Take the difference and send it to the PI regulator to obtain u cb3 , Calculate the modulation wave signals u c1 , S c2 , S c3 , S c4 of the fully controlled devices S sc1 , u sc2 , u sc3 , u sc4 ;

[0024]

[0025] Rectifier stage modulation method:

[0026] The three-phase rectifier stage adopts the carrier phase-shifting modulation method. Define four carrier signals of 0°, 90°, 180°, and 270° for the rectifier stage. Define the drive signals of the fully controlled devices S a1 , S a2 , S a3 , S a4 , S b1 , S b2 , S b3 , S b4 , S c1 , S c2 , S c3 , S c4 as G sa1 , G sa2 , G sa3 , G sa4 , G sb1 , G sb2 , G sb3 , G sb4 , G sc1 , G sc2 , G sc3 , G sc4 , When u sa1 is greater than the 0° carrier signal, the drive signal G sa1 outputs a high level, and outputs a low level in other cases; when u sa2 is greater than the 90° carrier signal, the drive signal G sa2 outputs a high level, and outputs a low level in other cases; when u sa3When the carrier signal is greater than 180°, the drive signal G sa3 outputs a high level, and outputs a low level in other cases; when u sa4 When the carrier signal is greater than 270°, the drive signal G sa4 outputs a high level, and outputs a low level in other cases; when u sb1 When the carrier signal is greater than 0°, the drive signal G sb1 outputs a high level, and outputs a low level in other cases; when u sb2 When the carrier signal is greater than 90°, the drive signal G sb2 outputs a high level, and outputs a low level in other cases; when u sb3 When the carrier signal is greater than 180°, the drive signal G sb3 outputs a high level, and outputs a low level in other cases; when u sb4 When the carrier signal is greater than 270°, the drive signal G sb4 outputs a high level, and outputs a low level in other cases; when u sc1 When the carrier signal is greater than 0°, the drive signal G sc1 outputs a high level, and outputs a low level in other cases; when u sc2 When the carrier signal is greater than 90°, the drive signal G sc2 outputs a high level, and outputs a low level in other cases; when u sc3 When the carrier signal is greater than 180°, the drive signal G sc3 outputs a high level, and outputs a low level in other cases; when u sc4 When the carrier signal is greater than 270°, the drive signal G sc4 outputs a high level, and outputs a low level in other cases;

[0027] Inverter stage modulation method:

[0028] Step 1: Define the modulation wave signal of the U-phase bridge arm 1 of the inverter stage as u su , and the fully controlled devices are S u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' ; The modulation wave signal of the U-phase bridge arm 2 is u su' , and the fully controlled devices are S u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' ; The modulation wave signal of the V-phase bridge arm 1 is usv , the fully controlled devices from top to bottom are S v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' ; the modulating wave signal of the V-phase bridge arm 2 is u sv' , the fully controlled devices from top to bottom are S v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' ; the modulating wave signal of the W-phase bridge arm 1 is u sw , the fully controlled devices from top to bottom are S w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' ; the modulating wave signal of the W-phase bridge arm 2 is u sw' , the fully controlled devices from top to bottom are S w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' ; ω is the angular frequency of the inverter-stage modulation signal, and the modulating wave signals of the six bridge arms of the inverter stage are calculated using the following formula;

[0029]

[0030] Step 2: Define the fully controlled devices S u1 , S u2 , S u3 , S u4 , S u'1 , S u'2 , S u'3 , S u'4 , S v1 , S v2 , S v3 , S v4 , S v'1 , S v'2 , S v'3 , S v'4 , S w1 , S w2, S w3 , S w4 , S w'1 , S w'2 , S w'3 , S w'4 The corresponding modulation signals are respectively u su1 , u su2 , u su3 , u su4 , u su '1, u su '2, u su '3, u su '4, u sv1 , u sv2 , u sv3 , u sv4 , u sv '1, u sv '2, u sv '3, u sv '4, u sw1 , u sw2 , u sw3 , u sw4 , u sw'1 , u sw'2 , u sw'3 , u sw'4 The respective modulation signals are calculated using the following formula;

[0031]

[0032] Step 3: Define fully controlled devices S u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' , S u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' , S v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' , S v'1 , S v'2 , S v'3 , S v'4 , S v'1' , Sv'2' , S v'3' , S v'4' , S w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' , S w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' The corresponding drive signals are G su1 , G su2 , G su3 , G su4 , G su1' , G su2' , G su3' , G su4' , G su'1 , G su'2 , G su'3 , G su'4 , G su'1' , G su'2' , G su'3' , G su'4' , G sv1 , G sv2 , G sv3 , G sv4 , G sv1' , G sv2' , G sv3' , G sv4' , G sv'1 , G sv'2 , G sv'3 , G sv'4 , G sv'1' , G sv'2' , G sv'3' , G sv'4' , G sw1 , G sw2 , G sw3 , G sw4 , G sw1' , G sw2' , G sw3' , G sw4' , G sw'1 , G sw'2 , G sw'3 , G sw'4 , G sw'1' , G sw'2' , G sw'3' , Gsw'4' , all fully controlled devices in the inverter stage share the same carrier signal. When u su1 is greater than the carrier signal of the inverter stage, the drive signal G su1 outputs a high level, and outputs a low level in other cases; the drive signal G su1' is opposite to G su1 ; when u su2 is greater than the carrier signal of the inverter stage, the drive signal G su2 outputs a high level, and outputs a low level in other cases; the drive signal G su2' is opposite to G su2 ; when u su3 is greater than the carrier signal of the inverter stage, the drive signal G su3 outputs a high level, and outputs a low level in other cases; the drive signal G su3' is opposite to G su3 ; when u su4 is greater than the carrier signal of the inverter stage, the drive signal G su4 outputs a high level, and outputs a low level in other cases; the drive signal G su4' is opposite to G su4 ; when u su'1 is greater than the carrier signal of the inverter stage, the drive signal G su'1 outputs a high level, and outputs a low level in other cases; the drive signal G su'1' is opposite to G su'1 ; when u su'2 is greater than the carrier signal of the inverter stage, the drive signal G su'2 outputs a high level, and outputs a low level in other cases; the drive signal G su'2' is opposite to G su'2 ; when u su'3 is greater than the carrier signal of the inverter stage, the drive signal G su'3 outputs a high level, and outputs a low level in other cases; the drive signal G su'3' is opposite to G su'3 ; when u su'4 is greater than the carrier signal of the inverter stage, the drive signal G su'4 outputs a high level, and outputs a low level in other cases; the drive signal G su'4' is opposite to G su'4 ; when u sv1 is greater than the carrier signal of the inverter stage, the drive signal G sv1 outputs a high level, and outputs a low level in other cases; the drive signal G sv1' is opposite to G sv1 ; when u sv2 is greater than the carrier signal of the inverter stage, the drive signal G sv2 outputs a high level, and outputs a low level in other cases; the drive signal G sv2' is opposite to G sv2On the contrary; when u sv3 is greater than the inverter-stage carrier signal, the drive signal G sv3 outputs a high level, and outputs a low level in other cases; the drive signal G sv3' is opposite to G sv3 On the contrary; when u sv4 is greater than the inverter-stage carrier signal, the drive signal G sv4 outputs a high level, and outputs a low level in other cases; the drive signal G sv4' is opposite to G sv4 On the contrary; when u sv'1 is greater than the inverter-stage carrier signal, the drive signal G sv'1 outputs a high level, and outputs a low level in other cases; the drive signal G sv'1' is opposite to G sv'1 On the contrary; when u sv'2 is greater than the inverter-stage carrier signal, the drive signal G sv'2 outputs a high level, and outputs a low level in other cases; the drive signal G sv'2' is opposite to G sv'2 On the contrary; when u sv'3 is greater than the inverter-stage carrier signal, the drive signal G sv'3 outputs a high level, and outputs a low level in other cases; the drive signal G sv'3' is opposite to G sv'3 On the contrary; when u sv'4 is greater than the inverter-stage carrier signal, the drive signal G sv'4 outputs a high level, and outputs a low level in other cases; the drive signal G sv'4' is opposite to G sv'4 On the contrary; when u sw1 is greater than the inverter-stage carrier signal, the drive signal G sw1 outputs a high level, and outputs a low level in other cases; the drive signal G sw1' is opposite to G sw1 On the contrary; when u sw2 is greater than the inverter-stage carrier signal, the drive signal G sw2 outputs a high level, and outputs a low level in other cases; the drive signal G sw2' is opposite to G sw2 On the contrary; when u sw3 is greater than the inverter-stage carrier signal, the drive signal G sw3 outputs a high level, and outputs a low level in other cases; the drive signal G sw3' is opposite to G sw3 On the contrary; when u sw4 is greater than the inverter-stage carrier signal, the drive signal G sw4 outputs a high level, and outputs a low level in other cases; the drive signal G sw4' is opposite to G sw4 On the contrary; when u sw'1When it is greater than the inverter - stage carrier signal, the drive signal G sw'1 outputs a high level, and outputs a low level in other cases; the drive signal G sw'1' is opposite to G sw'1 ; when u sw'2 is greater than the inverter - stage carrier signal, the drive signal G sw'2 outputs a high level, and outputs a low level in other cases; the drive signal G sw'2' is opposite to G sw'2 ; when u sw'3 is greater than the inverter - stage carrier signal, the drive signal G sw'3 outputs a high level, and outputs a low level in other cases; the drive signal G sw'3' is opposite to G sw'3 ; when u sw'4 is greater than the inverter - stage carrier signal, the drive signal G sw'4 outputs a high level, and outputs a low level in other cases; the drive signal G sw'4' is opposite to G sw'4 is opposite.

[0033] Through the above - mentioned technical solution conceived by the present invention, compared with the prior art, its remarkable advantages are as follows: Firstly, the present invention reduces the unbalance degree of the DC - side capacitor voltage during the operation of the inverter by improving the inverter - stage modulation method, and further realizes the balance control of the DC - side capacitor voltage through the rectifier - stage control. It not only realizes the balance control of the DC - side capacitor voltage but also ensures the quality of the output voltage waveform of the inverter - stage.

[0034] The following will be described in detail with reference to the embodiments and the accompanying drawings. Description of the Drawings

[0035] Figure 1 is a schematic diagram of a direct - connection type five - level medium - voltage variable - frequency system in an embodiment of the present invention;

[0036] Figure 2 is the rectifier - stage control strategy provided by the present invention;

[0037] Figure 3 is the rectifier - stage modulation method provided by the present invention;

[0038] Figure 4 is the inverter - stage modulation method provided by the present invention;

[0039] Figure 5 is the equivalent carrier of the inverter - stage modulation method provided by the present invention within different modulation - ratio ranges;

[0040] Figure 6 is the total DC - side voltage of phase A, the voltages of each split capacitor on the DC - side, and the output current of phase U during the constant V / f start of the inverter - stage provided by the present invention;

[0041] Figure 7 is the multilevel voltage output by the U-phase of the inverter stage when the modulation ratio of the inverter stage is 1 provided by the present invention;

[0042] Figure 8 is the multilevel voltage output by the U-phase of the inverter stage when the modulation ratio of the inverter stage is 0.8 provided by the present invention;

[0043] Figure 9 is the multilevel voltage output by the U-phase of the inverter stage when the modulation ratio of the inverter stage is 0.6 provided by the present invention;

[0044] Figure 10 is the multilevel voltage output by the U-phase of the inverter stage when the modulation ratio of the inverter stage is 0.3 provided by the present invention;

[0045] Figure 11 is the multilevel voltage output by the U-phase of the inverter stage when the modulation ratio of the inverter stage is 0.2 provided by the present invention. Detailed implementation manners

[0046] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not limited to the present invention.

[0047] As Figure 1 shown, the embodiment gives a schematic diagram of a direct-connected five-level medium-voltage frequency conversion system, whose rectifier input side adopts a star connection and the inverter output side adopts an open winding connection method.

[0048] The present invention provides a simplified unidirectional power flow five-level frequency converter capacitor voltage balance control strategy, which includes five parts: inverter stage unbalance degree calculation, rectifier stage maximum controllable unbalance degree calculation, rectifier stage control strategy, rectifier stage modulation method, and inverter stage modulation method;

[0049] Inverter stage unbalance degree calculation:

[0050] Define h i as the unbalance degree generated by the inverter stage, m i as the modulation ratio of the inverter stage, and calculate the unbalance degree generated by the inverter stage using the following formula, and take the maximum value of h i as h imax ;

[0051]

[0052] Rectifier stage maximum controllable unbalance degree calculation:

[0053] Define V s as the amplitude of the grid side phase voltage, V dc as the rated value of the DC side voltage, m ris the modulation ratio of the rectifier stage, and the modulation ratio of the rectifier stage is calculated using the following formula;

[0054]

[0055] Define h r as the controllable unbalance degree of the rectifier stage, and the controllable unbalance degree of the rectifier stage is calculated using the following formula;

[0056]

[0057] Compare h r and h i , and ensure that h r ≥h i . If h r <h i , then further modify the rated value of the DC-side voltage until h r and h i meet h r ≥h i .

[0058] Figure 2 is the rectifier stage control strategy provided by the present invention, including the following steps:

[0059] Step 1: Sample the DC-side capacitor voltages of the three phases A, B, and C to obtain the DC-side capacitor voltage signals v dca1 , v dca2 , v dca3 , v dca4 , v dcb1 , v dcb2 , v dcb3 , v dcb4 , v dcc1 , v dcc2 , v dcc3 , v dcc4 and the three-phase DC-side total voltage signals v dca , v dcb , v dcc . Calculate the average value of the three-phase DC-side total voltage, subtract the average value of the DC-side total voltage from the expected value V * dc of the DC-side voltage, and send the difference into the PI regulator to obtain the desired current i * dc required to maintain the stability of the DC-side voltage;

[0060] Step 2: Sample the three-phase grid input-side currents to obtain the three-phase grid input-side currents i a , i b , i c , and calculate the modulation wave signals u of the three phases A, B, and C using the following formulasa , u sb , u sc ;

[0061]

[0062] Step 3: v dca1 and v dca2 Sum them up to get u a1 , v dca3 and v dca4 Sum them up to get u a2 , u a1 and u a2 Take the difference and send it to the PI regulator to get u ab1 , v dca1 and v dca2 Take the difference and send it to the PI regulator to get u ab2 , v dca4 and v dca3 Take the difference and send it to the PI regulator to get u ab3 , Calculate the modulation wave signals u a1 , S a2 , S a3 , S a4 of the fully controlled devices S sa1 , u sa2 , u sa3 , u sa4 ;

[0063]

[0064] v dcb1 and v dcb2 Sum them up to get u b1 , v dcb3 and v dcb4 Sum them up to get u b2 , u b1 and u b2 Take the difference and send it to the PI regulator to get u bb1 , v dcb1 and v dcb2 Take the difference and send it to the PI regulator to get u bb2 , v dcb4 and v dcb3 Take the difference and send it to the PI regulator to get u bb3 , Calculate the modulation wave signals u b1 , S b2 , S b3 , S b4 of the fully controlled devices S sb1 , u sb2 , u sb3 , u sb4 ;

[0065]

[0066] v dcc1 and v dcc2 Sum to obtain u c1 ,v dcc3 and v dcc4 Sum to obtain u c2 ,u c1 and u c2 Take the difference and send it to the PI regulator to obtain u cb1 ,v dcc1 and v dcc2 Take the difference and send it to the PI regulator to obtain u cb2 ,v dcc4 and v dcc3 Take the difference and send it to the PI regulator to obtain u cb3 ,Calculate the modulation wave signals u c1 、S c2 、S c3 、S c4 of the fully controlled devices in the C-phase rectifier stage using the following formula sc1 、u sc2 、u sc3 、u sc4 。

[0067]

[0068] Figure 3 This is the rectifier stage modulation method provided by the present invention. The three-phase rectifier stage adopts a carrier phase-shifted modulation method. Define four carrier signals of 0°, 90°, 180°, and 270° for the rectifier stage. Define the drive signals of the fully controlled devices S a1 、S a2 、S a3 、S a4 、S b1 、S b2 、S b3 、S b4 、S c1 、S c2 、S c3 、S c4 in the rectifier stage are G sa1 、G sa2 、G sa3 、G sa4 、G sb1 、G sb2 、G sb3 、G sb4 、G sc1 、G sc2 、G sc3 、G sc4 ,When u sa1When the carrier signal is greater than 0°, the drive signal G sa1 outputs a high level, and outputs a low level in other cases; when u sa2 When the carrier signal is greater than 90°, the drive signal G sa2 outputs a high level, and outputs a low level in other cases; when u sa3 When the carrier signal is greater than 180°, the drive signal G sa3 outputs a high level, and outputs a low level in other cases; when u sa4 When the carrier signal is greater than 270°, the drive signal G sa4 outputs a high level, and outputs a low level in other cases; when u sb1 When the carrier signal is greater than 0°, the drive signal G sb1 outputs a high level, and outputs a low level in other cases; when u sb2 When the carrier signal is greater than 90°, the drive signal G sb2 outputs a high level, and outputs a low level in other cases; when u sb3 When the carrier signal is greater than 180°, the drive signal G sb3 outputs a high level, and outputs a low level in other cases; when u sb4 When the carrier signal is greater than 270°, the drive signal G sb4 outputs a high level, and outputs a low level in other cases; when u sc1 When the carrier signal is greater than 0°, the drive signal G sc1 outputs a high level, and outputs a low level in other cases; when u sc2 When the carrier signal is greater than 90°, the drive signal G sc2 outputs a high level, and outputs a low level in other cases; when u sc3 When the carrier signal is greater than 180°, the drive signal G sc3 outputs a high level, and outputs a low level in other cases; when u sc4 When the carrier signal is greater than 270°, the drive signal G sc4 outputs a high level, and outputs a low level in other cases.

[0069] Figure 4 is the inverter stage modulation method provided by the present invention, including the following steps:

[0070] Step 1: Define the modulation wave signal of the U-phase bridge arm 1 of the inverter stage as u su , and the fully controlled devices are S u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' ; the modulation wave signal of the U-phase bridge arm 2 is u su', the fully controlled devices are S from top to bottom in sequence u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' ; The modulation wave signal of phase V bridge arm 1 is u sv , the fully controlled devices are S from top to bottom in sequence v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' ; The modulation wave signal of phase V bridge arm 2 is u sv' , the fully controlled devices are S from top to bottom in sequence v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' ; The modulation wave signal of phase W bridge arm 1 is u sw , the fully controlled devices are S from top to bottom in sequence w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' ; The modulation wave signal of phase W bridge arm 2 is u sw' , the fully controlled devices are S from top to bottom in sequence w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' ; ω is the angular frequency of the inverter stage modulation signal, and the modulation wave signals of the six bridge arms of the inverter stage are calculated using the following formula;

[0071]

[0072] Step 2: Define the fully controlled devices S u1 , S u2 , S u3 , S u4 , S u'1 , S u'2 , S u'3 , S u'4 , Sv1 , S v2 , S v3 , S v4 , S v'1 , S v'2 , S v'3 , S v'4 , S w1 , S w2 , S w3 , S w4 , S w'1 , S w'2 , S w'3 , S w'4 The corresponding modulation signals are u su1 , u su2 , u su3 , u su4 , u su '1, u su '2, u su '3, u su '4, u sv1 , u sv2 , u sv3 , u sv4 , u sv '1, u sv '2, u sv '3, u sv '4, u sw1 , u sw2 , u sw3 , u sw4 , u sw'1 , u sw'2 , u sw'3 , u sw'4 The respective modulation signals are calculated using the following formula;

[0073]

[0074]

[0075] Step 3: Define fully-controlled devices S u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' , S u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' , Sv1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' , S v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' , S w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' , S w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' The corresponding drive signals are G su1 , G su2 , G su3 , G su4 , G su1' , G su2' , G su3' , G su4' , G su'1 , G su'2 , G su'3 , G su'4 , G su'1' , G su'2' , G su'3' , G su'4' , G sv1 , G sv2 , G sv3 , G sv4 , G sv1' , G sv2' , G sv3' , G sv4' , G sv'1 , G sv'2 , G sv'3 , G sv'4 , G sv'1' , G sv'2' , G sv'3' , G sv'4' , G sw1 , G sw2 , Gsw3 , G sw4 , G sw1' , G sw2' , G sw3' , G sw4' , G sw'1 , G sw'2 , G sw'3 , G sw'4 , G sw'1' , G sw'2' , G sw'3' , G sw'4' , all the fully controlled devices in the inverter stage share the same carrier signal. When u su1 is greater than the carrier signal of the inverter stage, the drive signal G su1 outputs a high level, and outputs a low level in other cases; the drive signal G su1' is opposite to G su1 ; when u su2 is greater than the carrier signal of the inverter stage, the drive signal G su2 outputs a high level, and outputs a low level in other cases; the drive signal G su2' is opposite to G su2 ; when u su3 is greater than the carrier signal of the inverter stage, the drive signal G su3 outputs a high level, and outputs a low level in other cases; the drive signal G su3' is opposite to G su3 ; when u su4 is greater than the carrier signal of the inverter stage, the drive signal G su4 outputs a high level, and outputs a low level in other cases; the drive signal G su4' is opposite to G su4 ; when u su'1 is greater than the carrier signal of the inverter stage, the drive signal G su'1 outputs a high level, and outputs a low level in other cases; the drive signal G su'1' is opposite to G su'1 ; when u su'2 is greater than the carrier signal of the inverter stage, the drive signal G su'2 outputs a high level, and outputs a low level in other cases; the drive signal G su'2' is opposite to G su'2 ; when u su'3 is greater than the carrier signal of the inverter stage, the drive signal G su'3 outputs a high level, and outputs a low level in other cases; the drive signal G su'3' is opposite to G su'3 ; when u su'4 is greater than the carrier signal of the inverter stage, the drive signal G su'4 outputs a high level, and outputs a low level in other cases; the drive signal G su'4' is opposite to G su'4On the contrary; when u sv1 is greater than the inverter-stage carrier signal, the drive signal G sv1 outputs a high level, and outputs a low level in other cases; the drive signal G sv1' is opposite to G sv1 ; when u sv2 is greater than the inverter-stage carrier signal, the drive signal G sv2 outputs a high level, and outputs a low level in other cases; the drive signal G sv2' is opposite to G sv2 ; when u sv3 is greater than the inverter-stage carrier signal, the drive signal G sv3 outputs a high level, and outputs a low level in other cases; the drive signal G sv3' is opposite to G sv3 ; when u sv4 is greater than the inverter-stage carrier signal, the drive signal G sv4 outputs a high level, and outputs a low level in other cases; the drive signal G sv4' is opposite to G sv4 ; when u sv'1 is greater than the inverter-stage carrier signal, the drive signal G sv'1 outputs a high level, and outputs a low level in other cases; the drive signal G sv'1' is opposite to G sv'1 ; when u sv'2 is greater than the inverter-stage carrier signal, the drive signal G sv'2 outputs a high level, and outputs a low level in other cases; the drive signal G sv'2' is opposite to G sv'2 ; when u sv'3 is greater than the inverter-stage carrier signal, the drive signal G sv'3 outputs a high level, and outputs a low level in other cases; the drive signal G sv'3' is opposite to G sv'3 ; when u sv'4 is greater than the inverter-stage carrier signal, the drive signal G sv'4 outputs a high level, and outputs a low level in other cases; the drive signal G sv'4' is opposite to G sv'4 ; when u sw1 is greater than the inverter-stage carrier signal, the drive signal G sw1 outputs a high level, and outputs a low level in other cases; the drive signal G sw1' is opposite to G sw1 ; when u sw2 is greater than the inverter-stage carrier signal, the drive signal G sw2 outputs a high level, and outputs a low level in other cases; the drive signal G sw2' is opposite to G sw2 ; when u sw3When it is greater than the inverter - stage carrier signal, the driving signal G sw3 outputs a high level, and outputs a low level in other cases; the driving signal G sw3' is opposite to G sw3 ; when u sw4 is greater than the inverter - stage carrier signal, the driving signal G sw4 outputs a high level, and outputs a low level in other cases; the driving signal G sw4' is opposite to G sw4 ; when u sw'1 is greater than the inverter - stage carrier signal, the driving signal G sw'1 outputs a high level, and outputs a low level in other cases; the driving signal G sw'1' is opposite to G sw'1 ; when u sw'2 is greater than the inverter - stage carrier signal, the driving signal G sw'2 outputs a high level, and outputs a low level in other cases; the driving signal G sw'2' is opposite to G sw'2 ; when u sw'3 is greater than the inverter - stage carrier signal, the driving signal G sw'3 outputs a high level, and outputs a low level in other cases; the driving signal G sw'3' is opposite to G sw'3 ; when u sw'4 is greater than the inverter - stage carrier signal, the driving signal G sw'4 outputs a high level, and outputs a low level in other cases; the driving signal G sw'4' is opposite to G sw'4 ; when u

[0076] Figure 5 are the carriers equivalent to the inverter - stage modulation method provided by the present invention in different modulation - ratio ranges, including the carriers in the high - modulation - ratio range, the carriers in the medium - modulation - ratio range, and the carriers in the low - modulation - ratio range.

[0077] Figure 6 are the total voltage of the DC side of phase A, the voltages of the split capacitors on the DC side, and the output current of phase U during the constant V / f start of the inverter - stage provided by the present invention. It can be seen that during the constant V / f start of the inverter - stage, the total voltage of the DC side of phase A and the voltages of the split capacitors on the DC side are both balanced, and the proposed control strategy can maintain balance within the full modulation - ratio range of the inverter - stage.

[0078] Figure 7 is the multilevel voltage output by phase U of the inverter - stage when the modulation ratio of the inverter - stage provided by the present invention is 1. It can be clearly seen that there are a total of 9 levels in the output voltage.

[0079] Figure 8 is the multilevel voltage output by phase U of the inverter - stage when the modulation ratio of the inverter - stage provided by the present invention is 0.8. It can be clearly seen that there are a total of 9 levels in the output voltage.

[0080] Figure 9 It is the multilevel voltage output by the U phase of the inverter stage when the modulation ratio of the inverter stage provided by the present invention is 0.6. It can be clearly seen that there are a total of 7 levels in the output voltage.

[0081] Figure 10 It is the multilevel voltage output by the U phase of the inverter stage when the modulation ratio of the inverter stage provided by the present invention is 0.3. It can be clearly seen that there are a total of 5 levels in the output voltage.

[0082] Figure 11 It is the multilevel voltage output by the U phase of the inverter stage when the modulation ratio of the inverter stage provided by the present invention is 0.2. It can be clearly seen that there are a total of 3 levels in the output voltage.

[0083] Through Figures 7 - 11 It can be seen that the proposed control strategy can still maintain the inverter output voltage at a relatively low THD while ensuring the balance control of the DC-side capacitor voltage.

[0084] It is easy for those skilled in the art to understand that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. The usage range of each modulation wave of the inverter stage is not limited to the range shown in the embodiment. Through corresponding modifications, the control strategy provided by the present invention is also applicable. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A simplified control strategy for capacitor voltage balance of a unidirectional power flow five-level frequency converter. The structure of the unidirectional power flow five-level frequency converter includes three single-phase AC-DC-AC converter circuits. Each single-phase AC-DC-AC converter circuit includes a single-phase rectifier stage circuit and a single-phase inverter stage circuit. The single-phase rectifier stage circuit is composed of a single-phase diode rectifier bridge connected to a five-level Boost converter. The single-phase inverter stage circuit is composed of a single-phase five-level diode clamped inverter. The input end of the single-phase five-level diode clamped inverter is directly connected to the output end of the five-level Boost converter. The single-phase rectifier stage circuit of the single-phase AC-DC-AC converter circuit has two AC input ends. The single-phase rectifier stage circuits of the three single-phase AC-DC-AC converter circuits have a total of six AC input ends. The first AC input ends of the single-phase rectifier stage circuits of the three single-phase AC-DC-AC converter circuits form a set of terminals. The second AC input ends of the single-phase rectifier stage circuits of the three single-phase AC-DC-AC converter circuits form another set of terminals. One set of terminals is connected to a common neutral point. The other set of terminals is respectively connected in series with three high-frequency filter inductors and connected to the three-phase power grid to form a star connection. The single-phase inverter stage circuit of the single-phase AC-DC-AC converter circuit has two AC output ends, forming a set of AC output ends. The three single-phase inverter stage circuits of the three single-phase AC-DC-AC converter circuits have a total of six AC output ends, forming three sets of AC output ends. The three sets of AC output ends of the three single-phase inverter stage circuits of the three single-phase AC-DC-AC converter circuits are connected to the three stator windings of the three-phase AC motor to form an open winding connection; The simplified unidirectional power flow five-level inverter capacitor voltage balance control strategy is characterized in that It includes five parts: calculation of inverter stage unbalance degree, calculation of maximum controllable unbalance degree of rectifier stage, control strategy of rectifier stage, modulation method of rectifier stage, and modulation method of inverter stage; Calculation of inverter stage unbalance degree: Define h i as the unbalance degree generated by the inverter stage, m i as the modulation ratio of the inverter stage. The unbalance degree generated by the inverter stage is calculated by the following formula, and the maximum value of h i is taken as h imax ; Calculation of maximum controllable unbalance degree of rectifier stage: Define V s as the grid-side phase voltage amplitude, V dc as the DC-side voltage rated value, m r as the rectifier stage modulation ratio, and calculate the rectifier stage modulation ratio using the following formula; Define h r as the unbalance degree that can be controlled by the rectifier stage, and calculate the unbalance degree that can be controlled by the rectifier stage using the following formula; Compare h r with h i , and ensure that h r ≥h i . If h r <h i , then further modify the DC-side voltage rating until h r and h i satisfy h r ≥h i ; Control strategy of rectifier stage: Step 1: Sample the DC-side capacitor voltages of three phases A, B, and C to obtain the DC-side capacitor voltage signals v dca1 、v dca2 、v dca3 、v dca4 、v dcb1 、v dcb2 、v dcb3 、v dcb4 、v dcc1 、v dcc2 、v dcc3 、v dcc4 and the total DC-side voltage signals v dca 、v dcb 、v dcc , calculate the average value of the total DC-side voltage, subtract the average value of the DC-side voltage from the expected DC-side voltage value V * dc and send the difference into a PI regulator to obtain the expected current i * dc ; Step 2: Sample the currents on the input side of the three-phase power grid of A, B, and C to obtain the currents i a 、i b 、i c on the input side of the three-phase power grid. Calculate the modulation wave signals u sa 、u sb 、u sc of the three phases of A, B, and C by using the following formula; Step 3: v dca1 and v dca2 are summed to obtain u a1 ,v dca3 and v dca4 are summed to obtain u a2 ,u a1 and u a2 are subtracted and fed into a PI regulator to obtain u ab1 ,v dca1 and v dca2 are subtracted and fed into a PI regulator to obtain u ab2 ,v dca4 and v dca3 are subtracted and fed into a PI regulator to obtain u ab3 ,and the modulation wave signals u a1 、u a2 、u a3 、u a4 of the fully controlled devices S sa1 、S sa2 、S sa3 、S sa4 in the A-phase rectifier stage are calculated using the following formula; v dcb1 and v dcb2 Sum them up to get u b1 ,v dcb3 and v dcb4 Sum them up to get u b2 ,u b1 and u b2 Take the difference and send it to the PI regulator to get u bb1 ,v dcb1 and v dcb2 Take the difference and send it to the PI regulator to get u bb2 ,v dcb4 and v dcb3 Take the difference and send it to the PI regulator to get u bb3 ,Calculate the modulating wave signals u b1 、S b2 、S b3 、S b4 of the fully controlled devices S sb1 、u sb2 、u sb3 、u sb4 ; v dcc1 and v dcc2 Sum them up to get u c1 ,v dcc3 and v dcc4 Sum them up to get u c2 ,u c1 and u c2 Take the difference and send it to the PI regulator to get u cb1 ,v dcc1 and v dcc2 Take the difference and send it to the PI regulator to get u cb2 ,v dcc4 and v dcc3 Take the difference and send it to the PI regulator to get u cb3 ,Calculate the modulation wave signals u c1 、u c2 、u c3 、u c4 of the fully controlled devices S sc1 、u sc2 、u sc3 、u sc4 ; Modulation method of rectifier stage: The three-phase rectifier stage adopts a carrier phase-shifted modulation method. Four carrier signals of 0°, 90°, 180°, and 270° are defined for the rectifier stage. The fully controlled devices S a1 、S a2 、S a3 、S a4 、S b1 、S b2 、S b3 、S b4 、S c1 、S c2 、S c3 、S c4 have drive signals G sa1 、G sa2 、G sa3 、G sa4 、G sb1 、G sb2 、G sb3 、G sb4 、G sc1 、G sc2 、G sc3 、G sc4 , when u sa1 is greater than the 0° carrier signal, the drive signal G sa1 outputs a high level, and outputs a low level in other cases; when u sa2 is greater than the 90° carrier signal, the drive signal G sa2 outputs a high level, and outputs a low level in other cases; when u sa3 is greater than the 180° carrier signal, the drive signal G sa3 outputs a high level, and outputs a low level in other cases; when u sa4 is greater than the 270° carrier signal, the drive signal G sa4 outputs a high level, and outputs a low level in other cases; when u sb1 is greater than the 0° carrier signal, the drive signal G sb1 outputs a high level, and outputs a low level in other cases; when u sb2 is greater than the 90° carrier signal, the drive signal G sb2 outputs a high level, and outputs a low level in other cases; when u sb3 is greater than the 180° carrier signal, the drive signal G sb3 outputs a high level, and outputs a low level in other cases; when u sb4 is greater than the 270° carrier signal, the drive signal G sb4 outputs a high level, and outputs a low level in other cases; when u sc1 is greater than the 0° carrier signal, the drive signal G sc1 outputs a high level, and outputs a low level in other cases; when u sc2 When the carrier signal is greater than 90°, the drive signal G sc2 outputs a high level, and outputs a low level in other cases; when u sc3 When the carrier signal is greater than 180°, the drive signal G sc3 outputs a high level, and outputs a low level in other cases; when u sc4 When the carrier signal is greater than 270°, the drive signal G sc4 outputs a high level, and outputs a low level in other cases; Modulation method of inverter stage: Step 1: Define the modulation wave signal of the U-phase bridge arm 1 of the inverter stage as u su , and the fully controlled devices are S u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' from top to bottom; the modulation wave signal of the U-phase bridge arm 2 is u su' , and the fully controlled devices are S u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' from top to bottom; the modulation wave signal of the V-phase bridge arm 1 is u sv , and the fully controlled devices are S v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' from top to bottom; the modulation wave signal of the V-phase bridge arm 2 is u sv' , and the fully controlled devices are S v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' from top to bottom; the modulation wave signal of the W-phase bridge arm 1 is u sw , and the fully controlled devices are S w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' from top to bottom; the modulation wave signal of the W-phase bridge arm 2 is u sw' , and the fully controlled devices are S w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' ; ω is the angular frequency of the modulation signal of the inverter stage, and the modulation wave signals of the six bridge arms of the inverter stage are calculated using the following formula; Step 2: Define fully controlled device S u1 , S u2 , S u3 , S u4 , S u'1 , S u'2 , S u'3 , S u'4 , S v1 , S v2 , S v3 , S v4 , S v'1 , S v'2 , S v'3 , S v'4 , S w1 , S w2 , S w3 , S w4 , S w'1 , S w'2 , S w'3 , S w'4 The corresponding modulation signals are respectively u su1 , u su2 , u su3 , u su4 , u su '1, u su '2, u su '3, u su '4, u sv1 , u sv2 , u sv3 , u sv4 , u sv '1, u sv '2, u sv '3, u sv '4, u sw1 , u sw2 , u sw3 , u sw4 , u sw'1 , u sw'2 , u sw'3 , u sw'4 Calculate each modulation signal using the following formula; Step 3: Define fully-controlled device S u1 、S u2 、S u3 、S u4 、S u1' 、S u2' 、S u3' 、S u4' 、S u'1 、S u'2 、S u'3 、S u'4 、S u'1' 、S u'2' 、S u'3' 、S u'4' 、S v1 、S v2 、S v3 、S v4 、S v1' 、S v2' 、S v3' 、S v4' 、S v'1 、S v'2 、S v'3 、S v'4 、S v'1' 、S v'2' 、S v'3' 、S v'4' 、S w1 、S w2 、S w3 、S w4 、S w1' 、S w2' 、S w3' 、S w4' 、S w'1 、S w'2 、S w'3 、S w'4 、S w'1' 、S w'2' 、S w'3' 、S w'4' The corresponding drive signals are G su1 、G su2 、G su3 、G su4 、G su1' 、G su2' 、G su3' 、G su4' 、G su'1 、G su'2 、G su'3 、G su'4 、G su'1' 、G su'2' 、G su'3' 、G su'4' 、G sv1 、G sv2 , G sv3 , G sv4 , G sv1' , G sv2' , G sv3' , G sv4' , G sv'1 , G sv'2 , G sv'3 , G sv'4 , G sv'1' , G sv'2' , G sv'3' , G sv'4' , G sw1 , G sw2 , G sw3 , G sw4 , G sw1' , G sw2' , G sw3' , G sw4' , G sw'1 , G sw'2 , G sw'3 , G sw'4 , G sw'1' , G sw'2' , G sw'3' , G sw'4' , all the fully controlled devices in the inverter stage share the same carrier signal. When u su1 is greater than the carrier signal of the inverter stage, the drive signal G su1 outputs a high level, and outputs a low level in other cases; the drive signal G su1' is opposite to G su1 ; when u su2 is greater than the carrier signal of the inverter stage, the drive signal G su2 outputs a high level, and outputs a low level in other cases; the drive signal G su2' is opposite to G su2 ; when u su3 is greater than the carrier signal of the inverter stage, the drive signal G su3 outputs a high level, and outputs a low level in other cases; the drive signal G su3' is opposite to G su3 ; when u su4 is greater than the carrier signal of the inverter stage, the drive signal G su4 outputs a high level, and outputs a low level in other cases; the drive signal G su4' is opposite to G su4 ; when u su'1 is greater than the carrier signal of the inverter stage, the drive signal G su'1 outputs a high level, and outputs a low level in other cases; the drive signal G su'1' is opposite to G su'1 ; when u su'2 is greater than the carrier signal of the inverter stage, the drive signal G su'2 Outputs a high level and a low level in other cases; drive signal G su'2' Is opposite to G su'2 When u su'3 Is greater than the inverter stage carrier signal, drive signal G su'3 Outputs a high level and a low level in other cases; drive signal G su'3' Is opposite to G su'3 When u su'4 Is greater than the inverter stage carrier signal, drive signal G su'4 Outputs a high level and a low level in other cases; drive signal G su'4' Is opposite to G su'4 When u sv1 Is greater than the inverter stage carrier signal, drive signal G sv1 Outputs a high level and a low level in other cases; drive signal G sv1' Is opposite to G sv1 When u sv2 Is greater than the inverter stage carrier signal, drive signal G sv2 Outputs a high level and a low level in other cases; drive signal G sv2' Is opposite to G sv2 When u sv3 Is greater than the inverter stage carrier signal, drive signal G sv3 Outputs a high level and a low level in other cases; drive signal G sv3' Is opposite to G sv3 When u sv4 Is greater than the inverter stage carrier signal, drive signal G sv4 Outputs a high level and a low level in other cases; drive signal G sv4' Is opposite to G sv4 When u sv'1 Is greater than the inverter stage carrier signal, drive signal G sv'1 Outputs a high level and a low level in other cases; drive signal G sv'1' Is opposite to G sv'1 When u sv'2 Is greater than the inverter stage carrier signal, drive signal G sv'2 Outputs a high level and a low level in other cases; drive signal G sv'2' Is opposite to G sv'2 When u sv'3 Is greater than the inverter stage carrier signal, drive signal G sv'3 Outputs a high level and a low level in other cases; drive signal G sv'3' Is opposite to G sv'3 When u sv'4 Is greater than the inverter stage carrier signal, drive signal G sv'4 Outputs a high level and outputs a low level in other cases; drive signal G sv'4' is opposite to G sv'4 ; when u sw1 is greater than the inverter-stage carrier signal, drive signal G sw1 outputs a high level and outputs a low level in other cases; drive signal G sw1' is opposite to G sw1 ; when u sw2 is greater than the inverter-stage carrier signal, drive signal G sw2 outputs a high level and outputs a low level in other cases; drive signal G sw2' is opposite to G sw2 ; when u sw3 is greater than the inverter-stage carrier signal, drive signal G sw3 outputs a high level and outputs a low level in other cases; drive signal G sw3' is opposite to G sw3 ; when u sw4 is greater than the inverter-stage carrier signal, drive signal G sw4 outputs a high level and outputs a low level in other cases; drive signal G sw4' is opposite to G sw4 ; when u sw'1 is greater than the inverter-stage carrier signal, drive signal G sw'1 outputs a high level and outputs a low level in other cases; drive signal G sw'1' is opposite to G sw'1 ; when u sw'2 is greater than the inverter-stage carrier signal, drive signal G sw'2 outputs a high level and outputs a low level in other cases; drive signal G sw'2' is opposite to G sw'2 ; when u sw'3 is greater than the inverter-stage carrier signal, drive signal G sw'3 outputs a high level and outputs a low level in other cases; drive signal G sw'3' is opposite to G sw'3 ; when u sw'4 is greater than the inverter-stage carrier signal, drive signal G sw'4 outputs a high level and outputs a low level in other cases; drive signal G sw'4' is opposite to G sw'4 is opposite.

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