Sewage treatment motor control system and method based on FPGA

Abstract

The invention discloses a sewage treatment motor control system and method based on an FPGA. The system comprises an FPGA controller, an ADC sampling device, an inverter, a Hall sensor and an upper computer. An encoder interface on the FPGA controller performs position decoding on a signal transmitted by the motor to calculate the real-time rotating speed of the motor so as to realize closed-loop control of a speed loop; the ADC sampling device completes current reconstruction by collecting voltage information of the Hall sensor and transmits the voltage information to the FPGA controller through the ADC sampling device interface, the problem that a traditional PLC controller in a sewage plant is insufficient in real-time performance and accuracy is solved, the FPGA adopts a parallel processing mechanism, the calculation speed and the response speed are high, flexibility is high, and the system can be widely applied to the field of sewage treatment. And high-precision and high-reliability control can be carried out on a lift pump system and an air blower system in the sewage treatment process.

Description

Technical Field

[0001] The present invention relates to the technical field of motor intelligent control, and in particular to a sewage treatment motor control system and method based on FPGA. Background Art

[0002] The forecast results of the World Water Comprehensive Assessment Report show that by 2025, the world's total population is expected to reach 8.3 billion, and the population living in countries with water shortages or frequent water shortages will increase from 300 million in 1990 to 3 billion in 2025, which means that more than one-third of the world's population will suffer from moderate to high water stress. How to effectively use freshwater resources, control pollution in rivers, lakes and reservoirs, and purify water has become an environmental issue of common concern to governments around the world.

[0003] With the continuous development of industrialization and urbanization in my country, water shortage and water pollution problems have become increasingly urgent. The main pollution indicators are total phosphorus, chemical oxygen demand and permanganate index. How to efficiently treat discharged sewage, protect the water environment to the maximum extent, and achieve sustainable utilization and benign circulation of freshwater resources has been included in the important strategic measures of the Chinese government for the comprehensive utilization of water resources.

[0004] As of the end of 2022, my country has built and put into operation more than 5,000 urban sewage treatment plants, with an annual sewage treatment capacity of more than 60 billion cubic meters.

[0005] In this regard, the state has not only promulgated increasingly stringent laws and regulations to control sewage discharge, invested huge human and financial resources, but also required high efficiency and energy saving. Sewage treatment involves the sustainable development of the environment and resources. With the in-depth research on water pollution prevention and control, advanced sewage treatment technology has been promoted and applied. Research on new sewage treatment energy-saving and consumption-reducing technologies is an inevitable development trend of the sewage treatment industry in the future.

[0006] At present, the production process of most sewage treatment plants in my country adopts PLC control system based on distributed control, and automatic control replaces manual control, which improves operating conditions and reduces labor intensity. However, in actual production and operation, some problems often arise, such as many sewage treatment plants rely on the experience of individual technicians, work for long hours, consume too much energy, and have irregular operations, a large number of equipment, and inconvenient maintenance during sewage treatment. Considering the complexity and variability of the sewage treatment process, in order to improve the management capabilities of sewage treatment plants and further improve the effect of sewage treatment, from the overall structural analysis, the working process of urban domestic sewage treatment is difficult to achieve integrated management, and there are certain differences between process management, detection methods and operating standards. At present, most of them are building terminal intelligent equipment, process intelligent measurement and control, and enterprise production information collection systems. The entire sewage treatment intelligent system is still in urgent need of improvement. There are many urban sewage treatment plants at home and abroad with more complete control intelligent equipment. These systems have three main functions:

[0007] The first is to use PLC and computers to collect, transmit and store information, and use big data technology to automatically optimize the statistical analysis of process settings.

[0008] Secondly, unified control of remote switches of various pumps, ventilation equipment, etc., equipment frequency conversion control, automatic alarm notification of equipment maintenance cycle failures, and full process control of the equipment are achieved.

[0009] The third is the energy monitoring system of the sewage treatment plant, which is based on the advanced technology of the Internet of Things, with computers, communication modules, measurement and control modules and other main software, to implement more detailed control of large-scale equipment through real-time information collection, platform-based distribution equipment monitoring and remote management of switch status, and record the main performance parameters of the equipment such as energy, power, pressure, flow, etc. in the energy monitoring and management system platform of the central control room, thereby realizing powerful data mining.

[0010] However, most of the automatic management platforms currently configured for sewage treatment plants do not have all the features of the above three software. They can generally only perform basic automatic control, monitoring and information collection, and are unable to globally control and optimize the system. Problems in the feedback module are also difficult to adjust in a timely manner.

[0011] Moreover, the sewage treatment process has very high requirements for analog closed-loop control systems, and the logical relationship of the process is very complex. Ensuring the efficiency of the sewage treatment process is the key to the sewage treatment process, so a high level of automated control design is essential. The main advantage of FPGA is its unparalleled design flexibility, which can set boundaries between hardware and software. In addition, it processes data in parallel, which has great advantages over PLC in terms of performance and processing speed. Therefore, it has strong research significance and application value. Summary of the invention

[0012] The present invention aims to solve the deficiencies of the above-mentioned prior art and provides a sewage treatment motor control system based on FPGA, which adopts magnetic field oriented control and seven-segment space vector pulse width modulation to control the motor. The closed-loop scheme is a double closed-loop of speed loop and current loop to solve the problems mentioned in the background technology.

[0013] To achieve the above object, the present invention provides the following technical solutions:

[0014] A sewage treatment motor control system based on FPGA comprises an FPGA controller, an ADC sampling device, an inverter, a Hall sensor and a host computer; the encoder interface on the FPGA controller performs position decoding on the signal transmitted by the motor to calculate the real-time rotation speed of the motor, thereby realizing closed-loop control of the speed loop; the ADC sampling device completes current reconstruction by collecting voltage information of the Hall sensor, and transmits it to the FPGA controller through the ADC sampling device interface, thereby realizing closed-loop control of the current loop; the FPGA controller controls the motor by transmitting SVPWM control signals to the inverter; and controls the initialization, start and stop of PMSM through buttons and the host computer interface.

[0015] As a further technical solution of the present invention: the FPGA controller includes a speed PI module, a current PI module, a coordinate transformation module, an SVPWM module, an ADC sampling module, a position decoding and a speed calculation module. The UART serial port on the FPGA controller is connected to the host computer. The host computer supports PI parameters and expected speed modification, and can view the three-phase current, three-phase voltage, PI parameters and real-time speed of the motor.

[0016] As a further technical solution of the present invention: the maximum sampling ratio of the Hall sensor is 100%.

[0017] As a further technical solution of the present invention: the keys include key1 and key2, the user triggers the system initialization process by key1, and controls the pause state of the system by key2; at the same time, the user can force the system to enter the pause mode by pressing the key.

[0018] As a further technical solution of the present invention: the closed-loop control of the speed loop takes the actual running speed and the target running speed of the motor as input, and outputs a control signal to adjust the operation of the motor to achieve the desired speed; firstly, the proportional gain, integral gain, target speed, maximum output limit and the parameters of the maximum count value of the control cycle of the PI controller are set; then the frequency management is controlled to ensure that the speed control is performed within a specific time interval, rather than every clock cycle; in each control cycle, the actual speed average value of the last few cycles is calculated for more accurate speed feedback; finally, the control signal is generated using the PI control algorithm according to the error between the set target speed and the calculated actual average speed.

[0019] As a further technical solution of the present invention: the closed-loop control of the current loop is to use a magnetic field oriented control algorithm and a PI controller to accurately control the current of the motor; the three-phase voltage of the motor is collected by the ADC signal acquisition module and reconstructed into a three-phase current, and when the ADC sampling is completed, the Clark transformation module converts the three-phase current into α and β currents in a two-phase stationary coordinate system; the α and β currents after Clark transformation and the angle information provided by the encoder are received, and the direct-axis and quadrature-axis currents in the rotating coordinate system are input into the current PI controller through Park transformation, and according to the direct-axis and quadrature-axis voltage command values ​​provided by the PI controller and the angle information provided by the encoder, they are converted into α and β voltages in a two-phase stationary coordinate system through inverse Park transformation, and a PWM signal for driving the inverter is generated according to the α and β voltages to control the motor to achieve current loop closed-loop control.

[0020] As a further technical solution of the present invention: the host computer communicates with the FPGA through the UART serial port; using full-duplex communication mode, the host computer receives the three-phase voltage, three-phase current, PI parameter value and real-time speed of the motor transmitted by the FPGA for display, and sends commands to the FPGA through the host computer interface to change the PI parameter value and speed of the motor.

[0021] As a further technical solution of the present invention: the ADC sampling scheme is Hall sensor sampling.

[0022] As a further technical solution of the present invention: using the above system, the following steps are included:

[0023] Step 1: Key control, set the key1 and key2 on the FPGA, and control the initialization and start / stop functions according to the key input and pause signal; debounce the key1 and key2 to ensure the stability of the key signal, generate a high-level pulse signal with a single clock cycle width through the key1 as the initialization start signal, use the key2 to switch the tentative state, and when the pause state is high, force it to be set to the pause state. The specific process is the following submodules:

[0024] 1-1. Reset processing: When the asynchronous reset signal is at a low level, the pause state is cleared to ensure that the system is in the initial state after power-on or reset;

[0025] 1-2. Key debounce: Debounce the keys key1 and key2. For key1, the debounced signal is directly used as the initialization start signal. For key2, the debounced signal is sent to the signal logic control module to generate a key pause state signal.

[0026] 1-3. Generate a pause signal: Through the signal logic control module, the pause state signal is switched according to the signal after key2 is debounced. Whenever key2 is pressed effectively, the key pause signal will flip between high level and low level once;

[0027] Step 2: Filter the raw pulse signal from the encoder to remove noise, and calculate the mechanical angle and electrical angle of the rotor based on these signals; perform direction judgment to determine the direction of motor rotation; decode the specific position of the rotor based on the encoder signal; use the CORDIC algorithm to calculate the sine and cosine values ​​based on the electrical angle; finally, calculate the speed of the motor based on the A phase pulse and the direction of rotation. The specific process includes the following submodules:

[0028] 2-1. Reset processing: Given an asynchronous reset signal, ensure that all internal state machines and registers can return to a known initial state when the system is powered on or reset;

[0029] 2-2. Photoelectric encoder signal filtering and position determination: Filter the A, B and Z phase pulses of the encoder to eliminate possible noise interference, determine the direction of motor rotation by analyzing the relative phase relationship between phase A and phase B, calculate the current mechanical angle and electrical angle of the rotor, and output a flag to indicate the occurrence of the A phase pulse for subsequent speed calculation;

[0030] 2-3. Solving the trigonometric function of the rotor position: Use the CORDIC algorithm to calculate the corresponding sine and cosine values ​​according to the electrical angle, and output an enable signal to indicate that the calculation result is valid;

[0031] 2-4. Speed ​​solution: Calculate the motor speed based on the frequency and rotation direction of the A-phase pulse, and provide an enable signal to indicate that the speed calculation result is valid;

[0032] Step 3: Perform speed loop closed-loop PI control, take the actual motor speed and target speed as input, and output a control signal to adjust the motor operation to achieve the desired speed. The specific process includes the following submodules:

[0033] 3-1. Reset processing: Initialize all registers to default values ​​to ensure that the system is in the initial state after power-on or reset;

[0034] 3-2. Enable signal delay: By delaying the enable signal by 4 beats, it is ensured that the system can stably enter a new control cycle each time the enable signal is activated;

[0035] 3-3. Control frequency setting: When the enable signal is activated, the enable count register starts counting until it reaches the maximum value defined by the control cycle, and then resets; this is used to control the update frequency of the speed loop to ensure that the speed control logic is not updated too frequently;

[0036] 3-4. Average speed calculation: When the enable signal is activated and the enable count register is close to the end of the count, the actual speed is accumulated to the speed accumulation register; when a complete control cycle is completed, that is, when the enable signal returns to zero, the accumulated speed is divided by 4 to obtain the average speed of the recent cycles and assigned to the speed register;

[0037] 3-5. PI control enable: Whenever a control cycle is completed and the enable delay signal is at a high level, the PI enable signal is set to a high level to trigger a PI control operation; at the same time, the calculated average speed is assigned to the speed register as the input of this PI control;

[0038] 3-6. PI controller instantiation: Call the PI controller using the provided parameters and the calculated average speed to generate the final control output P value and I value;

[0039] 3-7. Pause function: If the pause state signal is high level, the PI controller will pause and will not affect the current speed control state;

[0040] Step 4: Process the collected data through ADC, convert the collected voltage data into current data, calculate the corresponding current value, and provide the output of voltage data. The specific process includes the following submodules:

[0041] 4-1. Reset processing: Given an asynchronous reset signal, ensure that all internal state machines and registers can return to a known initial state when the system is powered on or reset;

[0042] 4-2. AD7606 data acquisition: By instantiating the AD7606 driver module, managing the control signal of AD7606, and receiving the busy and idle signals and data signals from AD7606; when the acquisition is completed, the ad completion signal is set to a high level, indicating that a complete data acquisition cycle is completed; the collected data is transmitted to the subsequent processing module through 8 independent output ports;

[0043] 4-3. Current reconstruction: Use the current reconstruction module to process the voltage data from AD7606 and convert it into current data; the input includes clock signal, reset signal, AD7606 data acquisition completion signal and 8 channels of voltage data; the output includes four sets of current data and one set of voltage data;

[0044] 4-4. Enable signal management: The ad enable signal is used to control the data acquisition process of AD7606. Only when this signal is valid will a new acquisition cycle be started;

[0045] 4-5. Output enable: The current reconstruction module is also responsible for generating an output enable signal, indicating that the current output data is valid;

[0046] Step 5: The current of the motor is precisely controlled through the field-oriented control algorithm and the PI controller. The specific process includes the following submodules:

[0047] 5-1. Reset processing: All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset;

[0048] 5-2. Initialization start: When the initialization start signal is received, the initialization process is started, and this process will continue until the initialization start signal is set to a high level;

[0049] 5-3. FOC algorithm instantiation: The FOC module is responsible for converting the three-phase current into the direct axis and quadrature axis components in the direct coordinate system, and generating PWM signals to control the inverter according to the voltage command value provided by the PI controller; and the FOC module also manages the ADC sampling enable and PI controller enable signals. The specific process includes the following sub-modules:

[0050] 5-3-1. Reset processing: All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset;

[0051] 5-3-2. Startup and switching logic: After initialization, it receives the direct-axis and quadrature-axis voltage command values ​​provided by the PI controller, and calculates the final direct-axis and quadrature-axis voltages based on the angle information of the encoder;

[0052] 5-3-3. Clark transformation: When ADC sampling is completed, the Clark transformation module converts the three-phase current into α and β currents in a two-phase stationary coordinate system;

[0053] 5-3-4. Park transformation: Receive the α and β currents after Clark transformation and the angle information provided by the encoder, and transform them into direct-axis and quadrature-axis currents in the rotating coordinate system; then output an enable signal to indicate that the transformation is complete and ready to enter the PI control link;

[0054] 5-3-5. Inverse Park transformation: According to the direct-axis and quadrature-axis voltage command values ​​provided by the PI controller and the angle information provided by the encoder, they are converted into α and β voltages in a two-phase stationary coordinate system, and the three-phase voltage is output for monitoring at the same time; the output enable signal indicates that the conversion is completed and is ready to enter the SVPWM wave generation link;

[0055] 5-3-6, SVPWM wave generation module: generates PWM signals for driving the inverter according to α and β voltages; outputs PWM enable signal to indicate that PWM output is valid; outputs sampling enable signal to indicate when a new ADC sampling cycle is to be performed; outputs initialization completion signal to start and switch logic;

[0056] Among them, after the SVPWM module is initialized, the sector of the space vector diagram where the current voltage vector is located is determined according to the voltage command value in the input α and β coordinate systems, and the sector information and the converted X, Y, and Z axis components are output; the action time of the two effective voltage vectors is calculated through the sector information and the X, Y, and Z axis components, and then the action time is limited to ensure that they do not exceed the safe working range of the inverter; according to the action time after limitation and the sector information, each switching moment is calculated to generate a periodic triangular wave counter for the generation of PWM signals; the final PWM output signal is generated using the information of the triangular wave counter and the previously calculated switching moment; and an ADC sampling enable signal is generated at the same time to indicate when a new voltage sampling is performed;

[0057] 5-4. Quadrature axis quantity PI control: Use the set proportional gain, integral gain and target current value to perform PI control on the quadrature axis current to generate the quadrature axis voltage command value; the pause signal can pause the PI control, and the enable signal allows the dynamic adjustment of the PI parameters;

[0058] 5-5. Direct axis PI control: Similar to quadrature axis PI control, but the goal here is to control the direct axis current near zero, and different proportional gain and integral gain are used;

[0059] 5-6. Output PWM signal: According to the calculated voltage command value, the FOC module generates a PWM signal for controlling the inverter, and indicates that the PWM output is valid through the PWM enable signal;

[0060] 5-7. Initialization completed: When the initialization process is completed, the initialization completed signal is set to a high level, indicating that the system is ready to enter the normal operation mode;

[0061] 5-8. ADC sampling enable: generated by the FOC module to indicate when a new ADC sampling cycle is to be performed;

[0062] 5-9. PI controller enable: Generated by the FOC module, used to control whether the PI controller should update its output;

[0063] Step 6: Use the UART serial port to allow the FPGA controller to perform bidirectional data transmission with the host computer. The specific process includes the following submodules:

[0064] 6-1. Initialization: All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset;

[0065] 6-2. UART communication: The UART module is responsible for handling serial communication, receiving data from external devices and converting it into 8-bit data for internal use, and outputting a receive completion signal; preparing data to be sent, starting to send when the send enable signal is activated, and outputting a send completion signal. The specific process includes the following submodules:

[0066] 6-2-1. Initialization: All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset; the reset signal is valid at low level;

[0067] 6-2-2, UART serial port reception: The receiving port receives serial data; the internal logic samples and synchronizes the input data according to the set baud rate and system clock frequency; once the start bit is detected, it starts receiving 8 bits of data, and updates the internal state machine for each bit received; after the reception is completed, it outputs a reception completion signal, and at the same time places the received 8 bits of data at the output end; it outputs a reception start signal, which is triggered when the start bit is detected;

[0068] 6-2-3, UART serial port transmission: When the transmission enable signal is activated and there is new 8-bit data ready to be sent, the transmission process is started; the internal logic generates a serial data stream according to the set baud rate and system clock frequency; during the transmission process, the transmission busy signal remains high to indicate that data is being sent; after the transmission is completed, the transmission completion signal is output, and the transmission pin signal returns to the idle state

[0069] 6-2-4. Status monitoring:

[0070] Input completion signal: When a complete frame of 8-bit data is received, it is set to a high level to indicate that the reception is completed;

[0071] Send busy signal: Maintain high level during the sending process to indicate whether there is data being sent;

[0072] Sending completion signal: When a complete frame of 8-bit data is sent, it is set to a high level to indicate that the sending is completed;

[0073] 6-3. Address and data judgment: Receive 8-bit data and receiving completion signal from UART, parse address information and actual data; output address parsing completion signal and data parsing completion signal;

[0074] 6-4. Data area judgment: determine which area the current data belongs to based on the parsed address information and the address parsing completion signal, and set the data splicing area flag accordingly; when the data area judgment is completed, output the splicing completion signal;

[0075] 6-5. Data splicing: Splice 8-bit data into 16-bit data for subsequent processing; after splicing is completed, output a splicing completion signal;

[0076] 6-6. Transmission control: Update the control logic according to the received commands and data, such as adjusting the speed control parameters of the motor; process the three-phase current and voltage information, as well as the received speed commands and PID parameters; output the data to be sent and the first sending enable signal; at the same time, it is also responsible for outputting the results of the received control command parsing to the external device, and providing the control enable signal and the pause signal;

[0077] 6-7. Data decomposition: Decompose 16-bit data into 8-bit format suitable for UART transmission; determine when to start sending based on the first transmission enable signal and the UART transmission completion signal, and generate a UART transmission enable signal.

[0078] Compared with the prior art, the present invention has the following beneficial effects:

[0079] 1. The present invention uses an FPGA controller to replace the PLC controller in the traditional sewage treatment plant. Due to the limited performance of the PLC hardware, the accuracy and real-time performance of the sewage treatment process cannot achieve good results, and there is still a gap in realizing intelligent control of sewage treatment. The hardware performance of FPGA can meet the needs of the sewage treatment process. FPGA has excellent response speed and is suitable for high-demand real-time control systems. It adopts a highly programmable and parallel architecture, which is suitable for hardware deployment of algorithms such as deep learning. It is also small in size, has low operating power consumption, and can run for a long time. Therefore, the FPGA controller is introduced into the sewage treatment process control to achieve the purpose of improving the operating efficiency of sewage treatment and saving energy and reducing consumption.

[0080] 2. At present, the sewage treatment controller interface in the sewage treatment plant is relatively simple and the function is also single. Some of them can only view PI parameters and manually input PI parameters for control. In order to observe the operating conditions of the sewage treatment motor system, this invention uses a host computer to interact with FPGA, and the motor operating conditions can be viewed through the host computer interface. The PI parameters and real-time speed of the motor can also be changed through the host computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figure 1 It is a schematic diagram of the sewage treatment process;

[0082] Figure 2 It is a flow chart of the motor control system;

[0083] Figure 3 It is the block diagram of the motor control system program module;

[0084] Figure 4 This is the function diagram of the host computer main interface;

[0085] Figure 5 This is the upper computer control interface diagram. DETAILED DESCRIPTION

[0086] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0087] like Figure 1-5 As shown, the present invention discloses a sewage treatment motor control system based on FPGA, which uses magnetic field oriented control and seven-segment space vector pulse width modulation to control the motor, and the closed-loop solution is a double closed-loop of speed loop and current loop. Specifically, it includes FPGA controller, ADC sampling device, inverter, Hall sensor and host computer. Thereby solving the problem of insufficient real-time and accuracy of traditional PLC controllers in sewage treatment plants, and FPGA adopts parallel processing mechanism, with fast calculation speed and response speed and high flexibility. Figure 1 The sewage treatment process diagram shown in the figure shows that in the primary treatment, the sewage is initially treated through the coarse grid and the fine grid, and then pumped into different primary sedimentation tanks through the lift pump. In the secondary treatment, the biochemical reaction tank requires a blower for aeration treatment. The present invention can perform high-performance control of the lift pump system and the blower system in the sewage treatment process, improve the efficiency of sewage treatment and achieve the purpose of energy saving and consumption reduction.

[0088] The motor control system flow chart is as follows Figure 2As shown in the figure, the encoder interface on the FPGA decodes the position of the signal transmitted by the motor to calculate the real-time speed of the motor and realize the closed-loop control of the speed loop; the ADC completes the current reconstruction by collecting the voltage information of the Hall sensor and transmits it to the FPGA through the ADC interface to realize the closed-loop control of the current loop; the FPGA controls the motor by transmitting the SVPWM control signal to the inverter; the UART serial port on the FPGA is connected to the host computer, and the operating condition of the motor can be viewed through the host computer interface;

[0089] The implementation of the system is as follows:

[0090] Step 1: Key control, set two keys (key1 and key2) on the FPGA, and control the initialization and start / stop functions according to the key input and pause signal; debounce key1 and key2 to ensure the stability of the key signal, generate a high-level pulse signal with a single clock cycle width through key1 as the initialization start signal, use key2 to switch the tentative state, and when the pause state is high, force it to be set to the pause state. The specific process is the following submodules:

[0091] 1-1: Reset processing:

[0092] When the asynchronous reset signal is at a low level, the pause state is cleared to ensure that the system is in the initial state after power-on or reset;

[0093] 1-2: Key debounce:

[0094] Debounce the keys key1 and key2. For key1, the debounced signal is directly used as the initialization start signal. For key2, the debounced signal is sent to the signal logic control module to generate a key pause state signal.

[0095] 1-3: Generate a pause signal:

[0096] Through the signal logic control module, the pause state signal is switched according to the signal after key2 is debounced. Whenever key2 is pressed effectively, the key pause signal will flip between high level and low level once;

[0097] Step 2: Filter the raw pulse signal from the encoder to remove noise, and calculate the mechanical angle and electrical angle of the rotor based on these signals; perform direction judgment to determine the direction of motor rotation; decode the specific position of the rotor based on the encoder signal; use the CORDIC algorithm to calculate the sine and cosine values ​​based on the electrical angle; finally, calculate the speed of the motor based on the A phase pulse and the direction of rotation. The specific process includes the following submodules:

[0098] 2-1: Reset processing:

[0099] Given an asynchronous reset signal, ensure that all internal state machines and registers return to a known initial state when the system is powered on or reset;

[0100] 2-2: Photoelectric encoder signal filtering and position determination:

[0101] Filter the A, B and Z phase pulses of the encoder to eliminate possible noise interference, determine the direction of motor rotation by analyzing the relative phase relationship between A and B phases, calculate the current mechanical angle and electrical angle of the rotor, and output a flag to indicate the occurrence of the A phase pulse for subsequent speed calculation;

[0102] 2-3: Solving the trigonometric functions of the rotor position:

[0103] Use the CORDIC algorithm to calculate the corresponding sine (sin) and cosine (cos) values ​​according to the electrical angle, and output an enable signal to indicate that the calculation result is valid;

[0104] 2-4: Speed ​​solution:

[0105] The speed of the motor is calculated based on the frequency of occurrence and rotation direction of the A-phase pulse, and an enable signal is provided to indicate that the speed calculation result is valid.

[0106] Step 3: Perform speed loop closed-loop PI control. The speed loop closed-loop process is as follows: Figure 3 As shown, the actual running speed of the motor is calculated through the filtering module and position decoding, the actual running speed of the motor and the target running speed are taken as input, and a control signal is output to adjust the operation of the motor to achieve the desired speed. The specific process includes the following sub-modules:

[0107] 3-1: Reset processing:

[0108] Initialize all registers to default values ​​to ensure that the system is in the initial state after power-on or reset;

[0109] 3-2: Enable signal delay:

[0110] By delaying the enable signal by 4 beats, it is ensured that the system can stably enter a new control cycle each time the enable signal is activated;

[0111] 3-3: Control frequency setting:

[0112] When the enable signal is activated, the enable count register starts counting until it reaches the maximum value defined by the control cycle, and then resets; this is used to control the update frequency of the speed loop to ensure that the speed control logic is not updated too frequently;

[0113] 3-4: Average speed calculation:

[0114] When the enable signal is activated and the enable count register is close to the end of the count, the actual speed is accumulated in the speed accumulation register; when a complete control cycle is completed, that is, when the enable signal returns to zero, the accumulated speed is divided by 4 to obtain the average speed of the recent cycles and assigned to the speed register;

[0115] 3-5: PI control enable:

[0116] Whenever a control cycle is completed and the enable delay signal is high, the PI enable signal is set to high to trigger a PI control operation; at the same time, the calculated average speed is assigned to the speed register as the input of this PI control;

[0117] 3-6: PI controller instantiation:

[0118] Call the PI controller using the provided parameters and the calculated average speed to generate the final control output P value and I value;

[0119] 3-7: Pause function:

[0120] If the pause state signal is high, the PI controller will pause and will not affect the current speed control state.

[0121] Step 4: Process the collected data through ADC, convert the collected voltage data into current data, calculate the corresponding current value, and provide the output of voltage data. The specific process includes the following submodules:

[0122] 4-1: Reset processing:

[0123] Given an asynchronous reset signal, ensure that all internal state machines and registers return to a known initial state when the system is powered on or reset;

[0124] 4-2: AD7606 data acquisition:

[0125] By instantiating the AD7606 driver module, the control signal of AD7606 is managed, and the busy and idle signals and data signals from AD7606 are received; when the acquisition is completed, the ad completion signal is set to a high level, indicating that a complete data acquisition cycle is completed; the collected data is transmitted to the subsequent processing module through 8 independent output ports (channel 1 to channel 8).

[0126] 4-3: Current reconstruction:

[0127] The voltage data from AD7606 is processed using the current reconstruction module and converted into current data; the input includes a clock signal, a reset signal, an AD7606 data acquisition completion signal, and voltage data of 8 channels; the output includes four sets of current data and one set of voltage data;

[0128] 4-4: Enable signal management:

[0129] The ad enable signal is used to control the data acquisition process of AD7606. Only when this signal is valid will a new acquisition cycle be started;

[0130] 4-5: Output enable:

[0131] The current reconstruction module is also responsible for generating an output enable signal, indicating that the current output data is valid.

[0132] Step 5: Use the field oriented control (FOC) algorithm and PI controller to accurately control the motor current. The specific current closed-loop control process is as follows: Figure 3 As shown in the figure, after ADC sampling, the three-phase current is converted into α and β currents in a two-phase stationary coordinate system through the Clark transformation module, and then input into the Park transformation module to convert them into direct-axis and quadrature-axis currents in a rotating coordinate system, and the quadrature-axis current output by the speed PI control is subtracted from the set direct-axis current, and then input into the current PI controller, and the direct-axis and quadrature-axis voltage command values ​​are output to the inverse Park transformation module. The specific process includes the following submodules:

[0133] 5-1: Reset processing:

[0134] All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset;

[0135] 5-2: Initialization starts:

[0136] When the initialization start signal is received, the initialization process is started, and this process will continue until the initialization start signal is set to a high level;

[0137] 5-3: FOC algorithm instantiation:

[0138] The FOC module is responsible for converting the three-phase current into the direct axis and quadrature axis components in the direct coordinate system, and generates a PWM signal to control the inverter according to the voltage command value provided by the PI controller; and the FOC module also manages the ADC sampling enable and PI controller enable signals. The specific process includes the following submodules:

[0139] 5-3-1: Reset processing:

[0140] All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset;

[0141] 5-3-2: Startup and switching logic:

[0142] After initialization, it receives the direct-axis and quadrature-axis voltage command values ​​provided by the PI controller, and calculates the final direct-axis and quadrature-axis voltages according to the angle information of the encoder;

[0143] 5-3-3: Clark transformation:

[0144] When the ADC sampling is completed, the Clark transformation module converts the three-phase current into α and β currents in the two-phase stationary coordinate system;

[0145] 5-3-4: Park Transformation:

[0146] Receive the α and β currents after Clark transformation and the angle information provided by the encoder, and convert them into direct-axis and quadrature-axis currents in the rotating coordinate system; then output an enable signal to indicate that the conversion is complete and ready to enter the PI control link.

[0147] 5-3-5: Inverse Park Transform:

[0148] According to the direct-axis and quadrature-axis voltage command values ​​provided by the PI controller and the angle information provided by the encoder, they are converted into α and β voltages in a two-phase stationary coordinate system, and the three-phase voltage is output for monitoring at the same time; the output enable signal indicates that the conversion is completed and is ready to enter the SVPWM wave generation link.

[0149] 5-3-6: SVPWM wave generation module:

[0150] Generate a PWM signal for driving the inverter based on the α and β voltages; output a PWM enable signal to indicate that the PWM output is valid; output a sampling enable signal to indicate when a new ADC sampling cycle is to be performed; output an initialization completion signal to start and switch logic;

[0151] Among them, after the SVPWM module is initialized, the sector of the space vector diagram where the current voltage vector is located is determined according to the voltage command value in the input α and β coordinate systems, and the sector information and the converted X, Y, and Z axis components are output; the action time of the two effective voltage vectors is calculated through the sector information and the X, Y, and Z axis components, and then the action time is limited to ensure that they do not exceed the safe working range of the inverter; according to the action time after limitation and the sector information, each switching moment is calculated to generate a periodic triangular wave counter for the generation of PWM signals; the final PWM output signal is generated using the information of the triangular wave counter and the previously calculated switching moment; and an ADC sampling enable signal is generated at the same time to indicate when a new voltage sampling is performed.

[0152] 5-4: Cross-axis PI control:

[0153] The quadrature axis current is PI controlled using the set proportional gain, integral gain and target current value to generate a quadrature axis voltage command value; the pause signal can pause the PI control, while the enable signal allows the PI parameters to be adjusted dynamically;

[0154] 5-5: Direct axis two PI control:

[0155] Similar to quadrature axis PI control, but here the goal is to control the direct axis current near zero, and different proportional and integral gains are used;

[0156] 5-6: Output PWM signal:

[0157] According to the calculated voltage command value, the FOC module generates a PWM signal for controlling the inverter and indicates that the PWM output is valid through a PWM enable signal.

[0158] 5-7: Initialization completed:

[0159] When the initialization process is finished, the initialization completion signal is set high, indicating that the system is ready to enter the normal operation mode;

[0160] 5-8: ADC sampling enable:

[0161] Generated by the FOC module to indicate when a new ADC sampling cycle is to be performed;

[0162] 5-9: PI controller enable:

[0163] Generated by the FOC module to control whether the PI controller should update its output.

[0164] Step 6: Use the UART serial port to allow the FPGA controller to perform bidirectional data transmission with the host computer, such as Figure 4 As shown in the upper computer main interface function diagram, the UART serial port on the FPGA is connected to the upper computer. The upper computer interface can display the three-phase voltage and three-phase current curves of the motor, as well as the PI parameters and real-time speed of the motor's speed loop. Figure 5 As shown in the figure, the host computer interface supports PI parameters and expected speed modification, and the speed range is between -3000 and 3000. From these two figures, it can be seen that the set speed is 2000 rpm, and the real-time speed transmitted by the host computer is 2024 rpm, with a small error and high control accuracy. The specific process includes the following submodules:

[0165] 6-1: Initialization:

[0166] All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset;

[0167] 6-2: UART communication:

[0168] The UART module is responsible for handling serial communication, receiving data from external devices and converting it into 8-bit data for internal use, and outputting a receive completion signal; preparing data to be sent, starting to send when the send enable signal is activated, and outputting a send completion signal. The specific process includes the following submodules:

[0169] 6-2-1: Initialization:

[0170] All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset. The reset signal is low level effective;

[0171] 6-2-2: UART serial port receiving:

[0172] The receiving port receives serial data; the internal logic samples and synchronizes the input data according to the set baud rate and system clock frequency; once the start bit is detected, it starts receiving 8 bits of data, updating the internal state machine for each bit received; after the reception is completed, it outputs a receive completion signal and places the received 8 bits of data at the output; it outputs a receive start signal, which is triggered when the start bit is detected;

[0173] 6-2-3: UART serial port sending:

[0174] When the transmit enable signal is activated and there is new 8-bit data ready to be sent, the transmission process is started; the internal logic generates a serial data stream according to the set baud rate and system clock frequency; during the transmission process, the transmit busy signal remains high to indicate that data is being sent; after the transmission is completed, the transmit completion signal is output, and the transmit pin signal returns to the idle state (usually a high level);

[0175] 6-2-4: Condition monitoring:

[0176] Input completion signal: When a complete frame of 8-bit data is received, it is set to a high level to indicate that the reception is completed;

[0177] Send busy signal: Maintain high level during the sending process to indicate whether there is data being sent;

[0178] Send completion signal: When a complete frame of 8-bit data is sent, it is set to a high level to indicate that the sending is completed.

[0179] 6-3: Address and data judgment:

[0180] Receive 8-bit data and receiving completion signal from UART, parse address information and actual data; output address parsing completion signal and data parsing completion signal;

[0181] 6-4: Data area judgment:

[0182] Determine which area the current data belongs to based on the parsed address information and the address parsing completion signal, and set the data splicing area flag accordingly; output the splicing completion signal when the data area judgment is completed;

[0183] 6-5: Data splicing:

[0184] Splice 8-bit data into 16-bit data for subsequent processing; output a splicing completion signal after splicing is completed;

[0185] 6-6: Transmission Control:

[0186] Update the control logic according to the received commands and data, such as adjusting the speed control parameters of the motor. Process the three-phase current and voltage information, as well as the received speed commands and PID parameters; output the data to be sent and the first sending enable signal; at the same time, it is also responsible for outputting the results of the received control command parsing to the external device, and providing the control enable signal and pause signal;

[0187] 6-7: Data decomposition:

[0188] Decompose 16-bit data into 8-bit format suitable for UART transmission; determine when to start transmission based on the first transmission enable signal and the UART transmission completion signal, and generate a UART transmission enable signal.

[0189] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0190] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode includes only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A sewage treatment motor control system based on FPGA, comprising an FPGA controller, an ADC sampling device, an inverter, a Hall sensor and a host computer; characterized in that: The encoder interface on the FPGA controller performs position decoding on the signal transmitted by the motor to calculate the real-time speed of the motor, thereby realizing closed-loop control of the speed loop; the ADC sampling device completes current reconstruction by collecting voltage information of the Hall sensor, and transmits it to the FPGA controller through the ADC sampling device interface to realize closed-loop control of the current loop; the FPGA controller controls the motor by transmitting the SVPWM control signal to the inverter; and controls the initialization, start and stop of the PMSM through buttons and the host computer interface.

2. The FPGA-based sewage treatment motor control system according to claim 1 is characterized in that: The FPGA controller includes a speed PI module, a current PI module, a coordinate transformation module, an SVPWM module, an ADC sampling module, a position decoding and a speed calculation module. The UART serial port on the FPGA controller is connected to a host computer. The host computer supports modification of PI parameters and expected speed, and can view the three-phase current, three-phase voltage, PI parameters and real-time speed of the motor.

3. The FPGA-based sewage treatment motor control system according to claim 2 is characterized in that: The maximum sampling rate of the Hall sensor is 100%.

4. The FPGA-based sewage treatment motor control system according to claim 3 is characterized in that: The buttons include a button key1 and a button key2. The user triggers the initialization process of the system by pressing the button key1, and controls the pause state of the system by pressing the button key2. At the same time, the user can force the system to enter the pause mode by pressing the button.

5. The FPGA-based sewage treatment motor control system according to claim 4 is characterized in that: The closed-loop control of the speed loop takes the actual running speed and the target running speed of the motor as inputs, and outputs a control signal to adjust the operation of the motor to achieve the desired speed; firstly, the parameters of the proportional gain, integral gain, target speed, maximum output limit and maximum count value of the control cycle of the PI controller are set; then the frequency management is controlled to ensure that the speed control is performed within a specific time interval rather than every clock cycle; in each control cycle, the actual speed average value of the recent few cycles is calculated for more accurate speed feedback; finally, the control signal is generated using the PI control algorithm according to the error between the set target speed and the calculated actual average speed.

6. The FPGA-based sewage treatment motor control system according to claim 5 is characterized in that: The closed-loop control of the current loop uses a magnetic field oriented control algorithm and a PI controller to accurately control the current of the motor; the three-phase voltage of the motor is collected by an ADC signal acquisition module and reconstructed into a three-phase current, and when the ADC sampling is completed, the Clark transformation module converts the three-phase current into α and β currents in a two-phase stationary coordinate system; the α and β currents after Clark transformation and the angle information provided by the encoder are received, and the direct-axis and quadrature-axis currents in the rotating coordinate system are input into the current PI controller through Park transformation, and according to the direct-axis and quadrature-axis voltage command values ​​provided by the PI controller and the angle information provided by the encoder, they are converted into α and β voltages in a two-phase stationary coordinate system through an inverse Park transformation, and a PWM signal for driving an inverter is generated according to the α and β voltages to control the motor to realize the closed-loop control of the current loop.

7. The FPGA-based sewage treatment motor control system according to claim 1 is characterized in that: The host computer communicates with the FPGA through the UART serial port; using full-duplex communication mode, the host computer receives the three-phase voltage, three-phase current, PI parameter value and real-time speed of the motor from the FPGA for display, and sends commands to the FPGA through the host computer interface to change the PI parameter value and speed of the motor.

8. The FPGA-based sewage treatment motor control system according to claim 1 is characterized in that: The ADC sampling scheme is Hall sensor sampling.

9. A sewage treatment motor control method based on FPGA, characterized in that: The system according to any one of claims 1 to 8 comprises the following steps: Step 1: Key control, set the key1 and key2 on the FPGA, and control the initialization and start and stop according to the key input and pause signal; debounce the key1 and key2 to ensure the stability of the key signal, generate a high-level pulse signal with a single clock cycle width through the key1 as the initialization start signal, use the key2 to switch the tentative state, and when the pause state is high, force it to be set to the pause state. The specific process is the following sub-modules: 1-1. Reset processing: When the asynchronous reset signal is at a low level, the pause state is cleared; 1-2. Key debounce: Debounce the keys key1 and key2. For key1, the debounced signal is directly used as the initialization start signal, and the debounced signal of key2 is sent to the signal logic control module to generate a key pause state signal; 1-3. Generate a pause signal: Through the signal logic control module, the pause state signal is switched according to the signal after key2 is debounced. Whenever key2 is pressed effectively, the key pause signal will flip between high level and low level once; Step 2: Filter the original pulse signal from the encoder to remove noise, and calculate the mechanical angle and electrical angle of the rotor based on these signals; perform direction judgment to determine the direction of motor rotation; decode the specific position of the rotor based on the encoder signal; use the CORDIC algorithm to calculate the sine and cosine values ​​based on the electrical angle; finally, calculate the speed of the motor based on the A phase pulse and the direction of rotation. The specific process includes the following submodules: 2-1. Reset processing: Given an asynchronous reset signal, ensure that all internal state machines and registers can return to a known initial state when the system is powered on or reset; 2-2. Photoelectric encoder signal filtering and position determination: Filter the A-phase, B-phase and Z-phase pulses of the encoder to eliminate noise interference, determine the direction of motor rotation by analyzing the relative phase relationship between phase A and phase B, calculate the current mechanical angle and electrical angle of the rotor, and output a flag to indicate the occurrence of the A-phase pulse for subsequent speed calculation; 2-3. Solving the trigonometric function of the rotor position: Use the CORDIC algorithm to calculate the corresponding sine and cosine values ​​according to the electrical angle, and output an enable signal to indicate that the calculation result is valid; 2-4. Speed ​​solution: Calculate the motor speed based on the frequency and rotation direction of the A-phase pulse, and provide an enable signal to indicate that the speed calculation result is valid; Step 3: Perform speed loop closed-loop PI control, take the actual motor speed and target speed as input, and output a control signal to adjust the motor operation to achieve the desired speed. The specific process includes the following submodules: 3-1. Reset processing: initialize all registers to default values; 3-2. Enable signal delay: delay the enable signal by 4 beats; 3-3. Control frequency setting: When the enable signal is activated, the enable count register starts counting until it reaches the maximum value defined by the control cycle, and then resets; 3-4. Average speed calculation: When the enable signal is activated and the enable count register is close to the end of counting, the actual speed is accumulated into the speed accumulation register; When a control cycle is completed, that is, when the enable signal returns to zero, the accumulated speed is divided by 4 to obtain the average speed of the recent cycles and assign it to the speed register; 3-5. PI control enable: Whenever a control cycle is completed and the enable delay signal is at a high level, the PI enable signal is set to a high level to trigger a PI control operation; at the same time, the calculated average speed is assigned to the speed register as the input of this PI control; 3-6. PI controller instantiation: Call the PI controller using the provided parameters and the calculated average speed to generate the final control output P value and I value; 3-7. Pause: If the pause state signal is high, the PI controller will pause; Step 4: Process the collected data through ADC, convert the collected voltage data into current data, calculate the corresponding current value, and provide the output of voltage data. The specific process includes the following submodules: 4-1. Reset processing: Given an asynchronous reset signal, when the system is powered on or reset, all internal state machines and registers can return to a known initial state; 4-2. AD7606 data acquisition: By instantiating the AD7606 driver module, managing the control signal of AD7606, and receiving the busy and idle signals and data signals from AD7606; when the acquisition is completed, the ad completion signal is set to a high level, indicating that a complete data acquisition cycle is completed; the collected data is transmitted to the subsequent processing module through 8 independent output ports; 4-3. Current reconstruction: Use the current reconstruction module to process the voltage data from AD7606 and convert it into current data; the input includes clock signal, reset signal, AD7606 data acquisition completion signal and 8 channels of voltage data; the output includes four sets of current data and one set of voltage data; 4-4. Enable signal management: The ad enable signal is used to control the data acquisition process of AD7606. Only when this signal is valid will a new acquisition cycle be started; 4-5. Output enable: The current reconstruction module is also responsible for generating an output enable signal, indicating that the current output data is valid; Step 5: The current of the motor is precisely controlled through the field-oriented control algorithm and the PI controller. The specific process includes the following submodules: 5-1. Reset processing: All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset; 5-2. Initialization start: When the initialization start signal is received, the initialization process is started, and this process will continue until the initialization start signal is set to a high level; 5-3. FOC algorithm instantiation: The FOC module is responsible for converting the three-phase current into the direct axis and quadrature axis components in the direct coordinate system, and generating PWM signals to control the inverter according to the voltage command value provided by the PI controller; and the FOC module also manages the ADC sampling enable and PI controller enable signals. The specific process includes the following sub-modules: 5-3-1. Reset processing: All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset; 5-3-2. Startup and switching logic: After initialization, it receives the direct-axis and quadrature-axis voltage command values ​​provided by the PI controller, and calculates the final direct-axis and quadrature-axis voltages based on the angle information of the encoder; 5-3-3. Clark transformation: When ADC sampling is completed, the Clark transformation module converts the three-phase current into α and β currents in a two-phase stationary coordinate system; 5-3-4. Park transformation: Receive the α and β currents after Clark transformation and the angle information provided by the encoder, and transform them into direct-axis and quadrature-axis currents in the rotating coordinate system; then output an enable signal to indicate that the transformation is complete and ready to enter the PI control link; 5-3-5. Inverse Park transformation: According to the direct-axis and quadrature-axis voltage command values ​​provided by the PI controller and the angle information provided by the encoder, they are converted into α and β voltages in a two-phase stationary coordinate system, and the three-phase voltage is output for monitoring at the same time; the output enable signal indicates that the conversion is completed and is ready to enter the SVPWM wave generation link; 5-3-6, SVPWM wave generation module: generates PWM signals for driving the inverter according to α and β voltages; Outputting PWM enable signal indicates that PWM output is valid; The output sampling enable signal indicates when a new ADC sampling cycle is to be performed; Output initialization completion signal is used to start and switch logic; Among them, after the SVPWM module is initialized, the sector of the space vector diagram where the current voltage vector is located is determined according to the voltage command value in the input α and β coordinate systems, and the sector information and the converted X, Y, and Z axis components are output; the action time of the two effective voltage vectors is calculated through the sector information and the X, Y, and Z axis components, and then the action time is limited; according to the action time after limitation and the sector information, each switching moment is calculated to generate a periodic triangular wave counter for the generation of PWM signals; the final PWM output signal is generated using the information of the triangular wave counter and the previously calculated switching moment; and an ADC sampling enable signal is generated at the same time to indicate when a new voltage sampling is performed; 5-4. Quadrature axis quantity PI control: Use the set proportional gain, integral gain and target current value to perform PI control on the quadrature axis current to generate a quadrature axis voltage command value; pause signal pauses PI control; 5-5. Direct axis PI control: control the direct axis current near zero and use different proportional gain and integral gain; 5-6. Output PWM signal: According to the calculated voltage command value, the FOC module generates a PWM signal for controlling the inverter, and indicates that the PWM output is valid through the PWM enable signal; 5-7. Initialization completed: When the initialization process is completed, the initialization completed signal is set to a high level; 5-8. ADC sampling enable: generated by the FOC module to indicate when a new ADC sampling cycle is to be performed; 5-9. PI controller enable: Generated by the FOC module, used to control whether the PI controller should update its output; Step 6: Use the UART serial port to allow the FPGA controller to perform bidirectional data transmission with the host computer. The specific process includes the following submodules: 6-1. Initialization: All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset; 6-2. UART communication: The UART module is responsible for handling serial communication, receiving data from external devices and converting it into 8-bit data for internal use, and outputting a receive completion signal; preparing data to be sent, starting to send when the send enable signal is activated, and outputting a send completion signal. The specific process includes the following submodules: 6-2-1. Initialization: All registers are initialized to default values ​​to ensure that the system is in the initial state after power-on or reset; the reset signal is valid at low level; 6-2-2. UART serial port reception: The receiving port receives serial data; the internal logic samples and synchronizes the input data according to the set baud rate and system clock frequency; after detecting the start bit, it starts to receive 8 bits of data, and updates the internal state machine for each bit received; after receiving is completed, it outputs a receive completion signal and places the received 8 bits of data at the output end; it outputs a receive start signal, which is triggered when the start bit is detected; 6-2-3. UART serial port sending: When the transmit enable signal is activated and there is new 8-bit data ready to be sent, the transmission process is started; the internal logic generates a serial data stream according to the set baud rate and system clock frequency; during the transmission process, the transmit busy signal remains high to indicate that data is being sent; after the transmission is completed, the transmit completion signal is output, and the transmit pin signal returns to the idle state; 6-2-4. Status monitoring: Input completion signal: When a complete frame of 8-bit data is received, it is set to a high level to indicate that the reception is completed; Send busy signal: Maintain high level during the sending process to indicate whether there is data being sent; Sending completion signal: When a complete frame of 8-bit data is sent, it is set to a high level to indicate that the sending is completed; 6-3. Address and data judgment: Receive 8-bit data and receiving completion signal from UART, parse out address information and actual data; output address parsing completion signal and data parsing completion signal; 6-4. Data area judgment: Determine which area the current data belongs to based on the parsed address information and the address parsing completion signal, and set the data splicing area flag accordingly; output the splicing completion signal when the data area judgment is completed; 6-5. Data splicing: Splice 8-bit data into 16-bit data for subsequent processing; output a splicing completion signal after splicing is completed; 6-6. Transmission control: Update the control logic according to the received commands and data, and adjust the speed control parameters of the motor; process the three-phase current and voltage information, as well as the received speed commands and PID parameters; output the data to be sent and the first sending enable signal; at the same time, it is also responsible for outputting the results of the received control command analysis to the external device, and providing the control enable signal and the pause signal; 6-7. Data decomposition: Decompose 16-bit data into 8-bit format suitable for UART transmission; determine when to start transmission based on the first transmission enable signal and the UART transmission completion signal, and generate a UART transmission enable signal.

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