Capacitive load power supply circuit and capacitive load starting impact current suppression circuit

Abstract

The invention belongs to the technical field of capacitive loads, and particularly relates to a capacitive load power supply circuit and a capacitive load starting impact current suppression circuit. The circuit comprises a pre-charging branch circuit which is connected with a high-side switch in parallel and used for pre-charging a capacitive load, a first switching tube and a current-limiting resistor are connected to the pre-charging branch circuit in series, and the resistance value of the current-limiting resistor can prevent the current in the pre-charging branch circuit from exceeding the maximum breakover current of the first switching tube and can also prevent the current in the pre-charging branch circuit from exceeding the maximum breakover current of the second switching tube. And the impact current when the pre-charged capacitive load is started can be ensured to be smaller than the resistance value of the current for triggering the short circuit of the high-side switch.

Description

Technical Field

[0001] The invention belongs to the technical field of capacitive loads, and in particular relates to a capacitive load power supply circuit and a capacitive load startup impact current suppression circuit. Background Art

[0002] Intelligent high-side switches have functions such as current monitoring, overcurrent / short-circuit protection, overtemperature protection, and open-circuit diagnosis. They are a good solution for electrification and intelligence. Therefore, many models use intelligent high-side switches to replace fuses and relays. However, the high impact current of capacitive loads will have an adverse effect on the operation of high-side switches.

[0003] Since controller-type loads use electrolytic capacitors at the power input, they have capacitive load characteristics and will generate a short-term high-current impact at the moment the load starts. When the impact current is too large, it is very easy to trigger the short-circuit protection of the intelligent high-side switch, causing the controller to fail to start.

[0004] In order to solve the technical problem that the high-side switch short-circuit protection is triggered by excessive impact current, resulting in the controller being unable to start, the Chinese invention patent application with application publication number CN115395935A proposes a technical means of using a pre-charging branch to pre-charge the capacitive load before the high-side switch is turned on so that the capacitive load capacitor has a certain voltage, thereby suppressing the impact current. A current-limiting resistor and a switch tube are connected in series in the pre-charging branch. The prior art does not disclose a method for setting the resistance value of the current-limiting resistor. If the resistance value of the current-limiting resistor is small, the current in the pre-charging branch will be too large, exceeding the maximum on-resistance of the switch tube, causing damage to the switch tube; if the resistance value of the current-limiting resistor is large, the pre-charging of the capacitive load will be insufficient, and the capacitive load capacitor voltage will be low, which is insufficient to suppress the impact current when the high-side switch is turned on, so that the impact current is less than the maximum working current of the high-side switch that does not trigger a short circuit, which still causes the controller to fail to start normally. Summary of the invention

[0005] The purpose of the present invention is to provide a capacitive load power supply circuit and a capacitive load startup impact current suppression circuit to solve the technical problem that the current limiting resistor in the pre-charging branch has too small a resistance to damage the switch tube or has too large a resistance to cause the controller to fail to start normally.

[0006] In order to solve the above technical problems, the present invention provides a capacitive load startup impact current suppression circuit, including a pre-charging branch connected in parallel with a high-side switch and used to pre-charge the capacitive load, wherein a first switch tube and a current limiting resistor are connected in series on the pre-charging branch, and the resistance value of the current limiting resistor can prevent the current in the pre-charging branch from exceeding the maximum conduction current of the first switch tube, and can ensure that the impact current of the pre-charged capacitive load when it starts is less than the current that triggers the short circuit of the high-side switch.

[0007] Furthermore, the method for determining the upper limit of the resistance value of the current limiting resistor is:

[0008]

[0009] Where VBAT is the power supply voltage, k is the derating factor, R1 max is the upper limit of the current limiting resistor, R ESR is the equivalent resistance of the capacitive load when the capacitor is short-circuited at the moment of power-on, RL is the equivalent resistance of the capacitive load during stable operation after power-on, and I_HSD_MAX is the maximum operating current that does not trigger a short circuit on the high-side switch;

[0010] The method to determine the lower limit of the current limiting resistor is:

[0011]

[0012] Where R1 min is the lower limit of the resistance of the current limiting resistor, and I_NTC_MAX is the maximum on-state current of the first switch tube.

[0013] Furthermore, the delay time between the first switch tube conduction signal being sent and the high-side switch conduction signal being sent satisfies the following formula:

[0014]

[0015] Where t_delay is the delay time, R1 is the resistance of the current limiting resistor at room temperature, RL is the equivalent resistance of the capacitive load when running stably after power-on, and CL is the capacitance of the capacitive load.

[0016] Furthermore, the on-resistance of the first switch tube satisfies the following conditions:

[0017]

[0018] In the formula, R DS_ON is the maximum on-resistance of the first switch tube; T JC is the junction temperature of the first switch tube, T amb is the ambient temperature, I_NTC_MAX is the maximum current of the first switch tube, t_delay is the delay time between the first switch tube conduction signal and the high-side switch conduction signal, Z thJC (t_delay) is the transient thermal resistance of the first switch tube pulse under the delay time.

[0019] Furthermore, a second switch tube is connected in series between the controlled end of the first switch tube and the ground, and the controlled end of the second switch tube is used to receive a first enable signal, and the first enable signal is used to turn on the first switch tube.

[0020] Furthermore, the power supply is connected to the second switch tube and grounded through a voltage dividing branch, the voltage dividing branch is sequentially connected in series with a fifth resistor and a fourth resistor along the current direction, and the second switch tube is connected to the controlled end of the first switch tube through a voltage dividing point of the two resistors.

[0021] Furthermore, a voltage stabilizing diode is connected in parallel between both ends of the fifth resistor.

[0022] Furthermore, the first switch tube is a power type PMOS tube.

[0023] The present invention is an improved invention. The capacitive load starting impact current suppression circuit of the present invention has a current limiting resistor connected in series in the pre-charging branch. By setting the resistance value of the current limiting resistor, it can ensure that the current after current limiting will not exceed the maximum on-current of the first switch in the pre-charging branch, and can also ensure that the capacitive load capacitor voltage is sufficient to suppress the impact current when the high-side switch is turned on, so that the impact current will not exceed the maximum on-current of the high-side switch, thereby ensuring that the capacitive load can start normally.

[0024] In order to solve the above technical problems, the present invention also provides a capacitive load power supply circuit, including a high-side switch, and also including a pre-charging branch connected in parallel with the high-side switch and used to pre-charge the capacitive load, the pre-charging branch is connected in series with a first switch tube and a current limiting resistor, and the resistance value of the current limiting resistor can not only prevent the current in the pre-charging branch from exceeding the maximum conduction current of the first switch tube, but also ensure that the impact current of the pre-charged capacitive load when it is started is less than the resistance value of the current that triggers the short circuit of the high-side switch.

[0025] Furthermore, the method for determining the upper limit of the resistance value of the current limiting resistor is:

[0026]

[0027] Where VBAT is the power supply voltage, k is the derating factor, R1 max is the resistance of the current limiting resistor, R ESR is the equivalent resistance of the capacitive load when the capacitor is short-circuited at the moment of power-on, RL is the equivalent resistance of the capacitive load during stable operation after power-on, and I_HSD_MAX is the maximum operating current that does not trigger a short circuit on the high-side switch;

[0028] The method to determine the lower limit of the current limiting resistor is:

[0029]

[0030] Where R1 min is the lower limit of the resistance of the current limiting resistor, and I_NTC_MAX is the maximum on-state current of the first switch tube.

[0031] Furthermore, the delay time between the first switch tube conduction signal being sent and the high-side switch conduction signal being sent satisfies the following formula:

[0032]

[0033] Where t_delay is the delay time, R1 is the resistance of the current limiting resistor at room temperature, RL is the equivalent resistance of the capacitive load when running stably after power-on, and CL is the capacitance of the capacitive load.

[0034] Furthermore, the on-resistance of the first switch tube satisfies the following conditions:

[0035]

[0036] In the formula, R DS_ON is the maximum on-resistance of the first switch tube; T JC is the junction temperature of the first switch tube, T amb is the ambient temperature, I_NTC_MAX is the maximum current passing through the first switch tube, t_delay is the delay time, Z thJC (t_delay) is the transient thermal resistance of the first switch tube pulse under the delay time.

[0037] The present invention is an improved invention, and its beneficial effects are the same as those of the capacitive load startup impact current suppression circuit of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a circuit structure diagram of a capacitive load inrush current suppression circuit of a circuit embodiment of the present invention;

[0039] Figure 2 It is a schematic diagram of parameter changes during the operation of the capacitive load inrush current suppression circuit of the circuit embodiment of the present invention;

[0040] Figure 3 It is a flow chart of a method for determining parameters of a capacitive load impact current suppression circuit in a circuit embodiment of the present invention. DETAILED DESCRIPTION

[0041] A capacitive load power supply circuit and a capacitive load startup impact current suppression circuit of the present invention have a current limiting resistor connected in series in a pre-charging branch. By setting the resistance value of the current limiting resistor, it can be ensured that the current after current limiting will not exceed the maximum on-current of the first switch in the pre-charging branch, and it can also be ensured that the capacitor voltage of the capacitive load is sufficient to suppress the impact current when the high-side switch is turned on, so that the impact current will not exceed the maximum on-current of the high-side switch, thereby ensuring that the capacitive load can start normally.

[0042] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0043] Power supply circuit embodiment:

[0044] The capacitive load power supply circuit of the present invention is as follows Figure 1 As shown, the high side switch HSD1 is included, and the high side switch HSD1 is used to start the capacitive load power supply when it is turned on. In order to pre-charge the capacitive load and thus suppress the impact current, the capacitive load power supply circuit of the present invention also includes a capacitive load startup impact current suppression circuit. The specific structure of the capacitive load startup impact current suppression circuit is as follows:

[0045] The capacitive load startup inrush current suppression circuit of the present invention comprises a pre-charging branch connected in parallel at both ends of a high-side switch HSD1. The pre-charging branch is connected in series with a first switch tube Q1 for controlling the on-off of the pre-charging branch and a current limiting resistor R1 for limiting the pre-charging current of the capacitive load. The pre-charging branch is used to pre-charge the capacitive load when the first switch tube Q1 is turned on.

[0046] The resistance of the current limiting resistor is such that it can prevent the current in the pre-charge branch from exceeding the maximum on-current of the first switch tube, and can ensure that the capacitive load after pre-charge is sufficient to suppress the impact current to be less than the maximum on-current of the high-side switch. In this embodiment, the first switch tube Q1 is a power PMOS tube, and the current limiting resistor R1 is a power NTC resistor. As other implementations, the first switch tube can also be an IGBT, and the current limiting resistor can also be a fixed resistor or other resistor. The source of the power PMOS tube Q1 is connected to the power supply, and the drain of the power PMOS tube Q1 is used to connect the capacitive load. In this embodiment, the power NTC resistor R1 is connected in series between the drain of the transistor and the capacitive load.

[0047] In order to control the on and off of the power type PMOS tube Q1, the capacitive load startup impact current suppression circuit of this embodiment also includes a startup branch for connecting the gate of the power type PMOS tube Q1. The startup branch is connected in series with a second switch tube Q2. In this embodiment, the second switch tube Q2 is a triode. The collector of the triode Q2 is used to connect the gate of the power type PMOS tube Q1, and the emitter of the triode Q2 is grounded. The collector of the triode Q2 is also used to connect to the power supply. The base of the triode Q2 is used to receive the enable signal EN1. When the enable signal EN1 is received, the triode Q2 is turned on.

[0048] In the start-up branch of this embodiment, a fourth resistor R4 is also connected in series, one end of the fourth resistor R4 is connected to the collector of the transistor Q2; the other end of the fourth resistor R4 is directly connected to the gate of the power type PMOS transistor Q1, and is also connected to the power supply through the fifth resistor R5. The fourth resistor R4 and the fifth resistor R5 form a voltage dividing branch, and the transistor Q2 is connected to the gate of the power type PMOS transistor Q1 through the voltage dividing point of the voltage dividing branch.

[0049] In this embodiment, a voltage stabilizing diode Z1 is connected in parallel to both ends of the fifth resistor R5. The voltage stabilizing diode Z1 is used to stabilize the voltage drop between both ends of R5.

[0050] When the transistor Q2 is turned on, a voltage drop is generated across R5 after the voltage is divided by R4 and R5. The voltage drop is stabilized by the Zener diode and the power PMOS tube Q1 is started using the voltage drop.

[0051] When working, the control signal EN1 is first enabled, and the transistor Q2 is controlled to be turned on through the resistor R2. When the transistor Q2 is turned on, the gate of the power PMOS tube Q1 is pulled down through the resistance value of R4, so that the power PMOS tube Q1 is turned on, and the capacitive load is powered through the power NTC resistor. After the delay time, the control signal EN2 is enabled to turn on the high-side switch HSD1. At this time, due to the initial voltage of the capacitor CL, the impact current when HSD1 is turned on is effectively suppressed, thereby realizing effective power supply to the capacitive load. During the process, the change of the current Is(Q1) of the first switch tube is as follows: Figure 2 As shown in the blue curve, the high-side switch current Is(Hsd) is Figure 2 As shown in the red curve, the change of the capacitive load capacitor voltage is as follows Figure 2 Shown as the green curve in the middle. Figure 2 At 1ms, the power PMOS tube Q1 is turned on, and the instantaneous current is equal to the maximum current that can pass through the power NTC resistor R1. The capacitive load begins to be pre-charged, the capacitive load voltage increases, and the current of the power PMOS tube Q1 decreases. After a delay of 3ms to 4ms, the high-side switch is turned on. Since the capacitive load has been pre-charged, the impact current can be suppressed. Under this effect, the high-side switch current decreases rapidly, and the initial peak value does not exceed the maximum peak value of the high-side switch triggering a short circuit.

[0052] In this embodiment, in order to filter the first enable signal EN1, the gate of the second switch tube is connected to a filter circuit. The filter circuit includes a filter capacitor C1 and a filter resistor R3 connected in parallel, one end of the filter circuit is connected to the base of the second switch tube Q2, and the other end is connected to the emitter of the second switch tube Q2. A second resistor R2 is also connected in series between the gate of the second switch tube and the second enable signal EN2.

[0053] In order to ensure the normal operation of the current suppression circuit, it is necessary to determine the parameters in the circuit. The specific parameter determination method is as follows: Figure 3 As shown, the following steps are included:

[0054] Step 1: Determine the resistance value of the power NTC resistor R1.

[0055] The power NTC resistor R1 serves as the current limiting resistor of the pre-charging branch. Its resistance cannot be too small, otherwise the current of the pre-charging branch will exceed the maximum current of the first switch tube. At the same time, its resistance cannot be too large, otherwise the capacitor voltage will be too low to effectively suppress the impact current when the high-side switch is started.

[0056] The resistance value of the power NTC resistor R1 should meet the following conditions:

[0057]

[0058]

[0059] In the formula, VBAT is the power supply voltage, k is the derating factor, which is equal to 1-1 / e≈0.63, so it is usually taken as 0.63, R1 max R is the upper limit of the resistance of power NTC at room temperature (25°C). ESR R1 is the equivalent resistance of the capacitive load when the capacitor is short-circuited at the moment of power-on at room temperature, and RL is the equivalent resistance of the capacitive load when it is running stably after power-on at room temperature. I_HSD_MAX is the maximum operating current that does not trigger a short circuit on the high-side switch. min is the lower limit of the resistance of the current limiting resistor, and I_NTC_MAX is the maximum current passing through the first switch tube.

[0060] After a time constant (delay time), the voltage across the capacitor reaches its maximum value. Constructing the voltage balance equation when the voltage across the capacitor reaches the maximum value, we can get Taking R1 out of the equation, we can get the calculation formula for the power NTC resistor R1.

[0061] When the power NTC resistor R1 is equal to the calculation result of the above formula, the pre-charge current of the capacitive load is exactly the maximum operating current that does not trigger a short circuit. As another embodiment, the resistance value of the capacitive load R1 should be greater than the calculation result of the above formula. Only then can it be ensured that the operating current of the capacitive load is less than the maximum operating current that does not trigger a short circuit, and the capacitive load will not short-circuit.

[0062] Step 2: Determine the delay time between the enable signals EN1 and EN2.

[0063] During the analysis, the left side of the current limiting resistor R1 is equivalent to the ground. After the equivalent, R1 and the resistance RL of the capacitive load model form a parallel relationship. The delay time can be obtained by multiplying the resistance of the two in parallel by the capacitive load capacitance.

[0064] Based on the above analysis, the delay time should meet the following conditions:

[0065]

[0066] Where t_delay is the delay time, R1 is the resistance of the current limiting resistor at room temperature, RL is the equivalent resistance of the capacitive load when running stably after power-on, and CL is the capacitance of the capacitive load.

[0067] Step 3: Determine the on-resistance of the power PMOS tube Q1.

[0068] The on-resistance of the power PMOS tube Q1 should meet the following conditions:

[0069]

[0070] In the formula, R DS_ON is the maximum on-resistance of the first switch tube; T JC is the junction temperature of the first switch tube, T amb is the ambient temperature, I_NTC_MAX is the maximum current passing through the first switch tube, Z thJC (t_delay) is the transient thermal resistance of the first switch tube pulse under the delay time condition. Under the same current conditions, the greater the on-resistance of the first switch tube, the greater the heat loss power generated, and the higher the junction temperature rises. Exceeding the junction temperature will cause PMOS damage. Therefore, the on-resistance of the first switch tube cannot be too large. In this embodiment, the maximum on-resistance of the first switch tube is calculated by the above formula. As long as the on-resistance of the first switch tube is less than or equal to the calculated result, it can be ensured that the switch tube will not be damaged by overheating.

[0071] Load startup inrush current suppression circuit implementation example:

[0072] The capacitive load startup impact current suppression circuit of the present invention is as described in the power supply circuit embodiment. The structure and principle of the circuit have been described in detail in the power supply circuit embodiment and will not be repeated in this embodiment.

[0073] A capacitive load power supply circuit and a capacitive load startup impact current suppression circuit of the present invention set the resistance value of the capacitive load in series in the pre-charging branch, and the resistance value can ensure that the current after current limiting will not exceed the maximum conduction current of the first switch in the pre-charging branch, and can also ensure that the capacitor voltage of the capacitive load is sufficient to suppress the impact current when the high-side switch is turned on, so that the impact current will not exceed the maximum conduction current of the high-side switch, and ensure that the capacitive load can start normally. Furthermore, the present invention proposes a method for calculating the delay time between the issuance of the first switch tube conduction signal of the pre-charging branch and the issuance of the conduction signal between the high-side switch, which can ensure that the pre-charging time is sufficient and the suppression effect on the impact current is guaranteed.

Claims

1. A capacitive load startup inrush current suppression circuit, comprising a pre-charging branch connected in parallel with a high-side switch and used to pre-charge the capacitive load, wherein a first switch tube and a current limiting resistor are connected in series on the pre-charging branch, characterized in that: The resistance of the current limiting resistor can prevent the current in the pre-charge branch from exceeding the maximum conduction current of the first switch tube, and can also ensure that the impact current of the pre-charged capacitive load when starting is less than the current that triggers the high-side switch short circuit.

2. The capacitive load startup inrush current suppression circuit according to claim 1, characterized in that: The method to determine the upper limit of the current limiting resistor is: Where VBAT is the power supply voltage, k is the derating factor, R1 max is the upper limit of the current limiting resistor, R ESR is the equivalent resistance of the capacitive load when the capacitor is short-circuited at the moment of power-on, RL is the equivalent resistance of the capacitive load during stable operation after power-on, and I_HSD_MAX is the maximum operating current that does not trigger a short circuit on the high-side switch; The method to determine the lower limit of the current limiting resistor is: Where R1 min is the lower limit of the resistance of the current limiting resistor, and I_NTC_MAX is the maximum on-state current of the first switch tube.

3. The capacitive load startup inrush current suppression circuit according to claim 1, characterized in that: The delay time between the first switch tube conduction signal and the high-side switch conduction signal satisfies the following formula: Where t_delay is the delay time, R1 is the resistance of the current limiting resistor at room temperature, RL is the equivalent resistance of the capacitive load when running stably after power-on, and CL is the capacitance of the capacitive load.

4. The capacitive load startup inrush current suppression circuit according to claim 1, characterized in that: The on-resistance of the first switch tube meets the following conditions: In the formula, R DS_ON is the maximum on-resistance of the first switch tube; T JC is the junction temperature of the first switch tube, T amb is the ambient temperature, I_NTC_MAX is the maximum current of the first switch tube, t_delay is the delay time between the first switch tube conduction signal and the high-side switch conduction signal, Z thJC (t_delay) is the transient thermal resistance of the first switch tube pulse under the delay time.

5. The capacitive load startup inrush current suppression circuit according to claim 1, characterized in that: A second switch tube is connected in series between the controlled end of the first switch tube and the ground. The controlled end of the second switch tube is used to receive a first enable signal. The first enable signal is used to turn on the first switch tube.

6. The capacitive load startup inrush current suppression circuit according to claim 5, characterized in that: The power supply is connected to the second switch tube through a voltage dividing branch and grounded. The voltage dividing branch is connected in series with a fifth resistor and a fourth resistor in sequence along the current direction, and the second switch tube is connected to the controlled end of the first switch tube through a voltage dividing point of the two resistors.

7. The capacitive load startup inrush current suppression circuit according to claim 6, characterized in that: A voltage stabilizing diode is connected in parallel to both ends of the fifth resistor.

8. The capacitive load startup inrush current suppression circuit according to any one of claims 1 to 7, characterized in that: The first switch tube is a power type PMOS tube.

9. A capacitive load power supply circuit, comprising a high-side switch, and also comprising a pre-charging branch connected in parallel with the high-side switch and used to pre-charge the capacitive load, wherein the pre-charging branch is connected in series with a first switch tube and a current limiting resistor, characterized in that: The resistance of the current limiting resistor can prevent the current in the pre-charge branch from exceeding the maximum conduction current of the first switch tube, and can also ensure that the impact current of the pre-charged capacitive load when starting is less than the current that triggers the high-side switch short circuit.

10. The capacitive load power supply circuit according to claim 9, characterized in that: The method to determine the upper limit of the current limiting resistor is: Where VBAT is the power supply voltage, k is the derating factor, R1 max is the resistance of the current limiting resistor, R ESR is the equivalent resistance of the capacitive load when the capacitor is short-circuited at the moment of power-on, RL is the equivalent resistance of the capacitive load during stable operation after power-on, and I_HSD_MAX is the maximum operating current that does not trigger a short circuit on the high-side switch; The method to determine the lower limit of the current limiting resistor is: Where R1 min is the lower limit of the resistance of the current limiting resistor, and I_NTC_MAX is the maximum on-state current of the first switch tube.

11. The capacitive load power supply circuit according to claim 9, characterized in that: The delay time between the first switch tube conduction signal and the high-side switch conduction signal satisfies the following formula: Where t_delay is the delay time, R1 is the resistance of the current limiting resistor at room temperature, RL is the equivalent resistance of the capacitive load when running stably after power-on, and CL is the capacitance of the capacitive load.

12. The capacitive load power supply circuit according to claim 9, characterized in that: The on-resistance of the first switch tube meets the following conditions: In the formula, R DS_ON is the maximum on-resistance of the first switch tube; T JC is the junction temperature of the first switch tube, T amb is the ambient temperature, I_NTC_MAX is the maximum current passing through the first switch tube, t_delay is the delay time, Z thJC (t_delay) is the transient thermal resistance of the first switch tube pulse under the delay time.

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