Image sensing device

Abstract

Disclosed is an image sensing apparatus capable of generating a high dynamic range (HDR) image. The image sensing device includes a pixel and a compensation circuit. The pixel is configured to output a sensing voltage corresponding to a voltage of a floating diffusion region to a sensing node, the floating diffusion region being included in the pixel and having a first capacitance and a second capacitance in respective first and second modes, the second capacitance being greater than the first capacitance. The compensation circuit controls an offset voltage level of the sensing node through the first path in a first interval, and boosts the sensing voltage through the second path in a second interval.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to an image sensing device capable of generating a high dynamic range (HDR) image. Background Art

[0002] Image sensing devices are devices that capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the development of the automotive, medical, computer, and communication industries, the demand for high-performance image sensing devices is increasing in various fields such as smartphones, digital cameras, game consoles, IoT (Internet of Things), robots, surveillance cameras, and medical micro cameras.

[0003] Recently, in order to provide high-quality images, interest in HDR images is rapidly increasing, and various technologies capable of acquiring HDR images are being developed. Among these technologies, a technology for varying the conversion gain of pixels that detect incident light and convert the incident light into electrical signals can accurately acquire images for each of high and low illumination.

[0004] However, according to the technology for varying the conversion gain, different conversion gains are applied to each pixel, resulting in an offset. In addition, since the technology for varying the conversion gain uses a dual conversion gain (DCG) method, the settling time of the pixel signal output through the readout line may increase. Summary of the invention

[0005] According to an embodiment of the present disclosure, an image sensing device may include: a pixel configured to output a sensing voltage corresponding to a voltage of a floating diffusion region to a sensing node, the floating diffusion region being included in the pixel and having a first capacitor and a second capacitor in corresponding first and second modes, the second capacitor being greater than the first capacitor; and a compensation circuit configured to control an offset voltage level of the sensing node through a first path in a first interval, and to boost the sensing voltage through a second path in a second interval.

[0006] According to another embodiment of the present disclosure, an image sensing device may include: a pixel configured to output a sensing voltage corresponding to a voltage of a floating diffusion region to a sensing node; and a voltage controller configured to control a first current flowing from a sensing node based on an offset voltage value of the sensing node when a first path is selected in a first interval, and to boost the first current when a second path is selected in a second interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0008] Figure 1 is a block diagram illustrating an imaging device according to some embodiments of the present disclosure.

[0009] Figure 2 Some embodiments of the present disclosure are shown Figure 1 A detailed circuit diagram of a unit pixel of an image sensing device is shown.

[0010] Figure 3 Some embodiments of the present disclosure are shown Figure 1 The detailed circuit diagram of the voltage controller is shown.

[0011] Figure 4 and Figure 5 Some embodiments of the present disclosure are shown Figure 2 A detailed circuit diagram of the control path of the voltage controller is shown.

[0012] Figure 6 and Figure 7 Some embodiments of the present disclosure are shown Figure 3 shows the timing diagram of the operation of the voltage controller.

[0013] Figure 8 Some embodiments of the present disclosure are shown Figure 1 A diagram of the stacked structure of an image sensing device is shown. DETAILED DESCRIPTION

[0014] Embodiments of the present disclosure provide implementations and examples of image sensing devices capable of generating high dynamic range (HDR) images, which can be used in a configuration that substantially solves one or more technical or engineering problems and alleviates limitations or shortcomings encountered in some image sensing devices in the art. Some embodiments of the present disclosure relate to an image sensing device capable of compensating for an offset voltage and reducing a stabilization time by using a voltage control circuit with a path change. Recognizing the above problems, an image sensing device based on some embodiments of the present disclosure can compensate for an offset voltage and can acquire a high dynamic range (HDR) image with a reduced stabilization time.

[0015] Reference will now be made in detail to some embodiments of the present disclosure, which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the accompanying drawings to represent the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are illustrated as examples in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0016] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0017] Various embodiments of the present disclosure are directed to an image sensing device capable of compensating for an offset voltage and reducing a stabilization time by using a voltage control circuit of path change.

[0018] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and descriptive and are intended to provide further description of embodiments of the disclosure as claimed.

[0019] Figure 1 is a block diagram showing an imaging device 1 according to some embodiments of the present disclosure.

[0020] Reference Figure 1 , the imaging device 1 may refer to a device such as a digital still camera for photographing still images or a digital video camera for photographing moving images. For example, the imaging device 1 may be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, or a smart phone, etc. The imaging device 1 may include a device having both a lens and an image pickup element, so that the device can capture (or photograph) a target object, and thus can create an image of the target object.

[0021] The imaging device 1 may include an image sensing device 10 and an image signal processor (ISP).

[0022] The image sensing device 10 may be a complementary metal oxide semiconductor image sensor (CIS) for converting incident light into an electrical signal and may include a pixel array 100 , a row driver 110 , a readout circuit 120 , a column driver 130 , a timing controller 140 , and a compensation circuit 200 . Figure 1 The components of image sensing device 10 shown are discussed merely as examples, and the present disclosure contemplates numerous other alterations, permutations, variations, changes, and modifications.

[0023] The pixel array 100 may include a plurality of imaging pixels (PX) that are continuously arranged into a two-dimensional (2D) pixel array including rows and columns. The plurality of imaging pixels (PX) may be continuously arranged in a column direction and a row direction. In another example, the plurality of imaging pixels (PX) may be arranged into a three-dimensional (3D) pixel array. The plurality of imaging pixels may convert an optical signal into an electrical signal based on a unit pixel or a pixel group, wherein the pixels in the pixel group share at least a specific internal circuit. The voltage output from the sensing node (SN) of each pixel (PX) may be referred to as a sensing voltage (V px ).

[0024] The pixel array 100 may receive a pixel control signal (CON) including a row selection signal, a pixel reset signal, a transfer signal, and a dual conversion gain (DCG) control signal from the row driver 110. Upon receiving the pixel control signal (CON), the corresponding imaging pixel in the pixel array 100 may be enabled to perform operations corresponding to the row selection signal, the pixel reset signal, the transfer signal, and the DCG control signal. Each pixel (PX) may generate a photocharge corresponding to the intensity (or illumination) of the incident light, and may generate an electrical signal having a size corresponding to the amount of the generated photocharge, thereby detecting the incident light.

[0025] Each pixel (PX) of the pixel array 100 may have at least two different sensitivities. Here, the sensitivity may mean an increase in the amount of image data IDATA (or an increase in response) relative to an increase in the amount of intensity of incident light. That is, as the sensitivity increases, the increase in the amount of image data (IDATA) in response to an increase in the intensity of incident light increases. As the sensitivity decreases, the increase in the amount of image data (IDATA) in response to an increase in the intensity of incident light decreases. In the present embodiment, the sensitivity may be determined by a conversion gain.

[0026] Row driver 110 may enable pixel array 100 to perform specific operations on imaging pixels in corresponding rows based on commands and control signals provided by controller circuitry (e.g., timing controller 140). In some embodiments, row driver 110 may select one or more imaging pixels arranged in one or more rows of pixel array 100. Row driver 110 may generate row selection signals to select one or more rows among a plurality of rows.

[0027] The row driver 110 may sequentially enable a pixel reset signal for resetting the imaging pixels (PX) corresponding to the selected at least one row and a transfer signal for the pixels (PX) corresponding to the selected at least one row. Therefore, a reference signal and an image signal, which are analog signals generated by the respective imaging pixels (PX) of the selected row, may be sequentially transmitted to the readout circuit 120. The reference signal may be an electrical signal provided to the readout circuit 120 when a sensing node (e.g., a floating diffusion region) of the imaging pixel is reset, and the image signal may be an electrical signal provided to the readout circuit 120 when photocharges generated by the imaging pixel are accumulated in the sensing node. The reference signal indicating the unique reset noise of each pixel and the image signal indicating the intensity of the incident light may be collectively referred to as a pixel signal as needed.

[0028] The image sensing device 10 may use correlated double sampling (CDS) to remove the undesired offset value of the pixel (called fixed pattern noise) by sampling the pixel signal twice to remove the difference between the two samples. In one example, correlated double sampling (CDS) may remove the undesired offset value of the pixel by comparing the pixel output voltage obtained before and after the photocharge generated by the incident light is accumulated in the sensing node so that only the pixel output voltage based on the incident light can be measured. The main purpose of CDS is to reduce or eliminate the effects of fixed pattern noise and other offset or drift sources in the sensor output.

[0029] In some embodiments of the present disclosure, the readout circuit 120 may sequentially sample and hold the voltage levels of the reference signal and the image signal provided to each of the plurality of column lines from the pixel array 100. That is, the analog-to-digital converter (ADC) included in the readout circuit 120 may sample and hold the pixel signals of each column (i.e., each column pixel signal) when receiving the pixel signals from the respective column lines of the pixel array 100, may convert the resulting signal into a digital signal (IDATA), and may output the digital signal (IDATA). In some embodiments, the ADC may be implemented as a ramp comparison type ADC. The ramp comparison type ADC may include a comparator circuit for comparing an analog pixel signal with a ramp signal that ramps up or down according to time, and a timer (or counter) for performing counting until the voltage of the ramp signal matches the analog pixel signal.

[0030] The column driver 130 may select a column of the readout circuit 120 upon receiving a control signal from the timing controller 140. The column driver 130 may temporarily store the image data (IDATA) of the selected column of the readout circuit 120, and may control the readout circuit 120 to sequentially output the image data (IDATA) temporarily stored in the selected column of the readout circuit 120. In some embodiments, upon receiving an address signal from the timing controller 140, the column driver 160 may generate a column selection signal based on the address signal, and may select a column of the readout circuit 120 so that the column driver may temporarily store the image data (IDATA) of the selected column from the readout circuit 120, and may output the stored image data (IDATA) to the outside.

[0031] The timing controller 140 may control at least one of the row driver 110, the readout circuit 120, the column driver 130, and the compensation circuit 200. The timing controller 140 may provide a clock signal required for the operation of each component of the image sensing device 10, a control signal for timing control, and an address signal for selecting a row or a column to at least one of the row driver 110, the readout circuit 120, the column driver 130, and the compensation circuit 200.

[0032] The image signal processor (ISP) may perform image processing of image data received from the image sensing device 10. The image signal processor (ISP) may reduce noise of the image data, and may perform various types of image signal processing for image quality improvement of the image data (e.g., interpolation, synthesis, gamma correction, color filter array interpolation, color matrix, color correction, color enhancement, lens distortion correction, etc.).

[0033] In addition, the image signal processor (ISP) may compress image data created by performing image signal processing for image quality improvement, so that the image signal processor (ISP) can create an image file using the compressed image data. Alternatively, the image signal processor (ISP) may restore the image data from the image file. In this case, the scheme for compressing such image data may be a reversible format or an irreversible format. As a representative example of such a compression format, in the case of using a still image, a Joint Photographic Experts Group (JPEG) format, a JPEG 2000 format, or the like may be used. In addition, in the case of using a moving image, a plurality of frames may be compressed according to the Moving Picture Experts Group (MPEG) standard, so that a moving image file may be created. For example, an image file may be created according to the Exchangeable Image File Format (Exif) standard.

[0034] The image signal processor (ISP) may generate an HDR image by synthesizing at least two images having different sensitivities. For example, the image sensing device 10 may output a low sensitivity image generated by pixels having relatively lower sensitivity (i.e., low conversion gain pixels) and a high sensitivity image generated by pixels having relatively higher sensitivity (i.e., high conversion gain pixels). The image signal processor (ISP) may combine the low sensitivity image and the high sensitivity image, resulting in an HDR image. Here, low sensitivity and high sensitivity may correspond to relative concepts, the image sensing device 10 may generate image data (IDATA) having at least N different sensitivities (where N is an integer of 2 or greater), and the image sensing processor (ISP) may use the resulting image data (IDATA) to generate an HDR image.

[0035] The image signal processor (ISP) may transmit ISP image data to a host device (not shown). The host device (not shown) may be a processor (e.g., an application processor) for processing the ISP image data received from the image signal processor (ISP), a memory (e.g., a nonvolatile memory) for storing the ISP image data, or a display device (e.g., a liquid crystal display (LCD)) for visually displaying the ISP image data.

[0036] In addition, the image signal processor (ISP) may transmit a control signal for controlling the operation of the image sensing device 10 (eg, whether to operate, operation timing, operation mode, etc.) to the image sensing device 10 .

[0037] On the other hand, the compensation circuit 200 may compensate for an offset voltage or a settling time of each pixel (PX) of the pixel array 100. The compensation circuit 200 may include a voltage controller 210, a path controller 220, and a bias voltage generator 230.

[0038] In order to obtain a high dynamic range (HDR) image, a technique of changing the conversion gain of a pixel may be used. The technique of changing the conversion gain may include a dual conversion gain (DCG) transistor (described later) to control the capacitance of the floating diffusion region. However, during the switching operation of the DCG transistor, an offset voltage may occur to change the capacitance of the floating diffusion region so that the sense voltage (V px ) may also change in response to such a changed capacitance.

[0039] Therefore, the compensation circuit 200 according to some embodiments of the present disclosure can compensate the sensing voltage (V px ) offset level. In addition, the compensation circuit 200 can compensate the sensing voltage (V px ) to quickly boost the voltage to reduce the stabilization time. The compensation circuit 200 according to some embodiments of the present disclosure may not separately configure a circuit for compensating the offset level and a circuit for reducing the stabilization time, but may be implemented as one voltage controller 210, and may control the offset level or perform a boost operation by changing one path to another.

[0040] Although the voltage controller 210 is shown as being separately provided in the compensation circuit 200 for ease of description, other embodiments are possible, and it should be noted that the voltage controller may be located within the pixel array 100, and the range of the location where the voltage controller 210 is to be provided is not limited thereto.

[0041] The voltage controller 210 can control the voltage of the sensing node (SN) of each unit pixel (PX) based on multiple switch control signals (SWC1 to SWC7 described later) and multiple bias voltages (Vb1 to Vb3 described later). The voltage controller 210 can select a path for adjusting the offset or a path for compensating the stabilization time based on the multiple switch control signals. When the offset adjustment path (also referred to as the "first path") is selected, the voltage controller 210 can compensate for the offset voltage of the sensing node (SN). In addition, when the stabilization time compensation path (also referred to as the "second path") is selected, the voltage controller 210 can reduce the stabilization time of the sensing node (SN).

[0042] When the offset voltage is compensated as in the embodiment of the present disclosure, the reduction of the input range can be prevented in the case of low voltage, and the influence of the offset voltage applied differently to each pixel (PX) can be reduced. In addition, when the sensing voltage (V px ) when boosting the voltage, the stabilization time can also be reduced.

[0043] The path controller 220 may selectively control a plurality of switch control signals to select one of the offset adjustment path and the settling time compensation path. The path controller 220 may be controlled by the timing controller 140. Although the path controller 220 is shown as being separately provided in the compensation circuit 200 for convenience of description, other embodiments are also possible, and it should be noted that the path controller 220 may be located in the timing controller 140, and the range of the position where the path controller 220 may be provided is not limited thereto.

[0044] The bias voltage generator 230 may generate a bias voltage to control the operation of the voltage controller 210. The bias voltage generator 230 may be controlled by the timing controller 140. Although the bias voltage generator 230 is shown as being separately provided in the compensation circuit 200 for convenience of description, other embodiments are possible, and it should be noted that the bias voltage generator 230 may be located in the timing controller 140, and the range of the location where the bias voltage generator 230 is to be provided is not limited thereto.

[0045] The detailed circuit and operation of the compensation circuit 200 including the above-mentioned constituent elements will be described later with reference to the following. Figures 3 to 7 to describe.

[0046] Figure 2 Some embodiments of the present disclosure are shown Figure 1 FIG. 1 is a detailed circuit diagram of a unit pixel (PX) of the image sensing device 10 .

[0047] Reference Figure 2 , the pixel (PX) may be one of a plurality of pixels included in the pixel array 100. Although for convenience of description, Figure 2 Only one pixel (PX) is shown, but other embodiments are possible, and it should be noted that other pixels may also have substantially the same structure and operation as that of the pixel (PX).

[0048] The pixel (PX) may include a photoelectric conversion element (PD), a transfer transistor (TX), a reset transistor (RX), a floating diffusion region (FD), a dual conversion gain (DCG) transistor (DCX), a source follower transistor (DX), a selection transistor (SX), and a plurality of capacitors (C1, C2). Although for the convenience of description, Figure 2The pixel (PX) is shown as including only one photoelectric conversion element (PD), but other embodiments are possible. Figure 2 The pixel (PX) may also be implemented as a shared pixel including a plurality of photoelectric conversion elements. In this case, a plurality of transfer transistors may be provided to correspond to the plurality of photoelectric conversion elements.

[0049] The photoelectric conversion element (PD) can generate and accumulate photoelectric charges corresponding to the intensity of the incident light by photoelectric conversion of the incident light. For example, the photoelectric conversion element (PD) can be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0050] When the photoelectric conversion element (PD) is implemented as a photodiode, the photoelectric conversion element (PD) may be a region in which impurities of a second conductivity type (eg, N type) are doped in a substrate having a first conductivity type (eg, P type).

[0051] The transfer transistor (TX) may be connected between the photoelectric conversion element (PD) and the floating diffusion region (FD). The transfer transistor (TX) may be turned on or off in response to a transfer signal (TG), and the turned-on transfer transistor (TX) may transfer the photocharge accumulated in the photoelectric conversion element (PD) to the floating diffusion region (FD).

[0052] The reset transistor (RX) may be connected between the power supply voltage (VDD) and the floating diffusion region (FD). The reset transistor (RX) may reset the voltage of the floating diffusion region (FD) to the power supply voltage (VDD) in response to the pixel reset signal (RG).

[0053] The floating diffusion region (FD) may accumulate photocharges received from the transfer transistor (TX). The floating diffusion region (FD) may be connected to a capacitor (C1) connected to a ground terminal. For example, the floating diffusion region (FD) may be a region doped with a second conductive impurity (e.g., an N-type impurity) in a substrate (e.g., a P-type substrate) including a first conductive impurity. In this case, the substrate and the doped region may be modeled as a capacitor (C1) acting as a junction capacitor. The floating diffusion region (FD) may be connected to the gate of a source follower transistor (DX).

[0054] The DCG transistor (DCX) may be coupled between the floating diffusion region (FD) and the capacitor (C2). The DCG transistor (DCX) may selectively connect the capacitor (C2) to the floating diffusion region (FD) in response to a DCG control signal (DCG).

[0055] The capacitor (C1) may be connected between the floating diffusion region (FD) and the ground voltage input terminal. In addition, the capacitor (C2) may be connected between the DCG transistor (DCX) and the ground voltage input terminal.

[0056] Each capacitor (C1, C2) may include at least one of a metal-insulator-metal (MIM) capacitor, a metal-insulator-polysilicon (MIP) capacitor, a metal-oxide-semiconductor (MOS) capacitor, and a junction capacitor. When the DCG transistor (DCX) is turned off, the floating diffusion region (FD) may have an electrostatic capacity (or a first electrostatic capacity) corresponding to the capacitance of the capacitor (C1). When the DCG transistor (DCX) is turned on, the floating diffusion region (FD) may have a capacitance corresponding to the sum of the capacitance of the capacitor (C1) and the capacitance of the capacitor (C2). That is, the DCG transistor (DCX) may control the capacitance of the floating diffusion region (FD), thereby controlling the conversion gain of the pixel (PX).

[0057] When the DCG control signal (DCG) has a logic high level, the pixel (PX) in a state where the DCG transistor (DCX) is turned on may operate in a low conversion gain (LCG) mode, in which photocharges are converted into electrical signals with a relatively low conversion gain. When the DCG control signal (DCG) has a logic low level, the pixel (PX) in a state where the DCG transistor (DCX) is turned off may operate in a high conversion gain (HCG) mode, in which photocharges are converted into electrical signals with a relatively high conversion gain.

[0058] In some embodiments, a logic high level may refer to a voltage level for enabling (eg, turning on) a corresponding element (eg, a transistor), and a logic low level may refer to a voltage level for disabling (eg, turning off) a corresponding element (eg, a transistor).

[0059] Although for the sake of convenience, Figure 2 The case of using only one DCG transistor (DCX) is shown, but other embodiments are possible, and multiple DCG transistors may be used as needed. In this case, the capacitance of the floating diffusion region (FD) may have a wider range of values ​​(eg, three or more values).

[0060] Although the DCG transistor (DCX) according to the present embodiment is connected between the floating diffusion region (FD) and the capacitor (C2) for the sake of convenience of description, other embodiments are possible, and it should be noted that the connection structure of the DCG transistor (DCX) and the capacitor (C1, C2) can be substantially changed without departing from the scope or spirit of the present disclosure.

[0061] The source follower transistor (DX) may be connected between a power supply voltage (VDD) input terminal and a selection transistor (SX). The source follower transistor (DX) may amplify a change in the potential of a floating diffusion region (FD) that has received photocharges accumulated in a photoelectric conversion element (PD), and may transmit the amplified result to the selection transistor (SX).

[0062] The selection transistor (SX) may be connected between the source follower transistor (DX) and the sensing node (SN), and may be turned on by the selection control signal (SG) so that the selection transistor (SX) may output the electrical signal received from the source follower transistor (DX) as a pixel signal (i.e., a pixel voltage V px ).

[0063] Figure 3 Some embodiments of the present disclosure are shown Figure 1 A detailed circuit diagram of the voltage controller 210 is shown.

[0064] Reference Figure 3 , the voltage controller 210 may be connected to Figure 1 and Figure 2 The voltage controller 210 may control the sensing voltage (V px ) level.

[0065] The voltage controller 210 may include a bias controller 211 , a current regulator 212 , a driving controller 213 , a boost controller 214 , a plurality of switching elements ( SW1 ˜ SW7 ), and a plurality of capacitors ( C3 ˜ C5 ).

[0066] The bias controller 211 can be based on the bias voltage (V b1 、V b2 ) to control the current (I px ). The bias controller 211 may include a plurality of transistors (NM1, NM2). In this case, the transistors (NM1, NM2) may be NMOS transistors. The transistor NM1 may be connected between the sensing node (SN) and the node (N1), and may receive a bias voltage (V b2 The transistor (NM2) may be connected between the node N1 and the ground voltage input terminal to receive a bias voltage (V b1 ).

[0067] The current regulator 212 can be based on the control voltage (V str ) to control the current (I cal). The current regulator 212 may include a transistor (NM3). Here, the transistor (NM3) may be an NMOS transistor. The transistor (NM3) may be connected between a power supply voltage input terminal and the node (N2) to receive a control voltage (V str ).

[0068] The driving controller 213 can be based on the input voltage (V in1 )Amplified sense voltage (V px ) changes, and the amplified voltage (V px ) is provided to the node (N3). In addition, the driving controller 213 may be based on the bias voltage (V b3 ) to control the current of node (N3). The driving controller 213 may include a transistor (PM1) and a transistor (NM4). Here, the transistor (PM1) may be a PMOS transistor, and the transistor (NM4) may be an NMOS transistor. Alternatively, the transistor (PM1) may also be implemented as an NMOS transistor.

[0069] The transistor (PM1) may be connected between a power supply voltage input terminal and a node (N3) to receive an input voltage (V in1 ). In addition, the transistor (NM4) may be connected between the node (N3) and the ground voltage input terminal to receive a bias voltage (V b3 ).

[0070] In addition, the boost controller 214 can be based on the input voltage (V in2 ) to control the boost signal (V bst ). The boost controller 214 may include a transistor (PM2) and a transistor (NM5). Here, the transistor (PM2) may be a PMOS transistor, and the transistor (NM5) may be an NMOS transistor. Alternatively, the transistor (PM2) may also be implemented as an NMOS transistor.

[0071] The transistor (PM2) may be connected between the power supply voltage input terminal and the node (N6) to receive the input voltage (V in2 The transistor (NM5) may be connected between the node (N4) and the ground voltage input terminal to receive the input voltage (V in2 Each of the transistor (PM2) and the transistor (NM5) can output a boost signal (V bst ).

[0072] In addition, the switch element (SW1) may be connected between the sensing node (SN) and the capacitor (C3) so that its switching operation can be operated according to the switch control signal (SWC1). When the switch element (SW1) is turned on, the compensation circuit 200 can be operated. The switch element (SW2) may be connected between the capacitor (C3) and the node (N3) so that its switching operation can be operated according to the switch control signal (SWC2). The switch element (SW3) may be connected between the capacitor (C4) and the node (N3) so that its switching operation can be operated according to the switch control signal (SWC3).

[0073] The switch element (SW4) may be connected between the gate terminal of the transistor (NM1) and the gate terminal of the transistor (NM3) so that its switch operation can be operated according to the switch control signal (SWC4). The switch element (SW5) may be connected between the node (N1) and the node (N2) so that its switch operation can be operated according to the switch control signal (SWC5). The switch element (SW6) may be connected between the capacitor (C5) and the node (N6), and its switch operation can be operated according to the switch control signal (SWC6). The switch element (SW7) may be connected between the node (N6) and the node (N4) so ​​that its switch operation can be operated according to the switch control signal (SWC7).

[0074] The capacitor (C3) may be connected between the switch element (SW1) and the gate terminal of the transistor (PM1). The capacitor (C4) may be connected between the gate terminal of the transistor (NM3) and the switch element (SW3). The capacitor (C5) may be connected between the node (N2) and the switch element (SW6).

[0075] The operation of the voltage controller 210 including the above-mentioned constituent elements will be described later with reference to the following. Figure 7 to describe.

[0076] Figure 4 and Figure 5 Some embodiments of the present disclosure are shown Figure 2 A detailed circuit diagram of the control path of the voltage controller 210 is shown. Figure 4 is a detailed circuit diagram illustrating the operation of the voltage controller 210 configured to compensate for the offset voltage of the sensing node (SN) when the offset adjustment path (P1) is selected. Figure 5 is a detailed circuit diagram illustrating the operation of the voltage controller 210 configured to compensate for the stable voltage of the sensing node (SN) when the stable time compensation path (P2) is selected.

[0077] Reference Figure 4, when the offset adjustment path (P1) is selected, the switch elements (SW1, SW3, SW5) of the voltage controller 210 are turned on, and the switch elements (SW2, SW4, SW6, SW7) of the voltage controller 210 are turned off.

[0078] The source follower transistor (DX) may receive the voltage of the floating diffusion region (FD) through its gate terminal and may output a sense voltage (V) corresponding to the gain of the source follower transistor (DX) through its source terminal. px ). The sensing voltage (V px ) may have a voltage value (V px +Δ+β).

[0079] When the switch element (SW1) is turned on, the input voltage (V in ) may include an auto-zero voltage (V az ) voltage value (V az +Δ). The transistor (PM1) can be based on the input voltage (V in ) outputs the amplified voltage value (V az +αΔ).

[0080] When the switch element (SW3) is turned on, the drive voltage (V out ) can have a voltage value (V az +αΔ). When the switch element (SW4) is turned off, the control voltage (V str ) can have a voltage value (V b2 +αΔ). The transistor (NM3) can be controlled by the voltage (V str ) to adjust the current (I cal ).

[0081] The feedback voltage (V fb ) can have a voltage value (V fb +γ). When the switch element (SW5) is turned on, the feedback voltage (V fb ) regulates the voltage of node (N1) (i.e., the current I flowing to node (N1) px ). Therefore, when adjusting the current (I px ), the sensing voltage (V px )’s offset voltage level.

[0082] Reference Figure 5, when the settling time compensation path (P2) is selected, the switch elements (SW1, SW5, SW6, SW7) of the voltage controller 210 are turned on, and the switch elements (SW2, SW3, SW4) of the voltage controller 210 may be turned off.

[0083] When the switch element (SW1) is turned on, the sensing voltage (V px )(i.e., V px' +sig, where "sig" corresponds to the voltage value of the image signal) may be applied to the gate terminal of the transistor (PM1). The transistor (PM1) may be based on the input voltage (V az' +sig) outputs the amplified voltage value (V az' +αsig). Here, the amplified voltage (V az' +αsig) can have a higher voltage than the input voltage (V az' +sig) level with high α value.

[0084] When the switch element (SW3) is turned off and the switch elements (SW6, SW7) are turned on, the transistors (PM2, NM5) can be operated by the voltage of the node (N5). When the input voltage (V in2 ) exceeds the threshold voltage, current can flow in the node (N6). Then, the voltage of the node (N1, N2) serving as the source terminal of the transistor (NM1, NM3) (i.e., the feedback voltage (V fb )(V fb +γδ)) may drop rapidly. Therefore, the value of the current (Ipx) may increase significantly instantaneously, and the level of the sensing voltage (Vpx) of the sensing node (SN) may be boosted.

[0085] The operation of the voltage controller 210 having such a path will be described later with reference to Figure 6 and Figure 7 Describe in more detail.

[0086] Figure 6 and Figure 7 Some embodiments of the present disclosure are shown Figure 3 A timing diagram of the operation of the voltage controller 210 is shown. Figure 6 is a timing diagram showing time points of operations generated when the compensation circuit 200 is not applied to the image sensing device 10, Figure 7 is a timing diagram showing time points of operations generated when the compensation circuit 200 is applied to the image sensing device 10 .

[0087] exist Figure 7In the operation timing diagram, the interval in which each switch control signal (SWC1~SWC7) has a logic high level may refer to a time interval for controlling the switch elements (SW1~SW7) to be turned on, and another interval in which each switch control signal (SWC1~SWC7) has a logic low level may refer to a time interval for controlling the switch elements (SW1~SW7) to be turned off.

[0088] Figure 6 and Figure 7 The timing diagram of may be applied to an operation mode in which the conversion gain of a pixel (PX) is changed using a dual conversion gain (DCG) method. The image sensing device 10 may read out a reset signal and an image signal for each of an LCG mode and an HCG mode during a readout period. The image sensing device 10 may read out a reset signal and an image signal for each of an LCG mode and an HCG mode during a readout period. For example, the image sensing device 10 may acquire LCG pixel data based on an LCG reset signal and an LCG image signal of a pixel (PX), and may acquire HCG pixel data based on an HCG reset signal and an HCG image signal of a pixel (PX).

[0089] The readout period of the pixel (PX) may be divided into four sub-intervals. The readout operation may be performed in different ways while being classified according to the first reset interval (LCG_RST), the second reset interval (HCG_RST), the first signal interval (HCG_SIG), and the second signal interval (LCG_SIG). For example, the image sensing device 10 may acquire the LCG reset signal of the pixel (PX) during the first reset interval (LCG_RST), and may acquire the HCG reset signal of the pixel (PX) during the second reset interval (HCG_RST). In addition, the image sensing device 10 may acquire the HCG image signal of the pixel (PX) during the first signal interval (HCG_SIG), and may acquire the LCG image signal of the pixel (PX) during the second signal interval (LCG_SIG). During the readout period, the selection transistor (SX) of the pixel (PX) may remain turned on.

[0090] The pixel (PX) may be operated in the LCG mode during each of the first reset interval (LCG_RST) and the second signal interval (LCG_SIG), and may be operated in the HCG mode during each of the second reset interval (HCG_RST) and the first signal interval (HCG_SIG). Figure 6 and Figure 7 As shown, a method of sequentially reading out an LCG reset signal, an HCG reset signal, an HCG image signal, and an LCG image signal during a readout period of a pixel (PX) may be referred to as a reset-reset-signal-signal (RRSS) readout method.

[0091] First, in the first reset interval (LCG_RST), when the pixel reset signal (RG) of the pixel (PX) is enabled, the reset transistor (RX) may be turned on. In addition, when the DCG control signal (DCG) of the pixel (PX) is enabled, the DCG transistor (DCX) may be turned on. When the reset transistor (RX) and the DCG transistor (DCX) are turned on, the floating diffusion region (FD) of the pixel (PX) may be reset. Then, a sensing voltage (V px ).

[0092] In the first reset interval (LCG_RST), since the switch control signals (SWC1-SWC5) are enabled, all the switch elements (SW1-SW5) may be turned on, and since the switch control signals (SWC6, SWC7) are disabled, the switch elements (SW6, SW7) may be turned off.

[0093] When the auto-zero operation is performed in the first reset interval (LCG_RST), the input voltage (V in ) and driving voltage (V out ) can be maintained at the auto-zero voltage (V az Here, the auto-zero operation may be for performing adjustment between the voltage level of a ramp signal (not shown) and the voltage level of a pixel signal to compare the ramp signal and the pixel signal (ie, the pixel voltage V px ) operation.

[0094] In the first reset interval (LCG_RST), the control voltage (V str ) can be maintained at a bias voltage (V b2 ) level, and the boost voltage (V bst ) can be maintained at a voltage (e.g., a power supply voltage (VDD) level). Therefore, the current (I px ) and current (I cal ) can be maintained at the same current level.

[0095] Thereafter, when the DCG control signal (DCG) is disabled in the second reset interval (HCG_RST), the DCG transistor (DCX) may be turned off. When the DCG transistor (DCX) is turned off in the second reset interval (HCG_RST), the capacitance of the floating diffusion region (FD) may be reduced. Then, a sensing voltage (V px ).

[0096] However, during a predetermined interval from the time point when the second reset interval (HCG_RST) starts, the sense voltage (V px ) may reduce the specific offset voltage (V off ),like Figure 6 As shown in (C). When the DCG transistor (DCX) included in the pixel (PX) changes from an on state to an off state, the coupling capacitance of the floating diffusion region (FD) may change so that the voltage of the floating diffusion region (FD) may change accordingly. Since each unit pixel (PX) has a different layout environment, the unit pixel (PX) may have a different parasitic capacitance.

[0097] Therefore, when the voltage of the floating diffusion region (FD) changes, as Figure 6 As shown in (C), the sensing voltage (V px ) can be reduced, and the offset voltage (V off ) level can also change. That is, the offset voltage (V off ) may not be a fixed value. For example, the offset voltage (V off ) may have different values ​​depending on the frame of the captured image, the photographing (or shooting) environment and / or the parasitic capacitance of the pixel (PX).

[0098] In order to compensate for the fluctuating offset voltage (V off ), the image sensing device 10 according to the embodiment of the present disclosure may use the voltage controller 210 (such as Figure 4 When the offset adjustment path P1 is selected, the offset adjustment path P1 can be selected as follows: Figure 7 The compensation sensing voltage (V px )’s offset voltage level.

[0099] In the second reset interval (HCG_RST), the switch control signal (SWC2) may be turned to a logic low level. When the switch element (SW2) is turned off and the offset voltage from the transistor (PM1) is transmitted through the switch element (SW3), the drive voltage (V out ) may rise to a predetermined level. Therefore, in response to the increased driving voltage (V out ), control voltage (V str ) can be higher than the bias voltage (V b2 ) voltage level.

[0100] When the switch control signal (SWC4) changes to a logic low level, the switch element (SW4) may be turned off. In this case, when the control voltage (V str) increases, the current (I cal ) can be increased to a predetermined level, and the current (I px ) can be reduced to a predetermined level. When the current (I px ) decreases, the sense voltage (V px ) increases to the sensing voltage (V px )’s voltage level so that the voltage level can be compensated.

[0101] Subsequently, when entering the first signal interval (HCG_SIG), the transfer transistor (TX) may be turned on. During the interval in which the transfer transistor (TX) of the pixel (PX) is turned on, the charges generated by the photodiode (PD) may be moved to the floating diffusion region (FD). During the first signal interval (HCG_SIG), the image sensing device 10 may output a sensing voltage (V px ).

[0102] In the first signal interval (HCG_SIG), the DCG transistor (DCX) maintains a logic low level so that the pixel (PX) can operate in the HCG mode. In addition, since the charges generated by the photodiode (PD) have moved to the floating diffusion region (FD), the pixel (PX) can output a sensing voltage (V px ).

[0103] However, when the offset voltage (V off ) level such as Figure 6 (C) changes when the sensing voltage (V px ) may not be sufficiently boosted and may gradually decrease. Then, if Figure 6 As shown in (E), the sensing voltage (V px )The time it takes for the device to stabilize (or settle) to the target potential. The stabilization time may increase.

[0104] Therefore, according to an embodiment of the present disclosure, during the first signal interval (HCG SIG), the voltage controller 210 may select the stable time compensation path (P2), such as Figure 5 When the settling time compensation path (P2) is selected, the sense voltage (V px ) to boost the voltage to reduce the stabilization time, such as Figure 7 As shown in (F).

[0105] In the first signal interval (HCG_SIG), the switch control signal (SWC3) may be changed to a logic low level, and the switch control signals (SWC6, SWC7) may be changed to a logic high level. Then, the switch element (SW3) may be turned off, and the switch elements (SW6, SW7) may be turned on. In addition, the transistors (PM2, NM5) may be amplified by the voltage value (V az' +αsig) drive. Then, the feedback voltage (V fb ) voltage level through the boost voltage (V bst ) is reduced so that the current (I cal ) and current (I px ) can be boosted instantaneously. The sensing voltage or the level of the sensing voltage (V px ) can be based on the instantaneous boost current (I px ) and boost the pressure.

[0106] Subsequently, when entering the second signal interval (LCG_SIG), the transfer transistor (TX) may be turned on. In addition, when the DCG control signal (DCG) is enabled, the DCG transistor (DCX) may be turned on. Therefore, in the second signal interval (LCG_SIG), the pixel (PX) may operate in the LCG mode. When the transfer transistor (TX) is turned on again, the charge generated by the photodiode (PD) but failed to move to the floating diffusion region (FD) may move to the floating diffusion region (FD). As a result, a sensing voltage (V px ).

[0107] In the second signal interval (LCG_SIG), the switch control signals (SWC2-SWC4) are enabled again so that all the switch elements (SW2-SW4) can be turned on. Then, the switch control signals (SWC6, SWC7) can be disabled again so that the switch elements (SW6, SW7) can be turned off.

[0108] As a result, the input voltage (V in1 ) and driving voltage (V out ) can maintain the automatic zero voltage (V az ) level, and the control voltage (V str ) and boost voltage (V bst ) can maintain the bias voltage (V b2 ) level.

[0109] Figure 8 Some embodiments of the present disclosure are shown Figure 1 A diagram of the stacked structure of the image sensing device 10 is shown.

[0110] Reference Figure 8 , the image sensing device 10 may include a first chip 300 and a second chip 400. The first chip 300 and the second chip 400 may be vertically bonded to each other, resulting in a stacked structure. The first chip 300 and the second chip 400 may be electrically connected to each other through a connector (not shown) so that signals may be communicated between the first chip 300 and the second chip 400. For example, the first chip 300 and the second chip 400 may be connected to each other through hybrid bonding.

[0111] The first chip 300 may include a pixel array 100, and the second chip 400 may include a logic circuit 500. The pixel array 100 may refer to Figure 1 The pixel array 100 shown in FIG. 1 is a pixel array 100, and a plurality of pixels (PX) may be connected to the logic circuit 500 through a plurality of row lines and a plurality of column lines. The logic circuit 500 may include a row driver 110, a readout circuit 120, a column driver 130, a timing controller 140, etc. required to drive the pixel array 100. The area occupied by each of the row driver 110, the readout circuit 120, the column driver 130, and the timing controller 140 within the logic circuit 500 and the arrangement shapes of the row driver 110, the readout circuit 120, the column driver 130, and the timing controller 140 within the logic circuit 500 may be modified in various ways.

[0112] According to one embodiment, Figure 1 The compensation circuit 200 shown may be included in the first chip 300. According to another embodiment, the compensation circuit 200 may be included in the second chip 400. According to another example, the voltage controller 210 of the compensation circuit 200 may be included in the first chip 300, and the path controller 220 and the bias voltage generator 230 may be included in the second chip 400. In the above-mentioned embodiment of the present disclosure, the location of the compensation circuit 200 is not limited thereto.

[0113] As apparent from the above description, an image sensing device according to some embodiments of the present disclosure may compensate for an offset voltage and may acquire a high dynamic range (HDR) image with a reduced settling time.

[0114] The embodiments of the present disclosure may provide various effects that can be recognized directly or indirectly.

[0115] Although a number of exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments are contemplated based on what is described and / or shown in this disclosure. In addition, these embodiments may be combined to form additional embodiments.

[0116] CROSS-REFERENCE TO RELATED APPLICATIONS

[0117] This patent application claims priority to and the benefit of Korean Patent Application No. 10-2023-0135935, filed on October 12, 2023, which is hereby incorporated by reference in its entirety.

Claims

1. An image sensing device, comprising: a pixel that outputs a sensing voltage corresponding to a voltage of a floating diffusion region to a sensing node, the floating diffusion region being included in the pixel and having a first capacitance and a second capacitance in respective first and second modes, the second capacitance being greater than the first capacitance; as well as A compensation circuit, the compensation circuit: controlling an offset voltage level of the sensing node through a first path in a first interval, and The sensing voltage is boosted through a second path in a second interval.

2. The image sensing device according to claim 1, wherein: The compensation circuit comprises: a voltage controller that controls the offset voltage level when the first path is selected and boosts the sensing voltage when the second path is selected; a path controller that controls a plurality of switch control signals to select one of the first path and the second path; and A bias voltage generator provides a bias voltage to the voltage controller.

3. The image sensing device according to claim 2, wherein: The voltage controller comprises: a bias controller that controls a first current flowing from the sensing node based on the bias voltage; a current regulator that controls a second current flowing to the first node based on a control voltage; a driving controller that amplifies a change of the sensing voltage based on an input voltage to provide the amplified change to a second node; a boost controller that controls a boost signal based on a voltage of the second node; and A plurality of switch elements are selectively operable according to corresponding switch control signals to select one of the first path and the second path.

4. The image sensing device according to claim 3, wherein: The bias controller comprises: a first transistor connected between the sensing node and a third node and receiving a first bias voltage through a gate terminal of the first transistor; and A second transistor is connected between the third node and a ground voltage input terminal and receives a second bias voltage through a gate terminal of the second transistor.

5. The image sensing device according to claim 4, wherein: The current regulator includes a third transistor connected between a power supply voltage input terminal and the first node and receiving the control voltage through a gate terminal of the third transistor.

6. The image sensing device according to claim 5, wherein: The drive controller comprises: a fourth transistor connected between the power supply voltage input terminal and the second node and receiving the input voltage through a gate terminal of the fourth transistor; and A fifth transistor is connected between the second node and the ground voltage input terminal and receives a third bias voltage through a gate terminal of the fifth transistor.

7. The image sensing device according to claim 6, wherein: The boost controller comprises: a sixth transistor connected between the power supply voltage input terminal and a fourth node and receiving the voltage of the second node through a gate terminal of the sixth transistor; and A seventh transistor is connected between the fourth node and the ground voltage input terminal and receives the voltage of the second node through a gate terminal of the seventh transistor.

8. The image sensing device according to claim 7, wherein: The plurality of switch elements include: a first switching element connected between the second node and a gate terminal of the third transistor and operable according to a first switching control signal of the switching control signals; a second switching element connected between the first node and the fourth node and operable according to a second switching control signal among the switching control signals; and A third switching element is connected between the fourth node and the seventh transistor and is operable according to a third switching control signal among the switching control signals.

9. The image sensing device according to claim 8, in, When the first switching element is turned on and the second switching element and the third switching element are turned off, the first path is selected, and When the first switch element is turned off and the second switch element and the third switch element are turned on, the second path is selected.

10. The image sensing device according to claim 9, wherein: When the first path is selected: The fourth transistor also provides a voltage higher than the sensing voltage as the control voltage, and The current regulator also outputs the second current which is larger according to the control voltage than according to a preset bias voltage, thereby controlling the offset voltage level of the sensing voltage.

11. The image sensing device according to claim 9, wherein: When the second path is selected, the fourth transistor also provides an output voltage having a level higher than the sensing voltage to the sixth transistor and the seventh transistor to reduce the boosted voltage to a level lower than a preset bias voltage, thereby controlling the voltage level of the first node and boosting the sensing voltage.

12. The image sensing device according to claim 8, wherein: The plurality of switch elements include: a fourth switching element connected between the sensing node and the gate terminal of the fourth transistor and operable according to a fourth switching control signal of the switching control signals; a fifth switching element connected between the gate terminal of the fourth transistor and the second node and operable according to a fifth switching control signal among the switching control signals; a sixth switching element connected between the gate terminal of the first transistor and the gate terminal of the third transistor and operable according to a sixth switching control signal among the switching control signals; and A seventh switching element is connected between the third node and the first node and is operable according to a seventh switching control signal among the switching control signals.

13. The image sensing device according to claim 12, wherein: The voltage controller further comprises: a first capacitor connected between the fourth switching element and a gate terminal of the fourth transistor; a second capacitor connected between a gate terminal of the third transistor and the first switching element; and A third capacitor is connected between the first node and the second switching element.

14. The image sensing device according to claim 1, wherein: The first mode is an HCG mode for reading HCG pixel data based on a high conversion gain HCG reset signal and an HCG image signal, and The second mode is an LCG mode for reading LCG pixel data based on a low conversion gain LCG reset signal and an LCG image signal.

15. The image sensing device according to claim 1, wherein: The first interval is a time interval for reading a high conversion gain HCG reset signal of the pixel, and The second interval is a time interval for reading the high conversion gain HCG image signal of the pixel.

16. The image sensing device according to claim 1, wherein: The pixel also includes a dual conversion gain DCG transistor that adjusts the capacitance of the floating diffusion region.

17. An image sensing device, comprising: a pixel that outputs a sensing voltage corresponding to a voltage of a floating diffusion region to a sensing node; as well as A voltage controller, which: When the first path is selected in the first interval, a first current flowing from the sensing node is controlled based on an offset voltage value of the sensing node, and When the second path is selected in the second interval, the first current is boosted.

18. The image sensing device according to claim 17, wherein: The voltage controller comprises: a bias controller that controls the sensing node to have an auto-zero voltage level based on a bias voltage; a current regulator that regulates the first current based on a control voltage; a driving controller that amplifies a change of the sensing voltage based on an input voltage to supply the amplified change as the control voltage; a boost controller that controls a boost signal for boosting the first current based on the input voltage; and A plurality of switch elements are selectively operable according to corresponding switch control signals to select one of the first path and the second path.

19. The image sensing device according to claim 17, wherein: The pixel includes a dual conversion gain DCG transistor that adjusts the capacitance of the floating diffusion region.

20. The image sensing device according to claim 17, wherein: The first interval is a time interval for reading a high conversion gain HCG reset signal of the pixel, and The second interval is a time interval for reading the high conversion gain HCG image signal of the pixel.

Images