Intelligent integrated RRU test method

Abstract

The invention relates to the technical field of communication, in particular to an intelligent integrated RRU test method, which comprises the following steps: simulating an ODU through a first upper computer, generating source data, transmitting the source data to a DDR through a PCIE interface, transmitting the source data to an RRU through a communication link based on option8, transmitting the source data to the outside through the RRU, and completing downlink communication, performing correctness test on input and output of each interface, data stored in each memory and a transmitting signal transmitted to the outside by the RRU to obtain a downlink communication test result; a signal is transmitted to an RRU through a second upper computer analog signal generator, the RRU transmits the received signal to a DDR through a communication link based on option8, and then the DDR transmits the received signal to a first upper computer through a PCIE interface to complete uplink communication. And performing correctness test on the input and output of each interface, the data stored in each memory and the data received by the first upper computer to obtain an uplink communication test result. According to the method, the test cost is reduced, and the test efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communication technology, and in particular to an intelligent integrated RRU testing method. Background Art

[0002] With the rapid development and application of 5G networks, the communications field has put forward higher requirements for the performance, security and reliability of base stations. The RRU (Remote Radio Unit) and BBU (Building Baseband Unit) of a 5G base station are connected by an optical fiber link, and the performance of the optical fiber link directly affects the communication quality of the entire base station. Data transmission in the optical fiber link includes ODU (Optical Distribution Unit) data transmission and reception, and it is crucial to ensure that this data can be transmitted efficiently and without error.

[0003] Traditional RRU testing methods are generally carried out in actual deployment environments, which may make the testing process complicated and difficult to control. In order to optimize the testing process and improve the accuracy of the test, small base stations (also known as micro base stations or small base stations) are introduced into RRU testing. Small base stations can simulate the RRU environment in actual deployment and can be tested in a more controllable experimental environment.

[0004] Small base stations can create a controlled test environment because they can provide data traffic and link loads similar to those in the real environment, thereby verifying the ODU data transmission and reception process in the optical fiber link. This method helps to identify and solve potential problems in the optical fiber link, such as signal attenuation, delay, bit error rate, etc., thereby improving the overall performance and reliability of the optical fiber link. Therefore, by using a test method that simulates ODU data transmission and reception using a small base station, the performance of the optical fiber link can be accurately evaluated and optimized before actual deployment, ensuring that the 5G base station can operate stably and efficiently in a real network environment. To a certain extent, it solves the problems of the traditional RUU equipment method, such as high complexity and difficulty, large waste of resources caused by testing, and the need to develop additional equipment for testing.

[0005] However, even if the small base station test method is adopted, the complete RRU test still requires three instruments to complete the test, which is very expensive. These three instruments are: ODU simulator, which is used to simulate the base station function, connect to RRU through CPRI interface or network port, send downlink data to RRU, and receive uplink data from RRU; signal analyzer, which receives the data sent by RRU through RF cable, displays RF index analysis and constellation diagram, etc.; signal source, which is used to generate uplink data and send the uplink data to RRU through RF cable.

[0006] Therefore, the cost of the test method for small base station simulation is still relatively high, and the actual construction is not convenient enough. Some testing and analysis links still need to be performed on the hardware side, and the analysis of test data is not intuitive enough. Therefore, the solution for 5G base station simulation testing still needs to be continuously improved. Summary of the invention

[0007] In view of this, an embodiment of the present application proposes an intelligent integrated RRU testing method, which performs integrated testing on the downlink and uplink communications of the communication link, greatly reduces the testing cost, and systematically verifies the multiple interfaces involved, providing an effective testing environment for the complete link from time domain data source to frequency domain modulation and demodulation.

[0008] On the first aspect, an embodiment of the present application proposes an intelligent integrated RRU testing method, which includes the following steps: simulating ODU through a first host computer, generating source data, and transmitting it to DDR through a PCIE interface, moving it to RAM through DMA, and then inputting it into a CPRI module for data processing, transmitting it to RRU through a CPRI interface, and finally transmitting it to the outside world by the RRU to complete the downlink communication based on the communication link of option 8; in the downlink communication based on the communication link of option 8, the input and output of the PCIE interface, the data stored in the DDR, the DMA movement operation, the data stored in the RAM, the data processing of the CPRI module, the input and output of the CPRI interface, and the transmission signal transmitted by the RRU to the outside world are respectively performed. The correctness test is performed to obtain the downlink communication test result; the signal is transmitted to the RRU through the second host computer analog signal generator, and the RRU transmits the received signal to the CPRI module through the CPRI interface for data processing, and then inputs it to the RAM, moves it to the DDR through DMA, and then transmits it to the first host computer through the PCIE interface to complete the uplink communication based on the option 8 communication link; in the uplink communication based on the option 8 communication link, the correctness test is performed on the input and output of the CPRI interface, the data processing of the CPRI module, the data stored in the RAM, the DMA movement operation, the data stored in the DDR, the input and output of the PCIE interface, and the data received by the first host computer to obtain the uplink communication test result.

[0009] Optionally, the PCIE interface and DDR are connected via a bus to read and write data, and a write address interval TX_BASE_ADDR and a read address interval RX_BASE_ADDR are respectively set, allowing the PCIE interface to write data to and read data from the DDR at the same time; the PCIE interface, DDR, DMA and RAM are all mounted on the internal bus of the FPGA, and DDR and RAM have different address allocations; while generating source data, the first host computer needs to send corresponding configuration parameters to each module through the PCIE interface for each module to initialize parameters.

[0010] Optionally, Quartus software and Matlab software are installed in the first host computer; in the downlink communication of the communication link based on option 8, the input and output data of the PCIE interface, the data stored in the DDR, the input and output data of the DMA, the data stored in the RAM, the input and output data of the CPRI module, and the input and output data of the CPRI interface are extracted by the signal tap tool in the Quartus software, and the waveform is drawn by Matlab software and compared with the standard waveform, and the data correlation is compared to verify the correctness of each module, and then the second host computer simulates the spectrum analyzer to verify the correctness of the transmission signal transmitted by the RRU to the outside world to obtain the downlink communication test result; wherein, when all modules pass the correctness verification, the downlink communication test result is determined to be passed; in the uplink communication of the communication link based on option 8, the signal The tap tool extracts the input and output data of the CPRI interface, the input and output data of the CPRI module, the data stored in the RAM, the input and output data of the DMA, the data stored in the DDR, the input and output data of the PCIE interface, and the data received by the first host computer, and uses the Matlab software to draw the waveform and compare it with the standard waveform. At the same time, a data correlation comparison is performed to verify the correctness of each module and obtain the uplink communication test result; among them, when all modules pass the correctness verification, the uplink communication test result is determined to be passed.

[0011] Optionally, DMA moves data from DDR to downstream RAM through a preset input source address, destination address, and data transfer length, and outputs data from downstream RAM to CPRI module; wherein DMA writes data to downstream RAM and reads data from downstream RAM and outputs it to CPRI module using ping-pong operation; divides the downstream RAM into a first address space, a second address space, and a downstream buffer, first writes data to the first address space, starts reading data from the first address space after the first address space is full, outputs data from the first address space to the downstream buffer for format conversion, and When the data is written to the second address space, the data writing operation is started; after the second address space is full, all data writing operations are suspended, and after waiting for the data in the first address space to be completely read out, the data reading operation is started from the second address space, and the data is output from the second address space to the downstream buffer for format conversion, and the data writing operation is started in the first address space at the same time; after the first address space is full again, the data writing operation is suspended, and after waiting for the data in the second address space to be completely read out, the data reading operation is started from the first address space, and the data reading and writing operation of the first address space and the second address space are performed alternately in a cycle until all the data are output to the downstream buffer for format conversion.

[0012] Optionally, the input data of the downstream buffer is 32 valid data in 96 clocks, and the output data is required to be 32 valid data in 80 clocks, and the lowest common multiple of 96 clocks and 80 clocks, 480 clocks, is taken as the cycle; for the data write operation, the DMA first writes a valid data into the first address space every 3 clocks, and after 160 valid data are written in 480 clocks, it writes a valid data into the second address space every 3 clocks for 480 clocks, and starts the data read operation at the same time; for the data read operation, the DMA reads a valid data from the first address space every 2 clocks according to the first 64 clocks of 80 clocks, stops reading for the next 16 clocks, and outputs 16 clocks of data according to the last valid data read, so that after 5 80 clocks, the data reading of the first address space is completed, and the sixth 80 clocks remain unchanged according to the last data read from the first address space, thereby realizing the effective storage of the input data and the effective output in the corresponding format.

[0013] Optionally, the data processing of the CPRI module includes: merging the input 8 groups of parallel 16-bit data according to each antenna to synthesize 4 groups of antenna data; grouping the 4 groups of antenna data according to 1, 3 and 2, 4, and multiplexing the two antenna data in both groups, and the multiplexed data is 64 valid data in 80 clocks and 16 invalid data; grouping the two groups of two-antenna multiplexed data separately to obtain four groups of antenna data and process them separately; using a block floating-point algorithm to process each group of antenna data, and through maximum value search, maximum value encoding, and compression processing operations, compressing each 16-bit data of each group of antenna IQ into 8 bits, and obtaining a compression factor, and outputting each antenna IQ data according to the corresponding arrangement; after data mapping of each antenna IQ data through a two-antenna data mapping mode or a four-antenna data mapping mode, the data is transmitted to the RRU through the CPRI interface.

[0014] Optionally, the Tx_data port of the CPRI IP core is used to transmit the control word and IQ data of the transmitter, and Tx_seq is used to indicate the sequence position of the data and control word of each basic frame, and the corresponding value range is 0 to 79; when each basic frame of CPRI transmits two-antenna data, IQ data is transmitted according to the two-antenna data mapping mode, when the value of Tx_seq is 0 to 4, the Tx_data port transmits a 160-bit control word, when the value of Tx_seq is 5 to 36, the Tx_data port transmits data associated with the first antenna, when the value of Tx_seq is 37 to 68, the Tx_data port transmits data associated with the second antenna, and when the value of Tx_seq is 69 to 79, the sequence position will be retained; when each basic frame of CPRI transmits four-antenna data , IQ data is transmitted according to the four-antenna data mapping modulus. When the value of Tx_seq is 0 to 4, the Tx_data port transmits a 160-bit control word. When the value of Tx_seq is 5 to 20, the Tx_data port transmits data associated with the first antenna. When the value of Tx_seq is 21 to 36, the Tx_data port transmits data associated with the second antenna. When the value of Tx_seq is 37 to 52, the Tx_data port transmits data associated with the third antenna. When the value of Tx_seq is 53 to 68, the Tx_data port transmits data associated with the fourth antenna. When the value of Tx_seq is 69, the Tx_data port transmits the compression factors corresponding to all four antennas. When the value of Tx_seq is 70 to 79, the sequence position will be retained.

[0015] Optionally, the protocol of the CPRI interface adopts CPRI Specification V7.0, and the line rate is 10.1376 Gbps.

[0016] An intelligent integrated RRU testing method proposed in an embodiment of the present application has the following beneficial effects.

[0017] First, through the integrated design, the host computer simulates the base station function to perform uplink and downlink communication tests on the RRU and base station function interface, replacing equipment such as ODU simulators and greatly reducing the cost required for testing.

[0018] Second, while the host computer receives the source data, it can implement parameter control according to the input instructions to achieve the purpose of flexibly adjusting the parameters of each module in the FPGA, including uplink and downlink communication modes, RRU interface switching and other functions, reducing the complexity and difficulty of the test and avoiding the waste of test resources as much as possible.

[0019] Third, the base station simulated data is sent and received through the PCIE interface and DDR, and is compatible with uplink and downlink communications. A variety of interface data sources can be flexibly designed. At the same time, the output end can be compatible with the network port, CPRI interface, etc., to enhance the test scalability.

[0020] Fourth, by using 5G time domain data source for data transmission, a reliable and complete 5G system interface verification platform was built. Multiple high-speed interfaces involved in the 5G system were systematically verified, providing an effective test environment for the complete link from time domain data source to frequency domain modulation and demodulation.

[0021] On the second aspect, an embodiment of the present application proposes an intelligent integrated RRU testing method, which includes the following steps: simulating ODU through a first host computer, generating source data, and transmitting it to DDR through a PCIE interface, moving it to RAM through DMA, and then transmitting it to RRU through a 10G / 25G network port, and finally transmitting it to the outside world by RRU to complete the downlink communication of the communication link based on option 7.2; in the downlink communication of the communication link based on option 7.2, the input and output of the PCIE interface, the data stored in the DDR, the DMA movement operation, the data stored in the RAM, the input and output of the 10G / 25G network port, and the transmission signal transmitted by the RRU to the outside world are respectively performed. Perform a correctness test to obtain the downlink communication test result; transmit a signal to the RRU through the second host computer analog signal generator, and the RRU inputs the received signal into the RAM through the 10G / 25G network port, moves it to the DDR through DMA, and then transmits it to the first host computer through the PCIE interface to complete the uplink communication based on the communication link of option 7.2; in the uplink communication based on the communication link of option 7.2, perform correctness tests on the input and output of the 10G / 25G network port, the data stored in the RAM, the DMA movement operation, the data stored in the DDR, the input and output of the PCIE interface, and the data received by the first host computer to obtain the uplink communication test result.

[0022] In a third aspect, an embodiment of the present application proposes a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement an intelligent integrated RRU testing method as described in the first aspect above, or it can implement an intelligent integrated RRU testing method as described in the second aspect above.

[0023] It can be understood that the beneficial effects of the second to third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related technologies, the drawings required for use in the embodiments of the present application or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 is a flow chart of an intelligent integrated RRU testing method provided in one embodiment of the present application;

[0026] Figure 2 is a schematic diagram of the structure of a communication link based on Option 8 provided in one embodiment of the present application;

[0027] Figure 3 It is a schematic diagram of the main implementation process of downlink communication based on the Option 8 communication link provided in one embodiment of the present application;

[0028] Figure 4 is a schematic diagram of the structure and working principle of a DMA provided in one embodiment of the present application;

[0029] Figure 5 is a schematic diagram of the input and output data format of the downlink buffer provided in an embodiment of the present application;

[0030] Figure 6 is a schematic diagram of data processing of a CPRI module provided in one embodiment of the present application;

[0031] Figure 7 It is a schematic diagram of a specific implementation process of compression and decompression provided in an embodiment of the present application;

[0032] Figure 8 is a schematic diagram of two data mapping modes of two antennas and four antennas provided in an embodiment of the present application;

[0033] Fig. 9 It is a schematic diagram of parameter configuration of a CPRI IP core provided in one embodiment of the present application;

[0034] Fig.10 is a schematic diagram of the overall functions of a CPRI interface provided in one embodiment of the present application;

[0035] Fig.11 is a schematic diagram of the input and output data format of the uplink buffer provided in an embodiment of the present application;

[0036] Fig.12 is a flow chart of an intelligent integrated RRU testing method provided in another embodiment of the present application;

[0037] Fig.13 It is a structural diagram of a communication link based on option 7.2 provided in another embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. In the various embodiments of the present application, many technical details are proposed in order to make the reader better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is only for the convenience of description, and the specific implementation mode of the present application should not constitute any limitation. The various embodiments can be combined with each other and referenced to each other under the premise of no contradiction.

[0039] In response to the problems existing in traditional RRU testing methods, small base station testing methods came into being.

[0040] The patent application number CN201710765955.X discloses an RRU test system and method. The test system includes an RRU to be tested, a test computer, an attenuator, a power divider, a spectrum analyzer, a signal source, and a switch. The test method includes starting the RRU, the RRU enters the test state, and performs a DDR self-test; the RRU receives a test command, the RRU performs a downlink test, the RRU performs an uplink test, and the RRU performs an optical link test. The test system solves the problems of the complexity and difficulty of RUU equipment testing in traditional technologies, the large waste of resources caused by testing, and the need to develop additional equipment for testing, and achieves the technical effect of reducing the complexity and difficulty of testing, reducing the waste of testing resources, and not having to develop additional equipment.

[0041] However, the test system still requires spectrum analyzers, signal sources and other equipment for testing, and the equipment is still relatively expensive. Although the test parameters are issued through the test software, there is no dedicated parameter configuration management module, and the actual test process is still cumbersome and not flexible enough. The accuracy of the test and analysis data still needs to be tested on the hardware side, which is not as convenient as directly transferring the data to the software side for software processing. The analysis of data performance cannot be intuitively reflected, which is not convenient for analyzing the performance advantages and disadvantages.

[0042] The patent with application number CN202011604839.8 discloses an RRU test method, device and medium, which relates to the field of communication technology. The method includes: inputting the uplink simulation data of at least one channel into the path processing module of the radio remote unit RRU, and ping-pong caching the uplink data output by the uplink channel packet processing module of the RRU. Then, the uplink data of the channel to be tested is extracted from the uplink data of the ping-pong cache, and the uplink data of the channel to be tested is cached in the random access memory RAM; the uplink data of the channel to be tested cached in the RAM is transmitted to the double rate synchronous dynamic random access memory DDR through the PCIE interface, and the uplink data of the channel to be tested cached in the DDR is transmitted to the test equipment, so that the test equipment compares the uplink data of the channel to be tested with the simulation output data of the channel to be tested to determine whether there is a fault in the channel to be tested. The development and maintenance efficiency of RRU can be improved.

[0043] However, this test method mainly tests whether a single channel has a fault through data transmission, and cannot perform overall loopback tests on uplink and downlink links, which is not conducive to testers to perform overall data tests. Without unified parameter management on the software side, the test is more complicated. Without matching multiple corresponding RRU protocol interfaces, it may not be able to adapt during the actual test process.

[0044] In order to solve the technical problems that the cost of the test method for small base station simulation is still high, the actual construction is not convenient enough, some testing and analysis links still need to be performed on the hardware side, and the analysis of test data is not intuitive enough, an embodiment of the present application proposes an intelligent integrated RRU test method, which is suitable for communication links based on option 8. The implementation details of the intelligent integrated RRU test method proposed in this embodiment are specifically described below. The following content is only the implementation details provided for the convenience of understanding, and is not necessary for the implementation of this solution.

[0045] The specific process of the intelligent integrated RRU testing method proposed in this embodiment is as follows: Figure 1 As shown, including:

[0046] Step 101, the first host computer simulates ODU, generates source data, and transmits it to DDR through the PCIE interface. After being moved to RAM through DMA, it is input into the CPRI module for data processing, transmitted to RRU through the CPRI interface, and finally transmitted to the outside by RRU, completing the downlink communication based on the communication link of option 8.

[0047] Step 102, in the downlink communication based on the communication link of option 8, the input and output of the PCIE interface, the data stored in the DDR, the DMA movement operation, the data stored in the RAM, the data processing of the CPRI module, the input and output of the CPRI interface, and the transmission signal transmitted by the RRU to the outside world are tested for correctness to obtain the downlink communication test result.

[0048] In the specific implementation, the RRU to be tested in this embodiment complies with the O-RAN standard. Due to the different interfaces used, the communication links of the RRU are different. If the CPRI module and CPRI interface are used in the communication, the communication link is based on option 8. If the 10G / 25G network port is used in the communication, the communication link is based on option 7.2. Testing the RRU requires not only testing the RRU itself, but also testing each module and each interface in the uplink and downlink communications of the entire communication link.

[0049] First, relevant tests on downlink communication are carried out. The first step of the test is to carry out downlink communication. At this time, the first host computer simulates ODU to generate source data (data to be sent), and transmits it to DDR through the PCIE interface. Then DMA moves the source data from DDR to RAM, and then inputs it into the CPRI module for data processing. It is transmitted to RRU through the CPRI interface, and finally transmitted to the outside world by RRU to complete the downlink communication based on the communication link of option 8.

[0050] In the downlink communication based on the option 8 communication link, the input and output of the PCIE interface, the data stored in the DDR, the DMA movement operation, the data stored in the RAM, the data processing of the CPRI module, the input and output of the CPRI interface, and the transmission signal transmitted by the RRU to the outside world are tested for correctness to obtain the downlink communication test results.

[0051] The communication link based on Option 8 can be as follows Figure 2 As shown in the figure, the main implementation process of the downlink communication based on the Option 8 communication link can be as follows Figure 3 As shown, the implementation process of the downlink communication based on the Option 8 communication link and the test of each module and interface in the downlink communication based on the Option 8 communication link are described in detail below.

[0052] First, it is necessary to confirm the function simulated by the first host computer. In downlink communication, the first host computer needs to simulate ODU (in uplink communication, the first host computer needs to simulate UE). After determining the simulated function, the first host computer formulates source data (data source) according to the corresponding format, stores the source data in the software, and waits for transmission. While generating the source data, the first host computer also needs to pre-formulate the corresponding interface data and the corresponding configuration parameters.

[0053] Before sending source data, the first host computer needs to send corresponding configuration parameters to each module through the PCIE interface for each module to perform parameter initialization.

[0054] The PCIE interface and DDR are connected via a bus to read and write data. The PCIE interface is respectively provided with a write address interval TX_BASE_ADDR and a read address interval RX_BASE_ADDR. During communication, the PCIE interface is allowed to write data to and read data from the DDR at the same time, that is, upstream and downstream communications (data reading and writing) can be performed simultaneously.

[0055] The PCIE interface, DDR, DMA and RAM are all mounted on the internal bus of the FPGA. DDR and RAM have different address assignments to prevent memory conflicts.

[0056] First, the host computer sends data to the DDR of the FPGA development board through the PCIE interface. The amount of data sent is controlled by the software. DMA moves data from DDR to the downstream RAM through the preset input source address, destination address, and data transfer length, and outputs data from the downstream RAM to the CPRI module. The structure and working principle of DMA can be shown as follows Figure 4 shown.

[0057] The rate of writing to the downlink RAM is 250M, and the rate of outputting data from the downlink RAM to the CPRI module is 307.2M. Therefore, DMA needs to use ping-pong operation to write data to the downlink RAM and read data from the downlink RAM to the CPRI module. The downlink RAM is divided into the first address space, the second address space and the downlink buffer. The DMA splits the read 256-bit data into 8 32-bit data and outputs them in sequence. Then each 32-bit data is split into a group of 16-bit data for each antenna QI and input them in parallel into the four antenna QIs, and finally input them into the downlink buffer.

[0058] DMA first writes data to the first address space. After the first address space is full, data reading from the first address space is started, data is output from the first address space to the downstream buffer for format conversion, and data writing to the second address space is started at the same time. After the second address space is full, all data writing operations are suspended, and after waiting for all the data in the first address space to be read out, data reading from the second address space is started, data is output from the second address space to the downstream buffer for format conversion, and data writing to the first address space is started at the same time. After the first address space is full again, data writing operations are suspended, and after waiting for all the data in the second address space to be read out, data reading from the first address space is started, and data reading and writing of the first address space and the second address space are performed alternately in a cycle until all the data are output to the downstream buffer for format conversion.

[0059] The input and output data formats of the downstream buffer can be as follows Figure 5 As shown in the figure, the input data of the downlink buffer is 32 valid data in 96 clocks, and the output data is required to be 32 valid data in 80 clocks. The input and output clock frequencies are both 307.2M, so the data needs to be processed, and the least common multiple of 96 clocks and 80 clocks, 480 clocks, is taken as the cycle. The last 80 clocks of the output data remain unchanged, and the format matching of the input CPRI module is achieved.

[0060] For data write operation, DMA first writes a valid data into the first address space every 3 clocks, and after 480 clocks are filled with 160 valid data, it writes 480 clocks into the second address space at the same time as one valid data every 3 clocks, and starts data read operation at the same time. For data read operation, DMA reads out a valid data from the first address space every 2 clocks according to the first 64 clocks of 80 clocks, stops reading for the last 16 clocks, and outputs 16 clocks of data according to the last valid data read. In this way, after 5 80 clocks, the data reading of the first address space is completed, and the sixth 80 clocks remain unchanged according to the last data read from the first address space, thereby realizing the effective storage of input data and the effective output in the corresponding format.

[0061] After the source data is read out from the downlink RAM to the CPRI module by DMA, it needs to be processed by the CPRI module, which includes multiplexing, compression, segmentation, etc. The data processing of the CPRI module can be as follows Figure 6As shown. The CPRI module merges the 8 sets of parallel 16-bit data input according to each antenna to synthesize 4 sets of antenna data, recorded as ch1, ch2, ch3 and ch4. Then the 4 sets of antenna data are grouped according to 1, 3 (ch1, ch3) and 2, 4 (ch2, ch4), and both groups are multiplexed with two-antenna data. After multiplexing, 64 data in 80 clocks are valid and 16 data are invalid. After that, the two sets of two-antenna multiplexed data are grouped separately to obtain four sets of antenna data and process them separately. Then, each set of antenna data is processed by block floating-point algorithm, and each 16-bit data of each set of antenna IQ is compressed into 8 bits through maximum value search, maximum value encoding, compression processing and other operations, and the compression factor is obtained, and the IQ data of each antenna is output according to the corresponding arrangement. Finally, the IQ data of each antenna is mapped through the two-antenna data mapping mode or the four-antenna data mapping mode, and then transmitted to the RRU through the CPRI interface. The specific implementation process of compression and decompression can be as follows Figure 7 shown.

[0062] In the CPRI frame format with a line rate of 10.1376G, every 10ms is a radio frame, each radio frame contains 150 superframes, the superframe number is Z, each superframe contains 256 basic frames, the basic frame number is X, and each basic frame transmission consists of 16 words, the word size is W. IQ data mapping is to distinguish data from different antennas, and IQ data mapping is based on a basic frame. The two-antenna and four-antenna data mapping modes facilitate compatible processing of antenna transmission in actual situations. The principles of the two-antenna and four-antenna data mapping modes can be as follows Figure 8 shown.

[0063] The Tx_data port of the CPRI IP core is used to transmit the control word and IQ data of the transmitter. Tx_seq is used to indicate the sequence position of the data and control word of each basic frame, and the corresponding value range is 0 to 79.

[0064] When each basic frame of CPRI transmits two-antenna data, IQ data is transmitted according to the two-antenna data mapping mode. When the value of Tx_seq is 0 to 4, the Tx_data port transmits a 160-bit control word. When the value of Tx_seq is 5 to 36, the Tx_data port transmits data associated with the first antenna. When the value of Tx_seq is 37 to 68, the Tx_data port transmits data associated with the second antenna. When the value of Tx_seq is 69 to 79, the sequence position will be retained.

[0065] When each basic frame of CPRI transmits four-antenna data, IQ data is transmitted according to the four-antenna data mapping modulus. When the value of Tx_seq is 0 to 4, the Tx_data port transmits a 160-bit control word. When the value of Tx_seq is 5 to 20, the Tx_data port transmits data associated with the first antenna. When the value of Tx_seq is 21 to 36, the Tx_data port transmits data associated with the second antenna. When the value of Tx_seq is 37 to 52, the Tx_data port transmits data associated with the third antenna. When the value of Tx_seq is 53 to 68, the Tx_data port transmits data associated with the fourth antenna. When the value of Tx_seq is 69, the Tx_data port transmits the compression factors corresponding to all four antennas. When the value of Tx_seq is 70 to 79, the sequence position will be retained.

[0066] The four-antenna data mapping mode ensures that the IQ data and compression factors from four different antennas can be organized in an orderly manner within a CPRI basic frame, while maintaining a certain degree of flexibility for future expansion or other purposes. In this way, the CPRI system can efficiently manage and transmit complex data flows of multi-antenna systems.

[0067] The CPRI interface is mainly used for data exchange between the platform and the RRU. Combined with the platform system design requirements, the CPRI interface protocol selects the CPRI Specification V7.0 standard, and the line rate is 10.1376Gbps. Therefore, it is necessary to set the parameters of the CPRI IP core so that data can be transmitted to the RRU / base station through the CPRI interface. The parameter configuration of the CPRI IP core can be as follows: Fig. 9 As shown, the overall functionality of the CPRI interface can be as follows Fig.10 shown.

[0068] The first host computer is installed with Quartus software and Matlab software. In the downlink communication based on the communication link of option 8, the input and output data of the PCIE interface, the data stored in the DDR, the input and output data of the DMA, the data stored in the RAM, the input and output data of the CPRI module, and the input and output data of the CPRI interface are extracted through the signal tap tool in the Quartus software, and the waveform is drawn by Matlab software and compared with the standard waveform. At the same time, the data correlation is compared to verify the correctness of each module, and then the second host computer simulates the spectrum analyzer to verify the correctness of the transmission signal transmitted by the RRU to the outside world, and obtain the downlink communication test result. Among them, when all modules pass the correctness verification, the downlink communication test result is determined to be passed.

[0069] Step 103, the second host computer analog signal generator transmits a signal to the RRU, and the RRU transmits the received signal to the CPRI module through the CPRI interface for data processing, and then inputs it into the RAM, moves it to the DDR through DMA, and then transmits it to the first host computer through the PCIE interface by the DDR, completing the uplink communication based on the communication link of option 8.

[0070] Step 104, in the uplink communication based on the communication link of option 8, the input and output of the CPRI interface, the data processing of the CPRI module, the data stored in the RAM, the DMA movement operation, the data stored in the DDR, the input and output of the PCIE interface, and the data received by the first host computer are tested for correctness to obtain the uplink communication test result.

[0071] After the relevant tests of downlink communication are completed, relevant tests of uplink communication are required. At this time, the second host computer simulates the signal generator to transmit a signal to the RRU. The RRU transmits the received signal to the CPRI module through the CPRI interface for data processing, and then inputs it into the RAM. After being moved to the DDR via DMA, the DDR transmits it to the first host computer through the PCIE interface (at this time, the first host computer is used to simulate the user equipment UE), completing the uplink communication based on the communication link of option 8.

[0072] In the uplink communication based on the option 8 communication link, the input and output of the CPRI interface, the data processing of the CPRI module, the data stored in the RAM, the DMA movement operation, the data stored in the DDR, the input and output of the PCIE interface, and the data received by the first host computer are tested for correctness to obtain the uplink communication test result.

[0073] For uplink communication, the RRU transmits data to the FPGA development board through the CPRI interface, and the CPRI module processes the data, including data demapping, data decompression, segmented data management and data demultiplexing. Data demapping restores the data to the data format before mapping. Data decompression uses the compression factor passed over and shift operations to achieve data decompression. Segmented data management is the opposite of downlink, and the segmented data is reintegrated. Data demultiplexing demultiplexes the multiplexed data and divides it into four antenna data outputs. Antenna data splitting: split the IQ data of each antenna, so that it is divided into 4 groups of 8 I, Q data for parallel output.

[0074] The next step is to convert the upstream buffer format. The input and output data formats of the upstream buffer can be as follows Fig.11As shown in the figure, the input data of the upstream buffer is 64 valid data and 16 invalid data in the first 5 80 clocks of 480 clocks. The data input in the sixth 80 clocks is invalid, and the output data is one valid data every 3 clocks. In this way, the input and output are exactly 160 valid data.

[0075] Data is written into the upstream RAM, and the data is moved from the upstream RAM to the upstream address space of the DDR through DMA. The address antenna data written into the upstream RAM is selected through the host computer parameters, and then the data written into the upstream RAM is moved to the upstream address space of the DDR through the bus through DMA. Finally, the data in the DDR upstream address space is transmitted to the first host computer through the PCIE interface.

[0076] In the uplink communication of the communication link based on option 8, the input and output data of the CPRI interface, the input and output data of the CPRI module, the data stored in the RAM, the input and output data of the DMA, the data stored in the DDR, the input and output data of the PCIE interface, and the data received by the first host computer are extracted by the signal tap tool in the Quartus software, and the waveform is drawn by Matlab software and compared with the standard waveform, and the data correlation is compared at the same time to verify the correctness of each module and obtain the uplink communication test result. Among them, when all modules pass the correctness verification, the uplink communication test result is determined to be passed.

[0077] When both the downlink communication and the uplink communication are tested through, it can be determined that all the RRUs to be tested have passed the test.

[0078] In this embodiment, an intelligent integrated RRU testing method is proposed, which has the following beneficial effects.

[0079] First, through the integrated design, the host computer simulates the base station function to perform uplink and downlink communication tests on the RRU and base station function interface, replacing equipment such as ODU simulators and greatly reducing the cost required for testing.

[0080] Second, while the host computer receives the source data, it can implement parameter control according to the input instructions to achieve the purpose of flexibly adjusting the parameters of each module in the FPGA, including uplink and downlink communication modes, RRU interface switching and other functions, reducing the complexity and difficulty of the test and avoiding the waste of test resources as much as possible.

[0081] Third, the base station simulated data is sent and received through the PCIE interface and DDR, and is compatible with uplink and downlink communications. A variety of interface data sources can be flexibly designed. At the same time, the output end can be compatible with the network port, CPRI interface, etc., to enhance the test scalability.

[0082] Fourth, by using 5G time domain data source for data transmission, a reliable and complete 5G system interface verification platform was built. Multiple high-speed interfaces involved in the 5G system were systematically verified, providing an effective test environment for the complete link from time domain data source to frequency domain modulation and demodulation.

[0083] The step division of the above methods is only for clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this application.

[0084] Another embodiment of the present application proposes an intelligent integrated RRU testing method, which is applicable to a communication link based on option 7.2. The implementation details of the intelligent integrated RRU testing method proposed in this embodiment are described in detail below. The following content is only the implementation details provided for the convenience of understanding and is not necessary for the implementation of this solution.

[0085] The specific process of the intelligent integrated RRU testing method proposed in this embodiment is as follows: Fig.12 As shown, including:

[0086] Step 201, the first host computer simulates the ODU to generate source data, and transmits it to the DDR through the PCIE interface. After being moved to the RAM through DMA, it is transmitted to the RRU through the 10G / 25G network port, and finally transmitted to the outside world by the RRU, completing the downlink communication of the communication link based on option 7.2.

[0087] Step 202, in the downlink communication of the communication link based on option 7.2, the input and output of the PCIE interface, the data stored in the DDR, the DMA movement operation, the data stored in the RAM, the input and output of the 10G / 25G network port, and the transmission signal transmitted by the RRU to the outside world are tested for correctness to obtain the downlink communication test result.

[0088] Step 203, the second host computer simulates a signal generator to transmit a signal to the RRU, and the RRU inputs the received signal into the RAM through the 10G / 25G network port, moves it to the DDR through DMA, and then transmits it to the first host computer through the PCIE interface by the DDR, completing the uplink communication based on the communication link of option 7.2.

[0089] Step 204, in the uplink communication of the communication link based on option 7.2, the input and output of the 10G / 25G network port, the data stored in the RAM, the DMA movement operation, the data stored in the DDR, the input and output of the PCIE interface, and the data received by the first host computer are tested for correctness to obtain the uplink communication test result.

[0090] like Fig.13 As shown in the figure, the difference between the communication link based on option 7.2 and the communication link based on option 8 lies in the different interfaces used. The communication link based on option 7.2 uses the 10G / 25G network port. The other test items are basically the same as those of the communication link based on option 8 and are not described here.

[0091] The step division of the above methods is only for clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this application.

[0092] Another embodiment of the present application proposes a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the intelligent integrated RRU testing method applicable to a communication link based on option 8 described in the above embodiment, or it can implement the intelligent integrated RRU testing method applicable to a communication link based on option 7.2 described in the above embodiment.

[0093] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a device (such as a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, ROM (Read-Only Memory), RAM (Random Access Memory), disk or optical disk and other media that can store program codes.

[0094] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. An intelligent integrated RRU testing method, characterized in that: include: The first host computer simulates ODU to generate source data, and transmits it to DDR through the PCIE interface. After being moved to RAM through DMA, it is input to the CPRI module for data processing, transmitted to RRU through the CPRI interface, and finally transmitted to the outside world by RRU, completing the downlink communication based on the communication link of option 8. In the downlink communication based on the Option 8 communication link, the correctness of the input and output of the PCIE interface, the data stored in the DDR, the DMA movement operation, the data stored in the RAM, the data processing of the CPRI module, the input and output of the CPRI interface, and the transmission signal transmitted by the RRU to the outside world are tested to obtain the downlink communication test results; The second host computer simulates the signal generator to transmit a signal to the RRU. The RRU transmits the received signal to the CPRI module through the CPRI interface for data processing, and then inputs it into the RAM. After being moved to the DDR through DMA, the DDR transmits it to the first host computer through the PCIE interface, completing the uplink communication based on the communication link of option 8. In the uplink communication based on the option 8 communication link, the input and output of the CPRI interface, the data processing of the CPRI module, the data stored in the RAM, the DMA movement operation, the data stored in the DDR, the input and output of the PCIE interface, and the data received by the first host computer are tested for correctness to obtain the uplink communication test result.

2. The intelligent integrated RRU testing method according to claim 1, characterized in that: The PCIE interface and DDR are connected via a bus to read and write data. A write address interval TX_BASE_ADDR and a read address interval RX_BASE_ADDR are set respectively, allowing the PCIE interface to write data to DDR and read data from DDR at the same time; The PCIE interface, DDR, DMA and RAM are all mounted on the internal bus of the FPGA, and DDR and RAM have different address assignments; When generating source data, the first host computer needs to send corresponding configuration parameters to each module through the PCIE interface for each module to initialize parameters.

3. The intelligent integrated RRU testing method according to claim 1, characterized in that: The first host computer is installed with Quartus software and Matlab software; In the downlink communication based on the communication link of option 8, the input and output data of the PCIE interface, the data stored in the DDR, the input and output data of the DMA, the data stored in the RAM, the input and output data of the CPRI module, and the input and output data of the CPRI interface are extracted by the signal tap tool in the Quartus software. The waveform is drawn by Matlab software and compared with the standard waveform. At the same time, the data correlation is compared to verify the correctness of each module. Then, the second host computer simulates the spectrum analyzer to verify the correctness of the transmission signal transmitted by the RRU to the outside world, and the downlink communication test result is obtained; wherein, when all modules pass the correctness verification, the downlink communication test result is determined to be passed; In the uplink communication of the communication link based on option 8, the input and output data of the CPRI interface, the input and output data of the CPRI module, the data stored in the RAM, the input and output data of the DMA, the data stored in the DDR, the input and output data of the PCIE interface, and the data received by the first host computer are extracted through the signal tap tool in the Quartus software. The waveform is drawn by Matlab software and compared with the standard waveform. At the same time, the data correlation comparison is performed to verify the correctness of each module and obtain the uplink communication test result. Among them, when all modules pass the correctness verification, the uplink communication test result is determined to be passed.

4. The intelligent integrated RRU testing method according to claim 1, characterized in that: DMA moves data from DDR to downstream RAM through the preset input source address, destination address, and data transfer length, and outputs data from downstream RAM to CPRI module. DMA writes data to downstream RAM and reads data from downstream RAM to CPRI module using ping-pong operation. The first address space, the second address space and the downstream buffer are divided in the downstream RAM. Data is first written to the first address space. After the first address space is full, data reading from the first address space is started, data is output from the first address space to the downstream buffer for format conversion, and data writing to the second address space is started at the same time. After the second address space is full, all data writing operations are suspended, and after all the data in the first address space is read out, data reading in the second address space is started, data is output from the second address space to the downstream buffer for format conversion, and data writing in the first address space is started at the same time; After the first address space is full again, the data writing operation is suspended, and after all the data in the second address space is read out, the data reading of the first address space is started, and the data reading and writing of the first address space and the second address space are performed alternately in a cycle until all the data are output to the downstream buffer for format conversion.

5. The intelligent integrated RRU testing method according to claim 4, characterized in that: The input data of the downstream buffer is 32 valid data in 96 clocks, and the output data is required to be 32 valid data in 80 clocks. The lowest common multiple of 96 clocks and 80 clocks, 480 clocks, is taken as the period; For data write operation, DMA first writes a valid data into the first address space every 3 clocks. After 160 valid data are written in 480 clocks, it writes a valid data into the second address space every 3 clocks for 480 clocks, and starts data read operation at the same time. For data reading operations, DMA reads out a valid data every 2 clocks from the first address space according to the first 64 clocks of 80 clocks, stops reading for the next 16 clocks, and outputs data for 16 clocks according to the last valid data read. In this way, after 5 80 clocks, the data reading of the first address space is completed, and the 6th 80 clocks remain unchanged according to the last data read from the first address space, thereby realizing the effective storage of input data and the effective output in the corresponding format.

6. The intelligent integrated RRU testing method according to claim 5, characterized in that: The data processing of the CPRI module includes: The 8 sets of parallel 16-bit data are input and combined according to each antenna to form 4 sets of antenna data. The 4 groups of antenna data are grouped into 1, 3 and 2, 4, and the two groups are multiplexed with two antenna data. After multiplexing, 64 data out of 80 clocks are valid and 16 data are invalid. The two groups of two-antenna multiplexed data are grouped separately to obtain four groups of antenna data and process them separately; Use block floating point algorithm to process each group of antenna data, compress each 16-bit data of each group of antenna IQ into 8 bits through maximum value search, maximum value encoding, and compression processing operations, and obtain the compression factor, and output each antenna IQ data according to the corresponding arrangement; After the IQ data of each antenna is mapped through the two-antenna data mapping mode or the four-antenna data mapping mode, it is transmitted to the RRU through the CPRI interface.

7. The intelligent integrated RRU testing method according to claim 6, characterized in that: The Tx_data port of the CPRI IP core is used to transmit the control word and IQ data of the transmitter. Tx_seq is used to indicate the sequence position of the data and control word of each basic frame, and the corresponding value range is 0 to 79; When each basic frame of CPRI transmits two-antenna data, IQ data is transmitted according to the two-antenna data mapping mode. When the value of Tx_seq is 0 to 4, the Tx_data port transmits a 160-bit control word. When the value of Tx_seq is 5 to 36, the Tx_data port transmits data associated with the first antenna. When the value of Tx_seq is 37 to 68, the Tx_data port transmits data associated with the second antenna. When the value of Tx_seq is 69 to 79, the sequence position will be reserved. When each basic frame of CPRI transmits four-antenna data, IQ data is transmitted according to the four-antenna data mapping modulus. When the value of Tx_seq is 0 to 4, the Tx_data port transmits a 160-bit control word. When the value of Tx_seq is 5 to 20, the Tx_data port transmits data associated with the first antenna. When the value of Tx_seq is 21 to 36, the Tx_data port transmits data associated with the second antenna. When the value of Tx_seq is 37 to 52, the Tx_data port transmits data associated with the third antenna. When the value of Tx_seq is 53 to 68, the Tx_data port transmits data associated with the fourth antenna. When the value of Tx_seq is 69, the Tx_data port transmits the compression factors corresponding to all four antennas. When the value of Tx_seq is 70 to 79, the sequence position will be retained.

8. An intelligent integrated RRU testing method according to any one of claims 1 to 7, characterized in that: The protocol of the CPRI interface adopts the CPRI Specification V7.0 standard, and the line rate is 10.1376Gbps.

9. An intelligent integrated RRU testing method, characterized in that: include: The first host computer simulates ODU to generate source data, and transmits it to DDR through the PCIE interface. After being moved to RAM through DMA, it is transmitted to RRU through the 10G / 25G network port. Finally, RRU transmits it to the outside world, completing the downlink communication based on the communication link of option 7.

2. In the downlink communication based on the communication link of option 7.2, the correctness of the input and output of the PCIE interface, the data stored in the DDR, the DMA movement operation, the data stored in the RAM, the input and output of the 10G / 25G network port, and the transmission signal transmitted by the RRU to the outside world are tested to obtain the downlink communication test results; The second host computer simulates the signal generator to transmit a signal to the RRU. The RRU inputs the received signal into the RAM through the 10G / 25G network port, moves it to the DDR through DMA, and then transmits it to the first host computer through the PCIE interface by the DDR, completing the uplink communication based on the communication link of option 7.

2. In the uplink communication of the communication link based on option 7.2, the input and output of the 10G / 25G network port, the data stored in the RAM, the DMA movement operation, the data stored in the DDR, the input and output of the PCIE interface, and the data received by the first host computer are tested for correctness to obtain the uplink communication test results.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, it can implement an intelligent integrated RRU testing method as described in any one of claims 1 to 8, or it can implement an intelligent integrated RRU testing method as described in claim 9.

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