Printed circuit board and method for manufacturing printed circuit board

Abstract

Provided is a printed circuit board or the like which suppresses unevenness in the thickness of an interlayer connection section and which has excellent flatness. A wired circuit board is provided with: a metal core layer having a through-hole; a first insulating layer disposed on one surface of the metal core layer; a second insulating layer disposed on the other surface of the metal core layer; a first wiring layer disposed on the first insulating layer; a second wiring layer disposed on the second insulating layer; and an interlayer connection portion that penetrates the through hole of the metal core layer, electrically connects the first wiring layer and the second wiring layer, and is not electrically connected to the metal core layer, the interlayer connection portion having a first interlayer connection portion and a second interlayer connection portion arranged in the thickness direction of the metal core layer, the first interlayer connection portion and the second interlayer connection portion are made of different materials.

Description

Technical Field

[0001] The present invention relates to a wiring circuit substrate and a method for manufacturing the wiring circuit substrate, and a semiconductor package and electronic equipment including the wiring circuit substrate. Background Art

[0002] The wired circuit board is manufactured by laminating conductors such as wiring and various insulating layers on a base material. The conductors and insulating layers are patterned by, for example, photolithography.

[0003] As a method for manufacturing a wiring circuit substrate using a metal core layer, for example, a method for manufacturing a metal core substrate is proposed, which includes: a process of forming a through hole penetrating the surface and back side of the metal layer in a metal layer serving as a core material; a process of stacking an insulating layer on the metal layer; a process of forming a through hole in the insulating layer that penetrates the through hole of the metal layer and penetrates the surface and back side of the insulating layer; a process of forming a via hole connected to the metal layer in the insulating layer; a process of supplying power to the metal layer and performing electrolytic plating to form a conductor portion connected to the metal layer in the via hole; a process of forming a conductor layer on the surface of the insulating layer and the inner wall of the through hole that is connected to the conductor portion in the via hole; and a process of forming a wiring pattern using the conductor layer formed on the surface of the insulating layer (see patent document 1). Prior art literature Patent Literature

[0004] Patent Document 1: Japanese Patent Application Publication No. 2003-304063 Summary of the invention Problems to be solved by the invention

[0005] The manufacture of a wiring circuit board using a metal core layer includes, for example, the following steps. First, a metal core layer 101 ( Fig. 6A Next, a through hole 101A is formed in the metal core layer 101 ( Figure 6B Next, after forming an insulating layer 102 on the surface and back surface of the metal core layer 101 having the through hole 101A, a through hole 103 penetrating the insulating layer 102 and the metal core layer 101 is formed ( Figure 6C Then, the inside of the through hole 103 is filled with plating (conductor portion 104). Fig.6D ). It should be noted that Fig.6D In the embodiment, the inside of the through hole 103 is filled with plating (conductor portion 104 ), and the wiring layer 105 is formed on the insulating layer 102 . In the manufactured wired circuit board, the plating (conductor portion) in the through hole serving as the interlayer connection portion is thick, so it may be difficult to control the uneven thickness of the interlayer connection portion. As a result, the flatness of the wired circuit board may be reduced.

[0006] An object of the present invention is to provide a wired circuit board having excellent flatness and a method for manufacturing the wired circuit board, and a semiconductor package and an electronic device including the wired circuit board. Technical solutions to solve problems

[0007] The inventors of the present invention have conducted intensive studies to solve the above-mentioned problems, and as a result, have found that the above-mentioned problems can be solved, and have completed the present invention having the following gist. That is, the present invention includes the following contents.

[0008] [1] A wiring circuit substrate comprising: a metal core layer having through holes; A first insulating layer, which is disposed on one surface of the metal core layer; A second insulating layer, which is disposed on the other surface of the metal core layer; A first wiring layer, which is arranged on the first insulating layer; A second wiring layer is disposed on the second insulating layer; and an interlayer connection portion that passes through the through hole of the metal core layer, electrically connects the first wiring layer to the second wiring layer, and is not electrically connected to the metal core layer, The interlayer connection portion includes a first interlayer connection portion and a second interlayer connection portion arranged in a thickness direction of the metal core layer, A material of the first interlayer connection portion is different from a material of the second interlayer connection portion. [2] In the wiring circuit substrate according to [1], the second interlayer connection portion is arranged at a position closer to the center of the through hole in the thickness direction of the metal core layer than the first interlayer connection portion. The second interlayer connecting portion has a thickness greater than that of the first interlayer connecting portion. [3] In the wired circuit board according to [1] or [2], the through hole in the metal core layer has a tapered shape. [4] Based on any one of [1] to [3], the side shape of the through hole in the metal core layer is arc-shaped in a cross section parallel to the thickness direction of the metal core layer. [5] Based on any one of [1] to [3], the side shape of the through hole in the metal core layer is linear in a cross section parallel to the thickness direction of the metal core layer. [6] In the wiring circuit substrate according to any one of [1] to [5], in the interlayer connection portion, the second interlayer connection portion is arranged at a position closer to the center of the through hole in the thickness direction of the metal core layer than the first interlayer connection portion. The thickness of the second interlayer connecting portion is 60% to 140% of the thickness of the metal core layer. [7] In the wiring circuit substrate according to any one of [1] to [6], the cross-sectional shape of the first interlayer connection portion is rectangular in a cross section parallel to the thickness direction of the metal core layer. [8] In the wiring circuit substrate according to any one of [1] to [6], the cross-sectional shape of the first interlayer connection portion is a trapezoid in a cross section parallel to the thickness direction of the metal core layer. [9] The wiring circuit substrate according to any one of [1] to [8], wherein the wiring circuit substrate has a terminal connection connection portion for electrically connecting an external terminal to the interlayer connection portion, The cross-sectional shape of the terminal connection connection portion is rectangular in a cross section parallel to the thickness direction of the metal core layer.

[10] In the wiring circuit substrate according to any one of [1] to [8], the wiring circuit substrate has a terminal connection connection portion for electrically connecting an external terminal to the interlayer connection portion, The cross-sectional shape of the terminal connection connection portion is a trapezoid in a cross section parallel to the thickness direction of the metal core layer.

[11] The wired circuit substrate according to any one of [1] to

[10] , wherein the wired circuit substrate comprises: a third insulating layer covering the first wiring layer; and The third wiring layer is arranged on the third insulating layer.

[12] Based on the wiring circuit substrate recorded in any one of [1] to

[11] , the first interlayer connection portion and the second interlayer connection portion are made of different materials in that they contain the same metal as a main component and at least one of the type and content of the auxiliary component is different.

[13] A semiconductor package comprising the wiring circuit substrate described in any one of [1] to

[12] .

[14] An electronic device comprising the semiconductor package described in

[13] .

[15] A method for manufacturing a wiring circuit substrate, for manufacturing the wiring circuit substrate described in any one of [1] to

[12] , comprising: forming a second interlayer connection portion in the through hole of the metal core layer without contacting the metal core layer; A step of forming a second insulating layer having an opening through which at least a portion of the second interlayer connecting portion is exposed on one surface of the metal core layer; and The step of forming a second wiring layer on the second insulating layer and forming a first interlayer connection portion on the second interlayer connection portion.

[16] The method for manufacturing a wired circuit board according to

[15] , wherein the second wiring layer and the first interlayer connection portion are formed integrally. Effects of the Invention

[0009] According to the present invention, it is possible to provide a wired circuit board having excellent flatness while suppressing uneven thickness of an interlayer connection portion, a method for manufacturing the wired circuit board, and a semiconductor package and an electronic device including the wired circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A This is a schematic diagram of one embodiment of a wired circuit board. Figure 1B This is a schematic diagram of one embodiment of a wired circuit board. Figure 2A This is a schematic diagram for explaining one embodiment of a method for manufacturing a wired circuit board (part 1). Figure 2B This is a schematic diagram for explaining one embodiment of a method for manufacturing a wired circuit board (part 2). Figure 2C This is a schematic diagram (part 3) for explaining one embodiment of a method for manufacturing a wired circuit board. Figure 2D This is a schematic diagram (part 4) for explaining one embodiment of a method for manufacturing a wired circuit board. Figure 2E This is a schematic diagram (part 5) for explaining one embodiment of a method for manufacturing a wired circuit board. Figure 2F This is a schematic diagram (part 6) for explaining one embodiment of a method for manufacturing a wired circuit board. Figure 2G This is a schematic diagram for explaining one embodiment of a method for manufacturing a wired circuit board (part 7). Figure 2H This is a schematic diagram (part 8) for explaining one embodiment of a method for manufacturing a wired circuit board. Fig.2I This is a schematic diagram (part 9) for explaining one embodiment of a method for manufacturing a printed circuit board. Figure 3This is a schematic diagram of another embodiment of a wired circuit board. Figure 4A This is a schematic diagram (part 1) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 4B This is a schematic diagram (part 2) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 4C This is a schematic diagram (part 3) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 4D This is a schematic diagram (part 4) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 4E This is a schematic diagram (part 5) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 4F This is a schematic diagram (part 6) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 4G This is a schematic diagram (part 7) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 4H This is a schematic diagram (part 8) for explaining another embodiment of the method for manufacturing a printed circuit board. Fig. 4I This is a schematic diagram (No. 9) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 4J This is a schematic diagram (No. 10 ) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 4K This is a schematic diagram (No. 11) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 4L This is a schematic diagram (No. 12) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 5 This is a schematic diagram of another embodiment of a wired circuit board. Fig. 6A This is a schematic diagram for explaining an example of a conventional method for manufacturing a wired circuit board (part 1). Figure 6B This is a schematic diagram (part 2) for explaining an example of a conventional method for manufacturing a wired circuit board. Figure 6C This is a schematic diagram for explaining an example of a conventional method for manufacturing a wired circuit board (part 3). Fig.6D This is a schematic diagram (part 4) for explaining an example of a conventional method for manufacturing a wired circuit board. DETAILED DESCRIPTION

[0011] (Wired Circuit Board, and Method for Manufacturing the Wired Circuit Board) The wired circuit board of the present invention comprises at least a metal core layer, a first insulating layer, a second insulating layer, a first wiring layer, a second wiring layer, and an interlayer connection portion, and may further comprise other members as necessary. The metal core layer has through holes. The first insulating layer is disposed on one surface of the metal core layer. The second insulating layer is disposed on the other surface of the metal core layer. The first wiring layer is configured on the first insulating layer. The second wiring layer is configured on the second insulating layer. The interlayer connection portion penetrates the through hole, electrically connects the first wiring layer and the second wiring layer, and is not electrically connected to the metal core layer. Furthermore, the interlayer connection portion includes a first interlayer connection portion and a second interlayer connection portion arranged in the thickness direction of the metal core layer. The material of the first interlayer connecting portion is different from the material of the second interlayer connecting portion.

[0012] The thicker the interlayer connection portion is, the more difficult it is to control the thickness, and as a result, the flatness of the wired circuit board is reduced. In the present invention, in the wiring circuit substrate, the interlayer connection portion is not formed in a structure formed at one time, but is divided into a plurality of connection portions arranged in the thickness direction of the metal core layer. Each connection portion is formed separately. As a result, the thickness of each connection portion becomes thinner, and the thickness control becomes easy. As a result, a wiring circuit substrate with excellent flatness and suppressed thickness variation of the interlayer connection portion can be obtained.

[0013] Below, use Figure 1A and Figure 1B An example of the wiring circuit board of the present invention is described. Figure 1B In FIG. 1 , the boundary between the interlayer connection portion 10 (third interlayer connection portion 10c) and the first wiring layer 3, and the boundary between the interlayer connection portion 10 (first interlayer connection portion 10a) and the second wiring layer 6 are shown by dotted lines. Figure 1B and Figure 1A same. Figure 1A and Figure 1B The wiring circuit substrate shown has a metal core layer 1, a first insulating layer 2, a second insulating layer 5, a first wiring layer 3, a second wiring layer 6, and an interlayer connection portion 10. The wiring circuit substrate also has a third insulating layer 7 and a fourth insulating layer 8. The first insulating layer 2 is disposed on one surface of the metal core layer 1 . The second insulating layer 5 is disposed on the other surface of the metal core layer 1 . The first wiring layer 3 is disposed on the first insulating layer 2 . The second wiring layer 6 is arranged on the second insulating layer 5 . The third insulating layer 7 covers the first wiring layer 3 . The fourth insulating layer 8 covers the second wiring layer 6 . The interlayer connection portion 10 passes through the through hole of the metal core layer 1. The interlayer connection portion 10 electrically connects the first wiring layer 3 and the second wiring layer 6. The interlayer connection portion 10 is not electrically connected to the metal core layer 1. Furthermore, the interlayer connection portion 10 includes a first interlayer connection portion 10a and a second interlayer connection portion 10b arranged in the thickness direction of the metal core layer 1. The interlayer connection portion 10 also includes a third interlayer connection portion 10c on the side of the second interlayer connection portion 10b opposite to the first interlayer connection portion 10a. The first interlayer connection portion 10a, the second interlayer connection portion 10b, and the third interlayer connection portion 10c constitute the interlayer connection portion 10, whereby the first wiring layer 3 and the second wiring layer 6 are electrically connected.

[0014] Figure 1B The dotted lines shown are the boundary between the interlayer connection portion 10 (third interlayer connection portion 10c) and the first wiring layer 3, and the boundary between the interlayer connection portion 10 (first interlayer connection portion 10a) and the second wiring layer 6. That is, in the present invention, the interface between the first insulating layer and the first wiring layer is the interface between the interlayer connection portion and the first wiring layer. The interface between the second insulating layer and the second wiring layer is the interface between the interlayer connection portion and the second wiring layer.

[0015] For example, a third wiring layer may be further arranged on the third insulating layer. A fourth wiring layer may be arranged on the fourth insulating layer.

[0016] The metal core layer is, for example, an element for ensuring the rigidity of the printed circuit board. The material of the metal core layer is not particularly limited, and examples thereof include Cu, Cu alloys, Al, stainless steel, FeNi alloys such as 42 alloy, and combinations thereof. Among them, Cu, Cu alloys, and stainless steel are preferred from the viewpoint of thermal conductivity and electrical conductivity. The thickness of the metal core layer is not particularly limited, and is, for example, 10 μm or more, preferably 15 μm or more, and, for example, 500 μm or less, preferably 300 μm or less. In the present invention, "thickness" refers to the length in the thickness direction of the metal core layer. The thickness direction of the metal core layer refers to the direction perpendicular to the surface direction of the metal core layer.

[0017] The material of the insulating layer (e.g., the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer) in the wiring circuit substrate is not particularly limited, and examples thereof include synthetic resins. Examples of synthetic resins include polyimide, polyether nitrile, polyether sulfone, polyethylene terephthalate, polyethylene naphthalate, and polyvinyl chloride. Polyimide is preferred. For example, the insulating layer is formed using photosensitive polyimide. The thickness of the insulating layer is not particularly limited, and is, for example, 1 μm or more, preferably 3 μm or more, and, for example, 35 μm or less, preferably 20 μm or less.

[0018] Examples of materials for the wiring layers (eg, the first wiring layer and the second wiring layer) in the wired circuit board include metal materials, such as copper, nickel, gold, solder, and alloys thereof. The thickness of the wiring layer is not particularly limited, and is, for example, 3 μm or more, preferably 5 μm or more, and, for example, 50 μm or less, preferably 30 μm or less.

[0019] The main component of the interlayer connection portion is not particularly limited, and examples thereof include metal materials. Examples of the metal material include copper, nickel, gold, solder, and alloys thereof. The material of the first interlayer connection part is different from the material of the second interlayer connection part. The material of the second interlayer connection part is preferably different from the material of the third interlayer connection part. The material of the first interlayer connection part and the material of the third interlayer connection part can be the same material or different materials. Here, the different materials include, for example, materials having different kinds of main components, materials having the same kind of main components but different at least one of the kind and content of auxiliary components, and the like. The first interlayer connection portion and the second interlayer connection portion contain, for example, the same metal as a main component, and at least one of the type and content of the subcomponent is different. For example, when the main component of the first interlayer connection portion and the second interlayer connection portion is Cu, and the subcomponents include Cl and S, and the contents of Cl and S are different, the material of the first interlayer connection portion and the material of the second interlayer connection portion are different materials. Table 1 shows an example of the combination of the material of the first interlayer connecting portion and the material of the second interlayer connecting portion.

[0020] [Table 1]

[0021] As a typical example in which the material of the first interlayer connecting portion and the material of the second interlayer connecting portion are different materials, the first interlayer connecting portion and the second interlayer connecting portion are formed using different plating solutions.

[0022] As a further advantage of the material of the first interlayer connection part being different from the material of the second interlayer connection part and / or the material of the third interlayer connection part being different from the material of the second interlayer connection part, the risk of migration can be reduced. For example, in the case of forming the interlayer connection part by plating, when the wiring circuit substrate is used for a medium or long term, the impurities contained in the plating solution may cause migration. In particular, in the through hole of the metal core layer, the thermal expansion coefficient of the insulating part that insulates the metal core layer from the interlayer connection part is greatly different from the thermal expansion coefficient of the interlayer connection part, and the volume of the insulating part is large, so the possibility of peeling of the interlayer connection part and the insulating part caused by a certain amount of impurities migrating to the boundary between the interlayer connection part and the insulating part is large. The plating of each connection part constituting the interlayer connection part is composed of different materials, thereby, the impurities contained in each plated part can be made different, so the risk of migration can be reduced.

[0023] exist Figure 1A and Figure 1B In the interlayer connection portion 10 of the wired circuit board shown, the second interlayer connection portion 10 b is arranged at a position closer to the center of the through hole in the thickness direction of the metal core layer 1 than the first interlayer connection portion 10 a. In this case, the relationship between the thickness of the second interlayer connecting portion and the thickness of the first interlayer connecting portion is not particularly limited, and the thickness of the second interlayer connecting portion may be thicker or thinner than the thickness of the first interlayer connecting portion. It is sometimes preferable that the second interlayer connection portion be thicker than the first interlayer connection portion because by making the first interlayer connection portion relatively thin, technically difficult via filling can be avoided and interlayer connection can be easily performed.

[0024] In addition, Figure 1A and Figure 1B In the interlayer connection portion 10 of the illustrated wired circuit board, the second interlayer connection portion 10 b is arranged at a position closer to the center of the through hole in the thickness direction of the metal core layer 1 than the third interlayer connection portion 10 c. In this case, the relationship between the thickness of the second interlayer connecting portion and the thickness of the third interlayer connecting portion is not particularly limited, and the thickness of the second interlayer connecting portion may be thicker or thinner than the thickness of the third interlayer connecting portion. It is sometimes preferable that the second interlayer connection portion be thicker than the third interlayer connection portion because by making the third interlayer connection portion relatively thin, technically difficult via filling can be avoided and interlayer connection can be easily performed.

[0025] The thickness of the second interlayer connecting portion is not particularly limited, but is preferably 60% to 140% of the thickness of the metal core layer. The thickness of the second interlayer connection portion disposed on the center side of the through hole in the thickness direction of the metal core layer is close to the thickness of the metal core layer, which is advantageous in maintaining the rigidity of the wired circuit board and suppressing warpage.

[0026] There is no particular limitation on the shape of the through hole in the metal core layer. The shape of the through hole in the metal core layer is preferably a tapered shape, thereby increasing the degree of freedom in designing the through hole. In the present invention, the tapered shape refers to a shape in which the opening of one side of the through hole is larger than the opening of the other side. Therefore, when the through hole is tapered, the side shape of the through hole in the cross section parallel to the thickness direction of the metal core layer is, for example, a trapezoid.

[0027] There is no particular limitation on the side surface shape of the through hole in the metal core layer. The side shape of the through hole in the metal core layer may be an arc shape or a straight line shape in a cross section parallel to the thickness direction of the metal core layer. The arc shape here refers to a shape that is recessed from the through-hole side toward the metal core layer side. If the shape is an arc, the close contact between the insulating portion and the metal core layer can be improved. The insulating portion is located between the metal core layer and the interlayer connecting portion and realizes electrical insulation between the metal core layer and the interlayer connecting portion. If the shape is a straight line, it becomes easy to form a seed layer when forming an interlayer connection portion (particularly a second interlayer connection portion) when manufacturing a wired circuit board.

[0028] There is no particular limitation on the shape of the second interlayer connecting portion. The cross-sectional shape of the second interlayer connecting portion is not particularly limited, and may be, for example, a rectangular shape or a trapezoidal shape in a cross section parallel to the thickness direction of the metal core layer.

[0029] The cross-sectional shape of the first interlayer connection portion is not particularly limited, and for example, in a cross section parallel to the thickness direction of the metal core layer, it may be a rectangle or a trapezoid. As a trapezoid, a trapezoid having the second interlayer connection portion side as the upper base and the opposite side as the lower base may be cited. The cross-sectional shape of the third interlayer connection portion is not particularly limited, and for example, in a cross section parallel to the thickness direction of the metal core layer, it may be a rectangle or a trapezoid. As a trapezoid, a trapezoid having the second interlayer connection portion side as the upper base and the opposite side as the lower base may be cited.

[0030] It is preferable that the contact area between the third interlayer connection portion and the second interlayer connection portion is larger than the contact area between the first interlayer connection portion and the second interlayer connection portion.

[0031] The wired circuit board may include a connection portion for connecting terminals. The terminal-connecting connection portion is a connection portion for electrically connecting an external terminal to an interlayer connection portion of the wired circuit board. The cross-sectional shape of the terminal connection connection portion is not particularly limited, and may be, for example, a rectangular shape in a cross section parallel to the thickness direction of the metal core layer.

[0032] The wired circuit board may include a seed layer (not shown). The seed layer is used as a conductive layer for electrolytic plating. Examples of the material of the seed layer include copper, chromium, nickel, and alloys thereof.

[0033] The method for producing a wired circuit board of the present invention includes the following steps. · A step of forming a second interlayer connection portion in the through hole of the metal core layer without contacting the metal core layer A step of forming a second insulating layer having an opening through which at least a portion of the second interlayer connection portion is exposed on one surface of the metal core layer. A step of forming a second wiring layer on the second insulating layer and forming a first interlayer connection portion on the second interlayer connection portion The method for producing the wired circuit board of the present invention is a method for producing the wired circuit board of the present invention.

[0034] use Figure 2A to Figure 2H right Figure 1A and Figure 1B An embodiment of a method for manufacturing a wired circuit board shown in FIG. 1 will be described. First, prepare the metal core layer 1 ( Figure 2A ).

[0035] Next, a first insulating layer 2 ( Figure 2B ) The first insulating layer 2 can be formed by, for example, applying a photosensitive resin composition containing a photosensitive polyimide and drying it.

[0036] Next, the first insulating layer 2 is processed into a pattern so as to have an opening 2a ( Figure 2C ) The pattern-shaped processing can be performed, for example, by selective exposure and development of the formed photosensitive polyimide film.

[0037] Next, a patterned first wiring layer 3 is formed on the first insulating layer 2, and a third interlayer connection portion 10c ( Figure 2D ) The first wiring layer 3 and the third interlayer connection portion 10c can be formed, for example, as follows. Forming a seed layer (not shown) on the first insulating layer 2 Forming a photoresist film on the seed layer (not shown) · Forming a resist pattern by selective exposure and development of the photoresist film (partial exposure of the seed layer) Electrolytic plating of the exposed seed layer ·Remove photoresist film and remove unnecessary seed layer The formed patterned electrolytic plating layer becomes the first wiring layer 3 . Through the above steps, the patterned first wiring layer 3 is formed. Furthermore, the third interlayer connection portion 10c is formed by performing electrolytic plating to fill the opening 2a of the first insulating layer 2. That is, the first wiring layer 3 and the third interlayer connection portion 10c are formed integrally.

[0038] Next, a through hole 4 is formed in the metal core layer 1 so that the entire surface of the third interlayer connection portion 10c on the metal core layer 1 side is exposed ( Figure 2E ) The through hole 4 can be formed, for example, as follows. Forming a photoresist film on the metal core layer 1 (not shown) · Forming a resist pattern (partial exposure of the metal core layer 1) by selective exposure and development of the photoresist film Wet etching of the exposed metal core layer 1 (for example, wet etching using ferric chloride) ·Remove photoresist film Through the above steps, the through hole 4 is formed.

[0039] Next, the second interlayer connection portion 10b is formed in the through hole 4 so as not to contact the metal core layer 1 but to contact the third interlayer connection portion 10c. Figure 2F ). For example, the second interlayer connection portion 10b is formed so as to be in contact with a portion of the surface of the third interlayer connection portion 10c on the side of the metal core layer 1. The second interlayer connection portion 10b can be formed, for example, as follows. Forming a photoresist film on the metal core layer 1 (not shown) · Forming a resist pattern (exposing the third interlayer connection portion 10c) by selective exposure and development of the photoresist film · Plating on the exposed third interlayer connection portion 10c ·Remove photoresist film Through the above steps, the second interlayer connection portion 10 b is formed.

[0040] Next, a second insulating layer 5 ( 10a ) having an opening 5a through which the second interlayer connecting portion 10b is exposed is formed on the metal core layer 1. Figure 2GFor example, the opening 5a is formed so as to expose a portion of the surface of the second interlayer connection portion 10b on the side opposite to the third interlayer connection portion 10c. The second insulating layer 5 having the opening 5a can be formed, for example, as follows. · Forming a photosensitive polyimide film by coating a photosensitive resin composition containing a photosensitive polyimide and drying it The opening 5a is formed by selective exposure and development of the photosensitive polyimide film

[0041] Next, a patterned second wiring layer 6 is formed on the second insulating layer 5, and a first interlayer connection portion 10a ( Figure 2H ) The second wiring layer 6 and the first interlayer connection portion 10a can be formed, for example, as follows. Forming a seed layer (not shown) on the second insulating layer 5 Forming a photoresist film on the seed layer (not shown) · Forming a resist pattern by selective exposure and development of the photoresist film (partial exposure of the seed layer) Electrolytic plating of the exposed seed layer ·Remove photoresist film and remove unnecessary seed layer The formed patterned electrolytic plating layer becomes the second wiring layer 6 . Through the above steps, the second wiring layer 6 is formed. Furthermore, the first interlayer connection portion 10a is formed by performing electrolytic plating to fill the opening portion 5a of the second insulating layer 5. That is, the second wiring layer 6 and the first interlayer connection portion 10a are formed integrally.

[0042] Next, a third insulating layer 7 is formed so as to cover the first wiring layer 3, and a fourth insulating layer 8 is formed so as to cover the second wiring layer 6 ( Fig.2I ) The third insulating layer 7 and the fourth insulating layer 8 can be formed by, for example, applying a photosensitive resin composition containing a photosensitive polyimide and drying it. Through the above steps, we can get Fig.2I ( Figure 1A and Figure 1B ) shown in the wiring circuit substrate.

[0043] Fig.2I The wiring circuit board shown may be further processed so that, for example, a terminal connection connection portion for electrically connecting an external terminal to the interlayer connection portion 10 is provided on the wiring circuit board.

[0044] Figure 3 FIG. 1 is a schematic diagram of another embodiment of a wiring circuit substrate. Figure 3In the embodiment, the cross-sectional shape of the first interlayer connection portion 10a is a rectangle in the cross section parallel to the thickness direction of the metal core layer 1. Figure 1A and Figure 1B The wiring circuit substrates shown are the same.

[0045] use Figure 4A to Figure 4L Another embodiment of the method for manufacturing a printed circuit board will be described. First, prepare the metal core layer 51 ( Figure 4A ).

[0046] Next, a first insulating layer 52 ( Figure 4B ) The first insulating layer 52 having the opening 52a can be formed, for example, as follows. · Applying a photosensitive resin composition containing a photosensitive polyimide and drying it ·Selective exposure and development of the formed photosensitive polyimide film

[0047] Next, a patterned first wiring layer 53 is formed on the first insulating layer 52, and a third interlayer connection portion 70c ( Figure 4C ) The first wiring layer 53 and the third interlayer connection portion 70c can be formed, for example, as follows. Forming a seed layer (not shown) on the first insulating layer 52 Forming a photoresist film on the seed layer (not shown) · Forming a resist pattern by selective exposure and development of the photoresist film (partial exposure of the seed layer) Electrolytic plating of the exposed seed layer ·Remove photoresist film and remove unnecessary seed layer The formed patterned electrolytic plating layer becomes the first wiring layer 53 . Through the above steps, the patterned first wiring layer 53 is formed. Furthermore, the third interlayer connection portion 70c is formed by performing electrolytic plating to fill the opening 52a of the first insulating layer 52. That is, the first wiring layer 53 and the third interlayer connection portion 70c are formed integrally.

[0048] Next, a patterned third insulating layer 54 ( Figure 4D The patterned third insulating layer 54 can be formed, for example, by applying a photosensitive resin composition containing a photosensitive polyimide, drying it, and selectively exposing and developing the formed photosensitive polyimide film.

[0049] Next, a third wiring layer 55 is formed on the patterned third insulating layer 54 ( Figure 4E ). At least a portion of the third wiring layer 55 is electrically connected to the first wiring layer 53. The third wiring layer 55 can be formed, for example, as follows. A seed layer (not shown) is formed on the third insulating layer 54 and the exposed first wiring layer 53. Forming a photoresist film on the seed layer (not shown) · Forming a resist pattern by selective exposure and development of the photoresist film (partial exposure of the seed layer) Electrolytic plating of the exposed seed layer ·Remove photoresist film and remove unnecessary seed layer The formed patterned electrolytic plating layer becomes the third wiring layer 55 . Through the above steps, the third wiring layer 55 is formed in a pattern.

[0050] Next, a patterned fourth insulating layer 56 ( Figure 4F The patterned fourth insulating layer 56 can be formed, for example, by applying a photosensitive resin composition containing a photosensitive polyimide, drying the composition, and selectively exposing and developing the formed photosensitive polyimide film.

[0051] Next, a through hole 57 ( Figure 4G ) The through hole 57 can be formed, for example, as follows. Forming a photoresist film (not shown) on the metal core layer 51 · Forming a resist pattern (partial exposure of the metal core layer 51) by selective exposure and development of the photoresist film Wet etching of the exposed metal core layer 51 (for example, wet etching using ferric chloride) ·Remove photoresist film Through the above steps, the through hole 57 is formed.

[0052] Next, the second interlayer connection portion 70b is formed in the through hole 57 so as not to contact the metal core layer 51 but to contact the third interlayer connection portion 70c. Figure 4H ). For example, the second interlayer connection portion 10b is formed so as to be in contact with the entire surface of the third interlayer connection portion 10c on the side of the metal core layer 1. The second interlayer connection portion 70b can be formed, for example, as follows. Forming a photoresist film (not shown) on the metal core layer 51 Formation of a resist pattern by selective exposure and development of the photoresist film (exposure of the third interlayer connection portion 70c) Plating on the exposed third interlayer connection portion 70c ·Remove photoresist film Through the above steps, the second interlayer connection portion 70 b is formed.

[0053] Next, a second insulating layer 58 ( 58b ) having an opening 58a through which the second interlayer connecting portion 70b is exposed is formed on the metal core layer 51. Fig. 4I For example, the opening 58a is formed so as to expose a portion of the surface of the second interlayer connection portion 70b on the side opposite to the third interlayer connection portion 70c. The second insulating layer 58 having the opening 58a can be formed, for example, as follows. The second insulating layer 58 is formed by applying a photosensitive resin composition containing a photosensitive polyimide and drying it. The opening 58a is formed by selectively exposing and developing the formed photosensitive polyimide film.

[0054] Next, a patterned second wiring layer 59 is formed on the second insulating layer 58, and a first interlayer connection portion 70a ( ) is formed on the second interlayer connection portion 70b exposed through the opening 58a. Figure 4J ) The second wiring layer 59 and the first interlayer connection portion 70a can be formed, for example, as follows. Forming a seed layer (not shown) on the second insulating layer 58 Forming a photoresist film on the seed layer (not shown) · Forming a resist pattern by selectively exposing and developing the photoresist film (partial exposure of the seed layer) Electrolytic plating of the exposed seed layer ·Remove photoresist film and remove unnecessary seed layer The formed patterned electrolytic plating layer becomes the second wiring layer 59 . Through the above steps, the second wiring layer 59 is formed. Furthermore, the first interlayer connection portion 70a is formed by performing electrolytic plating to fill the opening portion 58a of the second insulating layer 58. That is, the second wiring layer 59 and the first interlayer connection portion 70a are formed integrally.

[0055] Next, a connection portion 60 ( Figure 4K ) The connection portion 60 can be formed, for example, as follows. Forming a photoresist film (not shown) on the second wiring layer 59 · Formation of a resist pattern (partial exposure of the second wiring layer 59) by selective exposure and development of the photoresist film · The exposed second wiring layer 59 is electroplated

[0056] Next, a patterned fourth insulating layer 61 ( ) is formed between wirings of the second wiring layer 59, on the second wiring layer 59, and on a portion of the connection portion 60 so that a portion of the connection portion 60 is exposed. Figure 4L The patterned fourth insulating layer 61 can be formed, for example, by applying a photosensitive resin composition containing a photosensitive polyimide, drying the composition, and selectively exposing and developing the formed photosensitive polyimide film. Through the above steps, we can get Figure 4L and Figure 5 The wiring circuit substrate shown. It should be noted that Figure 5 In the wiring circuit substrate shown in FIG. 1 , the boundary between the interlayer connection portion 70 (third interlayer connection portion 70c) and the first wiring layer 53 and the boundary between the interlayer connection portion 70 (first interlayer connection portion 70a) and the second wiring layer 59 are shown by dotted lines. Figure 5 and Figure 4L same.

[0057] (Semiconductor Package) The semiconductor package of the present invention includes the wiring circuit substrate of the present invention. The semiconductor package includes, for example, a semiconductor chip connected to a wiring circuit board. The semiconductor package includes, for example, a sealing resin that seals a semiconductor chip. Examples of semiconductor packages include FC-CSP (Flip Chip-Chip Scale Package), MIS-BGA (Molded Interconnect Substrate-Ball Grid Array) packages, ETS-BGA (Embedded Trace Substrate-Ball Grid Array) packages, Fan-out WLP (Wafer Level Package), Fan-in WLP, Fan-out PLP (Panel Level Package), Fan-in PLP, FC-BGA (Flip Chip-Chip, -Ball Grid Array), high-end 2.5D and 3D packages, and the like.

[0058] (Electronic equipment) The electronic device of the present invention includes the semiconductor package of the present invention. There are no particular restrictions on electronic devices, and examples include: ICT infrastructure equipment such as servers, routers, supercomputers, mainframes, and workstations; antennas such as GPS antennas, antennas for wireless base stations, millimeter wave antennas, and RFID antennas; communication equipment such as portable phones, smart phones, PHS, PDAs, and tablet terminals; digital devices such as personal computers, televisions, digital cameras, digital video cameras, POS terminals, wearable terminals, and digital media players; in-vehicle electronic equipment such as electronic control system devices, in-vehicle communication equipment, car navigation equipment, millimeter wave radars, and in-vehicle camera modules; semiconductor testing equipment, high-frequency measuring equipment, etc. Explanation of symbols

[0059] 1: Metal core layer 2: First insulation layer 2a: Opening 3: First wiring layer 4: Through hole 5: Second insulation layer 5a: Opening 6: Second wiring layer 7: The third insulation layer 8: The fourth insulation layer 10: Interlayer connection 10a: First interlayer connection portion 10b: Second interlayer connection portion 10c: Third interlayer connection 51: Metal core layer 52: First insulation layer 52a: Opening 53: First wiring layer 54: The third insulation layer 55: The third wiring layer 56: Fourth insulation layer 57: Through hole 58: Second insulation layer 58a: Opening 59: Second wiring layer 60: Connection 70: Interlayer connection 70a: First interlayer connection portion 70b: Second interlayer connection portion 70c: Third interlayer connection portion.

Claims

1. A wiring circuit substrate, comprising: a metal core layer having through holes; A first insulating layer, which is disposed on one surface of the metal core layer; A second insulating layer, which is disposed on the other surface of the metal core layer; A first wiring layer, which is arranged on the first insulating layer; A second wiring layer, which is arranged on the second insulating layer; as well as an interlayer connection portion that passes through the through hole of the metal core layer, electrically connects the first wiring layer to the second wiring layer, and is not electrically connected to the metal core layer, The interlayer connection portion includes a first interlayer connection portion and a second interlayer connection portion arranged in a thickness direction of the metal core layer, A material of the first interlayer connection portion is different from a material of the second interlayer connection portion.

2. The wiring circuit substrate according to claim 1, wherein In the interlayer connection portion, the second interlayer connection portion is arranged at a position closer to the center of the through hole in the thickness direction of the metal core layer than the first interlayer connection portion. The second interlayer connecting portion has a thickness greater than that of the first interlayer connecting portion.

3. The wired circuit substrate according to claim 1, wherein: The through hole in the metal core layer has a tapered shape.

4. The wired circuit substrate according to claim 1, wherein: The side surface shape of the through hole at the metal core layer is an arc shape in a cross section parallel to the thickness direction of the metal core layer.

5. The wired circuit substrate according to claim 1, wherein: The side surface shape of the through hole at the metal core layer is a straight line in a cross section parallel to the thickness direction of the metal core layer.

6. The wired circuit substrate according to claim 1, wherein: In the interlayer connection portion, the second interlayer connection portion is arranged at a position closer to the center of the through hole in the thickness direction of the metal core layer than the first interlayer connection portion. The thickness of the second interlayer connecting portion is 60% to 140% of the thickness of the metal core layer.

7. The wired circuit substrate according to claim 1, wherein: The cross-sectional shape of the first interlayer connecting portion is a rectangle in a cross section parallel to a thickness direction of the metal core layer.

8. The wired circuit substrate according to claim 1, wherein: The cross-sectional shape of the first interlayer connecting portion is a trapezoid in a cross section parallel to a thickness direction of the metal core layer.

9. The wired circuit substrate according to claim 1, wherein: The wiring circuit substrate has a terminal connection connection portion for electrically connecting an external terminal to the interlayer connection portion. The cross-sectional shape of the terminal connection connection portion is rectangular in a cross section parallel to the thickness direction of the metal core layer.

10. The wired circuit substrate according to claim 1, wherein The wiring circuit substrate has a terminal connection connection portion for electrically connecting an external terminal to the interlayer connection portion. The cross-sectional shape of the terminal connection connection portion is a trapezoid in a cross section parallel to the thickness direction of the metal core layer.

11. The wired circuit substrate according to claim 1, wherein: The wiring circuit substrate comprises: a third insulating layer covering the first wiring layer; and The third wiring layer is arranged on the third insulating layer.

12. The wired circuit substrate according to claim 1, wherein: The material of the first interlayer connecting portion and the material of the second interlayer connecting portion are different in that they contain the same metal as a main component and at least one of the type and content of the subcomponent is different.

13. A semiconductor package, A wiring circuit substrate comprising the wiring circuit substrate according to any one of claims 1 to 12.

14. An electronic device, The semiconductor package comprises the semiconductor package as claimed in claim 13.

15. A method for manufacturing a wiring circuit substrate, for manufacturing the wiring circuit substrate according to any one of claims 1 to 12, the method for manufacturing the wiring circuit substrate comprising: forming a second interlayer connection portion in the through hole of the metal core layer without contacting the metal core layer; A step of forming a second insulating layer having an opening through which at least a portion of the second interlayer connecting portion is exposed on one surface of the metal core layer; and A step of forming a second wiring layer on the second insulating layer and forming a first interlayer connection portion on the second interlayer connection portion.

16. The method for manufacturing a wired circuit board according to claim 15, wherein: The second wiring layer is formed integrally with the first interlayer connection portion.

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