Silicon capacitor and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor capacitors, and particularly relates to a silicon capacitor and a preparation method thereof. The silicon capacitor provided by the invention comprises a silicon substrate, the upper surface of the silicon substrate is provided with a plurality of repeatedly arranged structural units, each structure is at least divided into two areas, and the upper surface of the silicon substrate in each area is provided with strip-shaped columns which are transversely or longitudinally arranged in an array. The arrangement directions of the strip-shaped stand columns in any adjacent areas are perpendicular to each other, and the ends of the strip-shaped stand columns on the outermost side in any area are connected with the adjacent ends of the strip-shaped stand columns on the outermost side in the adjacent areas. According to the silicon capacitor, the etching morphology of the strip-shaped stand columns and the filling morphology of the conducting layers are optimized, the electrical performance, the capacity density, the reliability and the integration degree of the capacitor are improved, and therefore the silicon capacitor can replace a traditional chip capacitor to be applied to a high-frequency and high-speed circuit, is compatible with an existing microelectronic technology and is good in expansibility.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor capacitors, and in particular relates to a silicon capacitor and a preparation method thereof. Background Art

[0002] Capacitors are widely used in electronic circuits, and their capacity and size are constantly evolving with the needs of actual scenarios. Capacitors with higher capacity can store more energy during the filtering process, making the output signal smoother and reducing the high-frequency components in the signal. In pursuit of large capacity, many new packaging technologies and capacitor integration methods have been developed, such as placing enough capacitors in parallel for wiring. However, the parasitic resistance and inductance caused by the wiring and the impedance effect of the capacitor itself will limit its application at high frequencies.

[0003] 3D silicon-based capacitors developed in recent years are manufactured on silicon substrates using micro-nano processes. They have attracted much attention for their ultra-stability and high capacitance density. 3D silicon-based capacitors use deep silicon etching technology to form grooves with a high aspect ratio on the silicon substrate, thereby increasing the electrode alignment area and achieving high capacitance density.

[0004] However, deep trench 3D silicon-based capacitor devices have low reliability and low yield due to stress during etching and deposition processes. Summary of the invention

[0005] The object of the present invention is to provide a silicon capacitor and a preparation method thereof. The silicon capacitor provided by the present invention has high electrical performance, capacity density, reliability, yield rate and integration. The silicon capacitor provided by the present invention can replace traditional chip capacitors and be applied in high-frequency and high-speed circuits. It is compatible with existing microelectronic processes and has good scalability.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] The present invention provides a silicon capacitor, comprising a silicon substrate, wherein a plurality of repeatedly arranged structural units are arranged on the upper surface of the silicon substrate;

[0008] Each structural unit is divided into at least two regions, and the upper surface of the silicon substrate in each region is provided with strip columns arranged in a horizontal or vertical array, and the gaps between any adjacent strip columns in the same region form grooves, and the arrangement directions of the strip columns in any adjacent regions are perpendicular to each other, and the ends of the outermost strip columns in any region are connected to the adjacent ends of the outermost strip columns in the adjacent region;

[0009] A dielectric layer covering the upper surface of the strip-shaped pillars, the sidewalls of the strip-shaped pillars and the upper surface of the silicon substrate between any adjacent strip-shaped pillars;

[0010] A conductive layer covering the upper surface of the dielectric layer, wherein the conductive layer fills the gaps between any adjacent strip-shaped columns;

[0011] an upper electrode located on the upper surface of the conductive layer;

[0012] A lower electrode is located on the lower surface of the silicon substrate.

[0013] Preferably, the structural unit is divided into four areas: upper left, upper right, lower left and lower right; the strip columns in the upper left area are arranged horizontally, the strip columns in the upper right area are arranged vertically, the strip columns in the lower left area are arranged vertically, and the strip columns in the lower right area are arranged horizontally;

[0014] The right end of the strip column located at the lowermost edge in the upper left area, the lower end of the strip column located at the leftmost edge in the upper right area, the upper end of the strip column located at the rightmost edge in the lower left area, and the left end of the strip column located at the uppermost edge in the lower right area are connected together to form a solid integrated structure.

[0015] Preferably, in the same area: the ratio of the height of the strip pillars to the width of the interval between any adjacent strip pillars is greater than 10:1;

[0016] The heights of the strip columns in different areas are equal, and the interval widths between any adjacent strip columns in different areas are equal.

[0017] Preferably, in the same area: the height of the strip-shaped columns is 20-200 μm.

[0018] Preferably, in the same area: the spacing width between any adjacent strip-shaped columns is 1-4 μm.

[0019] Preferably, the material of the strip pillars is the same as that of the silicon substrate, the silicon substrate is N-type doped or P-type doped, and the resistivity of the silicon substrate is less than 0.01Ω·cm; the sum of the height of the strip pillars and the thickness of the silicon substrate is 100-500μm.

[0020] Preferably, the dielectric layer includes at least two of a silicon oxide film, a silicon nitride film, an aluminum oxide film and a hafnium oxide film;

[0021] The total thickness of the dielectric layer is 10 nm to 1.5 μm.

[0022] Preferably, the material of the conductive layer includes polysilicon doped with phosphorus impurities and / or metal tungsten, and the resistivity of the conductive layer is less than 0.003Ω·cm;

[0023] The thickness of the conductive layer located above the strip-shaped pillars is 300-3 μm.

[0024] Preferably, the thickness of the upper electrode and the lower electrode are independently 300 nm to 10 μm.

[0025] The present invention provides a method for preparing the silicon capacitor described in the above technical solution, comprising the following steps:

[0026] Performing photolithography and etching on the upper surface of the silicon material to obtain a silicon substrate having strip-shaped columns on the upper surface;

[0027] Prepare a dielectric layer on the upper surface of the strip-shaped pillars, the sidewalls of the strip-shaped pillars and the upper surface of the silicon substrate between any adjacent strip-shaped pillars;

[0028] Preparing a conductive layer on the upper surface of the dielectric layer;

[0029] Preparing an upper electrode on the upper surface of the conductive layer;

[0030] A lower electrode is prepared on the lower surface of the silicon substrate to obtain the silicon capacitor.

[0031] The present invention provides a silicon capacitor, comprising a silicon substrate, wherein the upper surface of the silicon substrate is provided with a plurality of repeatedly arranged structural units; each structural unit is divided into at least two regions, the upper surface of the silicon substrate in each region is provided with strip columns arranged in a horizontal or vertical array, the gaps between any adjacent strip columns in the same region form grooves, the arrangement directions of the strip columns in any adjacent regions are perpendicular to each other, the ends of the outermost strip columns in any region are connected to the adjacent ends of the outermost strip columns in the adjacent regions; a dielectric layer covering the upper surface of the strip columns, the side walls of the strip columns and the upper surface of the silicon substrate between any adjacent strip columns; a conductive layer covering the upper surface of the dielectric layer, and the conductive layer fills the gaps between any adjacent strip columns; an upper electrode located on the upper surface of the conductive layer; and a lower electrode located on the lower surface of the silicon substrate. The silicon capacitor provided by the present invention forms a groove structure on the upper surface of the silicon substrate through strip columns, so that when the size of the silicon capacitor remains unchanged, the surface area of ​​the dielectric layer is increased by introducing the Y-axis direction, so that the capacity is increased by 1 to 2 orders of magnitude, and the parasitic effect is greatly reduced compared with multiple capacitor connections, and the capacity temperature stability and high-frequency application are significantly better than traditional multilayer ceramic capacitors (MLCC); at the same time, the present invention divides the upper surface of the silicon substrate into zones, and the strip columns in different zones are arranged alternately horizontally and vertically to form an array, which can effectively reduce the stress effect generated by the etching and deposition process, effectively avoid chip cracking, and the silicon capacitor has a high yield rate; at the same time, when the present invention arranges the strip columns alternately horizontally and vertically in different zones, the end of the outermost strip column in any zone is limited to be connected to the adjacent end of the outermost strip column in the adjacent zone, that is, the two strip columns located at the edge of any zone are connected to one end or both ends of the edge strip column in the adjacent zone, which can effectively eliminate the situation that the conductive layer is not fully filled in the gap of the strip columns, thereby improving the reliability of the silicon capacitor. In summary, the silicon capacitor provided by the present invention optimizes the etching morphology of the strip columns (i.e., grooves) and the filling morphology of the conductive layer, thereby improving the electrical performance, capacity density, reliability and integration of the capacitor. Therefore, the silicon capacitor provided by the present invention can replace traditional chip capacitors and be used in high-frequency and high-speed circuits. It is compatible with existing microelectronic processes and has good scalability.

[0032] Furthermore, in the present invention, the heights of the strip columns in different regions are equal, and the spacing widths between any adjacent strip columns in different regions are equal. The silicon capacitor structure provided by the present invention designs the height and spacing width of the strip column patterns to be etched in different regions to be of consistent size, so that the strip column height after etching can be consistent, the groove depth obtained is uniform, and the bottom morphology is flat, thereby effectively improving the capacitance value accuracy and electrical breakdown strength of the silicon capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0034] Figure 1 A schematic diagram of the structure of a silicon capacitor provided by the present invention;

[0035] Figure 2 A top view of a structural unit of a silicon capacitor provided by the present invention;

[0036] Figure 3 The actual photos of the chip samples prepared in Example 1 and Comparative Example 1;

[0037] Figure 4 This is a characterization diagram of the performance test results of the device prepared in Example 1 of the present invention;

[0038] In the figure: 1 is a silicon substrate, 21 is a first dielectric layer, 22 is a second dielectric layer, 23 is a third dielectric layer, 3 is a conductive layer, 4 is a structural unit, 5 is a strip column, 6 is a groove, 7 is an end connection position, 8 is an upper electrode, and 9 is a lower electrode. DETAILED DESCRIPTION

[0039] The present invention provides a silicon capacitor, comprising a silicon substrate, wherein a plurality of repeatedly arranged structural units are arranged on the upper surface of the silicon substrate;

[0040] Each structural unit is divided into at least two regions, and the upper surface of the silicon substrate in each region is provided with strip columns arranged in a horizontal or vertical array, and the gaps between any adjacent strip columns in the same region form grooves, and the arrangement directions of the strip columns in any adjacent regions are perpendicular to each other, and the ends of the outermost strip columns in any region are connected to the adjacent ends of the outermost strip columns in the adjacent region;

[0041] A dielectric layer covering the upper surface of the strip-shaped pillars, the sidewalls of the strip-shaped pillars and the upper surface of the silicon substrate between any adjacent strip-shaped pillars;

[0042] A conductive layer covering the upper surface of the dielectric layer, wherein the conductive layer fills the gaps between any adjacent strip-shaped columns;

[0043] an upper electrode located on the upper surface of the conductive layer;

[0044] A lower electrode is located on the lower surface of the silicon substrate.

[0045] In the present invention, unless otherwise specified, all preparation raw materials / components are commercially available products well known to those skilled in the art.

[0046] Figure 1 A schematic diagram of the structure of a silicon capacitor provided by the present invention; Figure 2 A top view of a structural unit of a silicon capacitor provided by the present invention is shown below in conjunction with Figure 1 and Figure 2 , the structure of the silicon capacitor provided by the present invention is described in detail.

[0047] The silicon capacitor provided by the present invention comprises a silicon substrate 1. In the present invention, a plurality of repeatedly arranged structural units 4 are arranged on the upper surface of the silicon substrate. The structural units 4 are repeated or the structural units 4 are repeatedly scaled to form an effective area of ​​the silicon capacitor. In the present invention, the heights of the strip columns 5 in each structural unit 4 in the effective area of ​​the silicon capacitor are preferably equal, and the width intervals of adjacent strip columns 5 in each structural unit 4 in the effective area of ​​the silicon capacitor are preferably equal.

[0048] In the present invention, each structural unit 4 is divided into at least two regions, and the upper surface of the silicon substrate in each region is provided with strip columns 5 arranged in a horizontal or vertical array, and the gaps between any adjacent strip columns 5 in the same region form grooves 6, and the arrangement directions of the strip columns 5 in any adjacent regions are perpendicular to each other, and the ends of the outermost strip columns in any region are connected to the adjacent ends of the outermost strip columns in the adjacent region. That is, the ends of the outermost strip columns in any region and the adjacent ends of the outermost strip columns in the adjacent region form an integrated structure.

[0049] In the present invention, the silicon substrate 1 is low-resistance silicon. The silicon substrate 1 is preferably N-type doped or P-type doped, and the resistivity of the silicon substrate 1 is preferably <0.01Ω·cm.

[0050] like Figure 2As shown, as one or more embodiments of the present invention, a structural unit 4 is divided into four regions: upper left, upper right, lower left and lower right; the strip columns in the upper left region are arranged horizontally, the strip columns in the upper right region are arranged vertically, the strip columns in the lower left region are arranged vertically, and the strip columns in the lower right region are arranged horizontally. The silicon capacitor provided by the present invention forms an array by arranging the strip columns alternately horizontally and vertically through the pattern design of the divided regions in the structural unit, which can effectively reduce the stress effects generated by the etching and deposition processes. The right end of the strip column at the bottom edge in the upper left region, the lower end of the strip column at the leftmost edge in the upper right region, the upper end of the strip column at the rightmost edge in the lower left region, and the left end of the strip column at the top edge in the lower right region are connected together to form a solid integrated structure (such as Figure 2 The silicon capacitor provided by the present invention can eliminate the situation where the subsequent conductive layer is not fully filled due to the large CD by designing the long strip structure at the intersection of different regions in the structural unit.

[0051] In the present invention, the minimum CD is the spacing distance between any adjacent strip columns in each region. However, when the upper surface of the silicon substrate 1 in the structural unit 4 is divided into four regions: upper left, upper right, lower left and lower right, the center positions of the four regions, upper left, upper right, lower left and lower right, need to be filled as a square composed of the middle grooves ( Figure 2 The filling process limit is calculated according to the CD with the farthest diagonal of the square at the center position and the end connection position 7).

[0052] In the present invention, in the same area: the ratio of the height of the strip pillars to the width of the interval between any adjacent strip pillars is preferably greater than 10:1, preferably (20-150): 1. The present invention can effectively achieve a high capacitance density of the silicon capacitor by controlling the ratio of the height of the strip pillars to the width of the interval between any adjacent strip pillars to preferably greater than 10:1.

[0053] In the present invention, the heights of the strip columns in different regions are preferably equal, and the spacing widths between any adjacent strip columns in different regions are preferably equal. The present invention designs the heights of the strip columns in different regions and the spacing widths between any adjacent strip columns in different regions to be equal, which can achieve the effect of uniform groove depth and flat bottom morphology between the strip columns after etching, thereby effectively improving the capacitance value accuracy and electrical breakdown strength.

[0054] In the present invention, in the same area: the height of the strip-shaped pillars is preferably 20 to 200 μm.

[0055] In the present invention, in the same region, the spacing width between any adjacent strip-shaped columns is preferably 1 to 4 μm.

[0056] In the present invention, the material of the strip-shaped pillars is the same as that of the silicon substrate.

[0057] In the present invention, the sum of the height of the strip-shaped pillars and the thickness of the silicon substrate is preferably 100-500 μm.

[0058] In the present invention, the structural unit 4 includes a dielectric layer covering the upper surface of the strip pillars 5, the sidewalls of the strip pillars 5 and the upper surface of the silicon substrate 1 between any adjacent strip pillars 5. In the present invention, the dielectric layer simultaneously covers the upper surface of the strip pillars 5, including the upper surface of the integral structure formed by the end of the outermost strip pillar in any region and the adjacent end of the outermost strip pillar in the adjacent region, such as Figure 2 The end portion in the connection position 7 is located on the upper surface.

[0059] In the present invention, the dielectric layer preferably includes at least two of a silicon oxide film, a silicon nitride film, an aluminum oxide film and a hafnium oxide film. The total thickness of the dielectric layer is preferably 10 nm to 1.5 μm.

[0060] In the present invention, the dielectric layer preferably includes a first dielectric layer 21, a second dielectric layer 22 and a third dielectric layer 23 stacked in sequence from bottom to top. The first dielectric layer 21 is preferably a silicon oxide film. The second dielectric layer 22 is preferably a silicon nitride film. The third dielectric layer 23 is preferably a silicon oxide film.

[0061] As one or more embodiments of the present invention, the dielectric layer includes, from bottom to top, a first silicon oxide film, a silicon nitride film, and a second silicon oxide film (ONO) stacked in sequence.

[0062] In the present invention, the structural unit 4 includes a conductive layer 3 covering the upper surface of the dielectric layer, and the conductive layer 3 fills the gap between any adjacent strip pillars. In the present invention, the material of the conductive layer 3 preferably includes polysilicon doped with phosphorus impurities and / or metal tungsten, and the resistivity of the conductive layer 3 is preferably <0.003Ω·cm. In an embodiment of the present invention, the material of the conductive layer 3 is preferably heavily doped POLY. The thickness of the conductive layer above the strip pillar is preferably 300 to 3μm.

[0063] In the present invention, the structural unit 4 includes an upper electrode 8 located on the upper surface of the conductive layer 3. In the present invention, the thickness of the upper electrode is preferably 300 nm to 10 μm. The material of the upper electrode 8 is preferably metal or AlSiCu.

[0064] In the present invention, the structural unit 4 includes a lower electrode 9 located on the lower surface of the silicon substrate. In the present invention, the thickness of the upper electrode is preferably 300nm to 10μm. The material of the lower electrode 9 is preferably metal or TiWAu. In the present invention, the upper electrode 8 and the lower electrode 9 form an ohmic contact to reduce the contact resistance and ensure that the charge in the silicon capacitor can be effectively extracted. In the present invention, the upper electrode 8 and the lower electrode 9 are used to connect and extract the capacitor.

[0065] The present invention optimizes the structural pattern of the structural unit 4, optimizes the etching morphology of the bottom of the groove formed by the strip-shaped columns and the filling morphology of the conductive layer, thereby improving the electrical performance, reliability and integration of the capacitor.

[0066] The present invention provides a method for preparing the silicon capacitor described in the above technical solution, comprising the following steps:

[0067] Performing photolithography and etching on the upper surface of the silicon material to obtain a silicon substrate having strip-shaped columns on the upper surface;

[0068] Prepare a dielectric layer on the upper surface of the strip-shaped pillars, the sidewalls of the strip-shaped pillars and the upper surface of the silicon substrate between any adjacent strip-shaped pillars;

[0069] Preparing a conductive layer on the upper surface of the dielectric layer;

[0070] Preparing an upper electrode on the upper surface of the conductive layer;

[0071] A lower electrode is prepared on the lower surface of the silicon substrate to obtain the silicon capacitor.

[0072] The present invention performs photolithography and etching on the upper surface of the silicon material to obtain a silicon substrate having strip-shaped columns on the upper surface. The present invention has no special requirements on the specific implementation of the photolithography and etching.

[0073] After obtaining the strip-shaped columns, the present invention prepares a dielectric layer on the upper surface of the strip-shaped columns, the side walls of the strip-shaped columns and the upper surface of the silicon substrate between any adjacent strip-shaped columns. In the present invention, the dielectric layer is preferably prepared by a chemical vapor deposition method. The present invention has no special requirements for the specific implementation method of preparing the dielectric layer by chemical vapor deposition. The present invention transfers the pattern of the unit structure in proportion to the deposited, exposed and developed photoresist by a photolithography method. During etching, the reactive gas reacts with silicon atoms on the surface of the silicon substrate in the graphic area not protected by the photoresist, and the reaction product detaches from the substrate surface to expose a deeper silicon surface, thereby continuously reacting toward the next layer of the silicon substrate until a specified depth is reached, and finally a height difference is formed with the adjacent area protected by the photoresist, thereby obtaining a strip-shaped column and forming a silicon deep groove.

[0074] After obtaining the dielectric layer, the present invention prepares a conductive layer on the upper surface of the dielectric layer. In the present invention, the conductive layer is preferably prepared by chemical vapor deposition. The present invention has no special requirements on the specific implementation of preparing the conductive layer by chemical vapor deposition.

[0075] After obtaining the conductive layer, the present invention prepares an upper electrode on the upper surface of the conductive layer. In the present invention, the upper electrode is preferably prepared by sputtering and / or electroplating. The present invention has no special requirements for the specific implementation of the sputtering and / or electroplating.

[0076] The present invention prepares a lower electrode on the lower surface of the silicon substrate to obtain the silicon capacitor. In the present invention, the present invention preferably thins the silicon substrate before preparing the lower electrode. The lower electrode is preferably prepared by sputtering and / or electroplating. The present invention has no special requirements for the specific implementation of the sputtering and / or electroplating.

[0077] The preparation method of the silicon capacitor provided by the present invention forms a strip-shaped column with a high aspect ratio on the upper surface of the silicon substrate through a single photolithography and etching, thereby forming a groove structure on the upper surface of the silicon substrate, and sequentially chemically vapor depositing a dielectric layer and a conductive layer in the groove. The preparation method provided by the present invention has a simple process, and the obtained device has a high capacity density. At the same time, the thickness of the dielectric layer and the conductive film can be adjusted, the capacitance value can be adjusted, and it is compatible with the existing microelectronic process and has good scalability.

[0078] In order to further illustrate the present invention, the technical solutions provided by the present invention are described in detail below in conjunction with embodiments, but they should not be construed as limiting the protection scope of the present invention.

[0079] Example 1

[0080] The present invention provides a silicon capacitor, the structure of which is as follows Figure 1 As shown, the silicon capacitor provided in this embodiment includes a silicon substrate, and a plurality of repeatedly arranged structural units 4 are arranged on the upper surface of the silicon substrate. A top view of a structural unit 4 is shown in FIG. Figure 2 The structure unit 4 is repeated or stretched to form the effective area of ​​the silicon capacitor. The heights of the strip columns 5 in each structure unit 4 in the effective area of ​​the silicon capacitor provided in this embodiment are equal, and the width intervals of adjacent strip columns 5 in each structure unit 4 in the effective area of ​​the silicon capacitor are equal.

[0081] In this embodiment, the silicon substrate 1 is low-resistance silicon, and the resistivity of the silicon substrate is less than 0.01Ω·cm.

[0082] In the silicon capacitor provided in this embodiment, each structural unit is divided into four regions: upper left, upper right, lower left and lower right; the strip columns in the upper left region are arranged horizontally, the strip columns in the upper right region are arranged vertically, the strip columns in the lower left region are arranged vertically, and the strip columns in the lower right region are arranged horizontally. The right end of the strip column at the bottom edge in the upper left region, the lower end of the strip column at the leftmost edge in the upper right region, the upper end of the strip column at the rightmost edge in the lower left region and the left end of the strip column at the top edge in the lower right region are connected together to form a solid integrated structure (such as Figure 2 The end connection position in 7).

[0083] In this embodiment, the height of the strip pillars is 200 μm, the spacing width between any adjacent strip pillars is 4 μm, and the ratio of the spacing width between any adjacent strip pillars is 50. The sum of the height of the strip pillars and the thickness of the silicon substrate is 300 μm.

[0084] In this embodiment, the dielectric layer includes a first silicon oxide film 21, a silicon nitride film 22 and a second silicon oxide film 23 (ONO) stacked in sequence. The total thickness of the dielectric layer is 1.5 μm, wherein the thickness of the first silicon oxide film 21 is equal to that of the second silicon oxide film 23 and is less than that of the silicon nitride film 22.

[0085] In this embodiment, the material of the conductive layer is heavily doped POLY. The resistivity of the conductive layer is less than 0.003Ω·cm. The thickness of the conductive layer located above the strip-shaped pillar is 3 μm.

[0086] In this embodiment, the material of the upper electrode 8 is AlSiCu, and the thickness is 0.8 μm.

[0087] In this embodiment, the material of the lower electrode 9 is TiWAu, and the thickness is 0.33 μm.

[0088] The method for preparing the silicon capacitor provided in this embodiment comprises the following steps:

[0089] The pattern of the photolithography mask is set according to the unit structure of the silicon capacitor, and the groove 6 is etched on the upper surface of the silicon substrate material by photolithography and etching, and the remaining silicon forms a strip column 5, such as Figure 2 As shown, the grooves 6 and the strip-shaped columns 5 are arranged in an array, alternating horizontally and vertically.

[0090] Then, a dielectric layer and a conductive layer are prepared by chemical vapor deposition; an upper electrode is prepared on the upper surface of the conductive layer; and a lower electrode is prepared after thinning the silicon substrate to obtain a silicon capacitor.

[0091] Figure 4The voltage-current characteristic curves of the central area and the edge area of ​​the chip prepared in Example 1 of the present invention are shown in FIG. Figure 4 It can be seen that the chip prepared in this embodiment has a higher capacity density and good electrical performance.

[0092] Comparative Example 1

[0093] The preparation method of the silicon capacitor provided in this comparative example is basically the same as the preparation method of the silicon capacitor provided in Example 1, except that: in this comparative example, the structural unit is not divided into zones, and the strip-shaped columns in the structural unit are all arranged horizontally.

[0094] Figure 3 The upper picture in the figure is a real photo of the chip prepared in Example 1. Figure 3 The following figure is a physical photo of the chip prepared in Example 2. Figure 3 It can be seen that, in Example 1, by dividing the structural units into regions, chip cracking can be effectively avoided, and the yield rate of silicon capacitors is high.

[0095] It can be seen from the above embodiments that the silicon capacitor provided by the present invention forms a groove structure on the upper surface of the silicon substrate through strip columns, so that when the size of the silicon capacitor remains unchanged, the surface area of ​​the dielectric layer is increased by introducing the Y-axis direction, so that the capacity is increased by 1 to 2 orders of magnitude, and the parasitic effect is greatly reduced compared with the connection of multiple capacitors, and the capacity temperature stability and high-frequency application are significantly better than the traditional multilayer ceramic capacitor (MLCC); at the same time, the present invention divides the upper surface of the silicon substrate into zones, and the strip columns in different areas are arranged alternately horizontally and vertically to form an array, which can effectively reduce the stress effect generated by the etching and deposition process, effectively avoid chip cracking, and the silicon capacitor has a high yield rate; at the same time, when the present invention arranges the strip columns alternately horizontally and vertically in different regions, the end of the outermost strip column in any region is connected to the adjacent end of the outermost strip column in the adjacent region, which can effectively eliminate the situation where the conductive layer is not fully filled in the gap of the strip column, thereby improving the reliability of the silicon capacitor. In summary, the silicon capacitor provided by the present invention optimizes the etching morphology of the strip columns (i.e., grooves) and the filling morphology of the conductive layer, thereby improving the electrical performance, capacity density, reliability and integration of the capacitor. Therefore, the silicon capacitor provided by the present invention can replace traditional chip capacitors and be used in high-frequency and high-speed circuits. It is compatible with existing microelectronic processes and has good scalability.

[0096] Although the above embodiment describes the present invention in detail, it is only a part of the embodiments of the present invention, not all of the embodiments. Other embodiments can be obtained based on this embodiment without creativity, and these embodiments all fall within the protection scope of the present invention.

Claims

1. A silicon capacitor, characterized in that: It comprises a silicon substrate, wherein a plurality of repeatedly arranged structural units are arranged on the upper surface of the silicon substrate; Each structural unit is divided into at least two regions, and the upper surface of the silicon substrate in each region is provided with strip columns arranged in a horizontal or vertical array, and the gaps between any adjacent strip columns in the same region form grooves, and the arrangement directions of the strip columns in any adjacent regions are perpendicular to each other, and the ends of the outermost strip columns in any region are connected to the adjacent ends of the outermost strip columns in the adjacent region; A dielectric layer covering the upper surface of the strip-shaped pillars, the sidewalls of the strip-shaped pillars and the upper surface of the silicon substrate between any adjacent strip-shaped pillars; A conductive layer covering the upper surface of the dielectric layer, wherein the conductive layer fills the gaps between any adjacent strip-shaped columns; an upper electrode located on the upper surface of the conductive layer; A lower electrode is located on the lower surface of the silicon substrate.

2. The silicon capacitor according to claim 1, characterized in that: The structural unit is divided into four areas: upper left, upper right, lower left and lower right; the strip columns in the upper left area are arranged horizontally, the strip columns in the upper right area are arranged vertically, the strip columns in the lower left area are arranged vertically, and the strip columns in the lower right area are arranged horizontally; The right end of the strip column located at the lowermost edge in the upper left area, the lower end of the strip column located at the leftmost edge in the upper right area, the upper end of the strip column located at the rightmost edge in the lower left area, and the left end of the strip column located at the uppermost edge in the lower right area are connected together to form a solid integrated structure.

3. The silicon capacitor according to claim 1, characterized in that: In the same area: the ratio of the height of the strip pillars to the width of the interval between any adjacent strip pillars is greater than 10:1; The heights of the strip columns in different areas are equal, and the interval widths between any adjacent strip columns in different areas are equal.

4. The silicon capacitor according to claim 1 or 3, characterized in that: In the same area: the height of the strip-shaped columns is 20 to 200 μm.

5. The silicon capacitor according to claim 1 or 3, characterized in that: In the same area: the spacing width between any adjacent strip columns is 1 to 4 μm.

6. The silicon capacitor according to claim 1, characterized in that: The material of the strip pillar is the same as that of the silicon substrate; the silicon substrate is N-type doped or P-type doped, and the resistivity of the silicon substrate is less than 0.01Ω·cm; the sum of the height of the strip pillar and the thickness of the silicon substrate is 100-500μm.

7. The silicon capacitor according to claim 1, characterized in that: The dielectric layer includes at least two of a silicon oxide film, a silicon nitride film, an aluminum oxide film and a hafnium oxide film; The total thickness of the dielectric layer is 10 nm to 1.5 μm.

8. The silicon capacitor according to claim 1, characterized in that: The material of the conductive layer includes polysilicon doped with phosphorus impurities and / or metal tungsten, and the resistivity of the conductive layer is less than 0.003Ω·cm; The thickness of the conductive layer located above the strip-shaped pillars is 300-3 μm.

9. The silicon capacitor according to claim 1, characterized in that: The thickness of the upper electrode and the lower electrode are independently 300nm-10μm.

10. The method for preparing a silicon capacitor according to any one of claims 1 to 9, characterized in that: The following steps are involved: Performing photolithography and etching on the upper surface of the silicon material to obtain a silicon substrate having strip-shaped columns on the upper surface; Prepare a dielectric layer on the upper surface of the strip-shaped pillars, the sidewalls of the strip-shaped pillars and the upper surface of the silicon substrate between any adjacent strip-shaped pillars; Preparing a conductive layer on the upper surface of the dielectric layer; Preparing an upper electrode on the upper surface of the conductive layer; A lower electrode is prepared on the lower surface of the silicon substrate to obtain the silicon capacitor.

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