IGBT device and manufacturing method thereof
By setting up gate trench structures and dielectric layers with different widths during the manufacturing process of IGBT devices, the problem of high alignment accuracy is solved, and the saturation voltage drop consistency and device performance are improved.
Patent Information
- Application Number
- CN202510117639.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-04-15
AI Technical Summary
During the manufacturing process of IGBT devices, the alignment accuracy of the body area contact hole mask plate and trench gate mask plate has high requirements, resulting in inconsistent saturation pressure drop, affecting yield and yield.
By setting the gate trench to include a first subtrench and a second subtrench that is interconnected, the width of the second subtrench is greater than the width of the first subtrench, and a continuous gate dielectric layer and a trench gate are formed in the gate trench, and the isolation dielectric layer covers and partially fills the gate trench to ensure the distance between the body region contact hole and the trench gate.
The requirements for the alignment accuracy of the contact hole mask plate and the gate trench mask plate are reduced, the saturation voltage drop consistency of IGBT devices is improved, the yield and yield are improved, and the performance of IGBT devices is improved.
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Figure CN119835954A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an IGBT device and a manufacturing method thereof. Background Art
[0002] As a hybrid power device, IGBT (Insulated Gate Bipolar Transistor) devices have the characteristics of MOS structure input and bipolar structure output. Therefore, they have the advantages of high input impedance of MOSFET, low drive circuit power, simple drive, fast switching speed and low switching loss, and have the advantages of high current density, strong current handling capability and low on-saturation voltage drop of bipolar power transistors. Since the early 1980s, IGBT devices have been widely studied at home and abroad. At present, IGBT devices are widely used in many fields such as new energy vehicles, industrial frequency conversion, photovoltaics, smart grids and locomotives. After nearly 40 years of development, IGBT devices have developed from planar to trench type, and the pitch between repeated structural units is getting smaller and smaller, so that the distance between the body contact hole and the trench gate is getting smaller and smaller, and the problem of wafer warpage is getting more and more serious, which leads to higher and higher requirements for the alignment accuracy of the body contact hole mask and the alignment accuracy of the trench gate mask, which ultimately leads to the increasing difficulty of the process of manufacturing IGBT devices. If the body contact hole mask and the trench gate mask are poorly aligned, the distance between the body contact hole and the trench gate will be too narrow, which will cause the saturation voltage drop (Vcesat) in the IGBT device to be discrete.
[0003] Therefore, how to reduce the requirements for the alignment accuracy of the body contact hole mask and the trench gate mask during the IGBT device manufacturing process, thereby improving the consistency of the saturation voltage drop of IGBT devices within and between wafers, improving the yield and yield of IGBT devices, and improving the performance of mass-produced IGBT devices, is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The present invention provides an IGBT device and a manufacturing method thereof, which are used to reduce the requirements for the alignment accuracy of a body region contact hole mask and a trench gate mask during the IGBT device manufacturing process, thereby improving the consistency of the saturation voltage drop of the IGBT device within a wafer and between wafers, improving the production rate and yield of the IGBT device, and improving the performance of the mass-produced IGBT device.
[0005] According to some embodiments, the present invention provides a method for manufacturing an IGBT device, comprising the following steps:
[0006] Forming a substrate, the substrate comprising a substrate, a carrier storage region located above the substrate, a body region located above the carrier storage region, an emitter region located above the body region, and a gate trench, the substrate comprising a front side and a back side that are relatively distributed, the gate trench continuously runs through the emitter region, the body region, and the carrier storage region, the gate trench comprising a first sub-trench that is interconnected and a second sub-trench that is located above the first sub-trench, and the width of the second sub-trench is greater than the width of the first sub-trench;
[0007] forming a gate structure in the gate trench, the gate structure comprising a gate dielectric layer continuously covering the inner wall of the first sub-trench and the inner wall of the second sub-trench and a trench gate at least filled in the first sub-trench, the top surface of the trench gate being lower than the top surface of the gate trench;
[0008] forming an isolation dielectric layer continuously covering the front surface of the substrate and the surface of the trench gate and partially filling the gate trench;
[0009] A body region contact hole is formed which at least penetrates the emitter region and exposes the body region.
[0010] In some embodiments, the specific steps of forming the substrate include:
[0011] providing an initial substrate;
[0012] Implanting doping ions into the initial substrate in sequence, forming the carrier storage region, the body region located above the carrier storage region along a first direction, and the emitter region located above the body region along the first direction in the initial substrate, the remaining initial substrate below the carrier storage region serves as the substrate, the substrate comprising a first main surface and a second main surface that are relatively distributed along the first direction;
[0013] A gate trench is formed along the first direction, penetrating the emitter region, the body region and the carrier storage region and extending to the interior of the substrate. A plurality of the gate trenches are arranged at intervals at least along a second direction, and the second direction is parallel to the first main surface.
[0014] In some embodiments, the specific steps of forming a gate trench that penetrates the emitter region, the body region, and the carrier storage region along the first direction and extends to the inside of the substrate include:
[0015] forming a mask layer on the front surface of the substrate, wherein the mask layer has an opening exposing the front surface of the substrate;
[0016] Etching the substrate along the opening to form an initial trench that penetrates the emitter region, the body region, and the carrier storage region along the first direction and extends to the interior of the substrate;
[0017] forming a sacrificial layer filled in the initial groove, wherein the top surface of the sacrificial layer is lower than the front surface of the substrate, and the initial groove above the sacrificial layer serves as the second sub-groove, and the initial groove below the second sub-groove serves as the first sub-groove;
[0018] enlarging the width of the second sub-groove;
[0019] The sacrificial layer and the mask layer are removed to form the gate trench including the second sub-trench and the first sub-trench.
[0020] In some embodiments, the specific steps of forming the sacrificial layer filled in the initial trench include:
[0021] forming the sacrificial layer that fills the initial trench and covers the surface of the mask layer;
[0022] The sacrificial layer is etched back to remove the sacrificial layer on the front side of the substrate and a portion of the sacrificial layer in the initial groove.
[0023] In some embodiments, the material of the substrate includes silicon, and the material of the sacrificial layer includes polyimide.
[0024] In some embodiments, the specific steps of expanding the width of the second sub-groove include:
[0025] A wet etching process is used to laterally etch a portion of the substrate along the second sub-groove, thereby expanding the width of the second sub-groove and making the sidewall of the second sub-groove obliquely intersect with the first main surface of the substrate.
[0026] In some embodiments, an angle between a sidewall of the second sub-trench and the first main surface of the substrate is 70° to 85°.
[0027] In some embodiments, along the first direction, a depth of the second sub-groove is 0.3 μm-0.6 μm.
[0028] In some embodiments, the specific steps of forming a gate structure in the gate trench include:
[0029] Using a thermal oxidation process to form a thermal oxide layer that continuously covers the inner wall of the first sub-trench and the inner wall of the second sub-trench, and using the thermal oxide layer as the gate dielectric layer;
[0030] Filling the gate trench with polysilicon material to form the trench gate filled only in the first sub-trench.
[0031] In some embodiments, the specific steps of forming a body contact hole at least penetrating the emitter region and exposing the body region include:
[0032] removing part of the isolation dielectric layer to expose the emitter region;
[0033] The emitter region and the body region are etched by a dry etching process to form the body region contact hole that penetrates the emitter region and extends into the body region.
[0034] According to some other embodiments, the present invention further provides an IGBT device, including:
[0035] substrate;
[0036] A carrier storage region, located above the substrate;
[0037] A body region, located on a surface of the carrier storage region facing away from the substrate;
[0038] an emitter region, located on a surface of the body region facing away from the substrate;
[0039] A trench gate structure, comprising a gate trench continuously penetrating the emitter region, the body region and the carrier storage region, a gate dielectric layer covering the inner wall of the gate trench, and a trench gate filled in the gate trench, wherein the gate trench comprises a first sub-trench interconnected with each other and a second sub-trench located above the first sub-trench, and the width of the second sub-trench is greater than the width of the first sub-trench, the gate dielectric layer continuously covers the inner wall of the first sub-trench and the inner wall of the second sub-trench, and the trench gate is at least filled in the first sub-trench;
[0040] An isolation dielectric layer, covering the surface of the trench gate and partially filling the gate trench;
[0041] The lead-out structure comprises a body contact hole which at least penetrates the emitter region and exposes the body region, a conductive contact layer located at the bottom of the body contact hole, and a front metal layer which at least covers the conductive contact layer and fills the body contact hole.
[0042] In some embodiments, the substrate includes a first main surface and a second main surface that are oppositely distributed along a first direction, and the carrier storage region is located on the first main surface of the substrate along the first direction;
[0043] In the first direction, the depth of the second sub-groove is 0.3 μm to 0.6 μm.
[0044] In some embodiments, the body region is made of silicon material including first doping ions, the emitter region is made of silicon material including second doping ions, the gate dielectric layer is made of silicon dioxide, and the isolation dielectric layer is made of borophosphosilicate glass.
[0045] In some embodiments, a sidewall of the second sub-trench intersects the first main surface of the substrate at an angle.
[0046] In some embodiments, an angle between a sidewall of the second sub-trench and the first main surface of the substrate is 70° to 85°.
[0047] The IGBT device and the manufacturing method thereof provided by the present invention are as follows: a gate groove is set to include a first sub-groove connected to each other and a second sub-groove located above the first sub-groove, and the width of the second sub-groove is greater than the width of the first sub-groove; a gate dielectric layer continuously covers the inner wall of the first sub-groove and the inner wall of the second sub-groove, and a trench gate is filled in the first sub-groove; an isolation dielectric layer covers the surface of the trench gate and partially fills the gate groove; when a body contact hole is subsequently formed by a self-aligned etching process, the distance between the body contact hole and the trench gate is ensured by the widened second sub-groove, and the problem of too narrow distance between the body contact hole and the trench gate is avoided, the requirement for the alignment accuracy of the contact hole mask and the gate trench mask is reduced, and the consistency of the saturation voltage drop of the IGBT device within a wafer and between wafers is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] Figure 1 is a flow chart of a method for manufacturing an IGBT device in a specific embodiment of the present invention;
[0049] Figure 2 is a schematic structural diagram of a substrate before forming a gate trench in a specific embodiment of the present invention;
[0050] Figure 3 is a schematic diagram of the structure after forming a gate trench in a specific embodiment of the present invention;
[0051] Figure 4 is a schematic diagram of the structure after a sacrificial layer is formed in a specific embodiment of the present invention;
[0052] Figure 5 is a schematic diagram of the structure after the sacrificial layer is etched back in a specific embodiment of the present invention;
[0053] Figure 6 is a schematic diagram of the structure after the width of the second sub-groove is enlarged in a specific embodiment of the present invention;
[0054] Figure 7is a schematic diagram of the structure after the sacrificial layer is removed in a specific embodiment of the present invention;
[0055] Figure 8 is a schematic diagram of the structure after a gate dielectric layer is formed in a specific embodiment of the present invention;
[0056] Fig. 9 is a schematic diagram of the structure after the trench gate is formed in a specific embodiment of the present invention;
[0057] Fig.10 is a schematic diagram of the structure after forming an isolation dielectric layer in a specific embodiment of the present invention;
[0058] Fig.11 is a schematic diagram of the structure after forming the body region contact hole in a specific embodiment of the present invention;
[0059] Fig.12 It is a schematic diagram of the structure after the front metal layer is formed in a specific embodiment of the present invention. DETAILED DESCRIPTION
[0060] The specific implementation manner of the IGBT device and the manufacturing method thereof provided by the present invention is described in detail below with reference to the accompanying drawings.
[0061] This specific embodiment provides a method for manufacturing an IGBT device. Figure 1 FIG. 1 is a flow chart of a method for manufacturing an IGBT device in a specific embodiment of the present invention. Figure 1 As shown, the manufacturing method of the IGBT device comprises the following steps:
[0062] Step S11, forming a substrate, the substrate comprising a substrate, a carrier storage region located above the substrate, a body region located above the carrier storage region, an emitter region located above the body region, and a gate trench, the substrate comprising a front side and a back side that are relatively distributed, the gate trench continuously runs through the emitter region, the body region, and the carrier storage region, the gate trench comprising a first sub-trench that is interconnected and a second sub-trench that is located above the first sub-trench, and the width of the second sub-trench is greater than the width of the first sub-trench;
[0063] Step S12, forming a gate structure in the gate trench, the gate structure comprising a gate dielectric layer continuously covering the inner wall of the first sub-trench and the inner wall of the second sub-trench and a trench gate at least filled in the first sub-trench, the top surface of the trench gate being lower than the top surface of the gate trench;
[0064] Step S13, forming an isolation dielectric layer that continuously covers the front surface of the substrate and the surface of the trench gate and partially fills the gate trench;
[0065] Step S14, forming a body contact hole at least penetrating the emitter region and exposing the body region.
[0066] Figure 2 is a schematic structural diagram of a substrate before forming a gate trench in a specific embodiment of the present invention, Figure 3 is a schematic diagram of the structure after forming the gate trench in a specific embodiment of the present invention. Figure 2 and Figure 3 As shown, the specific steps of forming the substrate include:
[0067] providing an initial substrate;
[0068] Implanting doping ions into the initial substrate in sequence, forming the carrier storage region 21, the body region 22 located above the carrier storage region 21 along the first direction D1, and the emitter region 23 located above the body region 22 along the first direction D1 in the initial substrate, the remaining initial substrate below the carrier storage region 21 is used as the substrate 20, and the substrate 20 includes a first main surface 201 and a second main surface 202 that are relatively distributed along the first direction D1;
[0069] A gate trench is formed along the first direction D1 that penetrates the emitter region 23 , the body region 22 and the carrier storage region 21 and extends to the inside of the substrate 20 . A plurality of the gate trenches are arranged at intervals at least along a second direction D2 , and the second direction D2 is parallel to the first main surface 201 .
[0070] For example, the initial substrate may be a silicon substrate doped with N-type ions. N-type ions (e.g., phosphorus ions) are implanted into the initial substrate to form the carrier storage region 21. In one example, during the process of implanting phosphorus ions into the initial substrate to form the carrier storage region 21, the implantation energy may be 1 MeV to 2 MeV, and the implantation dose may be 1×10 12 Pieces / cm 2 ~5×10 13 Pieces / cm 2 After forming the carrier storage region 21, P-type ions (e.g., boron ions) are implanted into the initial substrate to form the body region 22 located above the carrier storage region 21 along the first direction D1. In one example, during the process of implanting boron ions into the initial substrate to form the body region 22, the implantation energy may be 60keV to 200keV, and the implantation dose may be 2×10 13 Pieces / cm 2 ~5×10 14 Pieces / cm 2After forming the body region 22, N-type ions (e.g., arsenic ions) are implanted into the initial substrate to form the emitter region 23 located above the body region 22 along the first direction D1. In one example, during the process of implanting arsenic ions into the initial substrate to form the emitter region 23, the implantation energy may be 60keV to 600keV, and the implantation dose may be 3×10 15 Pieces / cm 2 ~2×10 16 Pieces / cm 2 . The ion doping concentration in the substrate 20, the ion doping concentration in the carrier storage area 21, the ion doping concentration in the body area 22, and the ion doping concentration in the emitter area 23 can be set according to the parameters such as the on-resistance and reverse withstand voltage performance of the IGBT device to be prepared. The remaining initial substrate below the carrier storage area 21 serves as the substrate 20, and the substrate 20 includes the first main surface 201 facing the carrier storage area 21 and the second main surface 202 opposite to the first main surface 201 along the first direction D1. The surface of the emitter area 23 facing away from the substrate 20 serves as the front side of the substrate, and the surface of the substrate 20 facing away from the carrier storage area 21 serves as the back side of the substrate.
[0071] Figure 4 is a schematic diagram of the structure after forming a sacrificial layer in a specific embodiment of the present invention, Figure 5 is a schematic diagram of the structure after the sacrificial layer is etched back in a specific embodiment of the present invention, Figure 6 is a schematic diagram of the structure after the width of the second sub-groove is enlarged in a specific embodiment of the present invention, Figure 7 2 is a schematic diagram of a structure after the sacrificial layer is removed in a specific embodiment of the present invention. In some embodiments, the specific steps of forming a gate trench that penetrates the emitter region 23, the body region 22, and the carrier storage region 21 along the first direction D1 and extends to the inside of the substrate 20 include:
[0072] forming a mask layer 24 on the front surface of the substrate, wherein the mask layer 24 has an opening 241 exposing the front surface of the substrate;
[0073] Etching the substrate along the opening 241 to form an initial trench 30 that penetrates the emitter region 23 , the body region 22 , and the carrier storage region 21 along the first direction D1 and extends to the inside of the substrate 20 ;
[0074] forming a sacrificial layer 40 filled in the initial groove 30, wherein the top surface of the sacrificial layer 40 is lower than the front surface of the substrate, and the initial groove 30 above the sacrificial layer 40 serves as the second sub-groove 52, and the initial groove 30 below the second sub-groove 52 serves as the first sub-groove 51;
[0075] Enlarging the width of the second sub-groove 52;
[0076] The sacrificial layer 40 and the mask layer 24 are removed to form the gate trench including the second sub-trench 52 and the first sub-trench 51 .
[0077] In some embodiments, the specific steps of forming the sacrificial layer 40 filled in the initial trench 30 include:
[0078] forming the sacrificial layer 40 filling the initial trench 30 and covering the surface of the mask layer 24;
[0079] The sacrificial layer 40 is etched back to remove the sacrificial layer 40 on the front side of the substrate and a portion of the sacrificial layer 40 in the initial trench 30 .
[0080] For example, if Figure 2 As shown, after forming the emitter region 23, a mask material is deposited on the substrate to form the mask layer 24 covering the top surface of the emitter region 23 (i.e., the surface of the emitter region 23 facing away from the substrate 20). In one example, the mask layer 24 is a hard mask layer made of a material such as silicon nitride. Next, a patterned photoresist layer 25 is formed on the mask layer 24, and the photoresist layer 25 has a plurality of etching windows 251 that penetrate the photoresist layer 25 along the first direction D1 and expose the mask layer 24, as shown in FIG. Figure 2 As shown. The mask layer 24 is etched downward along the etching window to form a plurality of openings 241 that penetrate the mask layer 24 along the first direction D1 and expose the emitter region 23. The plurality of openings 241 are arranged at intervals at least along the second direction D2. Then, a dry etching process can be used to simultaneously etch the substrate downward along the plurality of openings 241 to form a plurality of initial trenches 30 that penetrate the emitter region 23, the body region 22, and the carrier storage region 21 along the first direction D1 and extend into the substrate 20. After removing the photoresist layer 25, the initial trench 30 is obtained as shown. Figure 3 In one example, the depth of the initial trench 30 (eg, the depth of the initial trench 30 along the first direction D1) is 2 μm to 6 μm.
[0081] After forming the initial grooves 30, a sacrificial material is spin-coated on the substrate to form the sacrificial layer 40 that continuously fills the plurality of initial grooves 30, the plurality of openings 241 and covers the surface of the mask layer 24 facing away from the substrate. Figure 4 Afterwards, a part of the sacrificial layer 40 is etched back by dry etching or other processes, the sacrificial layer 40 on the surface of the mask layer 24 away from the substrate is removed, and part of the sacrificial layer 40 in the initial groove 30 is removed, so that the top surface of the sacrificial layer 40 remaining in the initial groove 30 (i.e., the surface of the sacrificial layer 40 away from the substrate 20) is lower than the front surface of the substrate (i.e., the top surface of the initial groove 30), as shown. Figure 5 Next, at least the width of the second sub-groove 52 along the second direction D2 is enlarged to obtain Figure 6 By filling the sacrificial layer 40 in the first sub-groove 51, it is possible to avoid affecting the morphology and size (for example, the width along the second direction D2) of the first sub-groove 51 during the process of expanding the width of the second sub-groove 52, thereby ensuring the electrical performance of the formed gate structure. Next, the sacrificial layer 40 and the mask layer 24 are removed to obtain the structure shown in FIG. Figure 7 The structure shown.
[0082] In some embodiments, the material of the substrate includes silicon, and the material of the sacrificial layer 40 includes polyimide.
[0083] In some embodiments, the specific steps of expanding the width of the second sub-groove 52 include:
[0084] A wet etching process is used to laterally etch a portion of the substrate along the second sub-groove 52 to expand the width of the second sub-groove 52 and make the sidewall of the second sub-groove 52 obliquely intersect with the first main surface 201 of the substrate 20 .
[0085] Specifically, the material of the substrate is silicon. In the process of etching part of the substrate laterally along the second sub-groove 52 by a wet etching process, since the etchant used in the wet etching process is an acidic etchant, the sacrificial layer 40 is formed by using polyimide, which can further reduce or even avoid the acidic etchant from corroding the sacrificial layer 40, thereby further ensuring the morphology and size of the first sub-groove 51. At the same time, in the process of etching part of the substrate laterally along the second sub-groove by a wet etching process, since the mask layer 24 covers the front surface of the substrate, the acidic etchant can be prevented from corroding the front surface of the substrate. In the process of laterally etching a portion of the substrate along the second sub-groove 52 by a wet etching process, by adjusting etching parameters, such as any one or a combination of two or more of the specific composition of the acidic etchant, the dosage of the acidic etchant, the etching temperature, the etching pressure and the etching time, the side wall of the second sub-groove 52 after the width is enlarged is obliquely intersected with the first main surface 201 of the substrate 20, that is, the cross-section of the second sub-groove 52 after the width is enlarged is an inverted trapezoidal shape, thereby increasing the area of the emitter region 23 remaining after the subsequent formation of the body region contact hole, so as to increase the RBSOA (Reverse Bias SOA) of the IGBT device, thereby further improving the performance of the IGBT device.
[0086] In some embodiments, the angle γ between the side wall of the second sub-groove 52 and the first main surface 201 of the substrate 20 is 70° to 85°, so as to further increase the area of the emitter region 23 remaining after forming the body region contact hole while satisfying the body region contact hole etching process.
[0087] In some embodiments, along the first direction D1, the depth of the second sub-groove 52 is 0.3 μm to 0.6 μm, that is, in the process of etching back the sacrificial layer 40, the depth of the sacrificial layer 40 etched back in the initial groove 30 is 0.3 μm to 0.6 μm, thereby avoiding affecting the electrical performance of the gate structure while providing sufficient space for subsequent filling of the isolation dielectric layer.
[0088] Figure 8 is a schematic diagram of the structure after the gate dielectric layer is formed in a specific embodiment of the present invention, Fig. 9 is a schematic diagram of a structure after a trench gate is formed in a specific embodiment of the present invention. In some embodiments, the specific steps of forming a gate structure in the gate trench include:
[0089] A thermal oxidation process is used to form a thermal oxidation layer that continuously covers the inner wall of the first sub-trench 51 and the inner wall of the second sub-trench 52, and the thermal oxidation layer is used as the gate dielectric layer 80. Figure 8 As shown;
[0090] Fill the gate trench with polysilicon material to form the trench gate 90 filled only in the first sub-trench 51. Fig. 9 shown.
[0091] Fig.10 is a schematic diagram of the structure after the isolation dielectric layer is formed in a specific embodiment of the present invention. For example, after removing the sacrificial layer 40 and the mask layer 24, a thermal oxidation layer that continuously covers the inner wall of the first sub-groove 51 and the inner wall of the second sub-groove 52 is formed in the furnace tube by a thermal oxidation process, and the thermal oxidation layer is used as the gate dielectric layer 80, as shown in FIG. Figure 8 In one example, the thickness of the thermal oxide layer formed by the thermal oxidation process is The oxidation temperature during the implementation of the thermal oxidation process is 1000°C to 1150°C. Before forming the gate dielectric layer 80, a sacrificial oxide layer covering the inner wall of the first sub-groove 51 and the inner wall of the second sub-groove 52 can also be formed by a thermal oxidation process, and the sacrificial oxide layer can be removed by a process such as wet etching to repair the lattice defects on the surface of the gate groove. After forming the gate dielectric layer 80, polysilicon material is deposited on the substrate to form the trench gate 90 that fills the gate trench and covers the gate dielectric layer 80. The trench gate 90 is partially etched back so that the remaining trench gate 90 after the back etching is only filled in the first sub-groove 51, that is, the back etching depth of the trench gate 90 in the gate trench is also 0.3μm to 0.6μm, such as Fig. 9 Next, deposit A thick borophosphosilicate glass (BPSG) is formed on the substrate to form the isolation dielectric layer 100 filling the second sub-trench 52 and covering the upper part of the substrate. Fig.10 After the isolation dielectric layer 100 is deposited, a borophosphosilicate glass reflow treatment is performed, the reflow temperature is 900° C. to 1000° C., and the reflow time is 30 min to 240 min.
[0092] Fig.11 is a schematic diagram of the structure after forming the body contact hole in a specific embodiment of the present invention. Fig.11 As shown, the specific steps of forming the body contact hole 110 at least penetrating the emitter region 23 and exposing the body region 22 include:
[0093] Removing part of the isolation dielectric layer 100 to expose the emitter region 23;
[0094] The emitter region 23 and the body region 22 are etched by dry etching process to form the body region contact hole 110 penetrating the emitter region 23 and extending into the body region 22 .
[0095] For example, a chemical mechanical polishing process or an etching process is used to remove a portion of the isolation dielectric layer 100 and the gate dielectric layer 80 covering the top surface of the emitter region 23, exposing the emitter region 23, so that the top surface of the remaining isolation dielectric layer 100 is flush with the top surface of the emitter region 23. Then, a dry etching process is used to etch the emitter region 23 and the body region 22 to form the body region contact hole 110 that penetrates the emitter region 23 and extends into the body region 22, as shown in FIG. Fig.11 As shown. Since the material of the isolation dielectric layer 100 (borophosphosilicate glass) and the material of the gate dielectric layer 80 (silicon dioxide) are both oxide materials, the material of the emitter region 23 and the material of the body region 22 are both silicon materials, the difference in etching rate between the oxide material and silicon can be used to etch the emitter region 23 and the body region 22 through a self-aligned process, thereby forming the body region contact hole 110 that penetrates the emitter region 23 and extends into the body region 22, as shown. Fig.11 By adopting the above method, even when the distance between the preset position of the body contact hole 110 and the gate trench is reduced, for example, when the distance between the preset position of the body contact hole 110 and the gate trench is less than 0.3 μm, damage to the gate structure in the gate trench can be reduced or even avoided, and the consistency of the distance between the plurality of body contact holes 110 and the adjacent gate trenches is improved, thereby avoiding the problem of discrete saturation voltage drop of the IGBT device.
[0096] Fig.12It is a schematic diagram of the structure after the front metal layer is formed in a specific embodiment of the present invention. In one example, the material of the body region 22 is a silicon material including a first doping ion, and the material of the emitter region 23 is a silicon material including a second doping ion, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion. After forming the body region contact hole 110, the first doping ion is injected into the body region 22 at the bottom of the body region contact hole 110 to form a conductive contact layer 120, and the concentration of the first doping ion in the conductive contact layer 120 is higher than the concentration of the first doping ion in the body region 22. Among them, the first doping ion can be a P-type ion, and the second doping ion is an N-type ion. By forming the conductive contact layer 120 with a high doping concentration, it can be ensured that the front metal layer formed in the body region contact hole 110 subsequently has a good ohmic contact with the body region 22. After forming the conductive contact layer 120 , an atomic layer deposition process may be used to deposit conductive materials such as metal tungsten in the body contact hole 110 to form a front metal layer 121 that fills the body contact hole 80 and covers the conductive contact layer 120 and the emitter region 23 .
[0097] This specific embodiment also provides an IGBT device. The IGBT device can be used as follows Figure 1-Figure 12 The manufacturing method of the IGBT device shown in FIG. 1 is formed, and the structural schematic diagram of the IGBT device can be seen in FIG. Fig.12 .like Figure 1-Figure 12 As shown, the IGBT device comprises:
[0098] Substrate 20;
[0099] A carrier storage region 21, located above the substrate 20;
[0100] a body region 22, located on a surface of the carrier storage region 21 facing away from the substrate 20;
[0101] an emitter region 23, located on a surface of the body region 22 facing away from the substrate 20;
[0102] A trench gate structure, comprising a gate trench continuously penetrating the emitter region 23, the body region 22 and the carrier storage region 21, a gate dielectric layer 80 covering the inner wall of the gate trench, and a trench gate 90 filled in the gate trench, wherein the gate trench comprises a first sub-trench 51 connected to each other and a second sub-trench 52 located above the first sub-trench 51, and the width of the second sub-trench 52 is greater than the width of the first sub-trench 51, the gate dielectric layer 80 continuously covers the inner wall of the first sub-trench 51 and the inner wall of the second sub-trench 52, and the trench gate 90 is at least filled in the first sub-trench 51;
[0103] An isolation dielectric layer 100, covering the surface of the trench gate 90 and partially filling the gate trench;
[0104] The lead-out structure includes a body contact hole 110 that at least penetrates the emitter region 23 and exposes the body region 22, a conductive contact layer 120 located at the bottom of the body contact hole 110, and a front metal layer 121 that at least covers the conductive contact layer 120 and fills the body contact hole.
[0105] In this specific embodiment, the gate groove is configured to include the first sub-groove 51 and the second sub-groove 52 which are interconnected, and the width of the second sub-groove 52 is greater than the width of the first sub-groove 51. Therefore, when the body contact hole is formed by a self-aligned etching process, the distance between the body contact hole and the trench gate is ensured by the widened second sub-groove, thereby avoiding the problem of too narrow distance between the body contact hole and the trench gate, reducing the requirements for the alignment accuracy of the contact hole mask and the gate trench mask, and improving the consistency of the saturation voltage drop of the IGBT device within the wafer and between wafers.
[0106] In some embodiments, the substrate 20 includes a first main surface 201 and a second main surface 202 that are oppositely distributed along a first direction D1, and the carrier storage region 21 is located on the first main surface 201 of the substrate 20 along the first direction D1;
[0107] Along the first direction D1 , the depth of the second sub-trench 52 is 0.3 μm to 0.6 μm, thereby providing sufficient space for filling the isolation dielectric layer while avoiding affecting the electrical performance of the gate structure.
[0108] In some embodiments, the material of the body region 22 is a silicon material including a first doping ion, the material of the emitter region 23 is a silicon material including a second doping ion, the material of the gate dielectric layer 80 includes silicon dioxide, and the material of the isolation dielectric layer 100 includes borophosphosilicate glass, so as to facilitate the formation of the body region contact hole 110 by a self-aligned etching process.
[0109] In some embodiments, the sidewall of the second sub-groove 52 intersects the first main surface 201 of the substrate 20 at an angle, thereby increasing the area of the emitter region 23 to increase the RBSOA (Reverse BiasSOA) of the IGBT device and further improve the performance of the IGBT device.
[0110] In some embodiments, the angle γ between the sidewall of the second sub-trench 52 and the first main surface 201 of the substrate 20 is 70° to 85°, so as to further increase the area of the emitter region 23 while satisfying the body region contact hole etching process.
[0111] The IGBT device and the manufacturing method thereof provided by the present invention are as follows: a gate groove is set to include a first sub-groove connected to each other and a second sub-groove located above the first sub-groove, and the width of the second sub-groove is greater than the width of the first sub-groove; a gate dielectric layer continuously covers the inner wall of the first sub-groove and the inner wall of the second sub-groove, and a trench gate is filled in the first sub-groove; an isolation dielectric layer covers the surface of the trench gate and partially fills the gate groove; when a body contact hole is subsequently formed by a self-aligned etching process, the distance between the body contact hole and the trench gate is ensured by the widened second sub-groove, and the problem of too narrow distance between the body contact hole and the trench gate is avoided, the requirement for the alignment accuracy of the contact hole mask and the gate trench mask is reduced, and the consistency of the saturation voltage drop of the IGBT device within a wafer and between wafers is improved.
[0112] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for manufacturing an IGBT device, characterized in that: The steps include: Forming a substrate, the substrate comprising a substrate, a carrier storage region located above the substrate, a body region located above the carrier storage region, an emitter region located above the body region, and a gate trench, the substrate comprising a front side and a back side that are relatively distributed, the gate trench continuously runs through the emitter region, the body region, and the carrier storage region, the gate trench comprising a first sub-trench that is interconnected and a second sub-trench that is located above the first sub-trench, and the width of the second sub-trench is greater than the width of the first sub-trench; forming a gate structure in the gate trench, the gate structure comprising a gate dielectric layer continuously covering the inner wall of the first sub-trench and the inner wall of the second sub-trench and a trench gate at least filled in the first sub-trench, the top surface of the trench gate being lower than the top surface of the gate trench; forming an isolation dielectric layer continuously covering the front surface of the substrate and the surface of the trench gate and partially filling the gate trench; A body contact hole is formed which at least penetrates the emitter region and exposes the body region.
2. The method for manufacturing an IGBT device according to claim 1, characterized in that: The specific steps of forming the substrate include: providing an initial substrate; Implanting doping ions into the initial substrate in sequence, forming the carrier storage region, the body region located above the carrier storage region along a first direction, and the emitter region located above the body region along the first direction in the initial substrate, the remaining initial substrate below the carrier storage region serves as the substrate, the substrate comprising a first main surface and a second main surface that are relatively distributed along the first direction; A gate trench is formed along the first direction, penetrating the emitter region, the body region and the carrier storage region and extending to the interior of the substrate. A plurality of the gate trenches are arranged at intervals at least along a second direction, and the second direction is parallel to the first main surface.
3. The method for manufacturing an IGBT device according to claim 2, characterized in that: The specific steps of forming a gate trench that penetrates the emitter region, the body region, and the carrier storage region along the first direction and extends to the inside of the substrate include: forming a mask layer on the front surface of the substrate, wherein the mask layer has an opening exposing the front surface of the substrate; Etching the substrate along the opening to form an initial trench that penetrates the emitter region, the body region, and the carrier storage region along the first direction and extends to the interior of the substrate; forming a sacrificial layer filled in the initial groove, wherein the top surface of the sacrificial layer is lower than the front surface of the substrate, and the initial groove above the sacrificial layer serves as the second sub-groove, and the initial groove below the second sub-groove serves as the first sub-groove; enlarging the width of the second sub-groove; The sacrificial layer and the mask layer are removed to form the gate trench including the second sub-trench and the first sub-trench.
4. The method for manufacturing an IGBT device according to claim 3, characterized in that: The specific steps of forming a sacrificial layer filled in the initial trench include: forming the sacrificial layer that fills the initial trench and covers the surface of the mask layer; The sacrificial layer is etched back to remove the sacrificial layer on the front side of the substrate and a portion of the sacrificial layer in the initial groove.
5. The method for manufacturing an IGBT device according to claim 3 or 4, characterized in that: The material of the substrate includes silicon, and the material of the sacrificial layer includes polyimide.
6. The method for manufacturing an IGBT device according to claim 5, characterized in that: The specific steps of expanding the width of the second sub-groove include: A wet etching process is used to laterally etch a portion of the substrate along the second sub-groove, thereby expanding the width of the second sub-groove and making the sidewall of the second sub-groove obliquely intersect with the first main surface of the substrate.
7. The method for manufacturing an IGBT device according to claim 6, characterized in that: An included angle between a sidewall of the second sub-trench and the first main surface of the substrate is 70° to 85°.
8. The method for manufacturing an IGBT device according to claim 3, characterized in that: In the first direction, the depth of the second sub-groove is 0.3 μm to 0.6 μm.
9. The method for manufacturing an IGBT device according to claim 2, characterized in that: The specific steps of forming a gate structure in the gate trench include: Using a thermal oxidation process to form a thermal oxide layer that continuously covers the inner wall of the first sub-trench and the inner wall of the second sub-trench, and using the thermal oxide layer as the gate dielectric layer; Filling the gate trench with polysilicon material to form the trench gate filled only in the first sub-trench.
10. The method for manufacturing an IGBT device according to claim 2, characterized in that: The specific steps of forming a body region contact hole that at least penetrates the emitter region and exposes the body region include: removing part of the isolation dielectric layer to expose the emitter region; The emitter region and the body region are etched by a dry etching process to form the body region contact hole that penetrates the emitter region and extends into the body region.
11. An IGBT device, characterized in that: include: substrate; A carrier storage region, located above the substrate; A body region, located on a surface of the carrier storage region facing away from the substrate; an emitter region, located on a surface of the body region facing away from the substrate; A trench gate structure, comprising a gate trench continuously penetrating the emitter region, the body region and the carrier storage region, a gate dielectric layer covering the inner wall of the gate trench, and a trench gate filled in the gate trench, wherein the gate trench comprises a first sub-trench interconnected with each other and a second sub-trench located above the first sub-trench, and the width of the second sub-trench is greater than the width of the first sub-trench, the gate dielectric layer continuously covers the inner wall of the first sub-trench and the inner wall of the second sub-trench, and the trench gate is at least filled in the first sub-trench; An isolation dielectric layer, covering the surface of the trench gate and partially filling the gate trench; The lead-out structure comprises a body contact hole which at least penetrates the emitter region and exposes the body region, a conductive contact layer located at the bottom of the body contact hole, and a front metal layer which at least covers the conductive contact layer and fills the body contact hole.
12. The IGBT device according to claim 11, characterized in that: The substrate comprises a first main surface and a second main surface that are oppositely distributed along a first direction, and the carrier storage region is located on the first main surface of the substrate along the first direction; In the first direction, the depth of the second sub-groove is 0.3 μm to 0.6 μm.
13. The IGBT device according to claim 11, characterized in that: The material of the body region is a silicon material including a first doping ion, the material of the emitter region is a silicon material including a second doping ion, the material of the gate dielectric layer includes silicon dioxide, and the material of the isolation dielectric layer includes borophosphosilicate glass.
14. The IGBT device according to claim 12, characterized in that: A sidewall of the second sub-trench obliquely intersects with the first main surface of the substrate.
15. The IGBT device according to claim 14, characterized in that: An included angle between a sidewall of the second sub-trench and the first main surface of the substrate is 70° to 85°.