Gallium nitride power device and preparation method thereof

Abstract

The invention provides a gallium nitride power device and a preparation method thereof. The gallium nitride power device comprises: a heterojunction; the gate structure is formed on the heterojunction; the transition layer is formed on the gate structure; the interlayer dielectric layer is formed on the transition layer; wherein the gate structure comprises a first dielectric layer adjacent to the transition layer, the first dielectric layer is made of silicon nitride, the interlayer dielectric layer is made of silicon oxide, and the transition layer is made of a material with low trap state density. According to the technical scheme, the advantages of the silicon oxide material and the silicon nitride material are combined, interface trap state charges are prevented from appearing at the combination position of the two materials, and meanwhile the production efficiency is improved through the Si-CMOS process production line.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and specifically provides a gallium nitride power device and a preparation method thereof. Background Art

[0002] The description in this section merely provides background information related to the disclosure of the present application and does not constitute prior art.

[0003] Figure 1 and Figure 2 The schematic diagram of the structure of a gallium nitride power device is shown. The gallium nitride power device in the prior art includes, from bottom to top: a substrate 11 (such as Silicon), a buffer layer 12 formed on the substrate 11, a channel layer 13 (for example, low-carbon GaN) formed on the buffer layer 12, a barrier layer 14 (for example, AlGaN or AlInGaN) formed on the channel layer 13, a gate structure 20 formed on the barrier layer 14, and two ohmic contacts located on both sides of the gate structure 20 and connected to the interface between the barrier layer 14 and the channel layer 13, the two ohmic contacts are used to form a source electrode 31 and a drain electrode 41, respectively. Among them, Figure 1 In the embodiment, the gate structure 20 includes a gate electrode 21 and a gate dielectric layer 22, and the gate electrode 21 is formed on the gate dielectric layer 22; Figure 2 In the embodiment, the gate structure 20 includes a gate electrode 21 , a gate dielectric layer 22 and a gate field plate 23 , and the gate field plate 23 includes a field plate metal 231 and a field plate dielectric 232 formed on the gate electrode 21 and the gate dielectric layer 22 .

[0004] Figure 2 The existing device preparation process in the invention generally includes the following steps:

[0005] Figure 3 EPI growth: epitaxially grow the following layers on the substrate 11 (Substrate) in sequence: buffer layer 12, channel layer 13 and barrier layer 14. Due to the polarization characteristics of the gallium nitride material, a layer of high-concentration two-dimensional electron gas (2D electron gas, referred to as 2DEG) will be generated within a few nanometers to tens of nanometers at the interface between the barrier layer 14 and the channel layer 13. This layer is the current channel for the HEMT device to conduct. The buffer layer 12 can use an AlN nucleation layer and an AlGaN / AlN superlattice structure or an AlN nucleation layer and a stepped aluminum content AlGaN multilayer structure. Of course, in some special application scenarios, it is not necessary to grow a buffer layer.

[0006] Figure 4 Dielectric DEP1: depositing a gate dielectric layer 22.

[0007] Figure 5Middle GO ET1: The first gate downward opening etch.

[0008] Figure 6 GM DEP and GM ET: The first layer of gate metal is deposited and then etched to form the gate electrode 21.

[0009] Figure 7 Dielectric DEP2: Deposition of field plate dielectric 232.

[0010] Figure 8 Middle Trench ET+TiN DEP: Trench etching, after etching is completed, field plate metal 231 is formed

[0011] Fig. 9 OHO ET: Ohmic contact opening etching.

[0012] Figure 2 OHM DEP and OHM ET: Finally, ohmic metal deposition is performed to form an ohmic contact, and a gate ohmic metal 24 , a source electrode 31 and a drain electrode 41 are formed by etching.

[0013] So far, it is completed Figure 2 The front-end manufacturing process of GaN power devices is shown in FIG. In order to further prepare the metal layer for forming the circuit, it is necessary to Figure 2 An interlayer dielectric layer 50 is deposited on the basis of the device shown. For the interlayer dielectric layer 50, two process routes are commonly used in the prior art, one is to manufacture on a traditional III-V semiconductor production line, and the other is to manufacture on a Si-CMOS process production line.

[0014] like Fig.10 As shown, GaN power devices are prepared on the III-V process production line, and the interlayer dielectric layer 50 is all made of silicon nitride as the dielectric material. However, the stress of silicon nitride material is large. The more layers of GaN power devices, the more difficult it is to control the internal stress, resulting in severe device warping or adverse effects in the subsequent packaging process. In addition, the process of the III-V production line is immature, and the wafer size that can be prepared is limited, currently mostly 6 inches, resulting in low production efficiency of GaN power devices.

[0015] In another scheme, a silicon-based gallium nitride power device is prepared on a Si-CMOS process production line, and the interlayer dielectric layer 50 is entirely made of silicon oxide as the dielectric material. However, in the prior art, silicon nitride is generally used as the dielectric material in the gate structure of a gallium nitride power device. When the silicon oxide in the gate structure is formed together with the silicon oxide in the interlayer dielectric layer, there are more trapped charges at the interface of the two dielectric materials due to the inconsistency of the body charge and interface charge of silicon nitride and silicon oxide. These charges are prone to dynamic behaviors such as capture / release when the device is operating at high voltage, which in turn affects the electron concentration in the gallium nitride material, affects parameters such as the resistance and saturation current of the device, and affects the reliability of the device.

[0016] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0017] Based on the above-mentioned defects of the prior art, the present application is used to solve the problems in the prior art. In order to achieve the above-mentioned purpose, the present application provides the following technical solutions: a gallium nitride power device, comprising: a heterojunction; a gate structure, the gate structure is formed on the heterojunction; a transition layer, the transition layer is formed on the gate structure; and an interlayer dielectric layer, the interlayer dielectric layer is formed on the transition layer; wherein the gate structure comprises a first dielectric layer adjacent to the transition layer, the first dielectric layer is composed of silicon nitride, the interlayer dielectric layer is composed of silicon oxide, and the transition layer is composed of a material with a low trap state density.

[0018] Preferably, the gate structure comprises a gate dielectric layer and a gate electrode, the transition layer is formed on the gate dielectric layer and the gate electrode, and the first dielectric layer constitutes at least a part of the gate dielectric layer.

[0019] Preferably, the gate structure includes a gate dielectric layer, a gate electrode and a field plate formed on the gate electrode and the gate dielectric layer, the transition layer is formed on the field plate, the field plate includes a field plate dielectric, and the first dielectric layer constitutes at least a part of the field plate dielectric.

[0020] Preferably, the transition layer is composed of one or more of aluminum nitride, aluminum oxide, silicon oxynitride, boron nitride, and mica.

[0021] Preferably, the interlayer dielectric layer is deposited by a Si-CMOS process.

[0022] Preferably, the interlayer dielectric layer comprises PE-SiO formed on the transition layer.2 layer and the TEOS-SiO formed on the 2 layer; or the interlayer dielectric layer includes the TEOS-SiO formed on the transition layer 2 layer.

[0023] The present application also provides a technical solution: a method for preparing a gallium nitride power device, comprising the steps of: forming a gate structure on a heterojunction, the gate structure comprising a first dielectric layer composed of silicon nitride, the first dielectric layer being located on a side of the gate structure away from the heterojunction or the dielectric in the gate structure only comprising the first dielectric layer; depositing a transition layer on the gate structure, the transition layer being composed of a material with a low trap state density; and depositing an interlayer dielectric layer on the transition layer, the interlayer dielectric layer being composed of silicon oxide.

[0024] Preferably, the gate structure comprises a gate dielectric layer and a gate electrode, the transition layer is formed on the gate dielectric layer, the gate electrode, the source electrode and the drain electrode, and the first dielectric layer constitutes at least a part of the gate dielectric layer.

[0025] Preferably, the gate structure includes a gate dielectric layer, a gate electrode and a field plate formed on the gate electrode and the gate dielectric layer, the transition layer is formed on the field plate, the source electrode and the drain electrode, the field plate includes a field plate dielectric, and the first dielectric layer constitutes at least a part of the field plate dielectric.

[0026] Preferably, the step of "depositing an interlayer dielectric layer on the transition layer" comprises: after the transition layer is deposited, depositing PE-SiO 2 , then TEOS-SiO is deposited on the PE-SiO2 2 , or after the transition layer is deposited, TEOS-SiO is deposited on the transition layer 2 .

[0027] By means of the above technical solution, the beneficial effects of the present application are:

[0028] (1) Silicon oxide is used as the dielectric material of the interlayer dielectric layer. After forming, the stress is small. After multi-layer interlayer dielectric deposition and circuit etching, the stress can still be controlled within an appropriate range to prevent severe warping or cracking during the packaging process. Silicon nitride is used as the dielectric material in the gate structure to increase the gate voltage swing and reduce gate leakage. Through the provision of a transition layer, the gallium nitride power device of the present invention can have the advantages of the above two materials at the same time, and avoid the interface trap state charge at the junction of the two materials, and prevent the interface trap state charge from being captured or released when the gate is working at a high voltage, thereby affecting the reliability of the device.

[0029] (2) Silicon nitride is used as the dielectric material in the gate structure, especially when all dielectric materials in the gate structure are made of silicon nitride, silicon nitride can be grown in situ in the MOCVD equipment used to form the channel layer and the barrier layer, thereby improving production efficiency and reducing production costs. Silicon oxide is used as the dielectric material of the interlayer dielectric layer, so that the gallium nitride power device of the present invention can be manufactured on the Si-CMOS process production line when the interlayer dielectric layer is deposited. The existing Si-CMOS process is mature, has a high production capacity, and can produce a wide range of wafer sizes. For gallium nitride power device wafers of sizes such as 6 inches, 8 inches, and 12 inches, corresponding Si-CMOS process production lines can be found for processing.

[0030] With reference to the following description and accompanying drawings, the specific embodiments of the present application are disclosed in detail, indicating the way in which the principles of the present application can be adopted. It should be understood that the embodiments of the present application are not therefore limited in scope. Within the scope of the spirit and clauses of the appended claims, the embodiments of the present application include many changes, modifications and equivalents.

[0031] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0032] It should be emphasized that the term “include / comprising” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are for explanation purposes only and are not intended to limit the scope of the present application in any way. In addition, the shapes and proportional dimensions of the components in the drawings are only for illustration purposes and are used to help understand the present application. They do not specifically limit the shapes and proportional dimensions of the components of the present application. Under the guidance of the present application, those skilled in the art can select various possible shapes and proportional dimensions to implement the present application according to specific circumstances. In the drawings:

[0034] Figure 1 A schematic structural diagram of a gallium nitride power device in the prior art is shown.

[0035] Figure 2 A schematic structural diagram of another gallium nitride power device in the prior art is shown.

[0036] Figure 3 Shows Figure 2 Schematic diagram of the structure of the EPI growth step in the preparation method of gallium nitride power devices.

[0037] Figure 4 Shows Figure 2 Schematic diagram of the structure of step Dielectric DEP1 in the method for preparing a gallium nitride power device.

[0038] Figure 5 Shows Figure 2 Schematic diagram of the structure of step GO ET1 in the method for preparing a gallium nitride power device.

[0039] Figure 6 Shows Figure 2 Schematic diagram of the structures of steps GM DEP and GM ET in the method for preparing gallium nitride power devices.

[0040] Figure 7 Shows Figure 2 Schematic diagram of the structure of step Dielectric DEP2 in the method for preparing a gallium nitride power device.

[0041] Figure 8 Shows Figure 2 Schematic diagram of the structure of the Trench ET+TiN DEP step in the method for preparing a gallium nitride power device.

[0042] Fig. 9 Shows Figure 2 Schematic diagram of the structure of step OHO ET in the method for preparing gallium nitride power devices.

[0043] Fig.10 A schematic structural diagram of another gallium nitride power device in the prior art is shown.

[0044] Fig.11 A schematic structural diagram of an embodiment of a gallium nitride power device of the present invention is shown.

[0045] Fig.12 A flow chart of an embodiment of a method for preparing a gallium nitride power device according to the present invention is shown.

[0046] List of reference numerals:

[0047] 100. GaN power device; 10. Heterojunction; 11. Substrate; 12. Buffer layer; 13. Channel layer; 14. Barrier layer; 20. Gate structure; 21. Gate electrode; 22. Gate dielectric layer; 23. Gate field plate; 231. Field plate metal; 232. Field plate dielectric; 24. Gate ohmic metal; 25. First dielectric layer; 30. Source structure; 31. Source electrode; 32. Source field plate; 40. Drain structure; 41. Drain electrode; 42. Drain field plate; 50. Interlayer dielectric layer; 51. PE-SiO2 layer; 52. TEOS-SiO2 layer; 60. Transition layer; 70. First metal circuit layer. DETAILED DESCRIPTION

[0048] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present invention and are not intended to limit the protection scope of the present invention.

[0049] It should be noted that, in the description of the present invention, the terms “first” and “second” are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0050] In addition, it should be noted that in the description of the present invention, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0051] The present invention provides a gallium nitride power device 100, comprising: a heterojunction 10; a gate structure 20, the gate structure 20 is formed on the heterojunction 10; a source electrode 31 and a drain electrode 41, the source electrode 31 and the drain electrode 41 are formed on the heterojunction 10 and are respectively located on both sides of the gate structure 20; a transition layer 60, the transition layer 60 is formed on the gate structure 20, the source electrode 31 and the drain electrode 41; and an interlayer dielectric layer 50, the interlayer dielectric layer 50 is formed on the transition layer 60; wherein the gate structure 20 comprises a first dielectric layer 25 adjacent to the transition layer 60, the first dielectric layer 25 is composed of silicon nitride, the interlayer dielectric layer 50 is composed of silicon oxide, and the transition layer 60 is composed of a material with a low trap state density.

[0052] like Fig.11 As shown, in one or more embodiments, from bottom to top, the heterojunction 10 may include a substrate 11 , a buffer layer 12 , a channel layer 13 , and a barrier layer 14 .

[0053] The substrate 11 may be a silicon substrate 11, or a composite substrate 11 made of sapphire, silicon carbide, gallium nitride, or silicon on insulator (SOI). The thickness of the substrate 11 may range from 50 μm to 3000 μm.

[0054] The buffer layer 12 can be selected according to the type of substrate 11, and its function is to regulate the stress of the epitaxial layer and isolate the substrate 11 from the subsequently epitaxial channel layer 13 and barrier layer 14. The buffer layer 12 can adopt an AlN nucleation layer and an AlGaN / AlN superlattice and a high-carbon GaN structure, or an AlN nucleation layer and a stepped aluminum content AlGaN multilayer and a high-carbon GaN structure. The thickness of the buffer layer 12 can range from 0 to 30 μm.

[0055] The channel layer 13 may be made of GaN, and its carbon content may be less than 1×10 17 cm -3 , the thickness ranges from 5nm-5000nm.

[0056] The barrier layer 14 includes at least one of AlN, GaN and InN. The Ga component ranges from 0 to 90%, the Al component ranges from 10 to 100%, and the In component ranges from 0 to 50%, based on the sum of the mass of the nitrides of Ga, Al and In being 100%. The sum of the components of Ga, Al and In being 100%, and the thickness of the barrier layer 14 ranges from 5 nm to 300 nm. Of course, in other optional embodiments, the barrier layer 14 may also be an AlGaN layer.

[0057] Continue reading Fig.11 In one or more embodiments, the gate structure 20 is formed on the barrier layer 14 and includes a gate dielectric layer 22, a gate electrode 21, and a gate field plate 23. The gate electrode 21 is formed on the gate dielectric layer 22, and the gate field plate 23 is formed on and covers the gate electrode 21 and the gate dielectric layer 22. Alternatively, the gate field plate 23 may be omitted.

[0058] Continue reading Fig.11 In an embodiment in which a gate field plate 23 is provided, the gate field plate 23 may include a field plate metal 231 and a field plate dielectric 232. The field plate metal 231 may be formed on the gate electrode 21 and electrically connected, or may be separated from the gate electrode 21 by a dielectric (e.g., the field plate dielectric 232). The field plate dielectric 232 may cover at least a portion of the gate electrode 21 and the gate dielectric layer 22. For example, a portion of the gate electrode 21 is located in a groove on the gate dielectric layer 22, and another portion is located above the gate dielectric layer 22. The field plate dielectric 232 may cover a portion of the gate electrode 21 located above the gate dielectric layer 22.

[0059] like Fig.11As shown, in one or more embodiments, the field plate structure 230 includes a layer of field plate metal 231 and a layer of field plate dielectric 232. Among them, the first dielectric layer 25 constitutes at least part of the field plate dielectric 232 and is made of silicon nitride (SiNx) material. Silicon nitride (SiNx) has good chemical stability and high dielectric constant, and can better increase the gate voltage swing and reduce gate leakage. Exemplarily, the field plate dielectric 232 may include only the first dielectric layer 25, forming a field plate dielectric 232 composed of a single silicon nitride (SiNx) material; or the first dielectric layer 25 is formed as a part of the field plate dielectric 232 adjacent to the interlayer dielectric layer 50, and the part not adjacent to the interlayer dielectric layer 50 may include other non-silicon nitride (SiNx) materials to form a field plate dielectric 232 composed of a composite material. In an alternative embodiment, the gate field plate 23 may include multiple layers stacked sequentially from bottom to top, and each layer of the gate field plate 23 includes a field plate metal 231 and a field plate dielectric 232, wherein the uppermost field plate dielectric 232, that is, away from the heterojunction 10 and adjacent to the interlayer dielectric layer 50, includes a first dielectric layer 25. Similarly, the first dielectric layer 25 may constitute at least a portion of the uppermost field plate dielectric 232. Except that the first dielectric layer 25 is silicon nitride (SiNx), the remaining field plate dielectrics 232 may be configured as other suitable materials according to actual needs.

[0060] In an embodiment without a field plate, the gate dielectric layer 22 may also include a composite of multiple layers of dielectric materials, wherein the uppermost dielectric layer, that is, the dielectric layer away from the heterojunction 10 and adjacent to the interlayer dielectric layer 50, is the first dielectric layer 25. In an alternative embodiment, the gate dielectric layer 22 may also be configured to include only one dielectric layer, which is the first dielectric layer 25. Similarly, the first dielectric layer 25 in the gate dielectric layer 22 is configured to be made of silicon nitride (SiNx) material, which can also better increase the gate voltage swing and reduce gate leakage. When the gate dielectric layer 22 includes multiple layers of dielectrics, except that the first dielectric layer 25 is silicon nitride (SiNx), the remaining dielectrics can be configured as other suitable materials according to actual needs.

[0061] Continue reading Fig.11 The gallium nitride power device 100 of the present invention further includes a transition layer 60. The transition layer 60 is formed on the gate structure 20 and covers the first dielectric layer 25 to prevent silicon oxide dielectric material from being deposited on the first dielectric layer 25 composed of silicon nitride (SiNx).

[0062] Continue reading Fig.11In one or more embodiments, the gallium nitride power device 100 further includes a source structure 30 and a drain structure 40 respectively disposed on both sides of the gate structure 20. In one or more embodiments, the source structure 30 may include a source field plate 32, and the field plate dielectric of the source field plate 32 may be deposited together with the field plate dielectric 232 in the gate structure 20. Similarly, the drain structure 40 may also include a drain field plate 42, and the field plate dielectric of the drain field plate 42 may be deposited together with the field plate dielectric 232 in the gate structure 20. The source electrode 31 and the drain electrode 41 both extend through the field plate dielectric 232, the gate dielectric layer 22, and are in ohmic contact with the barrier layer 14. Alternatively, when the field plate is not disposed in the gate structure 20, correspondingly, the field plate is not disposed in the source structure 30 and the drain structure 40, and the source electrode 31 and the drain electrode 41 both extend through the gate dielectric layer 22 and are in ohmic contact with the barrier layer 14.

[0063] Furthermore, when a field plate is set in the source region or the drain region and the field plate dielectric in the source field plate 32 and / or the drain field plate 42 is deposited together with the field plate dielectric 232 in the gate structure 20, the transition layer 60 also extends to the corresponding source region and / or the drain region to cover the first dielectric layer 25 in the source field plate 32 and / or the drain field plate 42.

[0064] In one or more embodiments, the first dielectric layer 25 needs to be configured as a dielectric material with a low trap state density, including but not limited to aluminum nitride, aluminum oxide, silicon oxynitride, boron nitride, and mica. The first dielectric layer 25 can be composed of one or more of them, that is, the first dielectric layer 25 can be composed of a single material or a composite structure composed of multiple materials. Alternatively, the first dielectric layer 25 can also be composed of other materials characterized by a low trap state density.

[0065] Continue reading Fig.11 In one or more embodiments, the gallium nitride power device 100 further includes an interlayer dielectric layer 50. The interlayer dielectric layer 50 covers the source structure 30, the drain structure 40 and the gate structure 20. The interlayer dielectric layer 50 can be deposited on a Si-CMOS production line by an IDL process. The interlayer dielectric layer 50 is mainly composed of silicon oxide. Due to the presence of the transition layer 60, the contact interface between the first dielectric layer 25 and the interlayer dielectric layer 50 that may originally exist is separated by the transition layer 60, so that the gallium nitride power device 100 of the present invention can have the advantages of two materials (i.e., the dielectric material in the gate structure 20 is silicon nitride, and the dielectric material in the interlayer dielectric layer 50 is silicon oxide), and avoid the interface trap state charge at the junction of the two materials, and prevent the interface trap state charge from being captured or released when the gate is working at a high voltage, thereby affecting the reliability of the device.

[0066] In one or more embodiments, the interlayer dielectric layer 50 may include a PE-SiO2 layer 51 (plasma enhanced silicon oxide) formed on the transition layer 60 by an ILD process and a TEOS-SiO2 layer 52 (tetraethyl orthosilicate) formed on the transition layer 60. Through the above-mentioned configuration, the interlayer dielectric layer 50 can effectively reduce the parasitic capacitance between the metal and the substrate 11, and improve the parasitic field effect formed by the metal crossing different regions. Alternatively, the interlayer dielectric layer 50 may also only include a TEOS-SiO2 layer 52 formed on the transition layer 60. After the interlayer dielectric layer 50 is deposited, CMP polishing may be further performed, and then the first metal line layer 70 above the heterojunction 10 is prepared.

[0067] The present invention also provides a method for preparing a gallium nitride power device. The method of the present invention can be used to prepare the gallium nitride power device 100 described above.

[0068] After the preparation method starts, step S1 is performed first, that is, providing a heterojunction 10, forming a gate structure 20 on the heterojunction 10, and the gate structure 20 includes a first dielectric layer 25 composed of silicon nitride. The first dielectric layer 25 is located on a side of the gate structure 20 away from the heterojunction 10, or the dielectric in the gate structure 20 only includes the first dielectric layer 25.

[0069] In one or more embodiments, the structure of the heterojunction 10 is as follows: Figure 3 Alternatively, the heterojunction 10 may also be configured as other suitable structures.

[0070] In one or more embodiments, the gate structure 20 includes a gate dielectric layer 22 and a gate electrode 21, a transition layer 60 is formed on the gate dielectric layer 22 and the gate electrode 21, and the first dielectric layer 25 constitutes at least a portion of the gate dielectric layer 22. In an alternative embodiment, the gate structure 20 includes a gate dielectric layer 22, a gate electrode 21, and a gate field plate 23 formed on the gate electrode 21 and the gate dielectric layer 22, the transition layer 60 is formed on the gate field plate 23, the gate field plate 23 includes a field plate dielectric 232, and the first dielectric layer 25 constitutes at least a portion of the field plate dielectric 232. In an alternative embodiment, a source field plate 32 is provided in the source region, a drain field plate 42 is provided in the drain region, and the transition layer 60 is also extended and formed on the source field plate 32 and the drain field plate 42 to cover the first dielectric layer 25 of the source field plate 32 and the drain field plate 42.

[0071] Then, step S2 is performed, that is, a transition layer 60 is deposited on the gate structure 20. The transition layer 60 is made of a material with a low trap state density, such as aluminum nitride, aluminum oxide, silicon oxynitride, boron nitride, mica, etc. The transition layer 60 can be made of one or more of them. The transition layer 60 covers the first dielectric layer 25 to prevent the first dielectric layer 25 from contacting with silicon oxide in other dielectric layers, thereby forming more trapped state charges at the contact interface and affecting the reliability of the device.

[0072] Finally, step S3 is performed, that is, an interlayer dielectric layer 50 is deposited on the transition layer 60, and the interlayer dielectric layer 50 is composed of silicon oxide. Silicon oxide is used as the dielectric material of the interlayer dielectric layer 50, and its stress after forming is small. After multi-layer interlayer dielectric deposition and circuit etching, the stress can still be controlled within a suitable range to prevent the device from being severely warped or broken during the packaging process. In one or more embodiments, step S3 can be that after the transition layer 60 is deposited, PE-SiO2 is deposited on the transition layer 60. Then TEOS-SiO2 is deposited on the PE-SiO2. Alternatively, after the transition layer 60 is deposited, TEOS-SiO2 can be directly deposited on the transition layer 60. Alternatively, the interlayer dielectric layer 50 composed of silicon oxide can also be deposited on the transition layer 60 in other suitable ways.

[0073] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A gallium nitride power device, characterized in that: The gallium nitride power device comprises: Heterojunction; a gate structure formed on the heterojunction; a transition layer formed on the gate structure; and an interlayer dielectric layer, the interlayer dielectric layer being formed on the transition layer; The gate structure includes a first dielectric layer adjacent to the transition layer, the first dielectric layer is made of silicon nitride, the interlayer dielectric layer is made of silicon oxide, and the transition layer is made of a material with a low trap state density.

2. The gallium nitride power device according to claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate electrode, and the transition layer is formed on the gate dielectric layer and the gate electrode. The first dielectric layer constitutes at least a portion of the gate dielectric layer.

3. The gallium nitride power device according to claim 1, characterized in that: The gate structure includes a gate dielectric layer, a gate electrode, and a gate field plate formed on the gate electrode and the gate dielectric layer, wherein the transition layer is formed on the gate field plate. The gate field plate includes a field plate dielectric, and the first dielectric layer constitutes at least a portion of the field plate dielectric.

4. The gallium nitride power device according to claim 1, characterized in that: The transition layer is composed of one or more of aluminum nitride, aluminum oxide, silicon oxynitride, boron nitride, and mica.

5. The gallium nitride power device according to claim 1, characterized in that: The interlayer dielectric layer is deposited by Si-CMOS process.

6. The gallium nitride power device according to claim 1, characterized in that: The interlayer dielectric layer includes a PE-SiO2 layer formed on the transition layer and a TEOS-SiO2 layer formed on the transition layer; or The interlayer dielectric layer only includes the TEOS-SiO2 layer formed on the transition layer.

7. A method for preparing a gallium nitride power device, characterized in that: The preparation method comprises: forming a gate structure on the heterojunction, the gate structure comprising a first dielectric layer composed of silicon nitride, the first dielectric layer being located on a side of the gate structure away from the heterojunction or the dielectric in the gate structure comprising only the first dielectric layer; Depositing a transition layer on the gate structure, wherein the transition layer is composed of a material with low trap state density; An interlayer dielectric layer is deposited on the transition layer, wherein the interlayer dielectric layer is made of silicon oxide.

8. The method for preparing a gallium nitride power device according to claim 7, characterized in that: The gate structure includes a gate dielectric layer and a gate electrode, and the transition layer is formed on the gate dielectric layer and the gate electrode. The first dielectric layer constitutes at least a portion of the gate dielectric layer.

9. The method for preparing a gallium nitride power device according to claim 8, characterized in that: The gate structure includes a gate dielectric layer, a gate electrode, and a gate field plate formed on the gate electrode and the gate dielectric layer, wherein the transition layer is formed on the gate field plate. The gate field plate includes a field plate dielectric, and the first dielectric layer constitutes at least a portion of the field plate dielectric.

10. The method for preparing a gallium nitride power device according to claim 7, characterized in that: The step of "depositing an interlayer dielectric layer on the transition layer" includes: After the transition layer is deposited, PE-SiO2 is deposited on the transition layer, and then TEOS-SiO2 is deposited on the PE-SiO2. Alternatively, after the transition layer is deposited, TEOS-SiO2 is deposited on the transition layer.

Images