Ferroelectric field effect transistor, preparation method and memory chip
By using a ferroelectric field effect transistor with a stacked structure with intercalation in a hafnium-based FeFET memory, leakage current is suppressed, and the problem of insufficient memory durability characteristics is solved, and a higher number of programming/erases is achieved.
Patent Information
- Application Number
- CN202411815866.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-04-15
AI Technical Summary
The lack of durability characteristics of hafnium-based FeFET memory limits its application in scenarios with high programming/erase times, mainly due to charge trapping and new trap generation in the gate structure.
By suppressing leakage current in the ferroelectric field effect transistor, a stacked structure with intercalation layers, including a first ferroelectric layer, a thin film intercalation layer and a second ferroelectric layer, is adopted to improve the durability characteristics of the device.
Effectively suppress the leakage current of the device and improve its durability characteristics, making it suitable for high programming/erase times.
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Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor device manufacturing, and in particular to a ferroelectric field effect transistor and a manufacturing method thereof, and a memory chip. Background Art
[0002] Compared with traditional Flash memory and other types of new memory (such as PCM memory, RRAM memory, hafnium-based FeRAM memory), hafnium-based FeFET memory has low write voltage, fast read and write speed, and can achieve non-volatility. In addition, hafnium-based FeFET memory is compatible with CMOS process, has simple structural units, can achieve multi-value storage, 3D integration, and has many advantages.
[0003] However, the insufficient durability of hafnium-based FeFETs limits their application in scenarios with high programming / erasing times. Therefore, it is urgent to provide a device structure and preparation method that can improve durability. The main reason for the degradation of durability is charge capture and the generation of new traps in the gate structure. At present, in order to suppress the charge capture behavior in the gate structure, the gate leakage current can be suppressed. In this way, the device durability characteristics can be improved by suppressing the gate leakage current. Summary of the invention
[0004] To solve the above problems, the present application provides a ferroelectric field effect transistor and a preparation method, and a memory chip, which improve the durability characteristics of the device by suppressing leakage current.
[0005] This application adopts the following technical solutions:
[0006] In a first aspect, a ferroelectric field effect transistor is provided, the ferroelectric field effect transistor comprising:
[0007] A substrate having a source, a drain, and a channel region between the source and the drain;
[0008] and, an interface layer, a stack having an intercalation layer, and a top electrode, which are located above the channel region and are sequentially arranged in a direction away from the substrate;
[0009] The stacked layer with the intercalation layer comprises: a first ferroelectric layer, a thin film intercalation layer and a second ferroelectric layer which are arranged in sequence in a direction away from the substrate.
[0010] Optionally, the material of the interface layer is one of silicon dioxide, silicon oxynitride, aluminum oxynitride and aluminum oxide.
[0011] Optionally, the material of the first ferroelectric layer and the material of the second ferroelectric layer are doped hafnium oxide-based ferroelectric materials.
[0012] Optionally, the doping is at least one of zirconium, silicon, aluminum, lanthanum, cerium, yttrium, gadolinium, strontium and scandium.
[0013] Optionally, the material of the thin film intercalation is one of silicon dioxide, titanium dioxide, aluminum oxide, hafnium dioxide, zirconium dioxide, and lanthanum oxide.
[0014] Optionally, the material of the top electrode is one of titanium nitride, tantalum nitride, polysilicon, tungsten, and aluminum.
[0015] In a second aspect, a method for preparing a ferroelectric field effect transistor is provided, the method comprising:
[0016] Providing a substrate; the substrate has a source electrode, a drain electrode, and a channel region between the source electrode and the drain electrode;
[0017] Forming a stacked structure; the stacked structure includes: an interface layer located above the channel region and arranged in sequence in a direction away from the substrate, a stacked layer having an intercalation layer, and a top electrode;
[0018] The stacked layer with the intercalation layer comprises: a first ferroelectric layer, a thin film intercalation layer and a second ferroelectric layer.
[0019] Optionally, the preparation method comprises:
[0020] Providing a substrate having a source, a drain, and a channel region between the source and the drain;
[0021] growing an interface layer on the channel region;
[0022] sequentially growing a first ferroelectric layer, a thin film intercalation layer, and a second ferroelectric layer on the interface layer;
[0023] growing a top electrode on the second ferroelectric layer;
[0024] Annealing treatment and photolithography and etching treatment are performed in sequence to obtain a ferroelectric field effect transistor.
[0025] In a third aspect, a memory chip is provided, the memory portion of which is composed of the above-mentioned ferroelectric field effect transistor.
[0026] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects:
[0027] The ferroelectric field effect transistor provided by the present application comprises: a substrate having a source, a drain, and a channel region between the source and the drain; and an interface layer, a stack having an intercalation layer, and a top electrode, which are located above the channel region and arranged in sequence in a direction away from the substrate; wherein the stack having an intercalation layer comprises: a first ferroelectric layer, a thin film intercalation layer, and a second ferroelectric layer, which are arranged in sequence in a direction away from the substrate. The ferroelectric field effect transistor proposed by the present application can suppress device leakage current and improve durability characteristics. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0029] Figure 1 A schematic structural diagram of a ferroelectric field effect transistor according to an embodiment of the present application is shown;
[0030] Figure 2 A flow chart showing a preparation method according to an embodiment of the present application;
[0031] Figure 3 A schematic structural diagram after providing a substrate in a preparation method according to an embodiment of the present application is shown;
[0032] Figure 4 A schematic diagram of the structure after the interface layer is grown in the preparation method of one embodiment of the present application is shown;
[0033] Figure 5 A schematic diagram of the structure after growing a stacked layer with an intercalated layer in a preparation method according to an embodiment of the present application is shown;
[0034] Figure 6 A schematic diagram of the structure after the top electrode is grown in the preparation method of one embodiment of the present application is shown;
[0035] Figure 7 A schematic structural diagram of a ferroelectric field effect transistor obtained in a preparation method according to an embodiment of the present application is shown. DETAILED DESCRIPTION
[0036] The exemplary embodiments of the present application will be described in more detail below. However, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully communicated to those skilled in the art.
[0037] The disclosure of the present invention provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described in the present invention. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplicity and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.
[0038] Generally, the terms may be understood at least in part based on the usage of the above invention. For example, the term "one or more" used in the present invention depends at least in part on the above invention, and may be used to describe any component, structure or feature in a singular form, or may be used to describe a combination of components, structures or features in a plural form. Similarly, terms such as "one", "an" or "the" may also be understood at least in part based on the above invention as conveying singular usage or conveying plural usage. In addition, the term "based on..." may be understood as not necessarily intended to convey a set of exclusive factors, but may alternatively, at least in part depending on the context, allow for the presence of additional factors that do not necessarily have to be explicitly described.
[0039] It should be noted that, in the description of the present application, the meanings of the terms "on", "over", "above", "over", etc. should be interpreted in the broadest way, meaning that the description containing these terms is interpreted as "the component can be set on another component in direct contact, or there can be intermediate components or layers between the components."
[0040] For ease of description, the present application may also use spatially relative terms such as "under", "beneath", "below", "under", "upper", "lower", etc. to describe the relationship of one component to another component shown in the drawings. In addition to the orientations described in the drawings, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways, and the spatially relative descriptions used in the present application can be interpreted accordingly.
[0041] An embodiment of the present application provides a ferroelectric field effect transistor. Figure 1 FIG. 1 shows a schematic diagram of the structure of a ferroelectric field effect transistor proposed in one embodiment of the present application. Figure 1 The ferroelectric field effect transistor may include: a substrate 10 having a source 101, a drain 102, and a channel region (not shown in the figure) between the source and the drain; and an interface layer 11 located above the channel region and arranged in sequence along a direction away from the substrate 10, a stack 12 with an intercalation layer, and a top electrode 13; wherein the stack 12 with an intercalation layer includes: a first ferroelectric layer 121, a thin film intercalation layer 122, and a second ferroelectric layer 123 arranged in sequence along a direction away from the substrate 10.
[0042] In this embodiment, the substrate 10 has a source doping region and a drain doping region. The specific materials and doping types of the substrate 10, the source doping region and the drain doping region are not specifically limited. As long as the substrate 10 can provide a ferroelectric field effect transistor and can form the source 101 and the drain 102, the material and doping type are all acceptable.
[0043] For example, the material of the substrate 10 may be a material with semiconductor properties (such as single crystal silicon, etc.), and the doping type of the substrate 10 may be P-type; then the corresponding source doping region and drain doping region are doped with N-type impurities, such as phosphorus or arsenic. Conversely, the material of the substrate 10 may be a material with semiconductor properties (such as single crystal silicon, etc.), and the doping type of the substrate 10 may be N-type; then the corresponding source doping region 11 and drain doping region 12 are doped with P-type impurities, such as gallium or indium.
[0044] A metal electrode is formed on the source doping region, and the metal electrode forms the source (S) 101 of the ferroelectric field effect transistor. A metal electrode is formed on the drain doping region, and the metal electrode forms the drain (D) 102 of the ferroelectric field effect transistor.
[0045] The substrate 10 also has a channel region between the source 101 and the drain 102 .
[0046] In some embodiments, the material of the interface layer 11 is one of silicon dioxide, silicon oxynitride, aluminum oxynitride, and aluminum oxide.
[0047] The material of the interface layer 11 can be silicon dioxide or aluminum oxide. In order to further improve the quality of the interface layer 11, the SiO2 interface layer 11 material can be nitrided or ammonia plasma annealed to form SiON; the Al2O3 interface layer 11 material can be nitrided or ammonia plasma annealed to form AlON. The interface layer 11 of SiON or AlON material can passivate traps near the interface layer (including the interior of the interface layer, the interface between the interface layer and the substrate, and the interface between the interface layer and the ferroelectric layer), reduce the interface state density, thereby improving the quality of the interface layer and further improving the durability characteristics of the device.
[0048] In some embodiments, the material of the first ferroelectric layer 121 and the second ferroelectric layer 123 is a hafnium oxide-based ferroelectric material with doping, and the doping is at least one of zirconium, silicon, aluminum, lanthanum, cerium, yttrium, gadolinium, strontium, and scandium.
[0049] The materials of the first ferroelectric layer 121 and the second ferroelectric layer 123 are both doped hafnium oxide-based ferroelectric materials. The doping of the first ferroelectric layer 121 and the second ferroelectric layer 123 can be the same or different.
[0050] For example, the materials of the first ferroelectric layer 121 and the second ferroelectric layer 123 can both be Hf x Zr 1-x O2; the material of the first ferroelectric layer 121 may be Hf x Zr 1-x O2, the material of the second ferroelectric layer 123 can be Hf x La 1-x O2; the material of the first ferroelectric layer 121 may be Al:Hfx Zr 1-x O2, the material of the second ferroelectric layer 123 can be Hf x La 1-x O2, etc.
[0051] In addition to including at least one of zirconium, silicon, aluminum, lanthanum, cerium, yttrium, gadolinium, strontium, and scandium, the doping may also include at least one of nitrogen, iron, lutetium, praseodymium, germanium, neodymium, magnesium, barium, indium, gallium, calcium, carbon, etc.
[0052] In some embodiments, the material of the thin film intercalation layer 122 is one of silicon dioxide, titanium dioxide, aluminum oxide, hafnium dioxide, zirconium dioxide, and lanthanum oxide.
[0053] A thin film intercalation layer 122 of a certain thickness can be introduced at any position inside a ferroelectric layer of any thickness (including the first ferroelectric layer 121 and the second ferroelectric layer 123). The thin film intercalation layer 122 interrupts the growth of ferroelectric material grains and inhibits the formation of leakage current paths, thereby improving the durability of the device.
[0054] For example, Al2O3 dielectric materials are compatible with silicon-based semiconductor CMOS processes and can be deposited using the same atomic layer deposition method as HZO, enabling continuous operation in the same chamber.
[0055] In some embodiments, the material of the top electrode 13 is one of titanium nitride, tantalum nitride, polysilicon, tungsten, and aluminum.
[0056] The material of the top electrode (G) 13 can at least meet the conductivity requirement and can be formed on a semiconductor, such as TiN, TaN, polysilicon, W or Al.
[0057] The ferroelectric field effect transistor provided by the present application comprises a substrate having a source, a drain, and a channel region between the source and the drain; and an interface layer, a stack having an intercalation layer, and a top electrode layer, which are arranged in sequence on the channel region and away from the substrate; wherein the stack having an intercalation layer comprises: a first ferroelectric layer, a thin film intercalation layer, and a second ferroelectric layer, which are arranged in sequence in a direction away from the substrate. The ferroelectric field effect transistor proposed by the present application can suppress device leakage current and improve durability characteristics.
[0058] The embodiment of the present application also provides a method for preparing a ferroelectric field effect transistor, which is used to prepare the ferroelectric field effect transistor in the above embodiment. Figure 2 The flowchart of the method for preparing a ferroelectric field effect transistor according to one embodiment of the present application is shown. Figure 2 , the preparation method comprises the following steps:
[0059] S201, providing a substrate; the substrate having a source electrode, a drain electrode, and a channel region between the source electrode and the drain electrode;
[0060] S202, forming a stacked structure; the stacked structure includes: an interface layer located above the channel region and arranged in sequence along a direction away from the substrate, a stacked layer with an intercalation layer, and a top electrode; wherein the stacked layer with an intercalation layer includes: a first ferroelectric layer, a thin film intercalation layer, and a second ferroelectric layer.
[0061] Figures 3 to 7 The process steps of the method for preparing a ferroelectric field effect transistor are shown. Figures 3 to 7 The above-mentioned preparation method is described.
[0062] Figure 3 A schematic diagram of the structure after providing a substrate is shown.
[0063] The substrate 10 has a source doping region and a drain doping region. The specific materials and doping types of the substrate 10, the source doping region and the drain doping region are not specifically limited. Any material and doping type that can provide a substrate 10 of a ferroelectric field effect transistor and form a source 101 and a drain 102 are acceptable.
[0064] For example, the material of the substrate 10 may be a material with semiconductor properties (such as single crystal silicon, etc.), and the doping type of the substrate 10 may be P-type; then the corresponding source doping region and drain doping region are doped with N-type impurities, such as phosphorus or arsenic. Conversely, the material of the substrate 10 may be a material with semiconductor properties (such as single crystal silicon, etc.), and the doping type of the substrate 10 may be N-type; then the corresponding source doping region 11 and drain doping region 12 are doped with P-type impurities, such as gallium or indium.
[0065] A metal electrode is formed on the source doping region, and the metal electrode forms the source (S) 101 of the ferroelectric field effect transistor. A metal electrode is formed on the drain doping region, and the metal electrode forms the drain (D) 102 of the ferroelectric field effect transistor.
[0066] The substrate 10 also has a channel region between the source 101 and the drain 102 .
[0067] Figure 4 A schematic diagram of the structure after the interface layer is grown is shown.
[0068] An interface layer 11 is grown on the channel region. The material of the interface layer 11 may be SiO2, SiON, AlON, Al2O3, etc.
[0069] The material of the interface layer 11 can be silicon dioxide or aluminum oxide. In order to further improve the quality of the interface layer 11, the SiO2 interface layer 11 material can be nitrided or ammonia plasma annealed to form SiON; the Al2O3 interface layer 11 material can be nitrided or ammonia plasma annealed to form AlON. The interface layer 11 of SiON or AlON material can passivate traps near the interface layer (including the interior of the interface layer, the interface between the interface layer and the substrate, and the interface between the interface layer and the ferroelectric layer), reduce the interface state density, thereby improving the quality of the interface layer and further improving the durability characteristics of the device.
[0070] The method of growing the interface layer 11 may include but is not limited to: ozone oxidation, atomic layer deposition, thermal oxygen oxidation, in-situ steam oxidation, etc. The method of growing the interface layer 11 may be selected according to the actual situation. For example, when the material of the interface layer 11 is SiO2, the interface layer 11 may be grown by ozone oxidation.
[0071] Figure 5 A schematic diagram of the structure after growing a stack with an intercalated layer is shown.
[0072] A first ferroelectric layer, a thin film intercalation layer and a second ferroelectric layer are sequentially grown on the interface layer 11 .
[0073] The materials of the first ferroelectric layer 121 and the second ferroelectric layer 123 are both doped hafnium oxide-based ferroelectric materials. The doping of the first ferroelectric layer 121 and the second ferroelectric layer 123 can be the same or different.
[0074] For example, the materials of the first ferroelectric layer 121 and the second ferroelectric layer 123 can both be Hf x Zr 1-x O2; the material of the first ferroelectric layer 121 may be Hf x Zr 1-x O2, the material of the second ferroelectric layer 123 can be Hf x La 1-x O2; the material of the first ferroelectric layer 121 may be Al:Hf x Zr 1-x O2, the material of the second ferroelectric layer 123 can be Hf x La 1-x O2, etc.
[0075] In addition to including at least one of zirconium, silicon, aluminum, lanthanum, cerium, yttrium, gadolinium, strontium, and scandium, the doping may also include at least one of nitrogen, iron, lutetium, praseodymium, germanium, neodymium, magnesium, barium, indium, gallium, calcium, carbon, etc.
[0076] In some embodiments, the material of the thin film intercalation layer 122 is one of silicon dioxide, titanium dioxide, aluminum oxide, hafnium dioxide, zirconium dioxide, and lanthanum oxide.
[0077] A thin film intercalation layer 122 of a certain thickness can be introduced at any position inside a ferroelectric layer of any thickness (including the first ferroelectric layer 121 and the second ferroelectric layer 123). The thin film intercalation layer 122 interrupts the growth of ferroelectric material grains and inhibits the formation of leakage current paths, thereby improving the durability of the device.
[0078] The first ferroelectric layer 121, the thin film intercalation layer 122 and the second ferroelectric layer 123 can be grown by the method in the prior art according to the actual situation. For example, the first ferroelectric layer 121, the thin film intercalation layer 122 and the second ferroelectric layer 123 can be grown in sequence by atomic layer deposition. Al2O3 dielectric material is compatible with silicon-based semiconductor CMOS process and can be used with Hf x Zr 1-x O2 is deposited using the same atomic layer deposition method, which can achieve continuous operation in the same chamber.
[0079] Figure 6 A schematic diagram of the structure after the top electrode is grown is shown.
[0080] A top electrode 13 is grown on the second ferroelectric layer 123. The material of the top electrode (G) 13 can at least meet the conductivity requirement and can be formed on a semiconductor, such as TiN, TaN, polysilicon, W or Al.
[0081] The top electrode 13 may be grown by a method in the prior art according to actual conditions. For example, the top electrode 13 may be grown by a physical vapor deposition method.
[0082] Figure 7 A schematic structural diagram of the obtained ferroelectric field effect transistor is shown.
[0083] It can be annealed for a certain time at a certain temperature and in a certain atmosphere, and then etched by spin coating photoresist, exposure, development and other operations to obtain a ferroelectric field effect transistor.
[0084] An embodiment of the present application also provides a memory chip, the memory part of which is composed of the above-mentioned ferroelectric effect transistor.
[0085] The above is only a specific implementation of the present application. Under the above teachings of the present application, those skilled in the art can make other improvements or modifications based on the above embodiments. Those skilled in the art should understand that the above specific description is only to better explain the purpose of the present application, and the protection scope of the present application shall be based on the protection scope of the claims.
[0086] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.
Claims
1. A ferroelectric field effect transistor, characterized in that: The ferroelectric field effect transistor comprises: A substrate having a source, a drain, and a channel region between the source and the drain; and, an interface layer, a stack having an intercalation layer, and a top electrode, which are located above the channel region and are sequentially arranged in a direction away from the substrate; The stacked layer with the intercalation layer comprises: a first ferroelectric layer, a thin film intercalation layer and a second ferroelectric layer which are arranged in sequence in a direction away from the substrate.
2. The ferroelectric field effect transistor according to claim 1, characterized in that: The material of the interface layer is one of silicon dioxide, silicon oxynitride, aluminum oxynitride and aluminum oxide.
3. The ferroelectric field effect transistor according to claim 1, characterized in that: The material of the first ferroelectric layer and the material of the second ferroelectric layer are doped hafnium oxide-based ferroelectric materials.
4. The ferroelectric field effect transistor according to claim 3, characterized in that: The doping is at least one of zirconium, silicon, aluminum, lanthanum, cerium, yttrium, gadolinium, strontium and scandium.
5. The ferroelectric field effect transistor according to claim 1, characterized in that: The material of the thin film intercalation layer is one of silicon dioxide, titanium dioxide, aluminum oxide, hafnium dioxide, zirconium dioxide and lanthanum oxide.
6. The ferroelectric field effect transistor according to claim 1, characterized in that: The material of the top electrode is one of titanium nitride, tantalum nitride, polysilicon, tungsten and aluminum.
7. A method for preparing a ferroelectric field effect transistor, characterized in that: The preparation method comprises: Providing a substrate; the substrate having a source electrode, a drain electrode, and a channel region between the source electrode and the drain electrode; Forming a stacked structure; the stacked structure comprises: an interface layer located above the channel region and arranged in sequence in a direction away from the substrate, a stacked layer having an intercalation layer, and a top electrode; Wherein, the stacked layer with the intercalation layer comprises: a first ferroelectric layer, a thin film intercalation layer and a second ferroelectric layer.
8. The method for preparing a ferroelectric field effect transistor according to claim 7, characterized in that: The preparation method comprises: Providing the substrate having the source, the drain, and the channel region between the source and the drain; growing the interface layer on the channel region; sequentially growing the first ferroelectric layer, the thin film intercalation layer and the second ferroelectric layer on the interface layer; growing the top electrode on the second ferroelectric layer; Annealing treatment and photolithography and etching treatment are performed in sequence to obtain the ferroelectric field effect transistor.
9. A memory chip, characterized in that: The storage part of the memory chip is composed of the ferroelectric field effect transistor according to any one of claims 1 to 6.