Enhanced HEMT structure capable of reducing grid electric leakage and implementation method

Abstract

The invention discloses an enhanced HEMT (High Electron Mobility Transistor) structure for reducing grid electric leakage and an implementation method, and the structure comprises a substrate, and a buffer layer, a UGaN layer, an ALGaN layer, a PGaN layer and a composite grid metal layer which are sequentially stacked on the surface of the substrate along the longitudinal direction, wherein the etching rate of the part, close to the PGaN layer, of the composite gate metal layer is higher than that of the part, far away from the PGaN layer, of the composite gate metal layer, so that the transverse sectional area of the part, close to the PGaN layer, of the etched composite gate metal layer is smaller than that of the part, far away from the PGaN layer, of the etched composite gate metal layer. The preparation process flow of the whole structure is simple, and a PGAN layer extension part formed through side wall deposition and side wall overall etching in a traditional process flow is avoided, so that plasma damage caused in the side wall dielectric deposition process is eliminated, and etching damage to the PGAN layer in the side wall process is eliminated.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device preparation, and in particular to an enhanced HEMT structure for reducing gate leakage and a method for realizing the same. Background Art

[0002] HEMT stands for high electron mobility transistor. Currently, the gate of the gallium nitride enhancement mode HEMT device mostly adopts a design in which the gate metal size is smaller than the PGaN size. This can reduce the electric field on the side wall of the Schottky junction where the gate metal contacts the PGaN. The PGaN protruding from the gate metal can also reduce the electric field at the gate corner, thereby reducing gate leakage and increasing gate reliability.

[0003] At present, the gate process generally adopts Figure 1 However, the existing gate process has complicated process steps, such as Figure 1 As shown, the PGaN interface is repeatedly damaged by plasma during dielectric deposition and etching, which results in more interface states at the PGaN interface and affects the reliability of the gate. Summary of the invention

[0004] In order to overcome the defects in the prior art, the embodiments of the present invention provide an enhanced HEMT structure and an implementation method for reducing gate leakage, which are used to solve one or more of the above problems.

[0005] The embodiment of the present application discloses: an enhanced HEMT structure for reducing gate leakage, comprising a substrate, and a buffer layer, a UGaN layer, an ALGaN layer, a PGaN layer and a composite gate metal layer stacked in sequence along the longitudinal direction on the surface of the substrate, wherein the etching rate of the portion of the composite gate metal layer adjacent to the PGaN layer is greater than that of the portion away from the PGaN layer, so that the lateral cross-sectional area of ​​the portion of the composite gate metal layer adjacent to the PGaN layer after etching is smaller than the lateral cross-sectional area of ​​the portion away from the PGaN layer.

[0006] Furthermore, the composite gate metal layer includes a first gate metal layer and a second gate metal layer, wherein the first gate metal layer is stacked on the PGaN layer, the second gate metal layer is stacked on the first gate metal layer, and the etching rate of the first gate metal layer is greater than the etching rate of the second gate metal layer.

[0007] Furthermore, the lateral cross-sectional area of ​​the first gate metal layer is smaller than the lateral cross-sectional areas of the second gate metal layer and the PGaN layer. Meanwhile, the lateral cross-sectional areas of the second gate metal layer and the PGaN layer are smaller than the lateral cross-sectional area of ​​the ALGaN layer. A second dielectric layer is also stacked on the surface of the ALGaN layer, and the second dielectric layer covers the PGaN layer, the first gate metal layer and the second gate metal layer.

[0008] Furthermore, the substrate is a silicon substrate, and the buffer layer is an EPI buffer layer.

[0009] The embodiment of the present application also provides a method for realizing an enhanced HEMT with reduced gate leakage, comprising the following steps: providing a substrate; depositing a buffer layer, a UGaN layer, an ALGaN layer and a PGaN layer in sequence along the longitudinal direction on the surface of the substrate; depositing a first gate metal layer and a second gate metal layer in sequence along the longitudinal direction on the surface of the PGaN layer, wherein the etching rate of the first gate metal layer is greater than the etching efficiency of the second gate metal layer; etching the first gate metal layer and the second gate metal layer, wherein the lateral cross-sectional area of ​​the first gate metal layer after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer.

[0010] Furthermore, after the step of "simultaneously etching the first gate metal layer and the second gate metal layer, and the lateral cross-sectional area of ​​the first gate metal layer after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer", the following steps are also included: etching the PGaN layer, and making the lateral cross-sectional area of ​​the PGaN layer after etching the same as the lateral cross-sectional area of ​​the second gate metal layer.

[0011] Furthermore, after the step of "etching the PGaN layer and making the lateral cross-sectional area of ​​the etched PGaN layer larger than the lateral cross-sectional area of ​​the first gate metal layer", the following steps are also included: depositing a second dielectric layer on the surface of the ALGaN layer, the second dielectric layer covering the PGaN layer, the first gate metal layer and the second gate metal layer.

[0012] Furthermore, the material of the first gate metal layer is Ti, and the material of the second gate metal layer is TiN.

[0013] Furthermore, in the step of "simultaneously etching the first gate metal layer and the second gate metal layer, wherein the lateral cross-sectional area of ​​the first gate metal layer after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer", the first gate metal layer is etched by dry etching or wet cleaning.

[0014] Furthermore, after the step of “simultaneously etching the first gate metal layer and the second gate metal layer, wherein the lateral cross-sectional area of ​​the first gate metal layer after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer”, the following step is also included: etching the first gate metal layer a second time separately.

[0015] The beneficial effects of the present invention are as follows:

[0016] 1. The preparation process of the entire structure is simple, and there is no PGAN layer extension formed by sidewall deposition and overall sidewall etching in the traditional process, thereby eliminating the plasma damage caused by the sidewall dielectric deposition process and the etching damage to the PGAN layer during the sidewall process.

[0017] 2. Since the composite gate metal layer away from the PGaN layer corresponds to the PGaN layer after etching, the surface damage of the PGaN layer caused during the etching of the composite gate metal layer can be eliminated, so that there are fewer interface states at the interface of the PGaN layer in the entire structure, thereby improving the reliability of the gate.

[0018] 3. In the HEMT structure, the second gate metal layer can correspond to the size of the PGaN layer after etching, thereby protecting the PGaN layer and avoiding surface damage to the PGaN layer during etching, and the first gate metal layer can be concave in the lateral direction relative to the second gate metal layer and the PGaN layer, so that the PGaN layer can also reduce the electric field at the gate corner, thereby reducing the probability of gate leakage and increasing the reliability of the gate.

[0019] 4. During the dielectric layer deposition process, the concave portion of the first gate metal layer is filled by plasma lateral diffusion, thereby ensuring that there is no plasma damage.

[0020] 5. Dielectric layers with different dielectric constants can be selected at the notch of the first gate metal layer to control the electric field at the gate corner.

[0021] 6. After the first gate metal layer and the second gate metal layer are etched once at the same time, the first gate metal layer can be etched twice alone, so as to control the degree to which the first gate metal layer is laterally recessed relative to the second gate metal layer and the PGaN layer, thereby improving the overall stability of the first gate metal layer.

[0022] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 It is a flow chart of preparation of enhanced HEMT structure in the prior art;

[0025] Figure 2 is a flow chart for preparing an enhanced HEMT structure with reduced gate leakage in an embodiment of the present invention;

[0026] Figure 3 is a schematic structural diagram of an enhanced HEMT structure with reduced gate leakage in an embodiment of the present invention at a first viewing angle;

[0027] Figure 4 is a schematic structural diagram of an enhanced HEMT structure with reduced gate leakage in an embodiment of the present invention at a second viewing angle;

[0028] Figure 5 It is a flow chart of a method for realizing an enhanced HEMT with reduced gate leakage in an embodiment of the present invention.

[0029] The figure markings of the above drawings are: 1. substrate; 2. buffer layer; 3. UGaN layer; 4. ALGaN layer; 5. PGaN layer; 6. gate metal; 7. composite gate metal layer; 71. first gate metal layer; 72. second gate metal layer; 8. first dielectric layer; 9. second dielectric layer. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0031] Reference Figure 1 The process flow of the currently commonly used GaN enhanced HEMT device structure includes: Figure 1 In Step 1, an EPI substrate 1 is deposited, thereby sequentially depositing an EPI buffer layer 2, a UGaN layer 3, an ALGaN layer 4 and a PGaN layer 5 on the silicon substrate 1; refer to Figure 1 Step 2 in the above step is to deposit a gate metal, thereby forming a gate metal 6 on the PGaN layer 5. The gate metal 6 is a single layer and is made of a single metal material. Figure 1Step 3 in the embodiment is gate metal etching, whereby the edge of the gate metal 6 is etched to expose the PGaN layer 5. In this step, the etching process of the gate metal 6 causes the first etching damage to the PGaN layer 5; Figure 1 Step 4 in the above is to deposit a spacer dielectric layer, thereby depositing a first dielectric layer 8 on the PGaN layer 5 and the etched gate metal 6. During this process, the first dielectric layer 8 will cause plasma damage to the PGaN layer 5 during the first dielectric layer deposition process; refer to Figure 1 Step 5, spacer etching, thereby etching the first dielectric layer 8, so that the first dielectric layer 8 is formed between the gate metal 6 and the PGaN layer 5, and a spacer is formed; refer to Figure 1 Step 6, PGaN etching, thereby etching the PGaN layer 5 outside the protection of the first dielectric layer 8, so that the etched PGaN layer 5 protrudes from the gate metal 6 in the lateral direction; refer to Figure 1 Step 7 in the embodiment, the spacer dielectric layer is removed, thereby removing the remaining first dielectric layer 8 between the PGaN layer 5 and the gate metal 6; Figure 1 In Step 8, the EPI protection layer (Passivation) is deposited, thereby depositing the second dielectric layer 9 on the PGaN layer 5 and the gate metal 6. In this process, the second dielectric layer 9 will cause a second dielectric layer deposition plasma damage to the PGaN layer 5. It can be seen that the structure prepared by the existing enhanced HEMT process has complicated preparation process steps, and the interface of the PGaN layer 5 is repeatedly damaged by the plasma of the dielectric layer dep deposition and etching, which will cause more interface states at the PGaN interface and affect the reliability of the gate.

[0032] To this end, the embodiments of the present application provide an enhanced HEMT structure and implementation method for reducing gate leakage. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] like Figures 2 to 4As shown, an enhanced HEMT structure for reducing gate leakage in this embodiment includes a substrate 1, and a buffer layer 2, a UGaN layer 3, an ALGaN layer 4, a PGaN layer 5 and a composite gate metal layer 7 stacked in sequence along the longitudinal direction on the surface of the substrate 1, so as to form a complete HEMT stacked structure. The etching rate of the composite gate metal layer 7 adjacent to the PGaN layer 5 is greater than that of the composite gate metal layer 7 away from the PGaN layer 5, so that the lateral cross-sectional area of ​​the composite gate metal layer 7 adjacent to the PGaN layer 5 after etching is smaller than the lateral cross-sectional area of ​​the composite gate metal layer 7 away from the PGaN layer 5.

[0034] In this embodiment, after the composite gate metal layer 7 is etched, the composite gate metal layer 7 away from the PGaN layer 5 can correspond to the size of the PGaN layer 5 to be etched, thereby avoiding surface damage to the PGaN layer 5 during the etching process of the PGaN layer 5. At the same time, the lateral cross-sectional area of ​​the composite gate metal layer 7 adjacent to the PGaN layer 5 is smaller than the cross-sectional area of ​​the PGaN layer 5 after etching, so that the composite gate metal layer 7 of this part is laterally recessed inward of the PGaN layer 5 to ensure that the structure can still reduce the electric field of the side wall of the Schottky junction where the composite gate metal layer 7 and the PGaN layer 5 contact. The PGaN layer 5 protruding from the composite gate metal layer 7 can also reduce the electric field at the gate corner, thereby reducing gate leakage and increasing gate reliability.

[0035] Correspondingly, the deposition and etching steps of the sidewall dielectric layer in the existing traditional process are also eliminated, which can eliminate the plasma damage to the PGaN layer 5 when the first dielectric layer 8 is deposited to form the first dielectric layer on the PGaN layer 5 in the prior art, and the damage to the PGaN layer 5 when etching during the removal of the sidewall dielectric layer.

[0036] With the above structure, the preparation process of the entire structure is simple, and there is no extension of the PGAN layer 5 formed by spacer deposition (spacer dep) and spacer blank etching (spacer blank etch) in the traditional process, thereby eliminating the plasma damage (plasma damage) caused by the deposition process of the sidewall dielectric and the etching damage to the PGAN layer during the sidewall process. In addition, since the composite gate metal layer 7 away from the PGaN layer 5 corresponds to the etched PGaN layer 5, the surface damage (surface damage) of the PGaN layer 5 caused during the etching of the composite gate metal layer 7 can be eliminated, so that there are fewer interface states at the interface of the PGaN layer 5 in the entire structure, thereby improving the reliability of the gate.

[0037] Specifically, the composite gate metal layer 7 includes a first gate metal layer 71 and a second gate metal layer 72, wherein the first gate metal layer 71 is stacked on the PGaN layer 5, the second gate metal layer 72 is stacked on the first gate metal layer 71, and the etching rate of the first gate metal layer 71 is greater than the etching rate of the second gate metal layer 72. Thus, in the HEMT structure, the second gate metal layer 72 can correspond to the size of the PGaN layer 5 after etching, thereby protecting the PGaN layer 5 and avoiding surface damage to the PGaN layer 5 during the etching process, and the first gate metal layer 71 can be concave in the lateral direction relative to the second gate metal layer 72 and the PGaN layer 5, so that the PGaN layer 5 can also reduce the electric field at the gate corner, thereby reducing the probability of gate leakage and increasing the reliability of the gate.

[0038] Specifically, the lateral cross-sectional area of ​​the first gate metal layer 71 is smaller than the lateral cross-sectional area of ​​the second gate metal 6 and the PGaN layer 5, and at the same time, the lateral cross-sectional area of ​​the second gate metal layer 72 and the PGaN layer 5 is smaller than the lateral cross-sectional area of ​​the ALGaN layer 4. A second dielectric layer 9 is also stacked on the surface of the ALGaN layer 4, and the second dielectric layer 9 covers the PGaN layer 5, the first gate metal layer 71 and the second gate metal layer 72. Therefore, during the deposition of the second dielectric layer 9, the concave part of the first gate metal layer 71 is filled by plasma lateral diffusion, which can ensure that there is no plasma damage.

[0039] It is worth noting that a second dielectric layer 9 with a different dielectric constant may be selected at the recess of the first gate metal layer 71 to control the electric field at the gate corner.

[0040] Specifically, the substrate 1 is a silicon substrate 1, sapphire, silicon carbide, QST, etc. Preferably, the substrate 1 is a silicon substrate 1 (Si substrate), and the buffer layer 2 is an EPI buffer layer 2 (EPI Buffer layer). Thus, the enhanced HEMT structure has good structural stability.

[0041] like Figures 2 to 5 As shown, the present application also provides a method for implementing an enhanced HEMT with reduced gate leakage, comprising the following steps:

[0042] Providing a substrate 1;

[0043] A buffer layer 2, a UGaN layer 3, an ALGaN layer 4 and a PGaN layer 5 are sequentially deposited on the surface of the substrate 1 along the longitudinal direction;

[0044] A first gate metal layer 71 and a second gate metal layer 72 are sequentially deposited on the surface of the PGaN layer 5 along the longitudinal direction, wherein the etching rate of the first gate metal layer 71 is greater than the etching efficiency of the second gate metal layer 72;

[0045] The first gate metal layer 71 and the second gate metal layer 72 are etched, and the lateral cross-sectional area of ​​the first gate metal layer 71 after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer 72 .

[0046] In this embodiment, after etching the first gate metal layer 71 and the second gate metal layer 72, the second gate metal layer 72 can correspond to the size of the PGaN layer 5 to be etched, thereby avoiding surface damage to the PGaN layer 5 during the etching process of the PGaN layer 5. At the same time, the lateral cross-sectional area of ​​the second gate metal layer 72 is smaller than the cross-sectional area of ​​the PGaN layer 5 after etching, so that the first gate metal layer 71 after etching is laterally recessed inward from the PGaN layer 5 to ensure that the structure can still reduce the electric field of the side wall of the Schottky junction where the first gate metal layer 71 and the PGaN layer 5 contact. The PGaN layer 5 protruding from the first gate metal layer 71 can also reduce the electric field at the gate corner, thereby reducing the probability of gate leakage and increasing the reliability of the gate.

[0047] Correspondingly, the deposition and etching steps of the sidewall dielectric layer in the existing traditional process are also eliminated, which can eliminate the plasma damage to the PGaN layer 5 when the first dielectric layer 8 is deposited to form the first dielectric layer on the PGaN layer 5 in the prior art, and the damage to the PGaN layer 5 when etching during the removal of the sidewall dielectric layer.

[0048] By using the above method, the entire preparation process is simple, and there is no extension portion of the PGAN layer 5 formed by spacer deposition and spacer blank etching in the traditional process, thereby eliminating the plasma damage caused by the spacer dielectric deposition process and the etching damage to the PGAN layer during the spacer process.

[0049] Specifically, after the step of “simultaneously etching the first gate metal layer 71 and the second gate metal layer 72, wherein the lateral cross-sectional area of ​​the first gate metal layer 71 after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer 72”, the following steps are also included:

[0050] The PGaN layer 5 is etched, and the lateral cross-sectional area of ​​the etched PGaN layer 5 is made the same as the lateral cross-sectional area of ​​the second gate metal layer 72. Thus, the second gate metal layer 72 corresponds to the etched PGaN layer 5, thereby eliminating the surface damage (surface damage) of the PGaN layer 5 caused during the etching of the first gate metal layer 71 and the second gate metal layer 72, so that there are fewer interface states at the interface of the PGaN layer 5 in the entire structure, thereby improving the reliability of the gate.

[0051] Specifically, after the step of “etching the PGaN layer 5 so that the lateral cross-sectional area of ​​the etched PGaN layer 5 is larger than the lateral cross-sectional area of ​​the first gate metal layer 71”, the following steps are also included:

[0052] A second dielectric layer 9 is deposited on the surface of the ALGaN layer 4, and the second dielectric layer 9 covers the PGaN layer 5, the first gate metal layer 71 and the second gate metal layer 72. Thus, during the deposition of the second dielectric layer 9, the concave portion of the first gate metal layer 71 is filled by plasma lateral diffusion, thereby ensuring that there is no plasma damage.

[0053] It is worth noting that a second dielectric layer 9 with a different dielectric constant may be selected at the recess of the first gate metal layer 71 to control the electric field at the gate corner.

[0054] Specifically, the material of the first gate metal layer 71 is Ti, and the material of the second gate metal layer 72 is TiN. Since the etching rate of Ti is greater than that of TiN, the first gate metal 6 can be laterally concave relative to the second gate metal layer 72 after etching. In addition, the reaction or influence between the first gate metal layer 71 and the second gate metal layer 72 can be avoided, thereby improving the stability of the composite gate metal layer 7 composed of the first gate metal layer 71 and the second gate metal layer 72.

[0055] Specifically, in the step of “etching the first gate metal layer 71 and the second gate metal layer 72 simultaneously, wherein the lateral cross-sectional area of ​​the first gate metal layer 71 after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer 72”, the first gate metal layer 71 is etched by dry etching or wet cleaning. That is, in this embodiment, the etching of the first gate metal layer 71 can be performed in the dry etching process or in the subsequent wet cleaning.

[0056] Specifically, after the step of “simultaneously etching the first gate metal layer 71 and the second gate metal layer 72, wherein the lateral cross-sectional area of ​​the first gate metal layer 71 after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer 72”, the following steps are also included:

[0057] The first gate metal layer 71 is etched twice separately. That is, in this embodiment, after the first gate metal layer 71 and the second gate metal layer 72 are etched once at the same time, the first gate metal layer 71 can be etched twice separately, so that the degree to which the first gate metal layer 71 is laterally recessed relative to the second gate metal layer 72 and the PGaN layer 5 can be controlled, thereby improving the overall stability of the first gate metal layer 71.

[0058] The following examples are used to describe in detail the process flow of preparing an enhanced HEMT structure for reducing gate leakage in the present application:

[0059] Reference Figure 2 In Step 1, an EPI substrate 1 is deposited, thereby sequentially depositing an EPI buffer layer 2, a UGaN layer 3, an ALGaN layer 4 and a PGaN layer 5 on the silicon substrate 1; refer to Figure 2 In Step 2, the first gate metal layer 71 and the second gate metal layer 72 are deposited, so that the first gate metal layer 71 and the second gate metal layer 72 are sequentially deposited on the PGaN layer 5; Figure 2Step 3 in the embodiment of the present invention is to etch the first gate metal layer 71 and the second gate metal layer 72, thereby etching the edges of the first gate metal layer 71 and the second gate metal layer 72; Figure 2 In Step 4, the first gate metal layer 71 is laterally etched so that the second gate metal layer 72 corresponds to the size of the PGaN layer 5 after etching, and the first gate metal layer 71 is laterally concave relative to the etched PGaN layer 5 and the second gate metal layer 72. It is worth noting that Figure 2 Step 3 and Step 4 can be completed step by step or simultaneously; refer to Figure 2 Step 5, PGaN etching, so that the etched PGaN layer 5 corresponds to the second gate metal layer 72 in the transverse cross section and protrudes from the first gate metal layer 71 in the transverse direction; Figure 2 Step 6 in the above method is to deposit an EPI protective layer (Passivation), thereby depositing a second dielectric layer 9 on the PGaN layer 5 and the first gate metal layer 71 and the second gate metal layer 72. The HEMT structure obtained by the above method is as follows: Figure 3 and Figure 4 shown.

[0060] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. An enhanced HEMT structure with reduced gate leakage, characterized in that: It includes a substrate, and a buffer layer, a UGaN layer, an ALGaN layer, a PGaN layer and a composite gate metal layer stacked in sequence along the longitudinal direction on the surface of the substrate, wherein the etching rate of the portion of the composite gate metal layer adjacent to the PGaN layer is greater than that of the portion away from the PGaN layer, so that the lateral cross-sectional area of ​​the portion of the composite gate metal layer adjacent to the PGaN layer after etching is smaller than the lateral cross-sectional area of ​​the portion away from the PGaN layer.

2. The enhanced HEMT structure with reduced gate leakage according to claim 1, characterized in that: The composite gate metal layer includes a first gate metal layer and a second gate metal layer, wherein the first gate metal layer is stacked on the PGaN layer, the second gate metal layer is stacked on the first gate metal layer, and the etching rate of the first gate metal layer is greater than the etching rate of the second gate metal layer.

3. The enhanced HEMT structure with reduced gate leakage according to claim 2, characterized in that: The lateral cross-sectional area of ​​the first gate metal layer is smaller than the lateral cross-sectional area of ​​the second gate metal layer and the PGaN layer, and the lateral cross-sectional area of ​​the second gate metal layer and the PGaN layer is smaller than the lateral cross-sectional area of ​​the ALGaN layer; A second dielectric layer is also stacked on the surface of the ALGaN layer, and the second dielectric layer covers the PGaN layer, the first gate metal layer and the second gate metal layer.

4. The enhanced HEMT structure with reduced gate leakage according to claim 1, characterized in that: The substrate is a silicon substrate, and the buffer layer is an EPI buffer layer.

5. A method for realizing an enhanced HEMT with reduced gate leakage, characterized in that: The following steps are involved: providing a substrate; Depositing a buffer layer, a UGaN layer, an ALGaN layer and a PGaN layer in sequence along the longitudinal direction on the surface of the substrate; Depositing a first gate metal layer and a second gate metal layer in sequence along the longitudinal direction on the surface of the PGaN layer, wherein an etching rate of the first gate metal layer is greater than an etching efficiency of the second gate metal layer; The first gate metal layer and the second gate metal layer are etched, and the lateral cross-sectional area of ​​the first gate metal layer after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer.

6. The method for realizing an enhanced HEMT with reduced gate leakage according to claim 5, characterized in that: After the step of "simultaneously etching the first gate metal layer and the second gate metal layer, wherein the lateral cross-sectional area of ​​the first gate metal layer after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer", the following steps are also included: The PGaN layer is etched so that the lateral cross-sectional area of ​​the etched PGaN layer is the same as the lateral cross-sectional area of ​​the second gate metal layer.

7. The method for realizing an enhanced HEMT with reduced gate leakage according to claim 5, characterized in that: After the step of "etching the PGaN layer so that the lateral cross-sectional area of ​​the etched PGaN layer is larger than the lateral cross-sectional area of ​​the first gate metal layer", the following steps are also included: A second dielectric layer is deposited on the surface of the ALGaN layer, wherein the second dielectric layer covers the PGaN layer, the first gate metal layer and the second gate metal layer.

8. The method for realizing an enhanced HEMT with reduced gate leakage according to claim 5, characterized in that: The material of the first gate metal layer is Ti, and the material of the second gate metal layer is TiN.

9. The method for realizing an enhanced HEMT with reduced gate leakage according to claim 5, characterized in that: In the step of "simultaneously etching the first gate metal layer and the second gate metal layer, wherein the lateral cross-sectional area of ​​the first gate metal layer after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer", the first gate metal layer is etched by dry etching or wet cleaning.

10. The method for realizing an enhanced HEMT with reduced gate leakage according to claim 5, characterized in that: After the step of "simultaneously etching the first gate metal layer and the second gate metal layer, wherein the lateral cross-sectional area of ​​the first gate metal layer after etching is smaller than the lateral cross-sectional area of ​​the second gate metal layer", the following steps are also included: The first gate metal layer is etched twice separately.

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