Chip and design method thereof, electronic equipment and circuit layout database

Abstract

The invention provides a chip and a design method thereof, electronic equipment and a circuit layout database, relates to the field of semiconductors, and can shorten an electric connection path between a second electrode of a first vertical transistor and a grid electrode of a second vertical transistor. The chip comprises a standard unit located on a substrate, and the standard unit comprises a first vertical transistor and a second vertical transistor which are arranged side by side, a spacing layer, and a first conductive layer arranged on the side, away from the substrate, of the spacing layer. Each of the first vertical transistor and the second vertical transistor comprises a first electrode, a grid electrode and a second electrode which are sequentially stacked in the Z direction; the Z direction is the direction from the substrate to the first pole. The first grid through hole of the spacing layer is filled with a grid communicating structure, the grid communicating structure is in contact with the grid of the second vertical transistor, and the grid communicating structure and the second electrode of the second vertical transistor are arranged in the Y direction. The second pole of the first vertical transistor is electrically connected with the gate of the second vertical transistor through the first conductive layer and the gate communication structure.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a chip and a design method thereof, an electronic device, and a circuit layout database. Background Art

[0002] With the development of integrated circuits, the characteristic size of transistors continues to shrink. The size of traditional lateral nanowire field-effect transistors has basically reached the process limit. It has been proven to be extremely difficult to further reduce the contacted poly pitch (CPP) of the pseudo gate, and it may lead to an increase in the resistance and capacitance of the transistor.

[0003] The source, gate, and drain of a vertical nanosheet field-effect transistor are arranged vertically, which reduces the space occupied horizontally and provides the possibility of further reducing the CPP. At the same time, it can also reduce the parasitic capacitance of the transistor, which is currently a hot topic in logic device research.

[0004] By combining vertical nanosheet transistors with other components, a basic logic gate circuit standard cell can be designed. However, based on the existing wiring design, when the drain of a vertical nanosheet transistor in a standard cell is electrically connected to the gate of another vertical nanosheet transistor, a long electrical connection path is required, resulting in a large delay in the signal transmission process, which reduces the performance speed of the standard cell. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a chip and its design method, electronic device, and circuit layout database, which can shorten the electrical connection path between the second electrode of the first vertical transistor and the gate of the second vertical transistor, reduce the delay in the signal transmission process, and improve the performance speed of the standard unit.

[0006] In the first aspect, the present application provides a chip, which includes a standard unit arranged on a substrate, and the standard unit includes: a first vertical transistor and a second vertical transistor arranged side by side along a first direction, a spacer layer, and a conductive layer arranged on the side of the spacer layer away from the substrate, and the conductive layer includes a first conductive layer. The first vertical transistor and the second vertical transistor both include a first pole, a gate, and a second pole stacked in sequence along a second direction; the first direction is perpendicular to the second direction, and the second direction is the direction from the substrate to the first pole. A first gate through hole is provided in the spacer layer, and a gate connection structure is filled in the first gate through hole. The gate connection structure is in contact with the gate of the second vertical transistor, and the gate connection structure is arranged along a third direction with the second pole of the second vertical transistor; wherein the first direction and the second direction are both perpendicular to the third direction. The first conductive layer is in contact with the second pole and the gate connection structure of the first vertical transistor, respectively, and the second pole of the first vertical transistor is electrically connected to the gate of the second vertical transistor through the first conductive layer and the gate connection structure.

[0007] In the present application, a first conductive layer is provided on the first vertical transistor and the second vertical transistor, the first conductive layer is in contact with the second electrode and the gate connection structure of the first vertical transistor respectively, and the gate connection structure is in contact with the gate of the second vertical transistor, so as to realize the electrical connection between the second electrode of the first vertical transistor and the gate of the second vertical transistor. The electrical connection path between the second electrode of the first vertical transistor and the gate of the second vertical transistor in the present application is: the second electrode of the first vertical transistor, the first conductive layer, the gate connection structure, and the gate of the second vertical transistor. Compared with the electrical connection path of the related art, the electrical connection path between the second electrode of the first vertical transistor and the gate of the second vertical transistor in the present application is shorter, which reduces the delay in the signal transmission process and improves the performance speed of the standard unit.

[0008] In some possible implementations, the spacer layer is located between the gate of the first vertical transistor and the gate of the second vertical transistor and the second electrode of the first vertical transistor and the second electrode of the second vertical transistor. The second electrode of the second vertical transistor is in the same layer and material as the first conductive layer.

[0009] The preparation process of the standard unit is as follows: after forming the first electrode and the gate of the first vertical transistor and the second vertical transistor in sequence, first forming an interval layer, in which a first gate through hole is opened; then forming the second electrode of the first vertical transistor and the second vertical transistor, and a conductive layer (including the first conductive layer) through the same semiconductor process. Wherein, while forming the second electrode of the first vertical transistor and the second vertical transistor, and the conductive layer, the gate connection structure can be filled into the first gate through hole; or, after forming the first gate through hole of the interval layer, before forming the second electrode of the first vertical transistor and the second vertical transistor, and the conductive layer, the gate connection structure can be filled into the first gate through hole.

[0010] In some possible implementations, the spacer layer covers the first vertical transistor and the second vertical transistor, and exposes the upper surface of the second electrode of the first vertical transistor. The upper surface of the second electrode of the first vertical transistor is in contact with the first conductive layer; wherein the upper surface of the second electrode of the first vertical transistor is the surface of the second electrode of the first vertical transistor that is away from the substrate.

[0011] In this case, the conductive layer can be prepared by the same semiconductor process as the drain connection structure. The drain connection structure can be in contact with the drain of the second vertical transistor to transmit the signal on the drain of the second vertical transistor. The drain connection structure can be located in a through hole in the dielectric layer 0, and the second electrode of the second vertical transistor can be electrically connected to the wiring in the metal layer M0 through the drain connection structure to transmit the signal.

[0012] In some possible implementations, the standard cell further includes a third vertical transistor and a fourth vertical transistor, and the conductive layer further includes a second conductive layer. The third vertical transistor and the fourth vertical transistor are arranged side by side in the first direction, and other vertical transistors are arranged between the third vertical transistor and the fourth vertical transistor. The third vertical transistor and the fourth vertical transistor both include a first pole, a gate, and a second pole stacked in sequence along the second direction; in the third direction, the second pole of the third vertical transistor exceeds the second pole of the fourth vertical transistor in the third direction, and the portion where the second pole of the third vertical transistor exceeds the second pole of the fourth vertical transistor is a protruding portion. The second conductive layer contacts the protruding portion and the second pole of the fourth vertical transistor respectively, and the second pole of the third vertical transistor is electrically connected to the second pole of the fourth vertical transistor through the second conductive layer, thereby avoiding the second pole of the third vertical transistor being electrically connected to the second pole of the fourth vertical transistor through the routing of the metal layer M0, and shortening the electrical connection path between the second pole of the third vertical transistor and the second pole of the fourth vertical transistor.

[0013] In some possible implementations, the cross-sections of the first conductive layer and the second conductive layer are both L-shaped; wherein the cross-section is a plane where the first direction and the third direction are located.

[0014] In some possible implementations, the standard cell further includes a fifth vertical transistor arranged side by side with the first vertical transistor in the first direction, and the fifth vertical transistor includes a first electrode, a gate, and a second electrode stacked in sequence along the second direction. The first electrode of the first vertical transistor is shared with the first electrode of the fifth vertical transistor, thereby achieving electrical connection between the first electrode of the first vertical transistor and the first electrode of the fifth vertical transistor, or in other words, achieving series connection between the first vertical transistor and the fifth vertical transistor.

[0015] In some possible implementations, the standard cell further includes a first dielectric layer (i.e., dielectric layer 0 hereinafter) and a routing layer sequentially disposed on the conductive layer. The routing layer includes a first power routing, a second power routing, a first gate routing, and a second gate routing, and the first power routing, the second power routing, the first gate routing, and the second gate routing are distributed on different wiring tracks in a third direction. Among them, the first power routing can be VSS, GND, etc., and the second power routing can be VDD, etc.

[0016] In some possible implementations, the standard cell is a two-input AND gate. The standard cell also includes a first N-type vertical transistor, a first P-type vertical transistor, a second P-type vertical transistor, and a third P-type vertical transistor; the first vertical transistor is the second N-type vertical transistor, and the second vertical transistor is the third N-type vertical transistor. The gate of the first N-type vertical transistor is electrically connected to the first gate wiring, the second electrode of the first N-type vertical transistor is electrically connected to the first power supply wiring, and the first electrode of the first N-type vertical transistor is electrically connected to the first electrode of the second N-type vertical transistor. The gate of the second N-type vertical transistor is electrically connected through the second gate wiring, and the second electrode of the second N-type vertical transistor is electrically connected to the second electrode of the first P-type vertical transistor, the second electrode of the second P-type vertical transistor, the gate of the third P-type vertical transistor, and the gate of the third N-type vertical transistor. The first electrode of the third N-type vertical transistor is electrically connected to the first power supply wiring, the second electrode of the third N-type vertical transistor is electrically connected to the second electrode of the third P-type vertical transistor, and the first electrode of the third P-type vertical transistor is electrically connected to the second power supply wiring. The gate of the first P-type vertical transistor is electrically connected to the first gate wiring, and the first electrode of the first P-type vertical transistor is electrically connected to the second power supply wiring. The gate of the second P-type vertical transistor is electrically connected to the second gate wiring, and the first electrode of the second P-type vertical transistor is electrically connected to the second power supply wiring. The second electrode of the second N-type vertical transistor is electrically connected to the gate of the third P-type vertical transistor and the gate of the third N-type vertical transistor through the first conductive layer.

[0017] In order to realize electrical connection between the second electrode of the second N-type vertical transistor and the second electrode of the first P-type vertical transistor and the second electrode of the second P-type vertical transistor, the second conductive layer can be used to electrically connect the second electrode of the first P-type vertical transistor and the second electrode of the second P-type vertical transistor, and then the connecting conductive structure in the metal layer M1 can be used to electrically connect the first conductive layer and the second conductive layer.

[0018] In some possible implementations, the first N-type vertical transistor is the fifth vertical transistor, and the first electrode of the first N-type vertical transistor is shared with the first electrode of the second N-type vertical transistor to save the number of wirings in the metal layer M0. For the first P-type vertical transistor and the second P-type vertical transistor connected in series, the first electrode of the first P-type vertical transistor and the first electrode of the second P-type vertical transistor can be shared to save the number of wirings in the metal layer M0.

[0019] In some possible implementations, the standard unit is a two-to-one data selector, which includes an inverter, a logic operator, and a strong drive inverter. The inverter includes a first vertical transistor, and the logic operator includes a second vertical transistor; the logic operator includes the first vertical transistor, and the strong drive inverter includes the second vertical transistor.

[0020] Specifically, the inverter includes a sixth N-type vertical transistor and a sixth P-type vertical transistor. The logic operator includes a first N-type vertical transistor, a second N-type vertical transistor, a third N-type vertical transistor, a fourth N-type vertical transistor, a first P-type vertical transistor, a second P-type vertical transistor, a third P-type vertical transistor, and a fourth P-type vertical transistor. The strong drive inverter includes a fifth P-type vertical transistor and a fifth N-type disposal transistor. The strong drive inverter includes a fifth P-type vertical transistor and a fifth N-type vertical transistor.

[0021] In the inverter, the gate of the sixth N-type vertical transistor and the gate of the sixth P-type vertical transistor are both electrically connected to the gate wiring S, and the first electrode of the sixth N-type vertical transistor is electrically connected to the second power supply wiring VDD. The second electrode of the sixth N-type vertical transistor is electrically connected to the gate of the first P-type vertical transistor and the gate of the first N-type vertical transistor. The sixth N-type vertical transistor and the sixth P-type vertical transistor in the inverter are used to invert the signal on the gate wiring S to obtain an inverted signal Sbar, and input the inverted signal Sbar to the gate of the first P-type vertical transistor and the gate of the first N-type vertical transistor through the second electrode of the sixth P-type vertical transistor and the first conductive layer.

[0022] Among them, the sixth P-type vertical transistor is the first vertical transistor of the present application, and the first P-type vertical transistor and the first N-type vertical transistor are the second vertical transistor of the present application.

[0023] In the logic operator, the first electrode of the first P-type vertical transistor, the first electrode of the second P-type vertical transistor, the first electrode of the third P-type vertical transistor, and the first electrode of the fourth P-type vertical transistor are electrically connected. The first electrode of the first P-type vertical transistor, the first electrode of the second P-type vertical transistor, the first electrode of the third P-type vertical transistor, and the first electrode of the fourth P-type vertical transistor can be electrically connected by sharing the first electrode of the first P-type vertical transistor, the first electrode of the second P-type vertical transistor, the first electrode of the third P-type vertical transistor, and the first electrode of the fourth P-type vertical transistor, so as to reduce the number of routings in the metal layer M0.

[0024] The second electrode of the first P-type vertical transistor, the second electrode of the third P-type vertical transistor, and the first electrode of the fifth P-type vertical transistor are all electrically connected to the second power supply line VDD; the second electrode of the second P-type vertical transistor and the second electrode of the fourth P-type vertical transistor are electrically connected through the second conductive layer, and the second electrode of the first N-type vertical transistor and the second electrode of the third N-type vertical transistor are electrically connected through the second conductive layer, and then the two second conductive layers are electrically connected by using the connecting conductive structure in the metal layer M1, thereby realizing the electrical connection of the second electrode of the first N-type vertical transistor, the second electrode of the third N-type vertical transistor, the second electrode of the first N-type vertical transistor, and the second electrode of the third N-type vertical transistor.

[0025] The gate of the second P-type vertical transistor is electrically connected to the gate of the sixth N-type vertical transistor and the gate of the sixth P-type vertical transistor through the gate wiring S, the gate of the third P-type vertical transistor is electrically connected to the gate wiring A, and the gate of the fourth P-type vertical transistor is electrically connected to the gate wiring B.

[0026] The first electrode of the first N-type vertical transistor is electrically connected to the first electrode of the second N-type vertical transistor, and the first electrode of the third N-type vertical transistor is electrically connected to the first electrode of the fourth N-type vertical transistor. The first electrode of the first N-type vertical transistor can be electrically connected to the first electrode of the second N-type vertical transistor by making the first electrode of the first N-type vertical transistor and the first electrode of the second N-type vertical transistor share the same electrode; the first electrode of the third N-type vertical transistor can be electrically connected to the first electrode of the fourth N-type vertical transistor by making the first electrode of the third N-type vertical transistor and the first electrode of the fourth N-type vertical transistor share the same electrode, so as to reduce the number of wirings in the metal layer M0.

[0027] The second electrode of the second N-type vertical transistor, the second electrode of the fourth N-type vertical transistor, the first electrode of the fifth N-type vertical transistor, and the second electrode of the sixth N-type vertical transistor are all electrically connected to the first power supply wiring VSS. The gate of the fourth N-type vertical transistor is electrically connected to the gate of the fourth P-type vertical transistor through the gate wiring B, the gate of the third N-type vertical transistor is electrically connected to the gate of the second P-type vertical transistor through the gate wiring S, and the gate of the second N-type vertical transistor is electrically connected to the gate of the third P-type vertical transistor through the gate wiring A.

[0028] The logic operator is used to select the input signal according to the signal input by the gate wiring S and the gate wiring Sbar to obtain the selection result. On this basis, the second electrode of the first N-type vertical transistor is also electrically connected to the gate of the fifth P-type vertical transistor and the gate of the fifth N-type disposal transistor through the first conductive layer, so that the second electrode of the first N-type vertical transistor can be used to input the selection result to the gate of the fifth P-type vertical transistor and the gate of the fifth N-type disposal transistor through the first conductive layer. Among them, the first N-type vertical transistor is the first vertical transistor of the present application, and the fifth N-type vertical transistor is the second vertical transistor of the present application.

[0029] In the strong drive inverter, the drain of the fifth N-type vertical transistor and the drain of the fifth P-type vertical transistor are both electrically connected to the output trace OUT in the metal layer M1. The strong drive inverter is used to invert the input signal under the control of the selection result and output the inversion result to the output trace OUT.

[0030] In a second aspect, the present application provides an electronic device, which includes a circuit board and the chip described in the first aspect, wherein the chip is arranged on the circuit board.

[0031] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0032] In a third aspect, the present application provides a circuit layout database, which includes a plurality of standard cells, each of which includes a layout and a circuit diagram of the standard cell; the standard cell includes a first vertical transistor and a second vertical transistor arranged side by side along a first direction. The layout of the standard cell includes a first layer, a second layer, and a third layer stacked in sequence. The first layer includes a first electrode of the first vertical transistor and a first electrode of the second vertical transistor; the second layer includes a gate of the first vertical transistor and a gate of the second vertical transistor; the third layer includes a second electrode of the first vertical transistor and a second electrode of the second vertical transistor. The third layer also includes a gate connection structure that overlaps with the gate of the second vertical transistor, and the gate connection structure and the second electrode of the second vertical transistor are arranged in a third direction, and the third direction is perpendicular to the first direction. Among them, the third layer also includes a conductive layer; or, the layout of the standard cell also includes a fourth layer located on the third layer, and the fourth layer includes a conductive layer; the conductive layer includes a first conductive layer, and the first conductive layer overlaps with the second electrode and the gate connection structure of the first vertical transistor respectively.

[0033] In some possible implementations, the standard cell further includes a third vertical transistor and a fourth vertical transistor, and the conductive layer further includes a second conductive layer. The first layer further includes a first electrode of the third vertical transistor and a first electrode of the fourth vertical transistor. The second layer further includes a gate of the third vertical transistor and a gate of the fourth vertical transistor. The third layer further includes a second electrode of the third vertical transistor and a second electrode of the fourth vertical transistor; in the third direction, the second electrode of the third vertical transistor exceeds the second electrode of the fourth vertical transistor in the third direction, and the portion where the second electrode of the third vertical transistor exceeds the second electrode of the fourth vertical transistor is a protruding portion. The second conductive layer overlaps with the second electrode and the protruding portion of the fourth vertical transistor, respectively.

[0034] In some possible implementations, the cross-sections of the first conductive layer and the second conductive layer are both L-shaped, wherein the cross-section is a plane where the first direction and the third direction are located.

[0035] In some possible implementations, the standard cell further includes a fifth vertical transistor arranged side by side with the first vertical transistor in the first direction. The first layer further includes a first electrode of the fifth vertical transistor, the second layer further includes a gate of the fifth vertical transistor, and the third layer further includes a second electrode of the fifth vertical transistor. The first electrode of the first vertical transistor is shared with the first electrode of the fifth vertical transistor.

[0036] In some possible implementations, the layout of the standard cell further includes a fifth layer; when the layout of the standard cell includes a fourth layer, the fifth layer is disposed on the fourth layer; when the layout of the standard cell does not include the fourth layer, the fifth layer is disposed on the third layer. The fifth layer includes a routing layer; the routing layer includes a first power routing, a second power routing, a first gate routing, and a second gate routing, and the first power routing, the second power routing, the first gate routing, and the second gate routing are distributed on different routing tracks in the third direction.

[0037] In some possible implementations, the circuit layout database also includes layer information, and the layer information includes graphic border information, graphic fill information, and graphic color information of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer.

[0038] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0039] In a fourth aspect, the present application provides a chip design method, comprising: receiving a target instruction; in response to the target instruction, calling one or more standard cells in the circuit layout database of the fourth aspect to design another circuit layout using the one or more standard cells.

[0040] The fourth aspect and any implementation of the fourth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the fourth aspect and any implementation of the fourth aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0041] In a fifth aspect, the present application provides a circuit layout design device, comprising: a memory and a processor, wherein the memory is electrically connected to the processor. The memory stores program instructions, and when the program instructions are executed by the processor, the electronic device executes the layout design method described in the fifth aspect.

[0042] The fifth aspect and any implementation of the fifth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the fifth aspect and any implementation of the fifth aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0043] In a sixth aspect, the present application provides a computer-readable storage medium, comprising a computer program, which, when executed on an electronic device, enables the electronic device to execute the layout design method described in the fifth aspect.

[0044] The sixth aspect and any implementation of the sixth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the sixth aspect and any implementation of the sixth aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0045] In a seventh aspect, the present application provides a computer program product, which, when executed on a computer, enables the computer to execute the layout design method as described in the fifth aspect.

[0046] The seventh aspect and any implementation of the seventh aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the seventh aspect and any implementation of the seventh aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a top view of a standard cell composed of FinFET;

[0048] Figure 2 The structural development process of lateral nanosheet transistors;

[0049] Figure 3 The development process from lateral nanosheet transistors to vertical nanosheet transistors;

[0050] Figure 4 A three-dimensional diagram of a vertical transistor is provided for an embodiment of the present application;

[0051] Figure 5 A layout of a standard cell provided in an embodiment of the present application;

[0052] Figure 6a for Figure 5 A1-A2 sectional view;

[0053] Figure 6b for Figure 5 Cross-sectional view along B1-B2 direction;

[0054] Figure 7a for Figure 5 A1-A2 sectional view;

[0055] Figure 7b for Figure 5Sectional view along B1-B2 direction;

[0056] Figure 8 A layout of a standard cell provided in an embodiment of the present application;

[0057] Figure 9a A layout of a standard cell provided in an embodiment of the present application;

[0058] Figure 9b A layout of a standard cell provided in an embodiment of the present application;

[0059] Fig.9c A layout of a standard cell provided in an embodiment of the present application;

[0060] Figure 9d A layout of a standard cell provided in an embodiment of the present application;

[0061] Fig.10a A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0062] Fig.10b A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0063] Fig.10c A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0064] Fig.10d A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0065] Fig.10e A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0066] Fig.10f A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0067] Figure 10g A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0068] Fig.10h A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0069] Fig.10i A process diagram for preparing a channel layer provided in an embodiment of the present application;

[0070] Fig.11 A layout of two vertical transistors arranged opposite to each other;

[0071] Fig.12a A perspective view of a standard cell including two transistors in series is provided for the related art;

[0072] Figure 12bA layout of a standard cell including two transistors in series is provided for the related art;

[0073] Fig.13 A layout of a standard cell including two transistors in series is provided for the related art;

[0074] Fig.14 A layout of a standard cell provided in an embodiment of the present application;

[0075] Fig.15 The positional relationship between the first conductive layer, the dielectric layer 0 and the metal layer M0 provided in the embodiment of the present application;

[0076] Fig.16a A circuit diagram of a standard unit provided in an embodiment of the present application;

[0077] Fig.16b A layout of a standard cell provided in an embodiment of the present application;

[0078] Fig.16c A partial stereogram of a standard unit provided in an embodiment of the present application;

[0079] Fig.16d A three-dimensional diagram of a standard unit provided in an embodiment of the present application;

[0080] Fig.17a A circuit diagram of a standard unit provided in an embodiment of the present application;

[0081] Fig.17b A layout of a standard cell provided in an embodiment of the present application;

[0082] Fig.18 A schematic diagram of a circuit layout database exemplarily shown in an embodiment of the present application;

[0083] Fig.19a A process diagram of drawing a layout provided in an embodiment of the present application;

[0084] Fig.19b A process diagram of drawing a layout provided in an embodiment of the present application;

[0085] Fig.19c A process diagram of drawing a layout provided in an embodiment of the present application;

[0086] Fig. 20 An interface diagram including layout and layer information provided in an embodiment of the present application;

[0087] Fig.21 A schematic block diagram of a device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0088] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0089] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0090] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0091] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0092] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0093] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a chip.

[0094] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain chips.

[0095] For the convenience of explanation, the following description takes a mobile phone as an example of an electronic device. The mobile phone may include a circuit board, and a processor, a memory, etc. may be integrated on the circuit board. Of course, the mobile phone may also include other components, and other circuit structures may be integrated on the circuit board, which is not limited in the embodiments of the present application.

[0096] Both the processor and the memory are composed of complex logic circuits. The logic circuit includes at least one standard cell, and a complex logic circuit is realized by combining multiple standard cells. Among them, the standard cell may include an inverter (INV), a NAND gate (NAND), a NOR gate (NOR), etc.

[0097] like Figure 1 As shown, the size of the standard cell in the X direction and the Y direction directly affects the area of ​​the chip. The size of the standard cell in the X direction is determined by the CPP, and the size of the standard cell in the Y direction is determined by the spacing (metal pitch) between the conductive metals between the layers and the number of metal tracks (metal track number). Among them, the metal track includes multiple routing lines, for example, power routing lines, output routing lines, etc. In an embodiment of the present application, the power routing line may include the operating voltage VDD, the ground terminal VSS, the ground terminal GND, etc. inside the standard cell, and the output routing line is the routing line used by the standard cell to output signals. The wiring track below refers to the metal track here. It should be understood that the wiring track refers to: a path used for wiring in a chip.

[0098] Under the same CPP, the smaller the number of wiring tracks, the smaller the size of the standard cell in the chip in the Y direction, and the smaller the area occupied by the standard cell. Figure 1As shown, the number of wiring tracks of the mainstream standard cells composed of fin field-effect transistors (FinFET) is mostly as low as 6T (6 metal tracks), realizing high-density standard cells, thereby manufacturing high-density circuits or chips.

[0099] Each standard cell includes at least one transistor. With the development of integrated circuits, the characteristic size of transistors continues to shrink. Figure 2 As shown in FIG, based on the traditional lateral transistor, it has gradually developed into FinFET and multi-bridge-channel field-effect transistor (MBCFET), but the size of FinFET and MBCFET has basically reached the process limit. It has been proven to be extremely difficult to further reduce the CPP to a smaller size (for example, below 45nm), and it may cause the resistance and capacitance of the transistor to increase.

[0100] Based on this, Figure 3 As shown, vertical transistors are used instead of lateral transistors. Since the source, gate, and drain of the vertical transistor are arranged along the longitudinal direction (Z direction), the space occupied in the lateral direction (X direction) is reduced, providing the possibility of further reducing the CPP, and at the same time, it can also reduce the parasitic capacitance of the transistor, which is currently a hot topic in logic device research.

[0101] like Figure 4 As shown, the vertical transistor includes a first electrode 11, a gate 12, and a second electrode 13 stacked sequentially on a substrate 10, wherein the first electrode 11 is disposed between the substrate 10 and the gate 12, and the first electrode 11 and the gate 12 can be electrically isolated by a dielectric material, and the gate 12 and the second electrode 13 can be electrically isolated by a dielectric material. The first electrode 11 is a source electrode, and the second electrode 13 is a drain electrode; or the first electrode 11 is a drain electrode, and the second electrode 13 is a source electrode. For ease of description, the following description is based on the example that the first electrode 11 is a source electrode 11 and the second electrode 13 is a drain electrode 13.

[0102] In addition, in addition to the vertical transistors, the chip also includes dielectric layers and metal layers stacked in sequence and alternately arranged on the transistors. For example, on the transistors, the chip also includes dielectric layer 0, metal layer M1, dielectric layer 1, metal layer M2, etc. stacked in sequence and alternately arranged. The metal layer M1 may include the above-mentioned power wiring, output wiring, gate wiring, etc., and the metal layer M2 may be used to further connect the various wirings in the metal layer M1, thereby realizing various circuit connections.

[0103] Figure 4In addition to showing the vertical transistor, multiple through holes V0 are also shown for electrically connecting the source 11, the gate 12, and the drain 13 to multiple routing lines M1. The multiple through holes V0 are located in the dielectric layer 0 covering the vertical transistor, and the multiple routing lines in the metal layer M1 can be electrically connected to the vertical transistor through the multiple through holes V0.

[0104] Among them, the multiple routing lines M1 include a first routing line, a second routing line, and a gate routing line. According to actual needs, the first routing line and the second routing line can be the above-mentioned power routing line and output routing line, etc. The multiple through holes V0 include a through hole V01, a through hole V02, and a gate through hole V03. The first routing line is electrically connected to the source 11 through the through hole V01, the second routing line is electrically connected to the drain 13 through the through hole V02, and the gate 12 can be electrically connected to the gate routing line through the gate through hole V03. In addition, the through hole V01, the through hole V02, and the gate through hole V03 are arranged in sequence along the Y direction.

[0105] For more complex standard cells, such as a two-input AND gate (AND2) and a two-to-one data selector (MUX2to1), the standard cells include a first vertical transistor and a second vertical transistor, and the drain 13 of the first vertical transistor is electrically connected to the gate 12 of the second vertical transistor.

[0106] In the related art, in order to realize the electrical connection between the drain 13 of the first vertical transistor and the gate 12 of the second vertical transistor, the drain 13 of the first vertical transistor is first electrically connected to the second wiring through the through hole V02, and the gate 12 of the second vertical transistor is electrically connected to the gate wiring through the gate through hole V03, and then the second wiring is electrically connected to the wiring M21 of the metal layer M2 through the through hole V11, and the gate wiring is electrically connected to the wiring M21 of the metal layer M2 through the through hole V12.

[0107] It can be seen from the above description that the electrical connection path between the drain 13 of the first vertical transistor and the gate 12 of the second vertical transistor is: the drain 13 of the first vertical transistor, the through hole V02, the second wiring of the metal layer M1, the through hole V11, the wiring M21 of the metal layer M2, the through hole V12, the gate wiring of the metal layer M1, the gate through hole V03, and the gate 12 of the second vertical transistor. This path is relatively long and has a large delay in the signal transmission process, which reduces the performance speed of the standard unit.

[0108] Based on this, Figure 5As shown, an embodiment of the present application provides a chip, the chip includes a standard unit disposed on a substrate, the standard unit includes a first vertical transistor 100 and a second vertical transistor 200 arranged side by side along a first direction (X direction, for the convenience of description, the following description is based on the X direction). The first vertical transistor 100 and the second vertical transistor 200 may be N-type vertical transistors, or the first vertical transistor 100 and the second vertical transistor 200 may be P-type vertical transistors.

[0109] In some possible implementations, one chip may include one or more standard cells. In the present application, the first vertical transistor 100 and the second vertical transistor 200 both belong to the same standard cell.

[0110] The first vertical transistor 100 and the second vertical transistor 200 of the embodiment of the present application can be a vertical nanowire transistor or a vertical nanosheet transistor, etc. The layout and stereogram provided in the present application are all based on the vertical transistor as a vertical nanosheet transistor. Along the second direction of the substrate 10 pointing to the first vertical transistor (Z direction, for the convenience of description, the following description is in Z direction, and the X direction is perpendicular to the Z direction), the source 11, gate 12, and drain 13 of the first vertical transistor 100 and the second vertical transistor 200 are stacked on the substrate 10 in sequence. The first vertical transistor 100 and the second vertical transistor 200 also include a channel layer 14, which runs through the source 11, the gate 12, and the drain 13.

[0111] The standard cell further includes a spacer layer 30, a first gate through hole is formed in the spacer layer 30, a gate connection structure 21 is filled in the first gate through hole, the gate connection structure 21 is in contact with the gate 12 of the second vertical transistor 200, and the gate connection structure 21 and the drain 13 of the second vertical transistor 200 are arranged along the Y direction. The X direction and the Z direction are both perpendicular to the Y direction.

[0112] The standard cell further includes a conductive layer disposed on a side of the spacer layer away from the substrate, and the conductive layer includes a first conductive layer 41. The first conductive layer 41 is in contact with the drain 13 and the gate connection structure 21 of the first vertical transistor 100, respectively, and the drain 13 of the first vertical transistor 100 is electrically connected to the gate 12 of the second vertical transistor 200 through the first conductive layer 41 and the gate connection structure 21.

[0113] It should be understood that in the region where the conductive layer is provided, except for the drain 13 and the gate connection structure 21 in contact with the conductive layer, other conductive structures in each vertical transistor are electrically isolated from the conductive layer by the spacer layer 30 .

[0114] In the present application, a first conductive layer 41 is provided on the first vertical transistor 100 and the second vertical transistor 200, and the first conductive layer 41 is in contact with the drain 13 and the gate connection structure 21 of the first vertical transistor 100, respectively, and the gate connection structure 21 is in contact with the gate 12 of the second vertical transistor 200, so as to realize that the drain 13 of the first vertical transistor 100 is electrically connected to the gate 12 of the second vertical transistor 200. The electrical connection path between the drain 13 of the first vertical transistor and the gate 12 of the second vertical transistor of the present application is: the drain 13 of the first vertical transistor, the first conductive layer 41, the gate connection structure 21, and the gate 12 of the second vertical transistor. Compared with the electrical connection path of the related art, the electrical connection path between the drain 13 of the first vertical transistor and the gate 12 of the second vertical transistor in the present application is shorter, which reduces the delay in the signal transmission process and improves the performance speed of the standard unit.

[0115] In some possible implementations, the embodiment of the present application does not limit the shape of the cross section of the first conductive layer 41, as long as the first conductive layer 41 extends from the position in contact with the drain 13 of the first vertical transistor 100 to the position in contact with the gate 12 of the second vertical transistor. Optionally, the cross section of the first conductive layer 41 may be L-shaped, wherein the cross section is the plane where the X direction and the Y direction are located.

[0116] In some possible implementations, the spacer layer 30 is disposed at different positions, and the conductive layer is disposed at different positions. The spacer layer 30 and the conductive layer can be disposed at the following two positions:

[0117] The first case, such as Figure 6a and Figure 6b As shown, the spacer layer 30 is located between the gate 12 of the first vertical transistor 100 and the gate 12 of the second vertical transistor 200 and the drain 13 of the first vertical transistor 100 and the drain 13 of the second vertical transistor 200, and is used to electrically isolate the gate 12 of the first vertical transistor 100 from the drain 13 of the first vertical transistor 100, and to electrically isolate the gate 12 of the second vertical transistor 200 from the drain 13 of the second vertical transistor 200.

[0118] The preparation process of the standard unit is as follows: after sequentially forming the source 11 and the gate 12 of the first vertical transistor 100 and the second vertical transistor 200, first forming the spacer layer 30, in which the first gate through hole is opened; then forming the drain 13 and the conductive layer of the first vertical transistor 100 and the second vertical transistor 200 through the same semiconductor process. Wherein, while forming the drain 13 and the conductive layer of the first vertical transistor 100 and the second vertical transistor 200, the gate connection structure 21 can be filled into the first gate through hole; or, after forming the first gate through hole of the spacer layer 30, before forming the drain 13 and the conductive layer of the first vertical transistor 100 and the second vertical transistor 200, the gate connection structure 21 can be filled into the first gate through hole.

[0119] In this case, the spacer layer 30 is a film layer used to separate the gate 12 of the first vertical transistor 100 and the gate 12 of the second vertical transistor 200 from the drain 13 of the first vertical transistor 100 and the drain 13 of the second vertical transistor 200, and is not the aforementioned dielectric layer 0; the first gate through hole in the spacer layer 30 of the present application is not the through hole V0; the first conductive layer 41 of the present application is not the metal layer M1. In this way, compared with the related art, the present application greatly shortens the electrical connection path between the drain 13 of the first vertical transistor and the gate 12 of the second vertical transistor.

[0120] The second case, such as Figure 7a and Figure 7b As shown, the spacer layer 30 covers the first vertical transistor 100 and the second vertical transistor 200, and exposes the upper surface of the drain 13 of the first vertical transistor 100, and the upper surface of the drain 13 of the first vertical transistor 100 is in contact with the first conductive layer 41. The upper surface of the drain 13 of the first vertical transistor 100 is the surface of the drain 13 of the first vertical transistor 100 that is away from the substrate 10.

[0121] In this case, the conductive layer can be prepared by the same semiconductor process as the drain connection structure. The drain connection structure can be in contact with the drain 13 of the second vertical transistor 200 to transmit the signal on the drain 13 of the second vertical transistor 200. The drain connection structure can be located in a through hole in the dielectric layer 0, and the drain 13 of the second vertical transistor 200 can be electrically connected to the wiring in the metal layer M0 through the drain connection structure to transmit the signal.

[0122] In some possible implementations, the present application does not limit the materials of the conductive layer, the gate interconnection structure, and the drain interconnection structure, as long as the conductive layer, the gate interconnection structure, and the drain interconnection structure contain conductive materials. For example, the materials of the conductive layer, the gate interconnection structure, and the drain interconnection structure include metal.

[0123] also, Figure 5 1 shows a case where a standard cell includes a first vertical transistor 100 and a second vertical transistor 200, and the first vertical transistor 100 and the second vertical transistor 200 are adjacent to each other. In other possible implementations, such as Figure 8 As shown, the standard unit may further include other vertical transistors arranged side by side with the first vertical transistor 100 and the second vertical transistor 200 in the X direction, and other vertical transistors are spaced between the first vertical transistor 100 and the second vertical transistor 200, and the first conductive layer 41 crosses the other vertical transistors between the first vertical transistor 100 and the second vertical transistor 200.

[0124] Here, the spacer layer 30 is also disposed between other vertical transistors and the conductive layer to electrically isolate the other vertical transistors from the conductive layer.

[0125] like Figure 9a and Figure 9b As shown, in the case where the standard cell further includes other vertical transistors in addition to the first vertical transistor 100 and the second vertical transistor 200 , the other vertical transistors may include, for example, a third vertical transistor 300 and a fourth vertical transistor 400 .

[0126] like Figure 9a As shown, if the third vertical transistor 300 and the fourth vertical transistor 400 are adjacent, it can also be said that no vertical transistor is arranged between the third vertical transistor 300 and the fourth vertical transistor 400. In order to realize the electrical connection between the drain 13 of the third vertical transistor 300 and the drain 13 of the fourth vertical transistor 400, the conductive layer may further include a second conductive layer 42, and the second conductive layer 42 is in contact with the drain 13 of the third vertical transistor 300 and the drain 13 of the fourth vertical transistor 400, respectively, thereby avoiding the electrical connection between the drain 13 of the third vertical transistor 300 and the drain 13 of the fourth vertical transistor 400 through the routing of the metal layer M0, thereby shortening the electrical connection path between the drain 13 of the third vertical transistor 300 and the drain 13 of the fourth vertical transistor 400.

[0127] like Figure 9bAs shown, if other vertical transistors are arranged between the third vertical transistor 300 and the fourth vertical transistor 400, in order to realize the electrical connection between the drain 13 of the third vertical transistor 300 and the drain 13 of the fourth vertical transistor 400, the drain 13 of the third vertical transistor 300 exceeds the drain 13 of the fourth vertical transistor 400 in the Y direction, and the portion where the drain 13 of the third vertical transistor 300 exceeds the drain 13 of the fourth vertical transistor 400 is a protruding portion. The second conductive layer 42 is in contact with the protruding portion and the drain 13 of the fourth vertical transistor 400, respectively, and the drain 13 of the third vertical transistor 300 is electrically connected to the drain 13 of the fourth vertical transistor 400 through the second conductive layer 42, thereby avoiding the electrical connection between the drain 13 of the third vertical transistor 300 and the drain 13 of the fourth vertical transistor 400 through the routing of the metal layer M0, and shortening the electrical connection path between the drain 13 of the third vertical transistor 300 and the drain 13 of the fourth vertical transistor 400.

[0128] In this case, the embodiment of the present application does not limit the shape of the cross section of the second conductive layer 42, as long as the second conductive layer 42 extends from the position in contact with the protruding portion to the position in contact with the drain 13 of the fourth vertical transistor 400. Optionally, the cross section of the second conductive layer 42 may be L-shaped, wherein the cross section is a plane where the X direction and the Y direction are located.

[0129] Figure 9a and Figure 9b 1 shows a case where the drain 13 of the third vertical transistor 300 is electrically connected to the drain 13 of the fourth vertical transistor 400. In other possible implementations, the drain 13 of the third vertical transistor 300 may also be electrically connected to the source 11 of the fourth vertical transistor 400, such as Fig.9c As shown, this can be achieved as follows:

[0130] The spacer layer 30 also includes a source connection through hole, in which a source connection structure 22 is filled, and the source connection structure 22 is in contact with the source 11 of the fourth vertical transistor 400. The second conductive layer 42 is in contact with the source connection structure 22 and the drain 13 of the third vertical transistor 300, respectively, thereby preventing the drain 13 of the third vertical transistor 300 from being electrically connected to the source 11 of the fourth vertical transistor 400 through the wiring of the metal layer M0, and shortening the electrical connection path between the drain 13 of the third vertical transistor 300 and the source 11 of the fourth vertical transistor 400.

[0131] In addition, if Figure 9dAs shown, the power supply line is usually located at the outermost periphery of all the lines. When the drain 13 of any vertical transistor needs to be electrically connected to the power supply line, a conductive layer can be overlapped on the drain 13 of any vertical transistor without changing the size of the drain 13, so that the drain 13 of any vertical transistor is connected to the line in the metal layer M0 by means of the conductive layer. The conductive layer overlapped on the drain 13 protrudes from the drain 13 in the Y direction.

[0132] In some possible implementations, the channel layer 14 of each of the vertical transistors can be prepared by the same semiconductor process, and the specific process is implemented by the following steps:

[0133] Figure 10a-Figure 10i Taking the preparation of four channel layers 14 as an example, the preparation process of the channel layer 14 is shown. Figure 9a As shown, a first mask layer 51, a second mask layer 52 and a photoresist 53 may be sequentially formed on the semiconductor film layer 141. Fig.10b As shown, the photoresist 53 is exposed and developed to obtain a photoresist pattern 531. Fig.10c and Fig.10d As shown, under the protection of the photoresist pattern 531, the second mask layer 52 is etched to obtain the second mask pattern 521, and the photoresist pattern 531 is removed. Fig.10e As shown, with the second mask pattern 521 as the main axis (mandrel), a spacer 54 is formed on the side of the second mask pattern 521 away from the substrate 10. Fig.10f As shown, dry etching is used to etch the spacer layer 54 to obtain spacer patterns 541, and the spacer patterns 541 are located on two opposite sides of each first mask pattern 521. Figure 10g As shown, the second mask pattern 521 is removed. Fig.10h As shown, under the protection of the spacer pattern 541, the first mask layer 51 is etched to obtain the first mask pattern 511. Fig.10i As shown, the spacer pattern 541 is removed, and under the protection of the first mask pattern 511 , the semiconductor film layer 141 is partially etched to obtain the channel layer 14 .

[0134] Figure 10a-Figure 10i Taking the self-aligned double patterning (SADP) technology as an example, the process of preparing the channel layer 14 is described. In other possible implementations, the channel layer 14 can also be prepared by using the self-aligned quadruple patterning (SAQP) technology or other technologies, which is not limited in the embodiments of the present application.

[0135] In some embodiments, based on the premise that the through hole V01, the through hole V02, and the gate through hole V03 are arranged in sequence along the Y direction, as shown in FIG. Fig.11 As shown, an N-type vertical transistor and a P-type vertical transistor are usually arranged opposite to each other along the Y direction, and the gate 12 of the two is shared. In the Y direction, the through hole V01 corresponding to the N-type vertical transistor, the through hole V02 corresponding to the N-type vertical transistor, the gate through hole V03, the through hole V02 corresponding to the P-type vertical transistor, and the through hole V01 corresponding to the P-type vertical transistor are arranged in sequence. Among them, the through hole V01 is located at the periphery of the through hole V02.

[0136] For standard cells with more complex circuit connections, such as a two-input NAND gate (NAND2) and a two-input NOR gate (NOR2), standard cells include an even number of N-type vertical transistors connected in series or an even number of P-type vertical transistors connected in series.

[0137] Multiple vertical transistors of the same N-type or P-type are usually arranged along the X direction. Fig.12a and Figure 12b The schematic diagram of two vertical transistors connected in series through wiring is shown. When the two vertical transistors are turned on, the first wiring 51 is electrically connected to the source 11 of the first vertical transistor through the through hole V01, and a signal is input. The signal is transmitted from the source 11 of the first vertical transistor through the channel layer 14 and the drain 13 of the first vertical transistor to the second wiring 52 electrically connected to the drains 13 of the two vertical transistors, so that the signal is transmitted from the drain 13 of the first vertical transistor to the drain 13 of the second vertical transistor through the second wiring 52. Then, the signal is transmitted from the drain 13 of the second vertical transistor through the channel layer 14 of the second vertical transistor to the source 11 of the second vertical transistor, and is output through the output wiring.

[0138] Based on the existing wiring design, without adding additional wiring tracks, because the two through holes V01 are arranged opposite to the first wiring 31, the source 11 of the second vertical transistor is electrically connected to the first wiring 31 through the through hole V01 instead of being electrically connected to the output wiring, thereby causing the two vertical transistors to be short-circuited.

[0139] in, Fig.12a and Figure 12b The bold dashed line with an arrow in the figure represents a signal transmission path, and the dashed box without an arrow in each figure represents each through hole. Two conductive structures located on opposite sides of the through hole can be electrically connected through the through hole.

[0140] The other corresponding figures below are still marked according to this rule and will not be described in detail one by one.

[0141] In order to solve the above short circuit problem, the related technology proposes the following three solutions:

[0142] First, as Fig.13 As shown, an additional wiring track is added so that the first wiring 51, the second wiring 52, and the output wiring 53 are staggered in the Y direction. However, the additional wiring track increases the size of the standard unit in the Y direction, which is less competitive.

[0143] Second, by using the backside power grid technology, a wiring track is designed on the side of the substrate 10 away from the transistor (the back side). However, the process of designing a wiring track on the back side of the substrate 10 is relatively difficult and is still in the experimental stage and has not been widely used.

[0144] Third, increase the number of metal layers and dielectric layers in the chip, increase the number of through holes in the dielectric layer, first use a metal layer to lead the signal to an open position, and then rely on the upper metal layer to connect. However, the design with more metal layers and through holes not only increases the design and manufacturing costs of the chip, but also causes a large transmission delay of the signal, affecting the performance and speed of the device.

[0145] Based on this, Fig.14 As shown, the second vertical transistor may be the first vertical transistor 100 of the present application, the first vertical transistor may be the fifth vertical transistor 500 of the present application, and the first vertical transistor 100 and the fifth vertical transistor 500 are arranged side by side in the X direction. The source 11 of the first vertical transistor 100 and the source 11 of the fifth vertical transistor 500 are shared, so that the source 11 of the first vertical transistor 100 and the source 11 of the fifth vertical transistor 500 are electrically connected, that is, the first vertical transistor 100 and the fifth vertical transistor 500 are connected in series.

[0146] The first wiring 51 is electrically connected to the drain 13 of the first vertical transistor through the through hole V01, and inputs a signal. The signal is transmitted from the drain 13 of the fifth vertical transistor 500, through the channel layer 14 and the source 11 of the fifth vertical transistor 500, to the source 11 of the first vertical transistor 100, and then from the source 11 of the first vertical transistor 100, through the channel layer 14 and the drain 13 of the first vertical transistor 100, to the gate 12 of the second transistor 200.

[0147] In this signal transmission path, the second wiring 52 is omitted, thereby preventing the first vertical transistor 100 and the fifth vertical transistor 500 from being short-circuited without adding additional wiring tracks.

[0148] It should be understood that, as mentioned above, the first trace 51 is located in the metal layer M0, and the metal layer M0 is located on the side of the dielectric layer 0 away from the substrate 10. The conductive layer is located on the side of the dielectric layer 0 facing the substrate 10. Therefore, Fig.15As shown, the first trace 51 and the conductive layer are not arranged in the same layer, but the conductive layer, dielectric layer 0, and metal layer M0 are stacked in sequence along the Z direction. Among them, dielectric layer 0 is the first dielectric layer of the embodiment of the present application, and metal layer M0 is the trace layer of the embodiment of the present application. Fig.15 FIG. 4 is an illustrative diagram showing the positional relationship among the conductive layer, the dielectric layer 0, and the metal layer M0.

[0149] In the embodiment of the present application, the metal layer M0 on each vertical transistor and the spacer layer 30 may include a first power supply line, a second power supply line, a first gate line, a second gate line, etc. Among them, the first power supply line may be VSS, GND, etc., and the second power supply line may be VDD, etc. The first gate line and the second gate line are located in different wiring tracks, that is, the first gate line and the second gate line are arranged at intervals in the Y direction. Correspondingly, refer to Fig.14 The gate through hole VO3 connected to the first gate wiring and the gate through hole VO3 connected to the second gate wiring are staggered in the Y direction.

[0150] In conjunction with actual circuits, the following describes in detail how the first vertical transistor 100 and the second vertical transistor 200 achieve circuit connection through various routings of the metal layer M0.

[0151] The first application scenario, such as Fig.16a As shown, the standard cell is a two-input AND gate (AND2). AND2 includes a first N-type vertical transistor N1, a second N-type vertical transistor N2, a third N-type vertical transistor N3, a first P-type vertical transistor P1, a second P-type vertical transistor P2, and a third P-type vertical transistor P3. Among them, the first vertical transistor 100 is the second N-type vertical transistor N2, and the second vertical transistor 200 is the third N-type vertical transistor N3.

[0152] like Fig.16a and Fig.16b As shown, the gate 12 of the first N-type vertical transistor N1 is electrically connected to the first gate wiring 61, the drain 13 of the first N-type vertical transistor N1 is electrically connected to the first power wiring VSS, and the source 11 of the first N-type vertical transistor N1 is electrically connected to the source of the second N-type vertical transistor N2.

[0153] The gate 12 of the second N-type vertical transistor N2 is electrically connected to the second gate wiring 62, and the drain 13 of the second N-type vertical transistor N2 is electrically connected to the drain 13 of the first P-type vertical transistor P1, the drain 13 of the second P-type vertical transistor P2, the gate 12 of the third P-type vertical transistor P3, and the gate 12 of the third N-type vertical transistor N3, respectively.

[0154] The source 11 of the third N-type vertical transistor N3 is electrically connected to the first power supply line VSS, the drain 13 of the third N-type vertical transistor N3 is electrically connected to the drain 13 of the third P-type vertical transistor P3, and the source 11 of the third P-type vertical transistor P3 is electrically connected to the second power supply line VDD.

[0155] The gate 12 of the first P-type vertical transistor P1 is electrically connected to the first gate wiring 61 , and the source 11 of the first P-type vertical transistor P1 is electrically connected to the second power wiring VDD.

[0156] The gate 12 of the second P-type vertical transistor P2 is electrically connected to the second gate wiring 62 , and the source 11 of the second P-type vertical transistor P2 is electrically connected to the second power wiring VDD.

[0157] Fig.16c A partial perspective view of AND2 is shown, Fig.16d FIG. 2 shows a stereogram of the AND2. Fig.16c and Fig.16d As shown, the drain 13 of the second N-type vertical transistor N2 is electrically connected to the gate 12 of the third P-type vertical transistor P3 and the gate 12 of the third N-type vertical transistor N3 through the first conductive layer 41 .

[0158] On this basis, in order to realize the electrical connection between the drain 13 of the second N-type vertical transistor N2 and the drain 13 of the first P-type vertical transistor P1 and the drain 13 of the second P-type vertical transistor P2, the second conductive layer 42 can be used to electrically connect the drain 13 of the first P-type vertical transistor P1 and the drain 13 of the second P-type vertical transistor P2, and then the connecting conductive structure 71 in the metal layer M1 can be used to electrically connect the first conductive layer 41 and the second conductive layer 42.

[0159] Among some possible implementations, Fig.16b As shown, for the first N-type vertical transistor N1 and the second N-type vertical transistor N2 connected in series, the source 11 of the first N-type vertical transistor N1 and the source 11 of the second N-type vertical transistor N2 can be shared to save the number of wirings in the metal layer M0. For the first P-type vertical transistor P1 and the second P-type vertical transistor P2 connected in series, the source 11 of the first P-type vertical transistor P1 and the source 11 of the second P-type vertical transistor P2 can be shared to save the number of wirings in the metal layer M0.

[0160] The second application scenario, such as Fig.17a and Fig.17b As shown, the standard unit is a two-to-one data selector, which includes an inverter, a logic operator, and a strong drive inverter.

[0161] The inverter includes a sixth N-type vertical transistor N6 and a sixth P-type vertical transistor P6. The logic operator includes a first N-type vertical transistor N1, a second N-type vertical transistor N2, a third N-type vertical transistor N3, a fourth N-type vertical transistor N4, a first P-type vertical transistor P1, a second P-type vertical transistor P2, a third P-type vertical transistor P3, and a fourth P-type vertical transistor P4. The strong drive inverter includes a fifth P-type vertical transistor P5 and a fifth N-type disposal transistor N5. The strong drive inverter includes a fifth P-type vertical transistor P5 and a fifth N-type vertical transistor N5.

[0162] In the inverter, the gate 12 of the sixth N-type vertical transistor N6 and the gate 12 of the sixth P-type vertical transistor P6 are both electrically connected to the gate wiring S, and the source 11 of the sixth N-type vertical transistor N6 is electrically connected to the second power wiring VDD. The drain 13 of the sixth N-type vertical transistor N6 is electrically connected to the gate 12 of the first P-type vertical transistor P1 and the gate 12 of the first N-type vertical transistor N1. The sixth N-type vertical transistor N6 and the sixth P-type vertical transistor P6 in the inverter are used to invert the signal on the gate wiring S to obtain an inverted signal Sbar, and input the inverted signal Sbar to the gate 12 of the first P-type vertical transistor P1 and the gate 12 of the first N-type vertical transistor N1 through the drain 13 of the sixth P-type vertical transistor P6 and the first conductive layer 41.

[0163] Among them, the sixth P-type vertical transistor P6 is the first vertical transistor 100 of the present application, and the first P-type vertical transistor P1 and the first N-type vertical transistor N1 are the second vertical transistor 200 of the present application.

[0164] In the logic operator, the source 11 of the first P-type vertical transistor P1, the source 11 of the second P-type vertical transistor P2, the source 11 of the third P-type vertical transistor P3, and the source 11 of the fourth P-type vertical transistor P4 are electrically connected. The source 11 of the first P-type vertical transistor P1, the source 11 of the second P-type vertical transistor P2, the source 11 of the third P-type vertical transistor P3, and the source 11 of the fourth P-type vertical transistor P4 can be made to share the source 11 of the first P-type vertical transistor P1, the source 11 of the second P-type vertical transistor P2, the source 11 of the third P-type vertical transistor P3, and the source 11 of the fourth P-type vertical transistor P4, so as to reduce the number of wirings in the metal layer M0.

[0165] The drain 13 of the first P-type vertical transistor P1, the drain 13 of the third P-type vertical transistor P3, and the source 11 of the fifth P-type vertical transistor P5 are all electrically connected to the second power supply line VDD; the drain 13 of the second P-type vertical transistor P2 and the drain 13 of the fourth P-type vertical transistor P4 are electrically connected through the second conductive layer 42, and the drain 13 of the first N-type vertical transistor N1 and the drain 13 of the third N-type vertical transistor N3 are electrically connected through the second conductive layer 42, and then the two second conductive layers 42 are electrically connected by using the connecting conductive structure 71 in the metal layer M1, so as to realize the electrical connection of the drain 13 of the first N-type vertical transistor N1, the drain 13 of the third N-type vertical transistor N3, the drain 13 of the first N-type vertical transistor N1, and the drain 13 of the third N-type vertical transistor N3.

[0166] The gate 12 of the second P-type vertical transistor P2 is electrically connected to the gate 12 of the sixth N-type vertical transistor N6 and the gate 12 of the sixth P-type vertical transistor P6 through the gate wiring S, the gate 12 of the third P-type vertical transistor P3 is electrically connected to the gate wiring A, and the gate 12 of the fourth P-type vertical transistor P4 is electrically connected to the gate wiring B.

[0167] The source 11 of the first N-type vertical transistor is electrically connected to the source 11 of the second N-type vertical transistor N2, and the source 11 of the third N-type vertical transistor N3 is electrically connected to the source 11 of the fourth N-type vertical transistor N4. The source 11 of the first N-type vertical transistor can be electrically connected to the source 11 of the second N-type vertical transistor N2 by making the source 11 of the first N-type vertical transistor and the source 11 of the second N-type vertical transistor N2 shared; the source 11 of the third N-type vertical transistor N3 can be electrically connected to the source 11 of the fourth N-type vertical transistor N4 by making the source 11 of the third N-type vertical transistor N3 and the source 11 of the fourth N-type vertical transistor N4 shared, so as to reduce the number of wirings in the metal layer M0.

[0168] The drain 13 of the second N-type vertical transistor N2, the drain 13 of the fourth N-type vertical transistor N4, the source 11 of the fifth N-type vertical transistor N5, and the drain 13 of the sixth N-type vertical transistor N6 are all electrically connected to the first power supply wiring VSS. The gate 12 of the fourth N-type vertical transistor N4 is electrically connected to the gate 12 of the fourth P-type vertical transistor P4 through the gate wiring B, the gate 12 of the third N-type vertical transistor N3 is electrically connected to the gate 12 of the second P-type vertical transistor P2 through the gate wiring S, and the gate 12 of the second N-type vertical transistor N2 is electrically connected to the gate 12 of the third P-type vertical transistor P3 through the gate wiring A.

[0169] The logic operator is used to select the input signal according to the signal input by the gate wiring S and the gate wiring Sbar to obtain the selection result. On this basis, the drain 13 of the first N-type vertical transistor N1 is also electrically connected to the gate 12 of the fifth P-type vertical transistor P5 and the gate 12 of the fifth N-type disposal transistor N5 through the first conductive layer 41, so that the drain 13 of the first N-type vertical transistor N1 can be used to input the selection result to the gate 12 of the fifth P-type vertical transistor P5 and the gate 12 of the fifth N-type disposal transistor N5 through the first conductive layer 41. Among them, the first N-type vertical transistor N1 is the first vertical transistor 100 of the present application, and the fifth N-type vertical transistor N5 is the second vertical transistor 200 of the present application.

[0170] In the strong drive inverter, the drain 13 of the fifth N-type vertical transistor N5 and the drain 13 of the fifth P-type vertical transistor P5 are both electrically connected to the output wiring OUT in the metal layer M1. The strong drive inverter is used to invert the input signal under the control of the selection result and output the inversion result to the output wiring OUT.

[0171] In some possible implementations, the channel layer 14 of the fifth N-type vertical transistor N5 and the channel layer 14 of the fifth P-type vertical transistor P5 are longer in the Y direction to provide a larger driving current, thereby achieving strong driving inversion.

[0172] In another embodiment, the present application also provides a circuit layout database, such as Fig.18 As shown, the circuit layout database (represented by Library) contains one or more folders (e.g., folder 1, folder 2, folder 3, folder 4), each folder includes one or more standard cells (e.g., AND gate, NAND gate, AND2, MUX2to1), and each standard cell includes the layout (layout), circuit diagram (schematic), and electrical component graphic symbol (symbol) of the standard cell. For example, the electrical component graphic symbol of the inverter is represented by a triangle.

[0173] by Fig.18 Taking the circuit layout database shown as an example, the circuit layout database includes folder 1, folder 2, folder 3, and folder 4. Folder 4 includes AND, NAND, AND2, MUX 2to1, etc., among which the layout, circuit diagram, and electrical component graphic symbols of the standard unit AND2 are presented in the View column.

[0174] In some possible implementations, the circuit layout database may be a database of functional devices required by the electronic device, or a database of standard cells set on one or more chips. Of course, the circuit layout database may also be other, and the embodiment of the present application does not limit the circuit specifically indicated by the circuit layout database. Among them, the functional devices required by the electronic device may be, for example, a memory, a processor, etc.

[0175] like Figure 5 As shown, the standard cell includes a first vertical transistor 100 and a second vertical transistor 200 arranged side by side along the X direction, and the layout of the standard cell includes a first layer, a second layer, and a third layer stacked in sequence.

[0176] The first layer includes the source 11 of the first vertical transistor 100 and the source 11 of the second vertical transistor 200; the second layer includes the gate 12 of the first vertical transistor 100 and the gate 12 of the second vertical transistor 200; the third layer includes the drain 13 of the first vertical transistor 100 and the drain 13 of the second vertical transistor 200.

[0177] The third layer further includes a gate connection structure 21 overlapping with the gate 12 of the second vertical transistor 200 . The gate connection structure 21 and the drain 13 of the second vertical transistor 200 are arranged along the Y direction, which is perpendicular to the X direction.

[0178] The third layer also includes a conductive layer; or the layout of the standard cell also includes a fourth layer located on the third layer, and the fourth layer includes a conductive layer. The conductive layer includes a first conductive layer 41, and the first conductive layer 41 overlaps with the drain 13 and the gate connection structure 21 of the first vertical transistor 100 respectively.

[0179] Those skilled in the art should know that Figure 5 As shown, the layout is a planar structure, which reflects the stacking relationship of each structure in the standard unit without using layers. As mentioned above, the first layer, the second layer, the third layer, and the fourth layer are stacked in sequence, and on the chip, the patterns contained in the first layer, the second layer, the third layer, and the fourth layer are stacked along the Z direction.

[0180] When drawing the layout, you can also draw it in the order of the first layer, the second layer, the third layer, and the fourth layer.

[0181] Specifically, after obtaining the circuit diagram of the standard unit, such as Fig.19a As shown, according to the circuit diagram, the source 11 of the first vertical transistor 100 and the source 11 of the second vertical transistor 200 arranged side by side along the X direction in the first layer are first drawn.

[0182] Then, if Fig.19bAs shown, according to the circuit diagram, the gate 12 of the first vertical transistor 100 and the gate 12 of the second vertical transistor 200 are drawn in the second layer.

[0183] Then, if Fig.19c As shown, according to the circuit diagram, the drain 13 of the first vertical transistor 100 and the drain 13 of the second vertical transistor 200 in the third layer, as well as the gate connection structure 21 overlapping with the gate 12 of the second vertical transistor 200 are drawn. Figure 5 As shown, a conductive layer in the third layer can also be drawn.

[0184] If Fig.19c As shown, the third layer does not include a conductive layer. Figure 5 As shown, the conductive layer in the fourth layer can also be drawn according to the circuit diagram.

[0185] In some possible implementations, such as Fig.19c As shown, the channel layer 14 is located on the chip through the drain 13, the gate 12, and the source 11, and in the layout of the standard unit, the channel layer 14 can be located in the first layer, the second layer, and the third layer; or, the channel layer 14 can also be located in the fourth layer.

[0186] In some embodiments, the circuit layout database also includes layer information, which includes graphic border information, graphic filler information, and graphic color information of the first layer, the second layer, the third layer, the fourth layer, the fifth layer, and the sixth layer. The layer information can be stored in the circuit layout database in text format.

[0187] For example, Fig. 20 As shown, the graphic borders of all graphics in the first layer including the source (bottom source drain, btm SD) 11 are solid lines, the graphic fills are denser dots, and the graphic color is black; the graphic borders of all graphics in the second layer including the gate (Gate) 12 are solid lines, the graphic fills are sparser dots, and the graphic color is black; the graphic borders of all graphics in the third layer including the second pole (top source drain, top SD) 13 are solid lines, the graphic fills are oblique lines, and the graphic color is black.

[0188] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as the explanations and beneficial effects of a chip in the aforementioned embodiment, and will not be repeated here.

[0189] In some possible implementations, the embodiment of the present application does not limit the shape of the cross section of the first conductive layer 41, as long as the first conductive layer 41 extends from the position in contact with the drain 13 of the first vertical transistor 100 to the position in contact with the gate 12 of the second vertical transistor. Optionally, the cross section of the first conductive layer 41 may be L-shaped, wherein the cross section is the plane where the X direction and the Y direction are located.

[0190] In some embodiments, Figure 9b As shown, the standard cell further includes a third vertical transistor 300 and a fourth vertical transistor 400, and the conductive layer further includes a second conductive layer 42. The first layer further includes a source 11 of the third vertical transistor and a source 11 of the fourth vertical transistor; the second layer further includes a gate 12 of the third vertical transistor 300 and a gate 12 of the fourth vertical transistor 400; the third layer further includes a drain 13 of the third vertical transistor and a drain 13 of the fourth vertical transistor; in the third direction, the drain 13 of the third vertical transistor 300 exceeds the drain 13 of the fourth vertical transistor 400 in the third direction, and the portion where the drain 13 of the third vertical transistor 300 exceeds the drain 13 of the fourth vertical transistor 400 is a protruding portion; the conductive layer overlaps with the drain 13 of the fourth vertical transistor 400 and the protruding portion, respectively.

[0191] The second conductive layer 42 overlaps with the protruding portion and the drain 13 of the fourth vertical transistor 400 respectively, and the drain 13 of the third vertical transistor 300 is electrically connected to the drain 13 of the fourth vertical transistor 400 through the second conductive layer 42, thereby avoiding the drain 13 of the third vertical transistor 300 being electrically connected to the drain 13 of the fourth vertical transistor 400 through the routing of the metal layer M0, shortening the electrical connection path between the drain 13 of the third vertical transistor 300 and the drain 13 of the fourth vertical transistor 400.

[0192] In this case, the embodiment of the present application does not limit the shape of the cross section of the second conductive layer 42, as long as the second conductive layer 42 extends from the position in contact with the protruding portion to the position in contact with the drain 13 of the fourth vertical transistor 400. Optionally, the cross section of the second conductive layer 42 may be L-shaped, wherein the cross section is a plane where the X direction and the Y direction are located.

[0193] In some embodiments, the standard cell further includes a fifth vertical transistor 500 arranged side by side with the first vertical transistor 100 in the first direction. The first layer also includes a source 11 of the fifth vertical transistor 500, the second layer also includes a gate 12 of the fifth vertical transistor 500, and the third layer also includes a drain 13 of the fifth vertical transistor 500. The source 11 of the first vertical transistor 100 is shared with the source 11 of the fifth vertical transistor 500, so that the source 11 of the first vertical transistor 100 and the source 11 of the fifth vertical transistor 500 are electrically connected, that is, the first vertical transistor 100 and the fifth vertical transistor 500 are connected in series.

[0194] In some embodiments, the layout of the standard cell further includes a fifth layer disposed on the fourth layer. The fifth layer includes a routing layer; the routing layer includes a first power routing, a second power routing, a second gate routing, and a second gate routing, and the first power routing, the second power routing, the second gate routing, and the second gate routing are distributed on different wiring tracks in the third direction.

[0195] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as the explanations and beneficial effects of a chip in the aforementioned embodiment, and will not be repeated here.

[0196] In another embodiment, the present application provides a chip design method. After obtaining the above-mentioned circuit layout database, the designer can directly call one or more required standard cells from the circuit layout database to design other circuit layouts using the one or more standard cells. Specifically, based on the designer's operation, the device storing the circuit layout database receives a target instruction, and in response to the target instruction, calls one or more standard cells in the circuit layout database described in the previous embodiment.

[0197] It is understandable that, in order to realize the above functions, the electronic device includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of the present application.

[0198] In one example, Fig.21 A schematic block diagram of a device 1000 according to an embodiment of the present application is shown. The device 1000 may include: a processor 301 and a transceiver / transceiver pin 302 , and optionally, a memory 303 .

[0199] The various components of the device 1000 are coupled together via a bus 304, wherein the bus 304 includes a power bus, a control bus, and a status signal bus in addition to a data bus. However, for the sake of clarity, various buses are referred to as bus 304 in the figure.

[0200] Optionally, the memory 303 may be used for instructions in the aforementioned method embodiment. The processor 301 may be used to execute instructions in the memory 303, and control the receiving pin to receive a signal, and control the sending pin to send a signal.

[0201] The apparatus 1000 may be the electronic device or a chip of the electronic device in the above method embodiment.

[0202] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here.

[0203] This embodiment also provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the chip design method in the above-mentioned embodiment.

[0204] This embodiment also provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute the above-mentioned related steps to implement the chip design method in the above-mentioned embodiment.

[0205] In addition, an embodiment of the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer execution instructions, and when the device is running, the processor can execute the computer execution instructions stored in the memory so that the chip executes the chip design method in the above-mentioned method embodiments.

[0206] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above and will not be repeated here.

[0207] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0208] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0209] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0210] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0211] Any content of each embodiment of the present application, as well as any content of the same embodiment, can be freely combined. Any combination of the above content is within the scope of the present application.

[0212] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0213] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A chip, characterized in that: The invention comprises a standard cell arranged on a substrate, wherein the standard cell comprises: A first vertical transistor and a second vertical transistor are arranged side by side along a first direction; the first vertical transistor and the second vertical transistor each include a first electrode, a gate, and a second electrode stacked in sequence along a second direction; the first direction is perpendicular to the second direction, and the second direction is a direction from the substrate to the first electrode; A spacer layer; a first gate through hole is formed in the spacer layer, a gate connection structure is filled in the first gate through hole, the gate connection structure is in contact with the gate of the second vertical transistor, and the gate connection structure and the second electrode of the second vertical transistor are arranged along a third direction; wherein the first direction and the second direction are both perpendicular to the third direction; A conductive layer is arranged on the side of the spacer layer away from the substrate, and the conductive layer includes a first conductive layer; the first conductive layer is respectively in contact with the second electrode of the first vertical transistor and the gate connection structure, and the second electrode of the first vertical transistor is electrically connected to the gate of the second vertical transistor through the first conductive layer and the gate connection structure.

2. The chip according to claim 1, characterized in that: The spacer layer is located between the gate of the first vertical transistor and the gate of the second vertical transistor and the second electrode of the first vertical transistor and the second electrode of the second vertical transistor; The second electrode of the second vertical transistor is formed in the same layer and material as the first conductive layer.

3. The chip according to claim 1, characterized in that: The spacer layer covers the first vertical transistor and the second vertical transistor, and exposes the upper surface of the second electrode of the first vertical transistor; The upper surface of the second electrode of the first vertical transistor is in contact with the first conductive layer; wherein the upper surface of the second electrode of the first vertical transistor is a surface of the second electrode of the first vertical transistor that is away from the substrate.

4. The chip according to any one of claims 1 to 3, characterized in that: The standard cell further includes a third vertical transistor and a fourth vertical transistor, and the conductive layer further includes a second conductive layer; The third vertical transistor and the fourth vertical transistor are arranged side by side in the first direction, and another vertical transistor is arranged between the third vertical transistor and the fourth vertical transistor; The third vertical transistor and the fourth vertical transistor each include the first electrode, the gate, and the second electrode sequentially stacked along the second direction; in the third direction, the second electrode of the third vertical transistor exceeds the second electrode of the fourth vertical transistor in the third direction, and a portion of the second electrode of the third vertical transistor exceeding the second electrode of the fourth vertical transistor is a protruding portion; The second conductive layer is in contact with the protruding portion and the second electrode of the fourth vertical transistor, respectively, and the second electrode of the third vertical transistor is electrically connected to the second electrode of the fourth vertical transistor through the second conductive layer.

5. The chip according to claim 4, characterized in that: The cross-sections of the first conductive layer and the second conductive layer are both L-shaped; The cross section is a plane where the first direction and the third direction are located.

6. The chip according to any one of claims 1 to 5, characterized in that: The standard cell further includes a fifth vertical transistor arranged side by side with the first vertical transistor in the first direction, and the fifth vertical transistor includes the first electrode, the gate, and the second electrode sequentially stacked along the second direction; The first electrode of the first vertical transistor is shared with the first electrode of the fifth vertical transistor.

7. The chip according to claim 6, characterized in that: The standard unit also includes a first dielectric layer and a routing layer sequentially arranged on the conductive layer; The routing layer includes a first power routing, a second power routing, a first gate routing, and a second gate routing. The first power routing, the second power routing, the first gate routing, and the second gate routing are distributed on different routing tracks in the third direction.

8. The chip according to claim 7, characterized in that: The standard cell is a two-input AND gate; The standard cell further includes a first N-type vertical transistor, a first P-type vertical transistor, a second P-type vertical transistor, and a third P-type vertical transistor; the first vertical transistor is a second N-type vertical transistor, and the second vertical transistor is a third N-type vertical transistor; The gate of the first N-type vertical transistor is electrically connected to the first gate wiring, the second electrode of the first N-type vertical transistor is electrically connected to the first power wiring, and the first electrode of the first N-type vertical transistor is electrically connected to the first electrode of the second N-type vertical transistor; The gate of the second N-type vertical transistor is electrically connected through the second gate wiring, and the second electrode of the second N-type vertical transistor is electrically connected to the second electrode of the first P-type vertical transistor, the second electrode of the second P-type vertical transistor, the gate of the third P-type vertical transistor, and the gate of the third N-type vertical transistor N3 respectively; The first electrode of the third N-type vertical transistor N3 is electrically connected to the first power supply line, the second electrode of the third N-type vertical transistor N3 is electrically connected to the second electrode of the third P-type vertical transistor, and the first electrode of the third P-type vertical transistor is electrically connected to the second power supply line; The gate of the first P-type vertical transistor is electrically connected to the first gate wiring, and the first electrode of the first P-type vertical transistor is electrically connected to the second power wiring; The gate of the second P-type vertical transistor is electrically connected to the second gate wiring, and the first electrode of the second P-type vertical transistor is electrically connected to the second power wiring; The second electrode of the second N-type vertical transistor is electrically connected to the gate of the third P-type vertical transistor and the gate of the third N-type vertical transistor N3 through the first conductive layer.

9. The chip according to claim 8, characterized in that: The first N-type vertical transistor is the fifth vertical transistor, and the first electrode of the first N-type vertical transistor is shared with the first electrode of the second N-type vertical transistor.

10. The chip according to claim 6, characterized in that: The standard unit is a two-to-one data selector, which includes an inverter, a logic operator, and a strong drive inverter; The inverter includes the first vertical transistor, and the logic operator includes the second vertical transistor; the logic operator includes the first vertical transistor, and the strong drive inverter includes the second vertical transistor.

11. An electronic device, characterized in that: It comprises a circuit board and the chip according to any one of claims 1 to 10, wherein the chip is arranged on the circuit board.

12. A circuit layout database, characterized in that: The method comprises a plurality of standard cells, each of which comprises a layout and a circuit diagram of the standard cell; the standard cell comprises a first vertical transistor and a second vertical transistor arranged side by side along a first direction; The layout of the standard cell includes a first layer, a second layer, and a third layer stacked in sequence; The first layer includes a first electrode of the first vertical transistor and the first electrode of the second vertical transistor; the second layer includes a gate of the first vertical transistor and the gate of the second vertical transistor; the third layer includes a second electrode of the first vertical transistor and the second electrode of the second vertical transistor; The third layer further includes a gate connection structure that overlaps with the gate of the second vertical transistor, and the gate connection structure and the second electrode of the second vertical transistor are arranged in a third direction, and the third direction is perpendicular to the first direction; The third layer also includes a conductive layer; or the layout of the standard unit also includes a fourth layer located on the third layer, and the fourth layer includes the conductive layer; the conductive layer includes a first conductive layer, and the first conductive layer overlaps with the second electrode and the gate connection structure of the first vertical transistor respectively.

13. The circuit layout database according to claim 12, characterized in that: The standard cell further includes a third vertical transistor and a fourth vertical transistor, and the conductive layer further includes a second conductive layer; The first layer also includes the first electrode of the third vertical transistor and the first electrode of the fourth vertical transistor; The second layer further includes the gate of the third vertical transistor and the gate of the fourth vertical transistor; The third layer further includes the second electrode of the third vertical transistor and the second electrode of the fourth vertical transistor; in the third direction, the second electrode of the third vertical transistor exceeds the second electrode of the fourth vertical transistor in the third direction, and a portion of the second electrode of the third vertical transistor exceeding the second electrode of the fourth vertical transistor is a protruding portion; The second conductive layer overlaps with the second electrode and the protruding portion of the fourth vertical transistor, respectively.

14. The circuit layout database according to claim 13, characterized in that: The cross-sections of the first conductive layer and the second conductive layer are both L-shaped; The cross section is a plane where the first direction and the third direction are located.

15. The circuit layout database according to any one of claims 12 to 14, characterized in that: The standard cell further includes a fifth vertical transistor arranged side by side with the first vertical transistor in the first direction; The first layer further includes the first electrode of the fifth vertical transistor, the second layer further includes the gate of the fifth vertical transistor, and the third layer further includes the second electrode of the fifth vertical transistor; The first electrode of the first vertical transistor is shared by the first electrode of the fifth vertical transistor.

16. The circuit layout database according to any one of claims 12 to 15, characterized in that: The layout of the standard cell further includes a fifth layer; when the layout of the standard cell includes a fourth layer, the fifth layer is arranged on the fourth layer; when the layout of the standard cell does not include the fourth layer, the fifth layer is arranged on the third layer; The fifth layer includes a routing layer; the routing layer includes a first power routing, a second power routing, a first gate routing, and a second gate routing, and the first power routing, the second power routing, the first gate routing, and the second gate routing are distributed in different wiring tracks in the third direction.

17. The circuit layout database according to claim 16, characterized in that: The circuit layout database also includes layer information, and the layer information includes graphic border information, graphic fill information, and graphic color information of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer.

18. A chip design method, characterized in that: include: receiving target instructions; In response to the target instruction, one or more standard cells in the circuit layout database of any one of claims 12-17 are called.

19. A circuit layout design device, characterized in that: include: A memory and a processor, wherein the memory is electrically connected to the processor; The memory stores program instructions, and when the program instructions are executed by the processor, the electronic device executes the chip design method according to claim 18.

20. A computer-readable storage medium comprising a computer program, characterized in that: When the computer program runs on an electronic device, the electronic device executes the chip design method according to claim 18.

21. A computer program product, characterized in that When the computer program product is run on a computer, the computer is enabled to execute the chip design method as claimed in claim 18 .

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