Array substrate, manufacturing method thereof and display panel

Abstract

The invention relates to an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a substrate, a metal composite layer, an active layer, a gate insulation layer and a gate. The active layer is arranged on the metal composite layer and comprises a channel part and conductor parts located on the two sides of the channel part, the channel part corresponds to the metal shading part in position, the conductor part on one side forms a source electrode, corresponds to the metal wire in position and is electrically connected with the metal wire, and the conductor part on the other side comprises a drain electrode and a second electrode part which are electrically connected with each other. The second electrode part corresponds to the first electrode part in position in the thickness direction of the array substrate; the gate insulating layer is arranged on the active layer, and the gate is arranged on the gate insulating layer.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] In display devices, TFT (Thin Film Transistor) is generally used as a switch element to control the operation of pixels, or as a driving element to drive pixels; and top-gate TFT is widely used in large-size panels due to its small parasitic capacitance and large Ion current (ion current). In order to simplify the process of top-gate TFT, the industry has introduced LSD technology, that is, LS (Light shield) and source and drain SD are patterned on the same metal layer. Compared with the conventional 9-10 Mask process, LSD technology uses an 8 Mask process, thereby saving costs and production capacity by reducing masks; however, the 8 Mask process of LSD technology is still relatively complex, and it is urgent to propose a TFT with a simpler structure and process. Summary of the invention

[0003] The embodiments of the present application provide an array substrate and a manufacturing method thereof, and a display panel, which can simplify the manufacturing process of a top-gate array substrate.

[0004] In order to achieve the above object, according to a first aspect of the present application, an array substrate is provided, comprising:

[0005] substrate;

[0006] A metal composite layer is disposed on the substrate, wherein the metal composite layer includes a metal wiring, a metal light shielding portion and a first electrode portion;

[0007] an active layer, arranged on the metal composite layer, the active layer comprising a channel portion and conductor portions located on both sides of the channel portion, the channel portion corresponding to the metal light shielding portion, the conductor portion on one side forming a source electrode corresponding to the metal wiring position and electrically connected, the conductor portion on the other side comprising an electrically connected drain electrode and a second electrode portion, the second electrode portion corresponding to the first electrode portion in the thickness direction of the array substrate; and

[0008] A gate insulating layer, disposed on the channel portion;

[0009] The gate is arranged on the gate insulating layer.

[0010] In one embodiment, the metal composite layer comprises:

[0011] A first metal layer includes a first conductor portion, a second conductor portion, and a third conductor portion;

[0012] A second metal layer, disposed on an upper surface of the first metal layer, the second metal layer comprising a fourth conductor portion and a fifth conductor portion;

[0013] The fourth conductor portion corresponds to the second electrode portion and forms the metal shading portion, the fifth conductor portion corresponds to the third conductor portion and forms the metal routing, the first metal layer is set as a transparent electrode layer, and the first conductor portion forms the first electrode portion.

[0014] In one embodiment, the array substrate further comprises a buffer layer, the buffer layer is disposed on the substrate and covers the metal composite layer, and a first via hole is disposed on the buffer layer at a position corresponding to the metal wiring;

[0015] Wherein, the active layer is arranged on the buffer layer, and the source electrode is electrically connected to the metal wiring through the first via hole.

[0016] In one embodiment, the array substrate further includes a dielectric layer, which is disposed on the buffer layer and covers the active layer, the gate insulating layer and the gate. An opening is disposed on the dielectric layer, and the second electrode portion is exposed from the opening.

[0017] In one embodiment, the film thickness of the buffer layer is set to

[0018] In one embodiment, the drain electrode and the second electrode portion are integrally formed.

[0019] In one embodiment, an orthographic projection edge of the second electrode portion on the substrate coincides with an orthographic projection edge of the first electrode portion on the substrate.

[0020] According to a second aspect of the present application, a method for manufacturing an array substrate is provided, comprising:

[0021] providing a substrate;

[0022] A first metal layer and a second metal layer are sequentially stacked on the upper surface of the substrate to form a metal composite layer;

[0023] Performing yellow light process on the metal composite layer by using a half-tone mask to form metal wiring, a metal light shielding portion and a first electrode portion;

[0024] Making a buffer layer covering the metal composite layer on the upper surface of the substrate, and etching a first via hole in the buffer layer by using a yellow light process;

[0025] An active layer is fabricated on the buffer layer, and a position on the active layer corresponding to the first electrode portion is patterned using a yellow light process;

[0026] forming a first insulating layer on the active layer;

[0027] Manufacturing a third metal layer on the first insulating layer, and patterning the third metal layer using a yellow light process to form a gate aligned with the metal light shielding portion;

[0028] Using the gate as a mask, etching the first insulating layer to form a gate insulating layer;

[0029] The exposed active layer is subjected to conductor processing to form a channel portion and conductor portions located on both sides of the channel portion, wherein the conductor portion on one side forms a source electrode corresponding to the position of the metal wiring and electrically connected thereto, and the conductor portion on the other side includes a drain electrode and a patterned second electrode portion, wherein the second electrode portion corresponds to the position of the first electrode portion and forms a storage capacitor.

[0030] In one embodiment, after the step of conducting the exposed active layer to form a channel portion and conductor portions located on both sides of the channel portion, the method further includes:

[0031] A dielectric layer is fabricated on the buffer layer, and an opening is etched on the dielectric layer using a yellow light process, wherein the dielectric layer covers the active layer, the gate insulating layer and the gate, and the second electrode portion is exposed from the opening.

[0032] According to a second aspect of the present application, a display panel is provided, comprising the above-mentioned array substrate.

[0033] In the array substrate of the embodiment of the present application, a metal composite layer is arranged on the substrate, and the metal composite layer is etched by a yellow light process to form a metal wiring, a metal shading portion and a first electrode portion; an active layer is arranged on the metal composite layer, and a position corresponding to the first electrode portion on the active layer is patterned by a yellow light process, and a gate insulating layer and a gate are sequentially arranged at a position corresponding to the metal shading portion on the active layer, and a channel portion is formed on the active layer, and after the exposed active layer is conductorized, conductor portions are formed on both sides of the channel portion, and the conductor portion on one side forms a source electrode, and the conductor portion on the other side includes a drain electrode and a second electrode portion, and in the thickness direction of the array substrate The second electrode portion corresponds to the first electrode portion in position, and an electric field can be formed between the two after voltage is applied; that is, the first electrode portion and the second electrode portion are equivalent to the common electrode and the pixel electrode, and by synchronously manufacturing the common electrode and the metal shading portion, and forming the pixel electrode by conductively converting the active layer, two photomasks for manufacturing the common electrode and the pixel electrode can be saved; and since the pixel electrode is formed by conductively converting the active layer, there is no need to separately set up a flat layer and a via in the prior art, and another photomask can be saved; in this way, three photomasks and etching processes can be saved, thereby simplifying the manufacturing process of the top-gate structure TFT and saving costs.

[0034] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0036] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0037] Figure 1 A schematic diagram of a film layer of an array substrate provided by the prior art;

[0038] Figure 2 A schematic diagram of a film layer of an array substrate provided in an embodiment of the present application;

[0039] Figure 3a A process diagram for etching the first metal layer and the second metal layer provided in an embodiment of the present application;

[0040] Figure 3b A process diagram for removing photoresist provided in an embodiment of the present application;

[0041] Figure 3cA process diagram for manufacturing a buffer layer provided in an embodiment of the present application;

[0042] Figure 3d A process diagram for making an active layer provided in an embodiment of the present application;

[0043] Figure 3e A process diagram for manufacturing a gate provided in an embodiment of the present application;

[0044] Figure 3f A process diagram for manufacturing a gate insulating layer provided in an embodiment of the present application;

[0045] Figure 3g A process diagram for conducting an active layer provided in an embodiment of the present application;

[0046] Figure 3h A process diagram for manufacturing a dielectric layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0048] The embodiments of the present application provide an array substrate 100 and a manufacturing method thereof, and a display panel. The following are detailed descriptions of each. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0049] In a first aspect, the present application embodiment provides an array substrate 100, see Figure 2 The array substrate 100 includes a substrate 1, a metal composite layer 2, an active layer 3, a gate insulating layer 4 and a gate 5; the metal composite layer 2 is arranged on the substrate 1, and the metal composite layer 2 includes a metal wiring 21, a metal shading portion 22 and a first electrode portion 23; the active layer 3 is arranged on the metal composite layer 2, and the active layer 3 includes a channel portion 31 and conductor portions 32 located on both sides of the channel portion 31, the channel portion 31 corresponds to the metal shading portion 22, the conductor portion 32 on one side forms a source 33, which corresponds to the metal wiring 21 and is electrically connected, and the conductor portion 32 on the other side includes an electrically connected drain 34 and a second electrode portion 35, and in the thickness direction F1 of the array substrate 100, the second electrode portion 35 corresponds to the first electrode portion 23; the gate insulating layer 4 is arranged on the channel portion 31; the gate 5 is arranged on the gate insulating layer 4.

[0050] See also Figure 1 In the prior art, in order to simplify the manufacturing process of the top-gate structure TFT 100′, the LSD technology is proposed. The LSD technology adopts an 8-Mask process to save costs and production capacity by reducing the number of masks. The prior LSD technology manufacturing process of the top-gate structure TFT 100′ is as follows:

[0051] A substrate 1' is provided, a first metal layer 25' is formed on the substrate 1', the first metal layer 25' is patterned to form a metal light shielding portion 22' and a metal wiring 21'; a buffer layer 6' is formed on the substrate 1' to cover the first metal layer 25', and a first via hole 61' is etched at a position corresponding to the metal wiring 21' on the buffer layer 6'; an active layer 3' is formed on the buffer layer 6'; a first insulating layer is formed on the active layer 3'; a gate 5' layer is formed on the first insulating layer, and the gate 5' layer is patterned. The first insulating layer 3′ is patterned and a gate 5′ is formed, and the gate 5′ corresponds to the metal light shielding portion 22′; the first insulating layer is etched using the gate 5′ as a mask to form a gate insulating layer 4′; the exposed active layer 3′ is conductorized to form two conductor portions 32′ as a source 33′ and a drain 34′; the source 33′ is electrically connected to the metal wiring 21′ through a first via 61′; a first dielectric layer 71′ is arranged on the buffer layer 6′, and the first dielectric layer 71′ covers the active layer 3′, the gate insulating layer 4′, and the gate insulating layer 4′. and the gate 5′, the first dielectric layer 71′ is etched with a second via hole 711′ at a position corresponding to the drain 34′; a flat layer 72′ is provided on the first dielectric layer 71′, a third via hole 721′ is etched on the flat layer 72′, and the third via hole 721′ is aligned with and connected to the second via hole 711′; a first electrode layer 24′ is provided on the flat layer 72′, the first electrode layer 24′ is patterned, and a common electrode 26′ is formed; a second dielectric covering the common electrode 26′ is provided on the flat layer 72′ Layer 73′, a fourth via hole 731′ is etched on the second dielectric layer 73′, the fourth via hole 731′ is aligned with the third via hole 721′ and is connected; a second electrode layer 22′ is arranged on the second dielectric layer 73′, the second electrode layer 22′ is patterned, and a pixel electrode 36′ is formed, the pixel electrode 36′ is electrically connected to the drain 34′ through the fourth via hole 731′, the third via hole 721′ and the second via hole 711′, and an electric field is formed between the pixel electrode 36′ and the common electrode 26′.

[0052] In the present application, a metal composite layer 2 is provided on the substrate 1, and the metal composite layer 2 is etched by a yellow light process to form a metal wiring 21, a metal shading portion 22 and a first electrode portion 23; an active layer 3 is provided on the second metal layer 25, and a position corresponding to the first electrode portion 23 on the active layer 3 is patterned by a yellow light process, and a gate insulating layer 4 and a gate 5 are sequentially provided at a position corresponding to the metal shading portion 22 on the active layer 3, and a channel portion 31 is formed on the active layer 3. At the same time, the exposed active layer 3 is conductorized, and conductor portions 32 are formed on both sides of the channel portion 31, and the conductor portion 32 on one side forms a source 33, and the conductor portion 32 on the other side includes a drain 34 and a second electrode portion 35. 00, the second electrode portion 35 corresponds to the first electrode portion 23 in position, and an electric field can be formed between the two after voltage is applied; that is, the first electrode portion 23 and the second electrode portion 35 are equivalent to the common electrode 26 and the pixel electrode 36, and by synchronously manufacturing the common electrode 26 and the metal shading portion 22, and forming the pixel electrode 36 through the conductor of the active layer 3, two photomasks for manufacturing the common electrode 26 and the pixel electrode 36 can be saved; and since the pixel electrode 36 is formed by the conductor of the active layer 3, there is no need to separately set up a flat layer and a via in the prior art, and another photomask can be saved; in this way, three photomasks and etching processes can be saved, thereby simplifying the manufacturing process of the top-gate structure TFT and saving costs.

[0053] See also Figure 2 In one embodiment, the metal composite layer 2 includes a first metal layer 24 and a second metal layer 25; the first metal layer 24 includes a first conductor portion 241, a second conductor portion 242 and a third conductor portion 243; the second metal layer 25 is arranged on the upper surface of the first metal layer 24, and the second metal layer 25 includes a fourth conductor portion 251 and a fifth conductor portion 252; wherein the fourth conductor portion 251 corresponds to the position of the second conductor portion 242 and forms the metal shading portion 22, the fifth conductor portion 252 corresponds to the position of the third conductor portion 243 and forms the metal wiring 21, the first metal layer 24 is set as a transparent electrode layer, and the first conductor portion 241 forms the first electrode portion 23.

[0054] In this embodiment, the second metal layer 25 is produced on the upper surface of the first metal layer 24, and the second metal layer 25 is stacked and directly contacted with the first metal layer 24; by using half-tone mask etching, the single-layered first conductor portion 241 forms the first electrode portion 23, which can be used as a common electrode 26; the double-layered fifth conductor portion 252 and the third conductor portion 243 form the metal routing 21, and the double-layered fourth conductor portion 251 and the second conductor portion 242 form the metal shading portion 22, and the first conductor portion 241 can also be used as a touch signal line of the display panel, thereby making the wiring of the array substrate 100 more reasonable.

[0055] In one embodiment, the array substrate 100 also includes a buffer layer 6, which is arranged on the substrate 1 and covers the metal composite layer 2, and a first via 61 is arranged on the buffer layer 6 at a position corresponding to the metal wiring 21; wherein the active layer 3 is arranged on the buffer layer 6, and the source 33 is electrically connected to the metal wiring 21 through the first via 61.

[0056] In this embodiment, after the metal composite layer 2 is arranged on the substrate 1, a buffer layer 6 is arranged on the substrate 1, and the buffer layer 6 covers the metal composite layer 2. At this time, the buffer layer 6 can also be used as a flat layer; the first via 61 is arranged at the position of the buffer layer 6 corresponding to the metal wiring 21, and the active layer 3 is arranged on the buffer layer 6. The source electrode 33 formed by the conductor of the active layer 3 is electrically connected to the metal wiring 21 through the first via 61.

[0057] In addition, the array substrate 100 further includes a dielectric layer 7 , which is disposed on the buffer layer 6 and covers the active layer 3 , the gate insulating layer 4 and the gate 5 . An opening 71 is disposed on the dielectric layer 7 , and the second electrode portion 35 is exposed from the opening 71 .

[0058] That is to say, the array substrate 100 also includes a buffer layer 6 and a dielectric layer 7; the manufacturing process of the array substrate 100 is as follows: a first metal layer 24 and a second metal layer 25 are manufactured on the substrate 1, and the first metal layer 24 and the second metal layer 25 are subjected to yellow light processing by using a half-tone mask, and a metal shading portion 22, a metal wiring 21 and a first electrode portion 23 (common electrode 26) are formed; a buffer layer 6 is arranged on the substrate 1, and covers the first metal layer 24 and the second metal layer 25, and the first via hole 61 is etched at a position corresponding to the metal wiring 21 on the buffer layer 6 by using a yellow light process; an active layer 3 is arranged on the buffer layer 6, and a position corresponding to the first electrode portion 23 on the active layer 3 is patterned by using a yellow light process, and a metal shading portion 22 is formed on the active layer 3 corresponding to the metal shading portion 2 2, a first insulating layer and a third metal layer are sequentially arranged at the position of the active layer 2, a gate 5 is patterned by a yellow light process, the first insulating layer is etched with the gate 5 as a mask, and a gate insulating layer 4 is formed, and a channel portion 31 is formed on the active layer 3; the exposed active layer 3 is conductorized, and conductor portions 32 are formed on both sides of the channel portion 31, one side of the conductor portion 32 forms a source 33, and the other side of the conductor portion 32 includes a drain 34 and a second electrode portion 35 (pixel electrode 36); a dielectric layer 7 is arranged on the buffer layer 6, the dielectric layer 7 covers the active layer 3, the gate insulating layer 4 and the gate 5, and an opening 71 is arranged on the dielectric layer 7 by a yellow light process; in this way, three photomasks and etching processes can be saved, and a top-gate structure TFT is manufactured by using 5Mask, thereby simplifying the manufacturing process of the top-gate structure TFT and saving costs.

[0059] Following the above-mentioned embodiment of "the buffer layer 6 covers the first metal layer 24 and the second metal layer 25 as a flat layer", as a flat layer, the buffer layer 6 of the present application needs to be set thicker than the buffer layer 6 of the prior art; the buffer layer 6 can be a single film layer structure, or a double film layer or a multi-film layer structure, and the film thickness of the buffer layer 6 is set to

[0060] Please read further Figure 2, following the above-mentioned embodiment of "the exposed active layer 3 is conductorized to form conductor parts 32 on both sides of the channel part 31, the conductor part 32 on one side forms the source 33, and the conductor part 32 on the other side includes the drain 34 and the second electrode part 35", since the second electrode part 35 is equivalent to the pixel electrode 36, and the conductor part 32 adjacent thereto is equivalent to the drain 34, the second electrode part 35 is provided to be electrically connected to the drain 34; and the second electrode part 35 and the drain 34 are both formed by conductorizing the active layer 3, so the parts on both sides of the channel part 31 can be directly conductorized as a whole to form a continuous conductive layer, so that the second electrode part 35 and the drain 34 are provided as a whole, thereby simplifying the manufacturing process of the second electrode part 35 and the drain 34.

[0061] In addition, the first electrode portion 23 serves as a common electrode 26, and the second electrode portion 35 serves as a pixel electrode 36. The second electrode portion 35 corresponds to the first electrode portion 23 in position and forms a storage capacitor. By arranging the positive projection edge of the second electrode portion 35 on the substrate 1 to coincide with the positive projection edge of the first electrode portion 23 on the substrate 1, the overlapping area between the first electrode portion 23 and the second electrode portion 35 can be increased, thereby increasing the capacitance of the storage capacitor.

[0062] In a second aspect, the present application provides a method for manufacturing an array substrate 100. Figure 3a~3h , the manufacturing method of the array substrate 100 is as follows:

[0063] S10: providing a substrate 1;

[0064] See also Figure 3a S20: A first metal layer 24 and a second metal layer 25 are sequentially stacked on the upper surface of the substrate 1 to form a metal composite layer 2. The material of the second metal layer 25 can be one or more of Al, Cu, Mo, Ti, and W. The film thickness of the second metal layer 25 is set to

[0065]

[0066] See also Figure 3b S30: using a half-tone mask to perform a yellow light process on the metal composite layer 2 to form a metal wiring 21, a metal light shielding portion 22 and a first electrode portion 23;

[0067] See also Figure 3cS40: a buffer layer 6 covering the metal composite layer 2 is formed on the upper surface of the substrate 1, and a first via hole 61 is formed on the buffer layer 6 at a position corresponding to the metal wiring 21 by a yellow light process, wherein the buffer layer 6 can be a single film layer structure, or a double film layer structure or a multi-film layer structure, and the material of the buffer layer 6 includes SiNX or SiO, and the film thickness of the buffer layer 6 is set to

[0068] See also Figure 3d S50: manufacturing an active layer 3 on the buffer layer 6, performing patterning on the active layer 3 at a position corresponding to the first electrode portion 23 by using a yellow light process, and the active layer 3 is made of a high-mobility material, including but not limited to IGZO;

[0069] S60: Form a first insulating layer on the active layer 3, the thickness of the first insulating layer is set to

[0070] See also Figure 3e S70: forming a third metal layer on the first insulating layer, patterning the third metal layer by a yellow light process, and forming a gate 5 aligned with the metal light shielding portion 22, wherein the material of the third metal layer can be one or more of Al, Cu, Mo, Ti, and W, and the film thickness of the third metal layer is set to

[0071] See also Figure 3f , S80: using the gate 5 as a mask to etch the first insulating layer to form a gate insulating layer 4;

[0072] See also Figure 3g S90: Conducting the exposed active layer 3 to form a channel portion 31 and conductor portions 32 located on both sides of the channel portion 31, wherein the conductor portion 32 on one side forms a source 33 corresponding to the position of the metal wiring 21 and electrically connected thereto, and the conductor portion 32 on the other side includes a drain 34 and a patterned second electrode portion 35, wherein the second electrode portion 35 corresponds to the position of the first electrode portion 23 and forms a storage capacitor.

[0073] Furthermore, after the step S90 of conducting the exposed active layer 3 to form the channel portion 31 and the conductor portions 32 located on both sides of the channel portion 31, the method further includes:

[0074] See also Figure 3hS100: a dielectric layer 7 is formed on the buffer layer 6, and an opening 71 is etched on the dielectric layer 7 by a yellow light process, wherein the dielectric layer 7 covers the active layer 3, the gate insulating layer 4 and the gate 5, and the second electrode portion 35 is exposed from the opening 71, wherein the material of the dielectric layer 7 is set to SiO2 or SiN, and the film thickness of the dielectric layer 7 is set to

[0075]

[0076] In an embodiment of the present application, a first metal layer 24 and a second metal layer 25 are manufactured on the substrate 1, and the first metal layer 24 and the second metal layer 25 are subjected to a yellow light process by using a half-tone mask to form a metal shading portion 22, a metal wiring 21 and a first electrode portion 23 (a common electrode 26); a buffer layer 6 is provided on the substrate 1 to cover the first metal layer 24 and the second metal layer 25, and the first via 61 is etched at a position of the buffer layer 6 corresponding to the metal wiring 21 by using a yellow light process; an active layer 3 is provided on the buffer layer 6, and a position of the active layer 3 corresponding to the first electrode portion 23 is patterned by using a yellow light process, and a first insulating layer and a first insulating layer are sequentially provided at a position of the active layer 3 corresponding to the metal shading portion 22. The three metal layers are patterned to form a gate 5 by using a yellow light process, the first insulating layer is etched with the gate 5 as a mask to form a gate insulating layer 4, and a channel portion 31 is formed on the active layer 3; the exposed active layer 3 is conductorized, and conductor portions 32 are formed on both sides of the channel portion 31, one side of the conductor portion 32 forms a source 33, and the other side of the conductor portion 32 includes a drain 34 and a second electrode portion 35 (pixel electrode 36); a dielectric layer 7 is set on the buffer layer 6, the dielectric layer 7 covers the active layer 3, the gate insulating layer 4 and the gate 5, and an opening 71 is set on the dielectric layer 7 by using a yellow light process; in this way, three photomasks and etching processes can be saved, and a top-gate structure TFT is manufactured by using 5Mask, thereby simplifying the manufacturing process of the top-gate structure TFT and saving costs.

[0077] In the third aspect, the embodiment of the present application provides a display panel. The display panel includes an array substrate 100; it should be noted that the array substrate 100 is set as the above-mentioned array substrate 100, that is, the array substrate 100 includes all the technical features of the above-mentioned array substrate 100, and the display panel includes all the embodiments of the above-mentioned array substrate 100, and also has all the technical effects of the above-mentioned embodiments, which will not be described one by one here.

[0078] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0079] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0080] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0081] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A metal composite layer is disposed on the substrate, wherein the metal composite layer includes a metal wiring, a metal light shielding portion and a first electrode portion; an active layer, arranged on the metal composite layer, the active layer comprising a channel portion and conductor portions located on both sides of the channel portion, the channel portion corresponding to the metal light shielding portion, the conductor portion on one side forming a source electrode corresponding to the metal wiring position and electrically connected, the conductor portion on the other side comprising an electrically connected drain electrode and a second electrode portion, the second electrode portion corresponding to the first electrode portion in the thickness direction of the array substrate; and A gate insulating layer, disposed on the channel portion; The gate is arranged on the gate insulating layer.

2. The array substrate according to claim 1, characterized in that: The metal composite layer comprises: A first metal layer includes a first conductor portion, a second conductor portion, and a third conductor portion; A second metal layer, disposed on an upper surface of the first metal layer, the second metal layer comprising a fourth conductor portion and a fifth conductor portion; The fourth conductor portion corresponds to the second electrode portion and forms the metal shading portion, the fifth conductor portion corresponds to the third conductor portion and forms the metal routing, the first metal layer is a transparent electrode layer, and the first conductor portion forms the first electrode portion.

3. The array substrate according to claim 1, characterized in that: The array substrate further comprises a buffer layer, which is disposed on the substrate and covers the metal composite layer, and a first via hole is disposed on the buffer layer at a position corresponding to the metal wiring; Wherein, the active layer is arranged on the buffer layer, and the source electrode is electrically connected to the metal wiring through the first via hole.

4. The array substrate according to claim 3, characterized in that: The array substrate further includes a dielectric layer, which is disposed on the buffer layer and covers the active layer, the gate insulating layer and the gate. An opening is disposed on the dielectric layer, and the second electrode portion is exposed from the opening.

5. The array substrate according to claim 3, characterized in that: The film thickness of the buffer layer is set to 6. The array substrate according to claim 1, characterized in that: The drain electrode and the second electrode portion are integrally arranged.

7. The array substrate according to claim 1, wherein: An orthographic projection edge of the second electrode portion on the substrate coincides with an orthographic projection edge of the first electrode portion on the substrate.

8. A method for manufacturing an array substrate, characterized in that: include: providing a substrate; A first metal layer and a second metal layer are sequentially stacked on the upper surface of the substrate to form a metal composite layer; Performing yellow light process on the metal composite layer by using a half-tone mask to form metal wiring, a metal light shielding portion and a first electrode portion; Making a buffer layer covering the metal composite layer on the upper surface of the substrate, and etching a first via hole in the buffer layer by using a yellow light process; An active layer is fabricated on the buffer layer, and a position on the active layer corresponding to the first electrode portion is patterned using a yellow light process; forming a first insulating layer on the active layer; Manufacturing a third metal layer on the first insulating layer, and patterning the third metal layer using a yellow light process to form a gate aligned with the metal light shielding portion; Using the gate as a mask, etching the first insulating layer to form a gate insulating layer; The exposed active layer is subjected to conductor processing to form a channel portion and conductor portions located on both sides of the channel portion, wherein the conductor portion on one side forms a source electrode corresponding to the position of the metal wiring and electrically connected thereto, and the conductor portion on the other side includes a drain electrode and a patterned second electrode portion, wherein the second electrode portion corresponds to the position of the first electrode portion and forms a storage capacitor.

9. The method for manufacturing an array substrate according to claim 8, wherein: After the step of conducting the exposed active layer to form a channel portion and conductor portions located on both sides of the channel portion, the method further includes: A dielectric layer is fabricated on the buffer layer, and an opening is etched on the dielectric layer using a yellow light process, wherein the dielectric layer covers the active layer, the gate insulating layer and the gate, and the second electrode portion is exposed from the opening.

10. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 7.

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