semiconductor devices

Abstract

A semiconductor device includes: a semiconductor substrate, in which a diode region, a first IGBT region, and a second IGBT region are disposed; the diode region is annular and surrounds the first IGBT region, while the second IGBT region surrounds the diode region; a first plug and a second plug are disposed through a first interlayer dielectric layer, wherein a first end of the first plug is electrically connected to a first active gate, and a first end of the second plug is electrically connected to a second active gate; a gate wiring portion is disposed on the first interlayer dielectric layer and electrically connects the second ends of the first plug and the second plug; a gate runner includes a gate wiring portion and a gate pad portion; and a gate pad is electrically connected to the gate pad portion. Heat generated by the diode can be evenly diffused to the first IGBT region located inside the diode region and the second IGBT region located outside the diode region, thereby improving heat dissipation uniformity of the diode and solving the problem of how to lead the active gate in the IGBT region to the gate pad.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] In recent years, from the viewpoint of energy conservation, semiconductor devices with low energy loss have been required in the fields of electric railways, vehicles, industrial machinery, and consumer equipment.

[0003] For example, a semiconductor device that arranges an insulated gate bipolar transistor (IGBT) and a diode on a single semiconductor substrate, namely an RC IGBT (reverse conducting power semiconductor device), has emerged. The IGBT chip and the diode chip are integrated into one chip, which reduces the number of chips, the complexity of wire connections, and the thermal resistance of the chip, thereby reducing energy loss.

[0004] However, the heat dissipation uniformity of the diode of the RC IGBT in the related art is poor, resulting in a high failure rate of the semiconductor device. Summary of the Invention

[0005] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention is not intended to limit the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] This application addresses the deficiencies in the prior art, and its main purpose is to provide a semiconductor device that improves the heat dissipation uniformity of the diode and reduces the failure rate of the semiconductor device.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In order to solve the existing problems, an embodiment of the present invention provides a semiconductor device, which includes:

[0009] A semiconductor substrate, wherein a diode region, a first IGBT region, and a second IGBT region are provided between a first main surface and a second main surface opposite the first main surface; when the semiconductor substrate is viewed from above, the diode region is annular and surrounds the first IGBT region, and the second IGBT region surrounds the diode region; the first IGBT region is provided with a first active gate on the first main surface side, and the second IGBT region is provided with a second active gate on the first main surface side;

[0010] a first interlayer dielectric layer disposed on the first main surface, wherein a first plug and a second plug are disposed through the first interlayer dielectric layer, wherein a first end of the first plug is electrically connected to the first active gate, and a first end of the second plug is electrically connected to the second active gate;

[0011] A gate runner includes a gate wiring portion and a gate pad portion disposed on the first interlayer dielectric layer, the gate wiring portion electrically connecting the first plug and the second end of the second plug, and the gate pad portion electrically connecting the gate wiring portion;

[0012] a second interlayer dielectric layer covering the gate runner, a fourth plug penetrating the second interlayer dielectric layer, a first end of the fourth plug electrically connected to the gate pad portion; and

[0013] The gate pad is disposed on the second interlayer dielectric layer and is electrically connected to the second end of the fourth plug.

[0014] The above embodiment has the following beneficial effects: by providing an annular diode area, IGBT areas are distributed on both the inner and outer sides of the annular diode area. When the diode is working, the heat generated by the diode can be evenly diffused to the first IGBT area located inside the diode area and the second IGBT area located outside the diode area, thereby improving the heat dissipation uniformity of the diode, avoiding damage to some areas of the diode due to heat concentration, and reducing the failure rate of the semiconductor device. Since the diode region completely separates the first active gate in the first IGBT region and the second active gate in the second IGBT region, when the active gate in the IGBT region is led out, the above embodiment provides a first interlayer dielectric layer, provides a first plug and a second plug in the first interlayer dielectric layer that are electrically connected to the first active gate and the second active gate, respectively, provides a gate wiring portion electrically connected to the first plug and the second plug on the first interlayer dielectric layer, and provides a gate pad portion electrically connected to the gate wiring portion on the first interlayer dielectric layer, so that the gate pad is electrically connected to the gate pad portion, thereby solving the problem of how to lead the active gate in the IGBT region to the gate pad when the diode region completely separates the first active gate in the first IGBT region and the second active gate in the second IGBT region, facilitating the reliable and stable application of gate voltage to the active gate in the IGBT region through the gate pad, and simplifying the structure. The fourth plug electrically connects the gate pad portion with a larger area to the gate pad, eliminating the need to electrically connect the fourth plug to the gate wiring portion with a narrower width, thereby simplifying the alignment between the opening for setting the fourth plug and the gate channel.

[0015] In some embodiments, the number of diode regions and first IGBT regions is multiple, and the multiple diode regions are arranged in an array spaced apart along the first direction and the second direction to form a diode array; wherein the first direction and the second direction are arranged crosswise; when looking down at the semiconductor substrate, each diode region corresponds to a first IGBT region and surrounds the corresponding first IGBT region.

[0016] The above embodiment has the following beneficial effects: by arranging a plurality of diode regions in an array spaced apart along the first direction and the second direction, a second IGBT region is provided between any two adjacent diode regions. Thus, when the diodes are operating, part of the heat generated by each diode can not only be diffused and dissipated toward the first IGBT region located inside the diode region, but can also be evenly diffused and dissipated outward from the second IGBT region outside the diode region, thereby avoiding damage to individual diode regions due to heat concentration, improving the heat dissipation uniformity between different diodes, and thereby reducing the failure rate of the semiconductor device.

[0017] In some embodiments, the number of the first plug and the number of the second plug are both plural, the plurality of first plugs are arranged in at least two rows along the second direction, and the plurality of second plugs are arranged in at least two rows along the second direction;

[0018] The gate wiring section includes:

[0019] a plurality of first gate wiring portions, each of which extends along the second direction and is arranged at intervals along the first direction, the first gate wiring portions being electrically connected to the second ends of the first plugs in the same column;

[0020] a plurality of second gate wiring portions, each of which extends along the second direction and is arranged at intervals along the first direction, the second gate wiring portions being electrically connected to the second ends of the second plugs in the same column;

[0021] A gate wiring bus portion is electrically connected to the gate pad portion, the gate wiring bus portion extends along a first direction and is located on a first side outside the diode array; the gate wiring bus portion electrically connects the first gate wiring portion and the first end of the second gate wiring portion to form a first comb tooth structure.

[0022] The above embodiment has the following beneficial effects: by adopting a gate wiring portion constituting a first comb-tooth structure, the first gate wiring portion extends above all the first IGBT regions in the same arrangement direction parallel to the second direction to electrically connect the second end of the first plug located in the same arrangement direction; the second gate wiring portion extends above the second IGBT region between two adjacent diode regions to electrically connect the second end of the second plug located in the same arrangement direction, and then the first gate wiring portion and the second gate wiring portion as comb teeth can be indirectly electrically connected to the gate pad portion through the gate wiring bus portion as the comb handle, thereby realizing the electrical connection between the first plug and the second plug at different positions and the gate pad portion, and simplifying the structure of the gate wiring portion.

[0023] In some embodiments, the first IGBT region is provided with a plurality of first active gates extending along the first direction and arranged at intervals along the second direction, each first active gate corresponds to a first plug and is electrically connected to the first end of the corresponding first plug; the second IGBT region is provided with a plurality of second active gates extending along the first direction and arranged at intervals along the second direction, each second active gate corresponds to a second plug and is electrically connected to the first end of the corresponding second plug.

[0024] The above embodiment has the following beneficial effects: by having all first active gates extend along the first direction and be spaced apart along the second direction, it is easier for the first gate wiring portion extending along the second direction to be electrically connected to all first active gates in the same arrangement direction parallel to the second direction via the first plug; and by having all second active gates extend along the first direction and be spaced apart along the second direction, it is easier for the second gate wiring portion extending along the second direction to be electrically connected to all second active gates in the same arrangement direction parallel to the second direction via the second plug. This simplifies the difficulty of electrically connecting the gate wiring portion to all active gates.

[0025] In some embodiments, a plurality of first gate wiring portions and a plurality of second gate wiring portions are staggered along the first direction.

[0026] The above embodiment has the following beneficial effects: by staggering the first gate wiring portion and the second gate wiring portion along the first direction, it is convenient to realize electrical connection between the first active gate and the second active gate at different positions and the gate wiring bus portion serving as the comb handle, thereby facilitating the extraction of the active gate and simplifying the structure.

[0027] In some embodiments, the gate pad portion is located at an intersection of the gate wiring bus portion and an outermost second gate wiring portion among the plurality of second gate wiring portions, and is also electrically connected to a first end of the outermost second gate wiring portion;

[0028] When looking down at the gate pad portion and the second active gate, the first portion of the gate pad portion overlaps with the second portion of the second active gate, and the first ends and second ends of some of the plurality of second plugs are electrically connected to the second portion and the first portion, respectively.

[0029] The above embodiment has the following beneficial effects: by arranging the gate pad portion at the intersection of the gate wiring bus and the outermost second gate wiring portion, electrical connection between the gate pad portion and the gate wiring portion is facilitated. Furthermore, the gate pad portion can also be arranged above the gate pad portion, so that the gate pad is located in a corner above the diode array, reserving a larger area for the emitter pad. By arranging the first portion of the gate pad portion and the second portion of the second active gate overlapping each other, a larger gate pad portion and gate pad can be provided, thereby improving current flow capacity. In this case, the second portion of the second active gate can be directly electrically connected to the first portion of the gate pad portion via the second plug, without the need for the second gate wiring portion and the gate wiring bus, thereby shortening the current path length when power is applied to the second active gate to which the second portion is connected.

[0030] In some embodiments, the semiconductor device further comprises:

[0031] an emitter runner, comprising an emitter wiring bus portion and a plurality of emitter wiring portions disposed on the first interlayer dielectric layer, wherein the plurality of emitter wiring portions extend along the second direction and are spaced apart along the first direction, the emitter wiring bus portion extending along the first direction and being located on the second side of the diode array; the emitter wiring bus portion electrically connecting first ends of the plurality of emitter wiring portions to form a second comb-tooth structure;

[0032] Among them, the second side is opposite to the first side, and the first comb tooth structure and the second comb tooth structure are relatively staggered and spaced apart; when looking down at the first comb tooth structure and the second comb tooth structure, the first comb tooth structure is a narrow strip comb tooth structure relative to the second comb tooth structure, and the second comb tooth structure is a wide strip comb tooth structure relative to the first comb tooth structure.

[0033] The above embodiment has the following beneficial effects: by providing the emitter runners in a second comb-tooth structure, it is easier to electrically connect the contact regions and emitter regions in the first and second IGBT regions to the emitter runners, and it is also easier to electrically connect the anode region in the diode region to the emitter runners. Furthermore, by configuring the first comb-tooth structure as a narrow strip comb-tooth structure and the second comb-tooth structure as a wide strip comb-tooth structure, the area of ​​the emitter runners can be increased, thereby improving the current carrying capacity of the emitter runners.

[0034] In some embodiments, a third plug is further provided in the first interlayer dielectric layer, a first end of the third plug is electrically connected to an emitter region of the first conductivity type, and a contact region and an anode region of the second conductivity type provided on the first main surface side, and a second end of the third plug is electrically connected to the emitter channel; when looking down at the third plug, the third plug extends along the first direction, and the third plug is disconnected at a position below the gate wiring portion.

[0035] The above embodiment has the following beneficial effects: by providing a strip-shaped structure extending along the first direction as the third plug, the cross-sectional area of ​​the third plug can be increased, which facilitates the electrical connection between the third plug and the emitter region, the contact region and the anode region, and can also improve the current flow capacity; and the third plug is disconnected at a position below the gate wiring portion, thereby preventing a short circuit defect between the third plug and the gate wiring portion.

[0036] In some embodiments, the semiconductor device further comprises:

[0037] The emitter pad is arranged on the second interlayer dielectric layer and is spaced apart from the gate pad; the second interlayer dielectric layer also covers the emitter flow channel, and a fifth plug is also provided through the second interlayer dielectric layer; when the fifth plug and the second comb-tooth structure are viewed from above, the shape of the fifth plug is comb-tooth-shaped, and the outline of the second comb-tooth structure surrounds the outline of the fifth plug; the first end of the fifth plug is electrically connected to the emitter flow channel, and the second end of the fifth plug is electrically connected to the emitter pad.

[0038] The above embodiment has the following beneficial effects: by providing the comb-tooth-shaped fifth plug, the outline of the second comb-tooth structure surrounds the outline of the fifth plug, thereby increasing the cross-sectional area of ​​the fifth plug and thus improving the current carrying capacity of the fifth plug.

[0039] In some embodiments, the emitter pad and the gate wiring portion are at least partially overlapped when the emitter pad and the gate wiring portion are viewed from above.

[0040] The above embodiment has the following beneficial effect: by providing the emitter pad to overlap at least part of the gate wiring portion, an emitter pad with a larger area can be provided, thereby improving the current flow capacity of the emitter pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The following drawings of the present invention are incorporated herein as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and the description thereof is used to explain the principle of the present invention.

[0042] In the attached figure:

[0043] Figure 1 A schematic top view of a semiconductor device according to a specific embodiment of the present invention is shown;

[0044] Figure 2 A schematic block diagram showing a top view of a first main surface of a semiconductor substrate in a semiconductor device according to a specific embodiment of the present invention is shown;

[0045] Figure 3 A schematic top view block diagram of a plug located in a first interlayer dielectric layer in a semiconductor device according to a specific embodiment of the present invention is shown;

[0046] Figure 4 A schematic top view block diagram of a gate flow channel of a semiconductor device according to a specific embodiment of the present invention is shown;

[0047] Figure 5 A schematic top view block diagram showing the spacing arrangement of gate flow channels and emitter flow channels of a semiconductor device according to a specific embodiment of the present invention is shown;

[0048] Figure 6 A schematic top view block diagram of a plug located in a second interlayer dielectric layer in a semiconductor device according to a specific embodiment of the present invention is shown;

[0049] Figure 7 A schematic top view block diagram showing the spacing arrangement of the gate pad and the emitter pad of a semiconductor device according to a specific embodiment of the present invention is shown;

[0050] Figure 8 A schematic structural diagram of an AA cross section of a semiconductor device according to a specific embodiment of the present invention is shown;

[0051] Figure 9 A schematic structural diagram of a BB cross-section of a semiconductor device according to a specific embodiment of the present invention is shown;

[0052] Figures 10 to 13 Schematic diagrams of top-view distribution of the areas and spacings of the diode region and the first IGBT region in different specific embodiments of the present invention are shown;

[0053] Figure 14 FIG2 shows a top view of a staggered array arrangement of diode arrays in a specific embodiment of the present invention.

[0054] Reference numerals:

[0055] 10-semiconductor substrate 11-first symmetry line 12-second symmetry line

[0056] 20-active area 30-diode area 31-anode area

[0057] 32- cathode region 33- virtual gate 40- drift region

[0058] 41 - first IGBT region 42 - second IGBT region 43 - first active gate

[0059] 44-second active gate 45-emitter region 46-contact region

[0060] 47-base region 48-P+ type well region 51-first interlayer dielectric layer

[0061] 52-second interlayer dielectric layer 61-first plug 62-second plug

[0062] 63-third plug 64-fourth plug 65-fifth plug

[0063] 66 - sixth plug 71 - first gate wiring portion 72 - second gate wiring portion

[0064] 73 - Gate wiring bus portion 74 - Gate pad portion 75 - Gate pad

[0065] 80-emitter wiring bus 81-emitter wiring 82-emitter pad

[0066] 91-field stop region 92-collector region 93-collector metal layer DETAILED DESCRIPTION

[0067] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features well known in the art are not described to avoid confusion with the present invention.

[0068] It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0069] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0070] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is turned over, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated or otherwise) and the spatial descriptors used herein are interpreted accordingly.

[0071] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0072] In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is N-type and the second conductivity type is P-type. Furthermore, N- represents a lower impurity concentration than N, and N+ represents a higher impurity concentration than N. Similarly, P- represents a lower impurity concentration than P, and P+ represents a higher impurity concentration than P.

[0073] Figure 1 A top view of a semiconductor device according to the present application illustrates a semiconductor device that is an RC-IGBT (Reverse Conducting IGBT). The RC-IGBT is a semiconductor device in which an IGBT region, which functions as an IGBT, and a diode region 30, which functions as a diode, are provided on a single semiconductor substrate 10. This semiconductor device can be used in electronic products such as, but not limited to, laptop computers, desktop computers, tablet computers, mobile phones, smart wearable devices, inverters, power factor correction circuits, and voltage converters.

[0074] In some embodiments, reference Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 7 、 Figure 8 and Figure 9 , a semiconductor device is proposed, the semiconductor device mainly comprising:

[0075] A semiconductor substrate 10 is provided with a diode region 30, a first IGBT region 41, and a second IGBT region 42 between a first main surface and a second main surface opposite the first main surface. When the semiconductor substrate 10 is viewed from above, the diode region 30 is annular and surrounds the first IGBT region 41, and the second IGBT region 42 surrounds the diode region 30. The first IGBT region 41 is provided with a first active gate 43 on the first main surface side, and the second IGBT region 42 is provided with a second active gate 44 on the first main surface side.

[0076] A first interlayer dielectric layer 51 is provided on the first main surface. A first plug 61 and a second plug 62 are provided through the first interlayer dielectric layer 51. A first end of the first plug 61 is electrically connected to the first active gate 43. A first end of the second plug 62 is electrically connected to the second active gate 44.

[0077] The gate runner includes a gate wiring portion and a gate pad portion 74 provided on the first interlayer dielectric layer 51 , wherein the gate wiring portion electrically connects the second ends of the first plug 61 and the second plug 62 , and the gate pad portion 74 electrically connects the gate wiring portion;

[0078] A second interlayer dielectric layer 52 covers the gate runner, a fourth plug 64 is provided through the second interlayer dielectric layer 52, and a first end of the fourth plug 64 is electrically connected to the gate pad portion 74; and

[0079] The gate pad 75 is disposed on the second interlayer dielectric layer 52 . The gate pad 75 is electrically connected to the second end of the fourth plug 64 .

[0080] The above embodiment has the following beneficial effects: by providing an annular diode region 30, with IGBT regions distributed both inside and outside the annular diode region 30, when the diode is operating, the heat generated by the diode can be evenly diffused to the first IGBT region 41 located inside the diode region 30 and the second IGBT region 42 located outside the diode region 30, thereby improving the uniformity of the diode's heat dissipation, preventing damage to certain regions of the diode due to heat concentration, and reducing the failure rate of the semiconductor device. Because the diode region 30 completely separates the first active gate 43 within the first IGBT region 41 and the second active gate 44 within the second IGBT region 42, when the active gates of the IGBT regions are led out, the above embodiment provides a first interlayer dielectric layer 51, disposes a first plug 61 and a second plug 62 in the first interlayer dielectric layer 51 to electrically connect the first active gate 43 and the second active gate 44, respectively, and disposes a gate wiring electrically connecting the first plug 61 and the second plug 62 on the first interlayer dielectric layer 51. A gate pad portion 74 electrically connected to the gate wiring portion is provided on the first interlayer dielectric layer 51, and a gate pad 75 is electrically connected to the gate pad portion. This solves the problem of how to lead the active gate in the IGBT region to the gate pad 75 when the diode region 30 completely separates the first active gate 43 in the first IGBT region 41 from the second active gate 44 in the second IGBT region 42. This facilitates reliable and stable application of gate voltage to the active gate in the IGBT region via the gate pad 75, and simplifies the structure. By electrically connecting the larger gate pad portion 74 and the gate pad 75 through the fourth plug 64, there is no need to electrically connect the fourth plug 64 to the narrower gate wiring portion, which simplifies the alignment between the opening for providing the fourth plug 64 and the gate runner.

[0081] The above structures are described in detail below with reference to the accompanying drawings.

[0082] The semiconductor substrate 10 described above is used to house an IGBT region, which functions as an IGBT, and a diode region 30, which functions as a diode. The diode region 30 in this application is annular in plan view. A first IGBT region 41 is located inside the annular diode region 30, and a second IGBT region 42 is located outside the annular diode region 30. Specifically, when viewed from above, the diode region 30 comprises an inner ring and an outer ring. The outer ring surrounds the inner ring, with a certain width between the inner ring and the inner ring, serving as the main body of the diode region 30. The first IGBT region 41 is located on the inner ring side of the diode region 30, toward the center of the ring. The second IGBT region 42 is located on the outer ring side of the diode region 30, away from the center of the ring. Consequently, when viewed from above, the diode region 30 surrounds the first IGBT region 41, while the second IGBT region 42 surrounds the diode region 30. The diode region 30 completely separates the first IGBT region 41 from the second IGBT region 42 within the semiconductor substrate 10.

[0083] For example, the diode may be a freewheeling diode, and the diode region 30 may be a region where the freewheeling diode is disposed. The diode region 30 may be disposed in any manner. Figure 8 The diode region 30 may include, but is not limited to, an anode region 31, a cathode region 32, a drift region 40, a field stop region 91, and other regions formed by N-type or P-type doping. Of course, the diode region 30 may also be provided with a dummy gate 33. Correspondingly, the first IGBT region 41 and the second IGBT region 42 may be provided in any manner. For example, referring to Figure 8 Each of the first IGBT region 41 and the second IGBT region 42 may include, but is not limited to, regions formed by N-type or P-type doping, such as an emitter region 45, a contact region 46, a collector region 92, a field stop region 91, a drift region 40, and a base region 47. Of course, active gates may also be provided in the first IGBT region 41 and the second IGBT region 42.

[0084] Exemplary, reference Figure 8 The semiconductor substrate 10 is common between the IGBT region and the diode region 30. In this example, one main surface of the semiconductor substrate 10 is referred to as a first main surface, and the other main surface of the semiconductor substrate 10 is referred to as a second main surface. Figure 8 For example, the first main surface is the upper surface of the semiconductor substrate 10, and the second main surface is the lower surface of the semiconductor substrate 10. Exemplarily, the semiconductor substrate 10 is a silicon substrate. However, in other examples, the semiconductor substrate 10 may also be a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium oxide (GaO) substrate.

[0085] It should be noted that the first main surface and the second main surface are only used to distinguish the two main surfaces of the semiconductor substrate 10 and are not intended to be substantial limitations. Figure 8 The cathode region 32 in the diode region 30 and the collector region 92 in the IGBT region are located on the second main surface side of the semiconductor substrate 10, while the anode region 31 and the dummy gate 33 in the diode region 30 are located on the first main surface side of the semiconductor substrate 10. Referring to the figure, the emitter region 45, the contact region 46, and the active gate in the IGBT region are located on the first main surface side of the semiconductor substrate 10.

[0086] Exemplary, reference Figure 8 The semiconductor substrate 10 has a P-type base region 47 from the first main surface to a predetermined depth position. The base region 47 in this example is provided in the IGBT region and the diode region 30. It should be noted that the base region 47 of the diode region 30 is also the anode region 31 of the diode region 30. In addition, the semiconductor substrate 10 has an N-type drift region 40 in the IGBT region and the diode region 30, from the base region 47 and the anode region 31 to a predetermined depth position. The anode region 31 of the diode region 30 is also connected to the emitter wiring portion 81, and the emitter wiring portion 81 located above the diode region 30 functions as an anode electrode. The diode region 30 has a diode formed by a PN junction of the P-type anode region 31 and the N-type drift region 40. The diode of the diode region 30 is connected in reverse parallel to the IGBT in the IGBT region, allowing the return current to flow when the IGBT is turned off.

[0087] Exemplary, reference Figure 8 , the emitter region 45 can be an N+ type semiconductor layer, and the contact region 46 can be a P+ type semiconductor layer. The N+ type emitter region 45 and the P+ type contact region 46 are arranged in a manner that they are exposed on the first main surface. The emitter region 45 and the contact region 46 are arranged on both sides of the first direction of the active gate. The emitter region 45 is arranged in direct contact with both sides of the active gate. In contrast, the contact region 46 is separated from the active gate. In the base region 47, the area in contact with the active gate acts as a channel formation area. It should be noted that the arrangement of the emitter region 45 and the contact region 46 is not limited to the arrangement shown above. In addition, other arrangement methods can also be used.

[0088] There are many ways to form the first active gate 43 and the second active gate 44. In some embodiments, a gate trench can be formed by etching from the first main surface of the semiconductor substrate 10 toward the drift region 40, and then a gate insulating film and an active gate are provided in the gate trench. The gate insulating film is provided in direct contact with the inner wall of the gate trench. The inner wall may include a bottom surface and a side surface. The active gate is provided in direct contact with the gate insulating film. That is, the interior of the gate trench is filled with a gate insulating film and an active gate. The material of the active gate may include polysilicon. The setting method of the virtual gate 33 is basically the same as the setting method of the active gate and will not be repeated here.

[0089] Exemplary, reference Figure 9 A P+ well region 48 deeper than the first active gate 43 can be formed around the end of the first active gate 43. The P+ well region 48 covers the bottom of the gate trench of the first active gate 43. As a result, no depletion layer is formed at the end of the first active gate 43, thereby preventing electric field concentration. Of course, it should be noted that the arrangement of the doped region at the end of the first active gate 43 is not limited to the arrangement shown above, and other arrangements can also be adopted.

[0090] Exemplary, reference Figure 8 The semiconductor substrate 10 includes a field stop region 91 (FS) below the drift region 40. The field stop region 91 may be an N-type semiconductor layer. The field stop region 91 may be commonly provided in the first IGBT region 41, the diode region 30, and the second IGBT region 42.

[0091] Exemplary, reference Figure 8 The semiconductor substrate 10 may include a collector region 92 and a cathode layer below the field stop region 91. In this example, the collector region 92 is provided in the first IGBT region 41 and the second IGBT region 42, and the cathode region 32 is provided in the diode region 30. The collector region 92 may be a P+ type semiconductor layer. Conversely, the cathode region 32 may be an N+ type semiconductor layer.

[0092] Exemplary, reference Figure 8 , a collector metal layer 93 is provided on the second main surface side of the semiconductor substrate 10. It should be noted that the collector metal layer 93 is provided on the second main surface side of the semiconductor substrate 10, but is not located between the first main surface and the second main surface, that is, it does not belong to the structure of the semiconductor substrate 10. For example, refer to Figure 8The collector metal layer 93 is commonly provided in the first IGBT region 41, the diode region 30, and the second IGBT region 42. Note that the collector metal layer 93 functions as a cathode electrode in the diode region 30. The collector pad in the semiconductor device can be electrically connected to the collector metal layer 93.

[0093] Exemplary, reference Figure 1 The IGBT region and diode region 30 disposed between the first and second principal surfaces of the semiconductor substrate 10 can both be located within the active region 20 of the semiconductor substrate 10. An edge termination portion can be provided outside the active region 20. The edge termination portion can be formed in a ring shape surrounding the entire outer side of the second IGBT region 42. The edge termination portion extends from the outermost side of the second IGBT region 42 to the end of the semiconductor substrate 10. The edge termination portion can include a voltage-resistant structure such as a guard ring structure and a channel stop.

[0094] For example, the semiconductor device may further include a gate flow channel, which includes a gate wiring portion and a gate pad portion 74. The gate wiring portion and gate pad portion 74 may be arranged in various ways. For example, the gate wiring portion and gate pad portion 74 may have a double-layer structure of a polysilicon film and an aluminum-silicon alloy film thereon. Alternatively, the gate wiring portion and gate pad portion 74 may have a single-layer structure of the aluminum-silicon alloy film.

[0095] In some embodiments, another semiconductor device is provided, referring to Figure 1 There are multiple diode regions 30 and multiple first IGBT regions 41 , with each diode region 30 spaced apart from each other. When viewing the semiconductor substrate 10 from above, each diode region 30 corresponds to a first IGBT region 41 and surrounds the corresponding first IGBT region 41 . Two adjacent diode regions 30 may be separated by a second IGBT region 42 , meaning that the second IGBT region 42 is at least distributed between the outer rings of two adjacent annular diode regions 30 . In some embodiments, the second IGBT region 42 may extend around the entire perimeter of all diode regions 30 . When viewed from above, the second IGBT region 42 has a closed perimeter and surrounds all diode regions 30 .

[0096] The above embodiment has the following beneficial effects: by providing a plurality of annular diode regions 30 arranged at intervals, each first IGBT region 41 corresponds to a diode region 30 and is located on the inner side of the corresponding diode region 30, while the second IGBT region 42 is located between adjacent diode regions 30 or on the outer side of all diode regions 30, so that the large-area diode region 30 is dispersed into a plurality of small-area diode regions 30 arranged at intervals, so that the outer side and the outer side of the annular diode region 30 are both IGBT regions. When the diode is working, the heat generated by the diode can be evenly dissipated from the inside and outside of the diode region 30 to the outside, thereby improving the heat dissipation uniformity of the diode, avoiding damage to some areas of the diode due to heat concentration, and reducing the failure rate of the semiconductor device.

[0097] The number of diode regions 30 may be as follows: Figure 1 、 Figure 10-14 The numbers 4, 10, 12, 15, and 25 shown in the figure may also be any value not less than 2. Accordingly, the number of first IGBT regions 41 is equal to the number of diode regions 30 . When viewed from above, each first IGBT region 41 is located inside a corresponding diode region 30 .

[0098] Regarding the number of the second IGBT regions 42, refer to Figure 1 The number of second IGBT regions 42 can be one, and when viewed from above, the second IGBT region 42 surrounds the outer rings of all diode regions 30 and connects them as a whole. In other embodiments, the number of second IGBT regions 42 can be two or more, up to the number of diode regions 30. When viewed from above, each second IGBT region 42 surrounds the outer ring of at least one diode region 30, and different second IGBT regions 42 may not be connected. For example, the number of second IGBT regions 42 can be equal to the number of diode regions 30, and the number of second IGBT regions 42 can also be ring-shaped. When viewed from above, each second IGBT region 42 corresponds to a diode region 30 and only surrounds the outer ring of the corresponding diode region 30. Different second IGBT regions 42 are not connected, thereby distinguishing them as different IGBT regions.

[0099] The multiple diode regions 30 can be arranged in a variety of ways, one of which is exemplified below.

[0100] In some embodiments, another semiconductor device is provided, referring to Figure 1There are multiple diode regions 30 and multiple first IGBT regions 41, and the multiple diode regions 30 are arranged in an array spaced apart along the first direction and the second direction to form a diode array; wherein the first direction and the second direction are arranged crosswise; when looking down at the semiconductor substrate 10, each diode region 30 corresponds to a first IGBT region 41 and surrounds the corresponding first IGBT region 41.

[0101] The above embodiment has the following beneficial effects: by arranging a plurality of diode regions 30 in an array spaced apart along the first direction and the second direction, any two adjacent diode regions 30 are separated by a second IGBT region 42. Therefore, when the diodes are operating, part of the heat generated by each diode can not only be diffused and dissipated toward the first IGBT region 41 located inside the diode region 30, but can also be evenly diffused and dissipated outward from the second IGBT region 42 outside the diode region 30, thereby preventing individual diode regions 30 from being damaged due to heat concentration, improving the heat dissipation uniformity between different diodes, and thereby reducing the failure rate of the semiconductor device.

[0102] It should be noted that the array arrangement of the plurality of diode regions 30 can be in various array arrangements. Figure 1 , multiple diode regions 30 can be arranged in an aligned array. In other embodiments, referring to Figure 14 , the multiple diode regions 30 can also be arranged in a staggered array.

[0103] Exemplary, reference Figure 1 The first direction can be perpendicular or substantially perpendicular to the second direction. It should be noted that the first direction is not limited to the horizontal direction as shown in the figure, and the second direction is not limited to the vertical direction as shown in the figure. In other embodiments, the first direction can also be a horizontal direction, and the second direction can also be a vertical direction.

[0104] Exemplarily, one of the first direction and the second direction is a row direction, and the other is a column direction. Exemplarily, the first direction may be a column direction, and the second direction may be a row direction. Alternatively, exemplarly, the second direction may be a column direction, and the first direction may be a row direction. In the following embodiments, the first direction is described as a row direction, and the second direction is a column direction.

[0105] In some embodiments, another semiconductor device is provided, referring to Figure 1 The shape of the diode region 30 may be a rectangular ring, and the shape of the first IGBT region 41 may be a rectangle.

[0106] The above embodiment has the following beneficial effects: by providing a rectangular ring-shaped diode region 30 and a rectangular first IGBT region 41, it is convenient to provide a strip-shaped virtual gate 33 in the diode region 30 and a strip-shaped active gate in the IGBT region, thereby simplifying the difficulty of providing the virtual gate 33 and the active gate.

[0107] It should be noted that, when viewed from above, the inner and outer rings of the rectangular ring can be regular rectangles or irregular rectangles connected by rounded corners at right angles. Correspondingly, the outer periphery of the first IGBT region 41 can be regular rectangles or irregular rectangles.

[0108] Of course, the diode region 30 may have other ring shapes besides a rectangular ring, such as an elliptical ring, a circular ring, etc. The shape of the first IGBT region 41 is the same as the shape of the inner side of the ring of the diode region 30 and may be changed according to the shape of the inner side of the ring of the diode region 30.

[0109] In some embodiments, another semiconductor device is provided, referring to Figure 1 When looking down at the semiconductor substrate 10 , the second IGBT regions 42 are distributed between adjacent diode regions 30 and outside the diode array to form a grid-like second IGBT region 42 .

[0110] Specifically, refer to Figure 1 The grids in the grid-like second IGBT region 42 are the locations where the diode region 30 and the first IGBT region 41 are set. The locations of the longitude and latitude lines of the grid are the locations of the body region of the second IGBT region 42. Of course, it should be noted that, referring to Figure 1 The longitude and latitude of the grid can be perpendicular or substantially perpendicular to each other, in which case the diode array adopts an aligned array configuration. In other embodiments, the longitude and latitude of the grid can be arranged at non-perpendicular angles, that is, at an acute or obtuse angle between the longitude and latitude of the grid, in which case the diode array can adopt a cross array configuration. Of course, in other embodiments, an irregular grid configuration can also be used as the top-view shape of the second IGBT region 42.

[0111] The above embodiment has the following beneficial effects: by adopting the grid-shaped second IGBT region 42, any two adjacent diode regions 30 are completely separated by the second IGBT region 42, which is not only beneficial to increasing the area of ​​the second IGBT region 42, but also beneficial to the heat generated by the diode region 30. After diffusing to the second IGBT region 42, the heat is diffused to the edge position of the semiconductor substrate 10 along the longitudinal and latitudinal extension directions of the grid-shaped second IGBT region 42, thereby improving the heat dissipation efficiency.

[0112] refer to Figure 1 and Figure 2 Since the diode region 30 completely separates the first IGBT region 41 from the second IGBT region 42, when the gate channel is directly disposed on the first main surface of the semiconductor substrate 10, a short circuit defect may occur, resulting in the gate channel being unable to be directly disposed on the first main surface of the semiconductor substrate 10. Figure 8 and Figure 9 In this application, a first interlayer dielectric layer 51 separates the gate runner from the first main surface of the semiconductor substrate 10 to prevent short circuits between the gate runner and the structures on the first main surface. The active gate within the IGBT region is connected via a plug provided in the first interlayer dielectric layer 51.

[0113] refer to Figure 3 and Figure 4 When there are multiple first IGBT regions 41, the arrangement and distribution of the multiple first IGBT regions 41 determine, to a certain extent, the extension position of the gate runner. It is necessary to ensure that at least a portion of the gate runner extends above each first IGBT region 41 so as to be electrically connected to the first active gate 43 in the first IGBT region 41 through the first plug 61 in the first interlayer dielectric layer 51. Figure 3 、 Figure 4 and Figure 9 Specifically, the first end of the first plug 61 contacts the first active gate 43 to achieve electrical connection therebetween, and the second end of the first plug 61 contacts the gate runner to achieve electrical connection therebetween. The first plug 61 can be formed by etching an opening in the first interlayer dielectric layer 51 to connect to the first active gate 43, and then filling the opening with a material such as, but not limited to, a metal to form the first plug 61. For example, the material of the first plug 61 can be tungsten.

[0114] Corresponding, reference Figure 3 and Figure 4 The number and distribution of the second IGBT regions 42 also determine the extension position of the gate runner. It is also necessary to ensure that at least part of the gate runner extends above the second IGBT region 42 to electrically connect to the active gate in the second IGBT region 42. The active gate in the second IGBT region 42 is electrically connected to the gate runner through the second plug 62 in the first interlayer dielectric layer 51. Figure 3 and Figure 4Specifically, the first end of the second plug 62 contacts the second active gate 44 to achieve electrical connection therebetween, while the second end of the second plug 62 contacts the gate runner to achieve electrical connection therebetween. The second plug 62 can be formed by etching an opening in the first interlayer dielectric layer 51 to connect to the second active gate 44, and then filling the opening with a material such as, but not limited to, a metal to form the second plug 62. For example, the material of the second plug 62 can be tungsten.

[0115] Of course, the number and arrangement of active gates in different IGBT regions also determine, to a certain extent, the extension of the gate flow channel. It is necessary to ensure that each active gate can be electrically connected to the gate flow channel through the plug structure. The following examples introduce some gate flow channel arrangements.

[0116] In some embodiments, another semiconductor device is provided, referring to Figure 3 and Figure 4 There are multiple first plugs 61 and multiple second plugs 62. The multiple first plugs 61 are arranged in at least two rows along the second direction, and the multiple second plugs 62 are arranged in at least two rows along the second direction. The gate wiring portion includes: multiple first gate wiring portions 71, multiple second gate wiring portions 72, and a gate wiring bus portion 73. The first gate wiring portions 71 extend in the second direction and are spaced apart in the first direction. The first gate wiring portions 71 are electrically connected to the second ends of the first plugs 61 in the same row. The second gate wiring portions 72 extend in the second direction and are spaced apart in the first direction. The second gate wiring portions 72 are electrically connected to the second ends of the second plugs 62 in the same row. The gate wiring bus portion 73 is electrically connected to the gate pad portion 74. The gate wiring bus portion 73 extends in the first direction and is located on the first side outside the diode array. The gate wiring bus portion 73 electrically connects the first ends of the first gate wiring portions 71 and the second gate wiring portions 72 to form a first comb-tooth structure.

[0117] The above embodiment has the following beneficial effects: by adopting a gate wiring portion constituting a first comb-tooth structure, the first gate wiring portion 71 extends above all the first IGBT regions 41 in the same arrangement direction parallel to the second direction to electrically connect the second ends of the first plugs 61 located in the same arrangement direction; the second gate wiring portion 72 extends above the second IGBT region 42 between two adjacent diode regions 30 to electrically connect the second ends of the second plugs 62 located in the same arrangement direction, and then the first gate wiring portion 71 and the second gate wiring portion 72 as comb teeth can be indirectly electrically connected to the gate pad portion 74 through the gate wiring confluence portion 73 as the comb handle, thereby realizing electrical connection between the first plugs 61 and the second plugs 62 at different positions and the gate pad portion 74, thereby simplifying the structure of the gate wiring portion.

[0118] Specifically, refer to Figure 3and Figure 4 When the diode array adopts an aligned array or a staggered array, taking the first direction as the row direction and the second direction as the column direction as an example, if there are at least two first IGBT regions 41 in the same column, a first gate wiring portion 71 can be extended above these first IGBT regions 41 to achieve electrical connection with the active gates in these first IGBT regions 41 through the first plugs 61 in the first interlayer dielectric layer 51. For example, the first plugs 61 corresponding to the first IGBT regions 41 in the same column can be arranged in the same row.

[0119] Correspondingly, second IGBT regions 42 are distributed between the two rows of diode regions 30. A second gate wiring portion 72 can be extended above the second IGBT regions 42 located between the two rows of diode regions 30 to electrically connect to the active gates of the second IGBT regions 42 at these locations through second plugs 62 in the first interlayer dielectric layer 51. For example, the second plugs 62 corresponding to the second IGBT regions 42 between the two rows of diode regions 30 can be arranged in the same row.

[0120] The first ends of the first gate wiring sections 71 and the second gate wiring sections 72 are both located on the first side outside the diode array (for example, Figure 3 and Figure 4 The first side shown is the upper side outside the diode array), so that at least part of the first gate wiring portion 71 and the second gate wiring portion 72 are directly in contact and electrically connected to the same gate wiring bus portion 73, forming a first comb tooth structure that is comb-tooth-shaped when viewed from above, thereby realizing mutual electrical connection between all active gates, so as to facilitate the application of gate voltage to all active gates at the same time.

[0121] In some embodiments, another semiconductor device is provided, referring to Figure 4 The gate pad portion 74 is located at the intersection of the gate wiring converging portion 73 and the outermost second gate wiring portion 72 among the plurality of second gate wiring portions 72, and is also electrically connected to the first end of the outermost second gate wiring portion 72. When viewing the gate pad portion 74 and the second active gate 44 from above, the first portion of the gate pad portion 74 overlaps with the second portion of the second active gate 44, and the first and second ends of some of the plurality of second plugs 62 are electrically connected to the second portion and the first portion, respectively.

[0122] The above embodiment has the following beneficial effects: by arranging the gate pad portion 74 at the intersection of the gate wiring bus 73 and the outermost second gate wiring portion 72, electrical connection between the gate pad portion 74 and the gate wiring portion is facilitated. Furthermore, the gate pad 75 portion can be positioned above the gate pad portion 74, positioning the gate pad 75 in a corner above the diode array, thereby reserving a larger area for the emitter pad 82. By arranging the first portion of the gate pad portion 74 and the second portion of the second active gate 44 to overlap, a larger gate pad portion 74 and gate pad 75 can be provided, thereby improving current flow capacity. In this case, the second portion of the second active gate 44 can be directly electrically connected to the first portion of the gate pad portion 74 via the second plug 62, without the need for the second gate wiring portion 72 and gate wiring bus 73. This shortens the current path length when power is applied to the second active gate 44 to which the second portion is connected.

[0123] Exemplary, reference Figure 4 The gate pad portion 74 is located at the intersection of the gate wiring converging portion 73 and the leftmost second gate wiring portion 72. It should be noted that the gate pad portion 74 is not limited to this position. For example, the gate pad portion 74 can also be located at the intersection of the gate wiring converging portion 73 and the rightmost second gate wiring portion 72.

[0124] It should also be noted that the gate pad portion 74 is not limited to being located at the intersection of the gate wiring confluence portion 73 and the outermost second gate wiring portion 72 among the plurality of second gate wiring portions 72. It can be located at any position in the first comb-tooth structure. For example, it can be located at the intersection of the gate wiring confluence portion 73 and any first gate wiring portion 71, or at the intersection of the third wiring portion and any second gate wiring portion 72. In some embodiments, the gate pad portion 74 can even be located at the end of one of the first gate wiring portions 71 or the second gate wiring portion 72. In other words, as long as electrical connection between the first comb-tooth structure and the gate pad portion 74 can be achieved, it is within the scope of protection of this application.

[0125] Exemplary, reference Figure 3 and Figure 4 The gate pad portion 74 has a large area and covers part of the second active gate 44 when viewed from above. The portion of the gate pad portion 74 that overlaps with the second active gate 44 can be defined as the first portion of the gate pad portion 74, and the portion of the second active gate 44 that overlaps with the gate pad portion 74 can be defined as the second portion of the second active gate 44. Figure 3 and Figure 4The second active gates 44 with the second portion are the two second active gates 44 located on the uppermost side. Because the first and second portions overlap, a portion of the second plug 62 can be directly placed between the first and second portions, thereby electrically connecting the gate pad 74 and a portion of the second active gate 44. This shortens the current path length between the gate pad 74 and the second active gate 44 with the second portion when current is applied. Furthermore, the gate pad 74 can be provided with a larger area.

[0126] In some embodiments, another semiconductor device is provided, referring to Figure 4 The plurality of first gate wiring portions 71 and the plurality of second gate wiring portions 72 are staggered along the first direction. Specifically, at least two columns of first plugs 61 and at least two columns of second plugs 62 are also staggered along the first direction, thereby facilitating the staggered plurality of first gate wiring portions 71 and the plurality of second gate wiring portions 72 to electrically connect the second ends of the corresponding column of first plugs 61 and the second ends of the corresponding column of second plugs 62, respectively.

[0127] The above embodiment has the following beneficial effects: by staggering the first gate wiring portion 71 and the second gate wiring portion 72 along the first direction, it is convenient to realize electrical connection between the first active gate 43 and the second active gate 44 at different positions and the gate wiring confluence portion 73 serving as the comb handle, thereby facilitating the extraction of the active gate and simplifying the structure.

[0128] Specifically, refer to Figure 3 and Figure 4 Because diode regions 30 in different columns (taking the second direction as an example) are separated by second IGBT regions 42, and second IGBT regions 42 between two diode regions 30 in an arrangement direction parallel to the first direction are also separated by diode regions 30, a first IGBT region 41 is disposed inside each column of diode regions 30. Therefore, when the first gate wiring portion 71 and the plurality of second gate wiring portions 72 are staggered along the first direction, the second gate wiring portion 72 can be extended above the second IGBT regions 42 between different types of diode regions 30, facilitating electrical connection to the active gates at these locations. This simplifies the active gate lead-out method and is applicable to various types of active gate extension arrangements.

[0129] Regarding the manner of setting the active gate in the first IGBT region 41 and the second IGBT region 42 , various manners may be adopted, and some of the manners are exemplarily introduced below.

[0130] In some embodiments, another semiconductor device is provided, referring to Figure 3 、 Figure 4 and Figure 9The first IGBT region 41 is provided with a plurality of first active gates 43 extending along the first direction and arranged at intervals along the second direction, each first active gate 43 corresponds to a first plug 61 and is electrically connected to the first end of the corresponding first plug 61; the second IGBT region 42 is provided with a plurality of second active gates 44 extending along the first direction and arranged at intervals along the second direction, each second active gate 44 corresponds to a second plug 62 and is electrically connected to the first end of the corresponding second plug 62.

[0131] The above embodiment has the following beneficial effects: by making all first active gates 43 extend along the first direction and be spaced apart along the second direction, the first gate wiring portion 71 extending along the second direction is facilitated to be electrically connected to all first active gates 43 in the same arrangement direction parallel to the second direction through the first plug 61; and by making all second active gates 44 extend along the first direction and be spaced apart along the second direction, the second gate wiring portion 72 extending along the second direction is facilitated to be electrically connected to all second active gates 44 in the same arrangement direction parallel to the second direction through the second plug 62. This simplifies the difficulty of electrically connecting the gate wiring portion to all active gates.

[0132] Exemplary, reference Figure 2 、 Figure 8 and Figure 9 , four first active gates 43 can be set in the first IGBT region 41. Of course, it should be noted that the number of first active gates 43 set in each first IGBT region 41 is not limited to four. In addition, it can also be any value of not less than one.

[0133] It should be noted that the arrangement of active gates within the IGBT region is not limited to the arrangement shown above; other arrangements may also be employed. For example, in some embodiments, the active gates within the first IGBT region 41 may be arranged in a circular extension, with one or more ring-shaped active gates. When there are multiple ring-shaped active gates, the multiple ring-shaped active gates may be spaced apart along the second direction, or may be arranged concentrically and spaced apart from each other outward from the center of the first IGBT region 41, similar to a "concentric circle" arrangement. As long as each active gate is electrically connected to the gate wiring portion through the first plug 61, the arrangement is within the scope of protection of this application. Correspondingly, the active gates within the second IGBT region 42 may also be arranged in a circular extension, such as, but not limited to, a circular extension. They may be spaced apart within the second IGBT region 42 in any manner, as long as each active gate is electrically connected to the gate wiring portion through the second plug 62, the arrangement is within the scope of protection of this application.

[0134] As mentioned above, reference Figure 7 and Figure 8, the first main surface side of the semiconductor substrate 10 is not limited to the active gate. The first main surface side of the semiconductor substrate 10 can also be provided with an emitter region 45, a contact region 46, an anode region 31, a virtual gate 33, etc. These structures all need to be electrically connected to the emitter pad 82 of the semiconductor device to apply an emitter voltage to these structures. When realizing the electrical connection between these structures and the emitter pad 82, it is also necessary to electrically connect the structures distributed at different positions on the first main surface side to each other first, so as to facilitate the electrical connection of the emitter pad 82. Specifically, the emitter region 45, contact region 46, anode region 31, virtual gate 33 and other structures at different positions on the first main surface side can be electrically connected to each other through the emitter flow channel. There are many ways to set up the emitter flow channel, and some of the methods are introduced as examples below.

[0135] In some embodiments, another semiconductor device is provided, referring to Figure 4 、 Figure 5 and Figure 8 The semiconductor device further includes: an emitter runner, including an emitter wiring bus 80 and a plurality of emitter wiring portions 81 arranged on the first interlayer dielectric layer 51, the plurality of emitter wiring portions 81 all extending along the second direction and arranged at intervals along the first direction, the emitter wiring bus 80 extending along the first direction and located on the second side of the diode array; the emitter wiring bus 80 electrically connects the first ends of the plurality of emitter wiring portions 81 to form a second comb tooth structure; wherein the second side is opposite to the first side, and the first comb tooth structure and the second comb tooth structure are relatively staggered and arranged at intervals.

[0136] The above embodiment has the following beneficial effects: by providing the emitter flow channel constituting the second comb-tooth structure, it is convenient to electrically connect the contact region 46 and the emitter region 45 located in the first IGBT region 41 and the second IGBT region 42 to the emitter flow channel, and it is also convenient to electrically connect the anode region 31 located in the diode region 30 to the emitter flow channel.

[0137] Specifically, the number of emitter wiring sections 81 can be 5, 8, 10, etc., depending on the number of similar teeth in the first comb-tooth structure. It is necessary to ensure that an emitter wiring section 81 is provided between any two teeth in the first comb-tooth structure to electrically connect structures located below these locations, such as, but not limited to, emitter region 45, contact region 46, anode region 31, and dummy gate 33. Emitter wiring sections 81 all extend along the second direction, and the first ends of several emitter wiring sections 81 are connected to an emitter wiring bus section 80 extending along the first direction and located on the second side of the diode array, thereby forming an integrated second comb-tooth structure.

[0138] It should be noted that the second side of the diode array is not limited to the second side outside the diode array, and can be a position directly above the diode array close to the second side, or can be the second side outside the diode array. The connection width between different emitter wiring portions 81 in the second direction can be as wide as possible to improve the current flow capacity. For example, refer to Figure 5 , the first side of the diode array is the upper side, and the second side of the diode region 30 is the lower side opposite to the upper side.

[0139] Of course, the width of the emitter wiring portion 81 in the first direction may also be as wide as possible to improve the current carrying capacity of the entire emitter wiring portion 81.

[0140] In some embodiments, another semiconductor device is provided, referring to Figure 5 When looking down at the first comb-tooth structure and the second comb-tooth structure, the first comb-tooth structure is a narrow comb-tooth structure relative to the second comb-tooth structure, and the second comb-tooth structure is a wide comb-tooth structure relative to the first comb-tooth structure. Specifically, the width of the emitter wiring portion 81 in the first direction is greater than the width of the first gate wiring portion 71 and the second gate wiring portion 72 in the first direction. For example, refer to Figure 5 The emitter wiring portion 81 has a width d9 in the first direction, and the first and second gate wiring portions 71 and 72 each have a width d10 in the first direction. Thus, d9 is greater than d10. Furthermore, the width of the emitter wiring bus portion 80 in the second direction is greater than the width of the gate wiring bus portion 73 in the second direction, thereby improving the current carrying capacity of the emitter wiring bus portion 80.

[0141] The above embodiment has the following beneficial effects: the first comb tooth structure is set as a narrow comb tooth structure, and the second comb tooth structure is set as a wide comb tooth structure, thereby increasing the area of ​​the emitter flow channel and improving the current flow capacity of the emitter flow channel.

[0142] refer to Figure 4 、 Figure 5 and Figure 8 To prevent a short circuit between the emitter runner and the active gate, the emitter runner is disposed above the first interlayer dielectric layer 51. The emitter runner can be electrically connected to structures disposed on the first main surface, such as, but not limited to, the emitter region, the contact region 46, and the anode region 31, via plugs in the first interlayer dielectric layer 51. Some exemplary methods are described below.

[0143] In some embodiments, another semiconductor device is provided, referring to Figure 4 、 Figure 5 and Figure 8A third plug 63 is also provided in the first interlayer dielectric layer 51. The first end of the third plug 63 is electrically connected to the first conductive type emitter region 45, the second conductive type contact region 46 and the anode region 31 provided on the first main surface side, and the second end of the third plug 63 is electrically connected to the emitter channel. When looking down at the third plug 63, the third plug 63 extends along the first direction, and the third plug 63 is disconnected at a position below the gate wiring portion.

[0144] Specifically, refer to Figure 4 、 Figure 5 and Figure 8 The first end of the third plug 63 faces the first principal surface and directly contacts and electrically connects to the emitter region 45, contact region 46, and anode region 31 on the first principal surface. The second end of the third plug 63 faces the emitter runner and directly contacts and electrically connects to the emitter runner. The top view of the third plug 63 is a strip extending in the first direction. The third plug 63 is disconnected below the gate wiring portion. When the first direction is the row direction, the third plugs 63 in the same row have multiple disconnected sections.

[0145] The above embodiment has the following beneficial effects: by providing a strip-shaped structure extending along the first direction as the third plug 63, the cross-sectional area of ​​the third plug 63 can be increased, which facilitates the electrical connection between the third plug 63 and the emitter region 45, the contact region 46 and the anode region 31, and can also improve the current flow capacity; and the third plug 63 is disconnected at a position below the gate wiring portion, thereby preventing a short circuit defect between the third plug 63 and the gate wiring portion.

[0146] When providing the third plug 63, an etching process can be used to form a strip-shaped opening extending along the first direction in the first interlayer dielectric layer 51. The opening is connected to the anode region 31, the contact region 46, and the emitter region 45 on the first main surface side. The third plug 63 is then formed by filling the opening with a material such as, but not limited to, a metal. For example, the material of the third plug 63 can be tungsten.

[0147] In some embodiments, reference Figure 8 The diode region 30 may only have the anode region 31 on the first main surface. In other embodiments, a contact region may be further provided in the anode region 31 of the diode region 30 , and the contact region is also exposed on the first main surface to be electrically connected to the first end of the third plug 63 .

[0148] For example, a P+ type contact region is provided on the first main surface side of the P-type anode region 31. The concentration of the P-type impurities in the P+ type contact region can be set to the same concentration as the P-type impurities in the P+ type contact region of the IGBT region, or it can be set to a different concentration. If it is necessary to distinguish between the P+ type contact region and the P-type anode region 31, each can be referred to separately, or the P+ type contact region and the P-type anode region 31 can be collectively referred to as the anode region 31.

[0149] In some embodiments, reference Figure 8 The first IGBT region 41 and the second IGBT region 42 may be provided with an emitter region 45 and a contact region 46 on the first main surface side. The emitter region 45 and the contact region 46 may be provided in any manner, as long as both the emitter region 45 and the contact region 46 have exposed areas on the first main surface side and are electrically connected to the first end of the third plug 63.

[0150] Exemplary, reference Figure 8 The portion of the first active gate 43 exposed on the first main surface side is separated from the third plug 63 and the emitter wiring portion 81 by the first interlayer dielectric layer 51, thereby achieving mutual insulation isolation.

[0151] In some embodiments, another semiconductor device is provided, referring to Figure 2 、 Figure 3 and Figure 5 A dummy gate 33 exposed on the first main surface side is provided in the diode region 30, and a sixth plug 66 is further provided in the first interlayer dielectric layer 51. The first end of the sixth plug 66 is electrically connected to the dummy gate 33 provided on the first main surface side, and the second end of the sixth plug 66 is electrically connected to the emitter flow channel. Specifically, the first end of the sixth plug 66 is in contact and electrically connected with the dummy gate 33, and the second end of the sixth plug 66 is in contact and electrically connected with the emitter flow channel, so as to realize the electrical connection between the dummy gate 33 provided in the diode region 30 and the emitter flow channel.

[0152] Regarding the setting of the virtual gate 33, there are many ways to adopt, and some of them are introduced as examples below. Figure 2 There are multiple dummy gates 33, and each dummy gate 33 extends along the first direction, and all dummy gates 33 are arranged at intervals along the second direction. Figure 2 、 Figure 3 and Figure 5Each dummy gate 33 is electrically connected to the emitter runner via a sixth plug 66. Of course, in other embodiments, the dummy gates 33 may extend along the first direction and be spaced apart along the second direction. Furthermore, in some embodiments, the dummy gates 33 may be annular in top view, and there may be multiple dummy gates 33, with the multiple dummy gates 33 being concentrically spaced from the inner circle to the outer circle of the annular diode region 30.

[0153] In some embodiments, another semiconductor device is provided, referring to Figure 5-Figure 9 The semiconductor device further includes: an emitter pad 82, which is disposed on the second interlayer dielectric layer 52 and spaced apart from the gate pad 75; the second interlayer dielectric layer 52 also covers the emitter flow channel, and a fifth plug 65 is further provided through the second interlayer dielectric layer 52; when looking down at the fifth plug 65 and the second comb-tooth structure, the fifth plug 65 has a comb-tooth shape, and the outline of the second comb-tooth structure surrounds the outline of the fifth plug 65; a first end of the fifth plug 65 is electrically connected to the emitter flow channel, and a second end of the fifth plug 65 is electrically connected to the emitter pad 82.

[0154] The above embodiment has the following beneficial effects: by providing the comb-shaped fifth plug 65 , the outline of the second comb-tooth structure surrounds the outline of the fifth plug 65 , thereby increasing the cross-sectional area of ​​the fifth plug 65 and thus improving the current carrying capacity of the fifth plug 65 .

[0155] Exemplary, reference Figure 5-Figure 9 The gap between the emitter flow channel and the gate flow channel is filled with a dielectric material, that is, the gap between the first comb-tooth structure and the second comb-tooth structure is filled with a dielectric material, thereby achieving mutual insulation isolation.

[0156] When setting the fifth plug 65, refer to Figure 6 First, an opening for arranging the fifth plug 65 is formed in the second interlayer dielectric layer 52, and the surface of the emitter runner is exposed in the opening. Then, the fifth plug 65 is formed by filling the opening with a conductive material such as, but not limited to, a metal material, so that the first end of the fifth plug 65 is in contact and electrically connected with the emitter runner. Exemplarily, the material of the fifth plug 65 is tungsten. Figure 6 Since the top view shape of the fifth plug 65 is comb-shaped, the top view shape of the opening for arranging the fifth plug 65 is also comb-shaped. The outline of the second comb-shaped structure surrounds the outline of the opening for arranging the fifth plug 65, so that the top view shape of the subsequently formed fifth plug 65 is also comb-shaped. After the fifth plug 65 is formed in the second interlayer dielectric layer 52, the emitter pad 82 can be formed on the second interlayer dielectric layer 52 to contact and connect with the fifth plug 65.

[0157] refer to Figure 6 Regarding the shape and size of the fourth plug 64, it is specifically related to the shape and size of the gate pad portion 74. When setting the fourth plug 64, it is necessary to first form an opening in the second interlayer dielectric layer 52 above the gate pad portion 74 by etching to ensure that the surface of the gate pad portion 74 is exposed in the opening. Then, the fourth plug 64 is formed by filling the opening with a conductive material such as but not limited to a metal material, so that the first end of the fourth plug 64 is in contact with and electrically connected to the gate pad portion 74. Exemplarily, the material of the fourth plug 64 is metal tungsten. The gate pad portion 74 is wider than the width of the gate wiring portion, so as to provide support for the setting of the fourth plug 64. And because the fourth plug 64 does not need to be in contact with and electrically connected to the gate wiring portion, it also reduces the difficulty of aligning the opening in the second interlayer dielectric layer 52 when setting the fourth plug 64. In a more preferred embodiment, it is necessary to ensure that when viewing the fourth plug 64 and the gate pad 74 from above, the outline of the gate pad 74 surrounds the outline of the fourth plug 64, while also making the size of the fourth plug 64 as large as possible to improve the current flow capacity. After forming the fourth plug 64 in the second interlayer dielectric layer 52, a gate pad 75 can be formed on the second interlayer dielectric layer 52 to contact and connect with the fourth plug 64.

[0158] For example, when the emitter pad 82 and the gate wiring portion are viewed from above, the emitter pad 82 and the gate wiring portion are at least partially overlapped.

[0159] The above embodiment has the following beneficial effect: by providing the emitter pad 82 to overlap at least part of the gate wiring portion, a larger emitter pad 82 can be provided, thereby improving the current flow capacity of the emitter pad 82 .

[0160] Exemplary, reference Figure 7 The shape of the emitter pad 82 is a rectangular shape with a missing corner, and a gate pad 75 is provided at the missing corner. The gate pad 75 is spaced apart from the emitter pad 82 to increase the area of ​​the emitter pad 82 and improve its current carrying capacity.

[0161] For example, the gap between the emitter pad 82 and the gate pad 75 may be filled with an insulating material to achieve insulation isolation.

[0162] It should be noted that the above only illustrates the arrangement of the first plug 61 to the sixth plug 66. In addition, other arrangement methods can also be used. For example, after forming an opening for arranging the plug in the interlayer dielectric layer, before filling the conductive material, a barrier metal can be formed at the bottom of the opening, and then the conductive material is filled to form the plug. This process is particularly suitable for the first plug 61, the second plug 62, the third plug 63, and the sixth plug 66, which are plugs that are directly in contact with the first main surface side, so that there is a barrier metal on the side of these plugs that is in contact with the semiconductor substrate 10. The type of conductive material is not limited to a single material layer. In some embodiments, a plug structure formed by stacking multiple conductive material layers can be used. For example, tungsten can be buried in a manner that is in contact with the barrier metal, and a plug structure can be formed on the tungsten using a conductive material such as aluminum.

[0163] For example, the materials of the first interlayer dielectric layer 51 and the second interlayer dielectric layer 52 may be silicon dioxide films, or an interlayer insulating film including other materials (eg, BPSG film) may be further provided on the silicon dioxide.

[0164] In some embodiments, another semiconductor device is provided, referring to Figure 10 The diode array has a first symmetry line 11 parallel to the second direction; as the first IGBT region 41 closest to the first symmetry line 11 moves toward the first IGBT region 41 closest to the edge of the diode array in the first direction, the area of ​​the first IGBT region 41 gradually decreases.

[0165] The above embodiment has the following beneficial effects: Due to the characteristic that the closer the semiconductor substrate 10 is to the first symmetry line 11, the worse the heat dissipation performance is, while the closer the semiconductor substrate 10 is to the edge regions on both sides in the first direction, the better the heat dissipation performance is. In other words, due to the characteristic that the heat dissipation performance gradually increases from the center of the semiconductor substrate 10 to the sides of the semiconductor substrate 10, the area of ​​the first IGBT region 41 closer to the edge of the diode array in the first direction is smaller, so that more heat generated by the diode at this location is evenly dissipated outward through the second IGBT region 42 outside it; and the area of ​​the first IGBT region 41 closer to the first symmetry line 11 of the diode array in the first direction is larger, so that more heat generated by the diode at this location is evenly dissipated outward through the first IGBT region 41 inside it. This ensures that the area of ​​the first IGBT region 41 at different locations matches the heat dissipation performance of the semiconductor substrate 10 at that location, thereby improving the heat dissipation uniformity of the diode regions 30 at different locations.

[0166] For example, the first direction may be a row direction, the second direction may be a column direction, and the number of diode regions 30 located in the same row is at least three. Specifically, the number of diode regions 30 located in the same row may be any value not less than three, such as 3, 4, 10, 20, or the like.

[0167] Exemplary, reference Figure 10 The semiconductor substrate 10 has two opposing first sides in the first direction, both of which extend along the second direction. The line of symmetry between the two first sides is also a first line of symmetry 11, and the first line of symmetry 11 is equidistant from the two first sides. In this case, the diode array is disposed in the middle region of the semiconductor substrate 10 in the first direction.

[0168] Exemplary, reference Figure 10 The area of ​​the first IGBT region 41 gradually decreases as the first IGBT region 41 closest to the first symmetry line 11 moves toward the first IGBT region 41 closest to the edge of the diode array in the first direction. Specifically, between two adjacent first IGBT regions 41 in the first direction, the closer the region is to the first symmetry line 11, the larger the area of ​​the first IGBT region 41; the farther the region is from the first symmetry line 11, the smaller the area of ​​the first IGBT region 41.

[0169] Exemplary, reference Figure 10 When the first symmetry line 11 is also the symmetry line of the two first side edges, between two adjacent first IGBT regions 41 in the first direction, the smaller the distance from the nearest first side edge of the two first side edges, the smaller the area of ​​the first IGBT region 41; the larger the distance from the nearest first side edge of the two first side edges, the larger the area of ​​the first IGBT region 41.

[0170] Exemplary, reference Figure 10 , the area of ​​the first IGBT region 41b may be set to be larger than the area of ​​the first IGBT region 41a, and the area of ​​the first IGBT region 41c may be set to be larger than the area of ​​the first IGBT region 41d.

[0171] In some embodiments, another semiconductor device is provided, referring to Figure 10 The first direction is the row direction, the second direction is the column direction, and the areas of all diode regions 30 located in the same row are equal.

[0172] The above embodiment has the following beneficial effects: the area of ​​the diode region 30 is positively correlated with the heat generated during operation, i.e., the larger the area of ​​the diode region 30, the more heat it generates during operation, and the smaller the area of ​​the diode region 30, the less heat it generates during operation. On the basis that all diode regions 30 in the same row have equal areas, smaller first IGBT regions 41 are positioned inside the diode regions 30 closer to the side edge of the semiconductor substrate 10, while larger first IGBT regions 41 are positioned inside the diode regions 30 farther from the side edge of the semiconductor substrate 10. This ensures that the areas of the diode regions 30 and first IGBT regions 41 at different locations match, thereby improving heat dissipation uniformity at different diode regions 30 locations.

[0173] For example, reference Figure 10 , the areas of the diode region 30a, the diode region 30b, the diode region 30c and the diode region 30d can be set to be equal.

[0174] In some other embodiments, another semiconductor device is provided, referring to Figure 10 As the diode region 30 closest to the first symmetry line 11 moves toward the diode region 30 closest to the edge of the diode array in the first direction, the area of ​​the diode region 30 gradually increases.

[0175] Specifically, refer to Figure 10 , between two adjacent diode regions 30 in the first direction, the area of ​​the diode region 30 closer to the first symmetry line 11 is smaller than the area of ​​the diode region 30 farther from the first symmetry line 11. That is, between two adjacent diode regions 30 in the first direction, the area of ​​the diode region 30 closer to the first symmetry line 11 is smaller, and the area of ​​the diode region 30 farther from the first symmetry line 11 is larger.

[0176] The above embodiment has the following beneficial effects: the area of ​​the diode region 30 is positively correlated with the heat generated during operation, i.e., the larger the area of ​​the diode region 30, the more heat it generates during operation, and the smaller the area of ​​the diode region 30, the less heat it generates during operation. Considering that the heat dissipation performance of the center of the semiconductor substrate 10 is worse than that of the two sides of the semiconductor substrate 10, the area of ​​the diode region 30 is smaller closer to the first symmetry line 11 to reduce the heat generated by the diode at that location during operation; while the area of ​​the diode region 30 is larger farther away from the first symmetry line 11 to increase the heat generated by the diode at that location during operation. Matching the area of ​​the diode region 30 at different locations with the heat dissipation performance of the semiconductor substrate 10 at that location is beneficial for improving the heat dissipation uniformity of the diode region 30 at different locations.

[0177] For example, reference Figure 10 , the area of ​​the diode region 30a can be made larger than the area of ​​the diode region 30b, and the area of ​​the diode region 30d can be made larger than the area of ​​the diode region 30c.

[0178] In some embodiments, another semiconductor device is provided, referring to Figure 11 The diode array has a second symmetry line 12 parallel to the first direction; as the first IGBT region 41 closest to the second symmetry line 12 moves toward the first IGBT region 41 closest to the edge of the diode array in the second direction, the area of ​​the first IGBT region 41 gradually decreases.

[0179] The above embodiment has the following beneficial effects: due to the characteristic that the heat dissipation performance decreases at locations closer to the second line of symmetry 12 on the semiconductor substrate 10 and increases at the edge regions closer to the sides in the second direction, i.e., due to the characteristic that the heat dissipation performance gradually increases from the center of the semiconductor substrate 10 toward the sides of the semiconductor substrate 10, the area of ​​the first IGBT region 41 inside the diode region 30 closer to the side of the semiconductor substrate 10 is smaller, and more heat generated by the diode at this location is evenly dissipated outward through the second IGBT region 42 outside it; and the area of ​​the first IGBT region 41 inside the diode region 30 closer to the second line of symmetry 12 is larger, and more heat generated by the diode at this location is evenly dissipated outward through the first IGBT region 41 inside it. As a result, the areas of the first IGBT region 41 at different locations in the first and second directions are consistent with the heat dissipation performance of the semiconductor substrate 10 at that location, thereby improving the heat dissipation uniformity of the diode region 30 at different locations.

[0180] Exemplary, reference Figure 11 The semiconductor substrate 10 has a second symmetry line 12 parallel to the first direction. For example, assuming the first direction is the row direction and the second direction is the column direction, the number of diode regions 30 located in the same column is at least three. Specifically, between two adjacent second IGBT regions 42 in the second direction, the area of ​​the first IGBT region 41 closer to the second symmetry line 12 is larger than the area of ​​the first IGBT region 41 farther from the second symmetry line 12.

[0181] Specifically, the number of diode regions 30 in the same column is at least three. Specifically, the number of diode regions 30 in the same column can be any value not less than three, such as 3, 4, 10, 20, etc.

[0182] Exemplary, reference Figure 11The semiconductor substrate 10 has two opposing second sides in the second direction. Both second sides extend along the first direction. The line of symmetry between the two second sides is also a second line of symmetry 12. The second line of symmetry 12 is equidistant from the two second sides. In other words, the diode array is disposed in the middle region of the semiconductor substrate 10 in the second direction.

[0183] refer to Figure 11 The area of ​​the first IGBT region 41 gradually decreases as the first IGBT region 41 closest to the second symmetry line 12 moves toward the first IGBT region 41 closest to the edge of the diode array in the second direction. Specifically, between two adjacent first IGBT regions 41 in the second direction, the closer the region is to the second symmetry line 12, the larger the area of ​​the first IGBT region 41; the farther the region is from the second symmetry line 12, the smaller the area of ​​the first IGBT region 41.

[0184] In other words, reference Figure 11 When the second symmetry line 12 is also the symmetry line of the two second sides, between two adjacent first IGBT regions 41 in the second direction, the smaller the distance from the nearest second side of the two second sides, the smaller the area of ​​the first IGBT region 41; the larger the distance from the nearest second side of the two second sides, the larger the area of ​​the first IGBT region 41.

[0185] For example, reference Figure 11 , the area of ​​the first IGBT region 41e may be set to be larger than the area of ​​the first IGBT region 41a and the area of ​​the first IGBT region 41f.

[0186] In some embodiments, another semiconductor device is provided, referring to Figure 10 and Figure 11 The first direction is the row direction, the second direction is the column direction, and the areas of all diode regions 30 located in the same column are equal.

[0187] The above embodiment has the following beneficial effects: the area of ​​the diode region 30 is positively correlated with the amount of heat it generates during operation, i.e., the larger the area of ​​the diode region 30, the more heat it generates during operation, and the smaller the area of ​​the diode region 30, the less heat it generates during operation. On the basis that all diode regions 30 in the same row have equal areas, the area of ​​the first IGBT region 41 inside the diode region 30 closer to the side edge of the semiconductor substrate 10 in the second direction is smaller, and the area of ​​the first IGBT region 41 inside the diode region 30 closer to the second symmetry line 12 is larger. This ensures that the areas of the diode region 30 and the first IGBT region 41 at different locations in the first and second directions are aligned with the heat dissipation performance of the semiconductor substrate 10 at those locations, thereby improving the heat dissipation uniformity of the diode regions 30 at different locations.

[0188] For example, reference Figure 10 and Figure 11 , the areas of the diode region 30a, the diode region 30e, and the diode region 30f can be set to be equal.

[0189] In some other embodiments, another semiconductor device is provided, referring to Figure 11 As the diode region 30 closest to the second symmetry line 12 moves toward the diode region 30 closest to the edge of the diode array in the second direction, the area of ​​the diode region 30 gradually increases.

[0190] Specifically, refer to Figure 11 , between two adjacent diode regions 30 in the second direction, the area of ​​the diode region 30 closer to the second symmetry line 12 is smaller than the area of ​​the diode region 30 farther from the second symmetry line 12. That is, between two adjacent diode regions 30 in the second direction, the area of ​​the diode region 30 closer to the second symmetry line 12 is smaller, and the area of ​​the diode region 30 farther from the second symmetry line 12 is larger.

[0191] The above embodiment has the following beneficial effects: the area of ​​the diode region 30 is positively correlated with the amount of heat it generates during operation, i.e., the larger the area of ​​the diode region 30, the more heat it generates during operation, and the smaller the area of ​​the diode region 30, the less heat it generates during operation. Considering that the heat dissipation performance of the center of the semiconductor substrate 10 is worse than that of the sides of the semiconductor substrate 10, the area of ​​the diode region 30 is made smaller as it approaches the second symmetry line 12, thereby reducing the heat generated by the diode at that location during operation; while the area of ​​the diode region 30 is made larger as it approaches the side edges of the semiconductor substrate 10 in the second direction, thereby increasing the heat generated by the diode at that location during operation. Matching the area of ​​the diode region 30 at different locations in the first and second directions with the heat dissipation performance of the semiconductor substrate 10 at that location facilitates improved heat dissipation uniformity of the diode region 30 at different locations.

[0192] For example, reference Figure 11 , the area of ​​the diode region 30e can be set to be smaller than the area of ​​the diode region 30a and the area of ​​the diode region 30f.

[0193] In some embodiments, another semiconductor device is provided, referring to Figure 11 The first direction is the row direction, the second direction is the column direction, and the areas of all first IGBT regions 41 located in the same column are equal; the areas of all diode regions 30 located in the same column are equal.

[0194] The above embodiment has the following beneficial effects: the areas of the first IGBT regions 41 at different positions in the first direction are matched with the heat dissipation performance of the semiconductor substrate 10 at the corresponding positions, thereby improving the heat dissipation uniformity of the diode regions 30 at different positions, while making the areas of the first IGBT regions 41 and the diode regions 30 at different positions in the second direction equal, thereby simplifying the topological structure of the array-arranged diode regions 30 and the first IGBT regions 41 and facilitating manufacturing.

[0195] For example, reference Figure 11 , the areas of the first IGBT region 41a, the first IGBT region 41e, and the first IGBT region 41f can be set to be equal, and the areas of the diode region 30a, the diode region 30e, and the diode region 30f can be set to be equal.

[0196] In some embodiments, another semiconductor device is provided, referring to Figure 12 The diode array has a first symmetry line 11 parallel to the second direction; the spacing between two adjacent diode regions 30 in the first direction gradually decreases from close to the first symmetry line 11 to away from the first symmetry line 11.

[0197] The above embodiment has the following beneficial effects: considering that the heat dissipation performance of the middle portion of the semiconductor substrate 10 is worse than that of the two sides of the semiconductor substrate 10, the spacing between two adjacent diode regions 30 in the first direction gradually decreases from close to the first symmetry line 11 to away from the first symmetry line 11, so that the arrangement spacing of the diode regions 30 in the first direction is sparser, and the arrangement spacing of the diode regions 30 in the first direction is denser, so that the arrangement spacing of the diode regions 30 at different positions in the first direction matches the heat dissipation performance of the semiconductor substrate 10 at that position, thereby improving the heat dissipation uniformity of the diode regions 30 at different positions.

[0198] It should be noted that the spacing between two adjacent diode regions 30 in the first direction refers to the minimum spacing between the outer circles of two adjacent diode regions 30 in the first direction. Correspondingly, the spacing between two adjacent diode regions 30 in the second direction refers to the minimum spacing between the outer circles of two adjacent diode regions 30 in the second direction.

[0199] Specifically, refer to Figure 12 For example, taking the first direction as the row direction and the second direction as the column direction, the number of diode regions 30 in the same row is at least four. The spacing between any two adjacent diode regions 30 in the first direction is defined as a first spacing. The closer the first spacing is to the first symmetry line 11, the larger the first spacing is, and the farther the first spacing is from the first symmetry line 11, the smaller the first spacing is. That is, of two adjacent first spacings in the first direction, the first spacing closer to the first symmetry line 11 is larger than the first spacing farther from the first symmetry line 11.

[0200] For example, taking the first direction as the row direction and the second direction as the column direction, the number of diode regions 30 located in the same row can be any value of not less than 3, such as 4, 10, 20, etc., so that there can be at least three first spacings in the first direction.

[0201] For example, reference Figure 12 The number of first intervals between two adjacent diode regions 30 in the first direction is four, namely d1, d2, d3, and d4, and d2>d1 and d3>d4 can be set.

[0202] Of course, in other embodiments, any two adjacent first spacings in the first direction may be made equal to simplify the setting difficulty. Figure 12 The number of first intervals between two adjacent first IGBT regions 41 in the first direction is four, namely d1, d2, d3, and d4, and d1=d2=d3=d4 can be set.

[0203] In some embodiments, another semiconductor device is provided, referring to Figure 13 The semiconductor substrate 10 has a second symmetry line 12 parallel to the first direction; the distance between two adjacent diode regions 30 in the second direction gradually decreases from close to the second symmetry line 12 to away from the second symmetry line 12.

[0204] The above embodiment has the following beneficial effects: considering that the heat dissipation performance of the middle portion of the semiconductor substrate 10 is worse than the heat dissipation performance of the two sides of the semiconductor substrate 10, the spacing between two adjacent diode regions 30 in the second direction gradually decreases from close to the second symmetry line 12 to away from the second symmetry line 12, so that the arrangement spacing of the diode regions 30 in the second direction is sparser the closer to the second symmetry line 12, and the arrangement spacing of the diode regions 30 in the second direction is denser the farther away from the second symmetry line 12, so that the arrangement spacing between the diode regions 30 at different positions in the first direction and the second direction matches the heat dissipation performance of the semiconductor substrate 10 at that position, thereby improving the heat dissipation uniformity of the diode regions 30 at different positions.

[0205] Specifically, refer to Figure 12 For example, taking the first direction as the row direction and the second direction as the column direction, the number of diode regions 30 located in the same column is at least four. The spacing between any two adjacent diode regions 30 in the second direction is defined as a second spacing. The closer the second spacing is to the second line of symmetry 12, the larger the second spacing is, and the farther the second spacing is from the second line of symmetry 12, the smaller the second spacing is. That is, of two adjacent second spacings in the second direction, the second spacing closer to the second line of symmetry 12 is larger than the second spacing farther from the second line of symmetry 12.

[0206] Exemplary, reference Figure 12 Taking the first direction as the row direction and the second direction as the column direction as an example, the number of diode regions 30 located in the same column can be 4, 10, 20, or any other value not less than 3, so that there can be at least three second spacings in the second direction.

[0207] For example, reference Figure 12 The number of second intervals between two adjacent diode regions 30 in the second direction is four, namely d5, d6, d7, and d8, and d6>d5 and d7>d8 ​​can be set.

[0208] Exemplarily, another semiconductor device is provided, referring to Figure 12 The first direction is the row direction, and the second direction is the column direction; in all the diode regions 30 located in the same column, the spacing between any two adjacent diode regions 30 is equal.

[0209] The above embodiment has the following beneficial effects: the spacing between any two adjacent diode regions 30 in all diode regions 30 located in the same column is equal, and the diode regions 30 are arranged at equal intervals along the second direction, which simplifies the topological structure of the diode array and facilitates manufacturing.

[0210] For example, any two adjacent second spacings in the second direction can be made equal to each other to simplify the setting difficulty. Figure 12 The number of second intervals between two adjacent diode regions 30 in the second direction is four, namely d5, d6, d7, and d8, and d5=d6=d7=d8 can be set.

[0211] Exemplarily, another semiconductor device is provided, referring to Figure 10 The spacing between two adjacent diode regions 30 in the first direction or the second direction is greater than half of the sum of the ring widths of the two diode regions 30 and less than the sum of the ring widths of the two diode regions 30 .

[0212] The above embodiment has the following beneficial effects: by ensuring that the spacing between two adjacent diode regions 30 is greater than half the sum of the ring widths of the two diode regions 30, the second IGBT region 42 between the two diode regions 30 is sufficiently wide, thereby enabling timely dissipation of heat from the two diode regions 30 during operation to the semiconductor substrate 10, thereby improving heat dissipation. Furthermore, by ensuring that the spacing between two adjacent diode regions 30 is less than the sum of the ring widths of the two diode regions 30, the arrangement of the diode regions 30 is prevented from being too sparse while ensuring heat dissipation. This balances the arrangement density of the diode regions 30 and heat dissipation performance, ensuring heat dissipation while also improving the arrangement density of the diode regions 30.

[0213] It should be noted that the ring width of the diode region 30 refers to the minimum distance between the inner circle and the outer circle of the diode region 30 .

[0214] by Figure 10 For example, the spacing between two adjacent diode regions 30 in the first direction is m1. The ring width of the left diode region 30 is m2, and the ring width of the right diode region 30 is m3. The relationship between m1, m2, and m3 satisfies: (m2+m3) / 2<m1<m2+m3. Consequently, the heat dissipation capacity of the second IGBT region 42 between the two diode regions 30, with a width m1 in the first direction, is sufficient to match the heat dissipation requirements of an area half the ring width of the two adjacent diode regions 30 during operation, improving heat dissipation while preventing the diode regions 30 from being too sparsely arranged in the first direction.

[0215] Continue with Figure 10 For example, the spacing between two adjacent diode regions 30 in the second direction is m6. The ring width of the lower diode region 30 is m2, and the ring width of the upper diode region 30 is m7. The relationship among m2, m6, and m7 satisfies: (m2+m7) / 2<m6<m2+m7. Consequently, the heat dissipation capacity of the second IGBT region 42 between the two diode regions 30, with a width m6 in the second direction, is sufficient to meet the heat dissipation requirements of an area half the ring width of the two adjacent diode regions 30 during operation, improving heat dissipation while preventing the diode regions 30 from being too sparsely arranged in the second direction.

[0216] Exemplarily, another semiconductor device is provided, referring to Figure 10 The width of each first IGBT region 41 in the first direction or the second direction is greater than the ring width of the diode region 30 surrounding it, and less than twice the ring width of the diode region 30 surrounding it.

[0217] The above embodiment has the following beneficial effects: the width of each first IGBT region 41 in the first or second direction is greater than the width of the ring surrounding the diode region 30, making the first IGBT region 41 sufficiently wide to promptly dissipate heat transferred from the surrounding diode region 30 during operation to the semiconductor substrate 10, thereby improving heat dissipation. Furthermore, the width of each first IGBT region 41 is controlled to be less than twice the width of the ring surrounding the diode region 30, thereby ensuring heat dissipation while avoiding a mismatch between heat dissipation capacity and heat dissipation requirements, such as when the width of the first IGBT region 41 is too large and the width of the ring surrounding the diode region 30 is too narrow. This ensures a good match between the heat dissipation capacity provided by the first IGBT region 41 and the heat dissipation requirements of the diode region 30, thus avoiding insufficient or excessive heat dissipation capacity in the first IGBT region 41.

[0218] It should be noted that when the first IGBT region 41 is an irregular shape such as a circle or an ellipse, the width of the first IGBT region 41 in the first direction refers to the maximum width of the first IGBT region 41 along the first direction. Correspondingly, the width of the first IGBT region 41 in the second direction refers to the maximum width of the first IGBT region 41 along the second direction.

[0219] by Figure 10For example, if the width of the first IGBT region 41 in the first direction is m4, and the ring width of the diode region 30 surrounding it is m3, then m3 and m4 satisfy the following relationship: m3 < m4 < 2*m3. This ensures that the heat dissipation capacity of the first IGBT region 41 in the first direction, m4, matches the heat dissipation requirements of the region of the diode region 30 surrounding it that is half the ring width during operation. This allows heat dissipated from the first IGBT region 41 to be promptly dissipated to the semiconductor substrate 10, improving heat dissipation. This also prevents the first IGBT region 41 from being too wide in the first direction, which could result in excessive heat dissipation capacity.

[0220] by Figure 10 For example, if the width of the first IGBT region 41 in the second direction is m5, and the ring width of the diode region 30 surrounding it is m3, then m3 and m5 satisfy the following relationship: m3 < m5 < 2*m3. This ensures that the heat dissipation capacity of the first IGBT region 41 in the second direction, m5, matches the heat dissipation requirements of the region of the diode region 30 surrounding it that is half the ring width during operation. This allows heat dissipated toward the first IGBT region 41 to be promptly dissipated to the semiconductor substrate 10, improving heat dissipation. This also prevents the first IGBT region 41 from being too wide in the second direction, which could result in excessive heat dissipation capacity.

[0221] The present invention has been described through the above-described embodiments. However, it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments and that various variations and modifications may be made based on the teachings of the present invention, all of which fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate having a diode region, a first IGBT region, and a second IGBT region provided between a first main surface and a second main surface opposite to the first main surface; When the semiconductor substrate is viewed from above, the diode region is annular and surrounds the first IGBT region, and the second IGBT region surrounds the diode region; the first IGBT region is provided with a first active gate on the first main surface side, and the second IGBT region is provided with a second active gate on the first main surface side; a first interlayer dielectric layer disposed on the first main surface, wherein a first plug and a second plug are disposed through the first interlayer dielectric layer, wherein a first end of the first plug is electrically connected to the first active gate, and a first end of the second plug is electrically connected to the second active gate; a gate runner, comprising a gate wiring portion and a gate pad portion provided on the first interlayer dielectric layer, the gate wiring portion electrically connecting the second ends of the first plug and the second plug, and the gate pad portion electrically connecting the gate wiring portion; a second interlayer dielectric layer covering the gate runner, wherein a fourth plug is provided through the second interlayer dielectric layer, and a first end of the fourth plug is electrically connected to the gate pad portion; and A gate pad is disposed on the second interlayer dielectric layer, and the gate pad is electrically connected to the second end of the fourth plug.

2. The semiconductor device according to claim 1, wherein There are multiple diode regions and multiple first IGBT regions, and the multiple diode regions are arranged in an array spaced apart along a first direction and a second direction to form a diode array; wherein the first direction and the second direction are arranged crosswise; When the semiconductor substrate is viewed from above, each of the diode regions corresponds to one of the first IGBT regions and surrounds the corresponding first IGBT region.

3. The semiconductor device according to claim 2, wherein There are multiple first plugs and multiple second plugs, the multiple first plugs are arranged in at least two rows along the second direction, and the multiple second plugs are arranged in at least two rows along the second direction; The gate wiring portion includes: a plurality of first gate wiring portions, each of the plurality of first gate wiring portions extending along the second direction and arranged at intervals along the first direction, the first gate wiring portions being electrically connected to the second ends of the first plugs in the same column; a plurality of second gate wiring portions, each of the plurality of second gate wiring portions extending along the second direction and arranged at intervals along the first direction, the second gate wiring portions being electrically connected to the second ends of the second plugs in the same column; A gate wiring bus portion, the gate wiring bus portion is electrically connected to the gate pad portion, the gate wiring bus portion extends along the first direction and is located on the first side outside the diode array; the gate wiring bus portion electrically connects the first gate wiring portion and the first end of the second gate wiring portion to form a first comb tooth structure.

4. The semiconductor device according to claim 3, wherein The first IGBT region is provided with a plurality of first active gates extending along the first direction and arranged at intervals along the second direction, each of the first active gates corresponds to a first plug and is electrically connected to the first end of the corresponding first plug; The second IGBT region is provided with a plurality of second active gates extending along the first direction and arranged at intervals along the second direction, and each second active gate corresponds to a second plug and is electrically connected to the first end of the corresponding second plug.

5. The semiconductor device according to claim 3, wherein A plurality of the first gate wiring portions and a plurality of the second gate wiring portions are alternately arranged along the first direction.

6. The semiconductor device according to claim 3, wherein The gate pad portion is located at an intersection of the gate wiring converging portion and the outermost second gate wiring portion among the plurality of second gate wiring portions, and is also electrically connected to a first end of the outermost second gate wiring portion; When looking down at the gate pad portion and the second active gate, the first portion of the gate pad portion overlaps with the second portion of the second active gate, and the first ends and second ends of some of the second plugs in the plurality of second plugs are electrically connected to the second portion and the first portion, respectively.

7. The semiconductor device according to any one of claims 3 to 6, wherein Also includes: an emitter runner, comprising an emitter wiring bus portion and a plurality of emitter wiring portions disposed on the first interlayer dielectric layer, wherein the plurality of emitter wiring portions extend along the second direction and are spaced apart along the first direction, the emitter wiring bus portion extending along the first direction and being located on a second side of the diode array; the emitter wiring bus portion electrically connecting first ends of the plurality of emitter wiring portions to form a second comb-tooth structure; Among them, the second side is opposite to the first side, and the first comb tooth structure and the second comb tooth structure are relatively staggered and spaced apart; when looking down at the first comb tooth structure and the second comb tooth structure, the first comb tooth structure is a narrow strip comb tooth structure relative to the second comb tooth structure, and the second comb tooth structure is a wide strip comb tooth structure relative to the first comb tooth structure.

8. The semiconductor device according to claim 7, wherein A third plug is further provided through the first interlayer dielectric layer, wherein a first end of the third plug is electrically connected to an emitter region of the first conductivity type, a contact region of the second conductivity type, and an anode region provided on the first main surface side, and a second end of the third plug is electrically connected to the emitter runner; When the third plug is viewed from above, the third plug extends in the first direction and is disconnected at a position below the gate wiring portion.

9. The semiconductor device according to claim 7, wherein Also includes: An emitter pad is arranged on the second interlayer dielectric layer and is spaced apart from the gate pad; the second interlayer dielectric layer also covers the emitter flow channel, and a fifth plug is also provided through the second interlayer dielectric layer; when looking down at the fifth plug and the second comb tooth structure, the shape of the fifth plug is comb tooth-shaped, and the outline of the second comb tooth structure surrounds the outline of the fifth plug; the first end of the fifth plug is electrically connected to the emitter flow channel, and the second end of the fifth plug is electrically connected to the emitter pad.

10. The semiconductor device according to claim 9, wherein When the emitter pad and the gate wiring portion are viewed in plan, the emitter pad and the gate wiring portion are at least partially overlapped.

Images