Image pickup element and electronic apparatus

Abstract

The invention relates to an imaging element and an electronic apparatus. Wherein the imaging element may include: a photodiode; a transfer transistor connected to the photodiode; a first transistor wherein an output of the pass transistor is connected to an input of the first transistor; an output of the first transistor is connected to an input of the second transistor, a gate of the first transistor and a gate of the second transistor are arranged in a first direction in a plan view, and a gate of the first transistor and a gate of the second transistor are arranged in a second direction in the plan view. A gate of the reset transistor, a gate of the amplification transistor, and a gate of the selection transistor are arranged in a second direction, and wherein the first direction and the second direction are perpendicular.

Description

[0001] This application is a divisional application of the patent application with application number 201980059245.2, whose application date is September 9, 2019 and invention name is “Solid-state imaging device and electronic device”. Technical Field

[0002] The present invention relates to a solid-state imaging device and an electronic device. Background Art

[0003] Solid-state imaging devices are used in electronic devices including, for example, imaging units such as digital cameras and digital video cameras, and mobile terminal units having imaging functions. Examples of solid-state imaging devices include CMOS (Complementary MOS) image sensors that read charges accumulated in a photodiode serving as a photoelectric conversion element via a MOS (Metal Oxide Semiconductor) transistor (for example, see Patent Document 1).

[0004] In a CMOS image sensor with a global shutter function, a charge accumulation unit is provided in each pixel. Since the signal of the previous frame is retained in the charge accumulation unit, it is necessary to set a structure in which the charge accumulation unit is shielded from light to prevent the signal of the next frame from entering the charge accumulation unit. However, by simply setting such a structure, it is difficult to fully prevent light from leaking into the charge accumulation unit. In view of this situation, for example, the methods described in Patent Documents 1 and 2 can be considered as countermeasures to this problem.

[0005] Reference List

[0006] Patent Literature

[0007] Patent Document 1: Japanese Unexamined Patent Application No. 2013-150232

[0008] Patent Document 2: Japanese Unexamined Patent Application No. 2012-175259 Summary of the invention

[0009] However, the method described in Patent Document 1 has a disadvantage in that the resolution is greatly reduced. In addition, the method described in Patent Document 2 has a disadvantage in that it is difficult to accurately eliminate the influence of oblique incident light leaking into the charge accumulation portion, and the conversion efficiency is also low. Therefore, it is desirable to provide a solid-state imaging device that can accurately eliminate the influence of oblique incident light leaking into the charge accumulation portion while suppressing a reduction in resolution and a reduction in conversion efficiency, and an electronic device including the solid-state imaging device.

[0010] A solid-state imaging device according to an embodiment of the present invention includes: a light receiving surface; and two or more pixels, which are opposite to the light receiving surface. Each pixel includes: a photoelectric conversion unit, which performs photoelectric conversion on light incident through the light receiving surface, a first charge holding unit, which holds the charge transferred from the photoelectric conversion unit, and a second charge holding unit, wherein all or part of the second charge holding unit is arranged at a position overlapping with the first charge holding unit in a planar layout, and is formed to be non-conductive with the first charge holding unit. Each pixel also includes a first transfer transistor, which transfers the charge held by the first charge holding unit to a floating diffusion unit; and a second transfer transistor, which transfers the charge held by the second charge holding unit to a floating diffusion unit.

[0011] An electronic device according to an embodiment of the present invention includes: a solid-state imaging device that outputs image data corresponding to incident light; and a signal processing circuit that processes the image data. The solid-state imaging device provided in the electronic device has the same configuration as the aforementioned solid-state imaging device.

[0012] In the solid-state imaging device and the electronic device according to various embodiments of the present invention, there is provided: a first charge holding portion that holds the charge transferred from the photoelectric conversion portion, and a second charge holding portion that is formed to be non-conductive with the first charge holding portion. This makes it possible to reduce the PLS (Parastic Light Sensitibity) component contained in the signal charge based on the signal charge read from the first charge holding portion and the noise charge read from the second charge holding portion. In addition, in the solid-state imaging device and the electronic device according to various embodiments of the present invention, all or part of the second charge holding portion is configured at a position overlapping with the first charge holding portion in the planar layout. Compared with the case where the first charge holding portion and the second charge holding portion are configured in parallel with each other in the planar layout, this can more accurately estimate the PLS component caused by oblique incidence. In addition, in the solid-state imaging device and the electronic device according to various embodiments of the present invention, the first transfer transistor is used to read the charge from the first charge holding portion, and the second transfer transistor is used to read the charge from the second charge holding portion. As a result, a higher conversion efficiency is achieved compared with the case where the switch element is kept turned on during the reading of the charge from the first charge holding portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram showing an example of a schematic configuration of a solid-state imaging device according to an embodiment of the present invention.

[0014] Figure 2 It shows Figure 1 FIG. 5 is a diagram of an example of a circuit configuration of a sensor pixel and a readout circuit.

[0015] Figure 3 It shows Figure 1FIG. 4 is a diagram of an example of a planar configuration of a sensor pixel.

[0016] Figure 4 It shows that along Figure 3 FIG. 2 is a diagram showing an example of a cross-sectional structure along line AA.

[0017] Figure 5 It shows that including Figure 4 FIG. 1 is a diagram showing an example of a timing chart of a sensor pixel of a solid-state imaging device during imaging.

[0018] Figure 6 It shows that including Figure 4 FIG. 1 is a diagram showing a modified example of a timing diagram of a solid-state imaging device having sensor pixels during imaging.

[0019] Figure 7 It shows Figure 1 FIG. 4 is a diagram showing a modified example of the planar structure of a sensor pixel.

[0020] Figure 8 It shows that along Figure 7 FIG. 2 is a diagram showing an example of a cross-sectional structure along line AA.

[0021] Fig. 9 It shows that along Figure 7 A diagram showing a modified example of the cross-sectional structure along line AA.

[0022] Fig.10 It shows that along Figure 3 A diagram showing a modified example of the cross-sectional structure along line AA.

[0023] Fig.11 is a diagram showing an example of a schematic configuration of an electronic device including a solid-state imaging device according to any of the foregoing embodiments and their modified examples.

[0024] Fig.12 It shows Fig.11 FIG. 1 is a diagram of an example of an imaging step of an electronic device.

[0025] Fig.13 is a diagram showing an example of a correction coefficient for each pixel.

[0026] Fig.14 is a diagram showing an example of a correction coefficient for each pixel.

[0027] Fig.15 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0028] Fig.16 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the description will be made in the following order.

[0030] 1. Example (Solid-state imaging device) Figures 1 to 6

[0031] 2. Modification Example (Solid-state imaging device) Figures 7 to 10

[0032] 3. Application examples (electronic equipment) Figures 11 to 14

[0033] 4. Application examples Figure 15 to Figure 16

[0034] <1. Example>

[0035] [structure]

[0036] A solid-state imaging device 1 according to an embodiment of the present invention will be described. The solid-state imaging device 1 is, for example, an upper surface illumination type image sensor including a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like. The solid-state imaging device 1 receives light from a subject and performs photoelectric conversion on the light to generate an image signal, thereby capturing an image. The solid-state imaging device 1 outputs a pixel signal corresponding to the incident light.

[0037] The upper surface illumination type image sensor is an image sensor having the following structure: a photoelectric conversion unit such as a photodiode is provided between the light receiving surface on which the light from the subject is incident and the back surface of the semiconductor substrate. The photoelectric conversion unit receives the light from the subject and converts the light into an electrical signal. It should be noted that the present invention is not limited to application to CMOS image sensors.

[0038] Figure 1An example of a schematic configuration of a solid-state imaging device 1 according to an embodiment of the present invention is shown. The solid-state imaging device 1 includes a pixel array section 10 and a logic circuit 20. The pixel array section 10 includes two or more sensor pixels 11 and two or more reading circuits 12 (described later). The sensor pixel 11 corresponds to a specific example of a "pixel" of the present invention. Each sensor pixel 11 performs photoelectric conversion and outputs a charge corresponding to the amount of light received. The two or more sensor pixels 11 are opposite to a light receiving surface 10A (described later) and are arranged in a rectangular shape in the pixel matrix section 10. Each reading circuit 12 outputs a pixel signal or a noise signal (described later) based on the charge output from the sensor pixel 11. For example, in the pixel array section 10, one of the two or more reading circuits 12 is provided for each sensor pixel 11. It should be noted that in the pixel array section 10, one of the two or more reading circuits 12 can also be provided for two or more sensor pixels 11.

[0039] The pixel array section 10 includes two or more pixel drive lines HSL and two or more data output lines VSL. The pixel drive line HSL is a wiring that receives a control signal for controlling the output of the charge accumulated in the sensor pixel 11. The pixel drive line HSL extends, for example, in the row direction. The data output line VSL is a wiring for outputting a pixel signal or a noise signal output from each reading circuit 12 to the logic circuit 20. The data output line VSL extends, for example, in the column direction.

[0040] The logic circuit 20 includes, for example, a vertical drive circuit 21, a column signal processing circuit 22, a horizontal drive circuit 23, and a system control circuit 24. The logic circuit 20 (specifically, the horizontal drive circuit 23) outputs the output voltage of each sensor pixel 11 to an external device, thereby providing image data to the external device.

[0041] For example, the vertical drive circuit 21 sequentially selects two or more sensor pixels 11 on a predetermined pixel row unit basis. The "predetermined pixel row unit" refers to a pixel row whose pixel selection is enabled by the same address. For example, in the case where a single sensor pixel 11 is assigned to a single read circuit 12, the "predetermined pixel row unit" refers to a single pixel row. In addition, for example, in the case where two or more sensor pixels 11 share a single read circuit 12, if the layout of the two or more sensor pixels 11 sharing the read circuit 12 is 2 pixel rows × n pixel columns (n ​​is an integer greater than 1), the "predetermined pixel row unit" refers to two pixel rows. Similarly, if the layout of the two or more sensor pixels 11 sharing the read circuit 12 is 4 pixel rows × n pixel columns (n ​​is an integer greater than 1), the "predetermined pixel row unit" refers to four pixel rows. The vertical drive circuit 21 controls the transistors (e.g., transfer transistors TRX, TRG, and DMG and discharge transistor OFG) in each sensor pixel 11 via the pixel drive line HSL, and also controls the transistors (e.g., reset transistor RST and selection transistor SEL) in each read circuit 12.

[0042] The column signal processing circuit 22 performs, for example, a correlated double sampling (CDS) process on the pixel signal or noise signal output from each sensor pixel 11 of the row selected by the vertical drive circuit 21. For example, by performing the CDS process, the column signal processing circuit 22 extracts the signal level of the pixel signal or the noise signal, and holds pixel data corresponding to the amount of light received by each pixel 11 or noise pixel data corresponding to the PLS. The column signal processing circuit 22 includes, for example, a column signal processing section for each data output line VSL. The column signal processing section includes, for example, a single slope A / D converter. The single slope A / D converter includes, for example, a comparator and a counter circuit. The horizontal drive circuit 23 outputs, for example, the pixel data or noise pixel data held in the column signal processing circuit 22 to the outside in sequence. The system control circuit 24 controls, for example, the driving of each block (the vertical drive circuit 21, the column signal processing circuit 22, and the horizontal drive circuit 23) in the logic circuit 20.

[0043] Figure 2 An example of the circuit configuration of the sensor pixel 11 and the reading circuit 12 is shown. Figure 2, a case where a single sensor pixel 11 is assigned to a single reading circuit 12 is shown as an example. Each sensor pixel 11 includes components common to each other. Each sensor pixel 11 includes, for example, a photodiode PD, transfer transistors TRX, TRG, and DMG, charge holding portions MEM and DM, a floating diffusion portion FD, a discharge transistor OFG, and a discharge floating diffusion portion OFD. The transfer transistors TRX, TRG, and DMG and the discharge transistor OFG are, for example, NMOS (Metal Oxide Semiconductor) transistors.

[0044] The photodiode PD corresponds to a specific example of the “photoelectric conversion unit” of the present invention. The charge retention unit MEM corresponds to a specific example of the “first charge retention unit” of the present invention. The charge retention unit DM corresponds to a specific example of the “second charge retention unit” of the present invention. The transfer transistor TRG corresponds to a specific example of the “first transistor” of the present invention. The transfer transistor DMG corresponds to a specific example of the “second transistor” of the present invention. The transfer transistor TRX corresponds to a specific example of the “third transistor” of the present invention.

[0045] The photodiode PD performs photoelectric conversion on light incident via a light receiving surface 10A (described later). The photodiode PD performs photoelectric conversion to generate a charge corresponding to the amount of light received. The photodiode PD is, for example, a PN junction photoelectric conversion element. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TRX. The anode of the photodiode PD is electrically connected to a reference potential line (for example, ground GND).

[0046] The transfer transistor TRX is connected between the photodiode PD and the transfer transistor TRG. The transfer transistor TRX controls the potential of the charge retention unit MEM in response to a control signal applied to the gate of the transfer transistor TRX. For example, when the transfer transistor TRX is turned on, the potential of the charge retention unit MEM becomes deeper. In addition, for example, when the transfer transistor TRX is turned off, the potential of the charge retention unit MEM becomes shallower. Once the transfer transistor TRX is turned on, the charge accumulated in the photodiode PD is transferred to the charge retention unit MEM through the transfer transistor TRX. The drain of the transfer transistor TRX is electrically connected to the source of the transfer transistor TRG. The gate of the transfer transistor TRX is connected to the pixel drive line HSL.

[0047] The charge retention portion MEM is an impurity semiconductor region that temporarily retains the charge accumulated in the photodiode PD. The charge retention portion MEM retains the charge transferred from the photodiode PD. The charge retention portion DM is an impurity semiconductor region that temporarily retains the charge for PLS (Parastic Light Sensitibity) correction. The charge retention portion DM temporarily retains the charge generated by the PLS. The charge retention portion DM is an impurity semiconductor region that is formed to be non-conductive with the charge retention portion MEM. The charge retention portion MEM, the charge retention portion DM, and the floating diffusion portion FD described later each include an impurity semiconductor region having a common conductivity type. In addition, the impurity concentration of each of the charge retention portion MEM and the charge retention portion DM is lower than the impurity concentration of the floating diffusion portion FD described later.

[0048] PLS refers to stray light that occurs according to the amount of incident light when strong light is incident on the photodiode PD. If the charge generated by the stray light (hereinafter referred to as "noise charge") is mixed into the charge holding portion MEM, the noise charge is superimposed on the charge held in the charge holding portion MEM (hereinafter referred to as "signal charge") as a noise component. This causes the noise to be included in the pixel signal, and thus the image quality of the resulting image is degraded. In order to remove the noise component from the pixel signal, the charge holding portion DM holds the noise charge having a correlation with the noise charge to be superimposed on the signal charge.

[0049] The transfer transistor TRG is connected between the transfer transistor TRX and the floating diffusion FD. The transfer transistor TRG transfers the charge held in the charge holding portion MEM to the floating diffusion FD in response to a control signal applied to the gate of the transfer transistor TRG. For example, when the transfer transistor TRX is turned off and the transfer transistor TRG is turned on, the charge held in the charge holding portion MEM is transferred to the floating diffusion FD via the transfer transistor TRG. The drain of the transfer transistor TRG is electrically connected to the floating diffusion FD. The gate of the transfer transistor TRG is connected to the pixel drive line HSL.

[0050] The transfer transistor DMG is connected between the charge holding portion DM and the floating diffusion portion FD. The transfer transistor DMG transfers the charge held in the charge holding portion DM to the floating diffusion portion FD in response to a control signal applied to the gate of the transfer transistor DMG. For example, when the transfer transistor DMG is turned on, the charge held in the charge holding portion DM is transferred to the floating diffusion portion FD via the transfer transistor DMG. The drain of the transfer transistor DMG is electrically connected to the floating diffusion portion FD. The gate of the transfer transistor DGM is connected to the pixel drive line HSL.

[0051] The floating diffusion FD is a floating diffusion region (impurity semiconductor region) that temporarily holds the charge output from the photodiode PD via the transfer transistor TRX and the transfer transistor TRG. For example, the reset transistor RST is connected to the floating diffusion FD. The vertical signal line VSL is also connected to the floating diffusion FD via the amplifier transistor AMP and the selection transistor SEL. In addition, the floating diffusion FD is a floating diffusion region that temporarily holds the charge output from the charge holding portion DM via the transfer transistor DMG.

[0052] The discharge transistor OFG is connected between the photodiode PD and the power line VDD. The discharge transistor OFG initializes (resets) the photodiode PD in response to a control signal applied to the gate of the discharge transistor OFG. For example, when the discharge transistor OFG is turned on, the potential of the photodiode PD is reset to the potential level of the power line VDD. In other words, the photodiode PD is initialized. In addition, the discharge transistor OFG forms, for example, an overflow path between the transfer transistor TRX and the power line VDD, and discharges the charge overflowing from the photodiode PD to the power line VDD. The drain of the discharge transistor OFG is connected to the power line VDD, and the source of the discharge transistor OFG is connected between the photodiode PD and the transfer transistor TRX. The gate of the discharge transistor OFG is connected to the pixel drive line HSL.

[0053] The reset transistor RST is connected between the floating diffusion FD and the power line VDD. The reset transistor RST initializes (resets) various regions from the charge retention unit MEM to the floating diffusion FD in response to a control signal applied to the gate of the reset transistor RST. For example, when the transfer transistors TRG and DMG and the reset transistor RST are turned on, the potentials of the charge retention units MEM and DM and the floating diffusion FD are reset to the potential level of the power line VDD. In other words, the charge retention units MEM and DM and the floating diffusion FD are initialized. The drain of the reset transistor RST is connected to the power line VDD, and the source of the reset transistor RST is connected to the floating diffusion FD. The gate of the reset transistor RST is connected to the pixel drive line HSL.

[0054] The amplifier transistor AMP has a gate connected to the floating diffusion FD, a drain connected to the power supply line VDD, and a source connected to the drain of the selection transistor SEL. The amplifier transistor AMP is used as an input part of a source follower circuit that reads the charge obtained by photoelectric conversion at the photodiode PD or the charge accumulated in the charge holding part DM. Since the source of the amplifier transistor AMP is connected to the vertical signal line VSL via the selection transistor SEL, the amplifier transistor AMP constitutes a source follower circuit together with a constant current source connected to one end of the vertical signal line VSL. The amplifier transistor AMP converts the charge obtained by photoelectric conversion at the photodiode PD into a pixel signal, and outputs the pixel signal to the vertical signal line VSL via the selection transistor SEL. In addition, the amplifier transistor AMP converts the charge accumulated in the charge holding part DM into a noise signal, and outputs the noise signal to the vertical signal line VSL via the selection transistor SEL.

[0055] The selection transistor SEL has a drain connected to the source of the amplifier transistor AMP, a source connected to the vertical signal line VSL, and a gate connected to the pixel drive line HSL. The selection transistor SEL controls the output of the pixel signal or noise signal output from the amplifier transistor AMP to the vertical signal line VSL in response to a control signal applied to the gate of the selection transistor SEL. When the control signal is turned on, the selection transistor SEL enters a conducting state, and the sensor pixel 11 connected to the selection transistor SEL enters a selected state. When the sensor pixel 11 enters the selected state, the pixel signal or noise signal output from the amplifier transistor AMP is read out to the column signal processing circuit 22 via the vertical signal line VSL.

[0056] Next, the configuration of the sensor pixel 11 will be described in detail. Figure 3 An example of a planar configuration of the sensor pixel 11 is shown. Figure 4 Shown along Figure 3 An example of a cross-sectional structure along line AA. Figure 3 and Figure 4 are schematic and not necessarily drawn to scale. Figure 4 In the present invention, the density of the impurity concentration is represented by symbols including "P+", "N-", "N+", and "N++". Herein, for example, in a position represented as "P+", the concentration of the p-type impurity (acceptor) has a value higher than a value in the range of 1×1016 cm-3 to 5×1018 cm-3. "N+" means that the concentration of the n-type impurity (donor) is higher than that of "N-". "N++" means that the concentration of the n-type impurity (donor) is higher than that of "N+". In a position represented as "N-", for example, the concentration of the n-type impurity (donor) has a value in the range of 1×1016 cm-3 to 5×1018 cm-3.

[0057] The sensor pixel 11 is formed on a semiconductor substrate 30. For example, the semiconductor substrate 30 is a silicon substrate. The semiconductor substrate 30 includes a p-well layer 32 located on the upper surface of the semiconductor substrate 30 and in the vicinity thereof, and includes an n-type semiconductor layer 31 located at a position deeper than the p-well layer 32. The p-well layer 32 is a p-type semiconductor region formed at and around the upper surface of the semiconductor substrate 30. In the p-well layer 32, an n-type semiconductor region 33 and a p-type semiconductor region 34 are formed. The p-type semiconductor region 34 is formed at the upper surface of the semiconductor substrate 30 and is in contact with the n-type semiconductor region 33. The n-type semiconductor region 33 and the p-type semiconductor region 34 are stacked in the thickness direction (normal direction) of the semiconductor substrate 30, and constitute a photodiode PD. The photodiode PD is arranged at a position adjacent to the charge holding portion MEM and the charge holding portion DM in a planar layout. The region of the upper surface of the semiconductor substrate 30 where the p-type semiconductor region 34 is formed is the light receiving surface 10A. In terms of positional relationship with the photodiode PD, the light receiving surface 10A is formed at a position on the transfer transistor TRX side.

[0058] The charge retention portion MEM is formed at a position opposite to the gate of the transfer transistor TRX in the p-well layer 32. The charge retention portion MEM is formed at a predetermined depth from the upper surface of the semiconductor substrate 30. The charge retention portion MEM includes a semiconductor region of n-type impurities formed in the p-well layer 32. A p-type semiconductor region 35 is formed between the upper surface of the semiconductor substrate 30 and the charge retention portion MEM.

[0059] The charge retention portion DM is formed at a position where all or part of the charge retention portion DM in the p-well layer 32 overlaps with the charge retention portion MEM in the planar layout. In other words, the sensor pixel 11 includes the charge retention portion DM at a position where all or part of the charge retention portion DM in the p-well layer 32 overlaps with the charge retention portion MEM in the planar layout. The p-type semiconductor region 35, the charge retention portion MEM, and the charge retention portion DM are sequentially arranged in the p-well layer 32 from the upper surface (or light receiving surface 10A) side of the semiconductor substrate 30. The charge retention portion DM includes a semiconductor region of n-type impurities formed in the p-well layer 32. The charge retention portion DM is formed to be non-conductive with the charge retention portion MEM. The n-type impurity (donor) concentration of each of the charge retention portion MEM and the charge retention portion DM is lower than the n-type impurity (donor) concentration of the floating diffusion FD.

[0060] The floating diffusion FD and the exhaust floating diffusion OFD are formed to surround the region including the photodiode PD, the p-type semiconductor region 35, and the charge holding portion DM. In other words, the sensor pixel 11 has the floating diffusion FD and the exhaust floating diffusion OFD surrounding the region including the photodiode PD, the p-type semiconductor region 35, and the charge holding portion DM. The floating diffusion FD and the exhaust floating diffusion OFD each include a semiconductor region formed in the p-well layer 32 and having an n-type high impurity concentration.

[0061] The transfer transistor DMG is formed near the floating diffusion portion FD. In other words, the sensor pixel 11 includes the transfer transistor DMG located near the floating diffusion portion FD. The transfer transistor DMG includes a vertical gate VG reaching the charge holding portion DM. For example, the vertical gate VG includes a metal material. The discharge transistor OFG is formed near the discharge floating diffusion portion OFD. In other words, the sensor pixel 11 includes the discharge transistor OFG located near the discharge floating diffusion portion OFD.

[0062] The sensor pixel 11 includes a light shielding layer 36 located on the semiconductor substrate 30. The light shielding layer 36 has an opening 36A at a position facing the photodiode PD. The light receiving surface 10A is exposed in the opening 36A. The light shielding layer 36 is arranged around the light receiving surface 10A and at least at a position facing the charge holding portion MEM. For example, the light shielding layer 36 contains a metal material.

[0063] [operate]

[0064] Next, the imaging operation of the solid-state imaging device 1 according to the present embodiment will be described.

[0065] The solid-state imaging device 1 (specifically, the system control circuit 24) performs an imaging operation under the global shutter scheme according to an imaging instruction from the operation section 250 described later. According to the global shutter scheme, the charge of the current frame is accumulated in the charge holding section MEM of each sensor pixel 11, and then the charge accumulated in the charge holding section MEM of each sensor pixel 11 is sequentially read. Figure 5 An example of a timing chart during an imaging operation of the solid-state imaging device 1 is shown.

[0066] First, before starting to capture images, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the discharge transistor OFG and discharges the excess charge remaining in the photodiode PD to the outside. Then, the solid-state imaging device 1 (specifically, the system control circuit 24) starts to capture images. Specifically, the solid-state imaging device 1 (specifically, the system control circuit 24) starts to accumulate charge when the transfer transistors TRX, TRG and DMG and the discharge transistor OFG are in the off state. When light enters the photodiode PD via the light receiving surface 10A, charge is generated at the photodiode PD by photoelectric conversion. The charge generated at the photodiode PD starts to accumulate in the photodiode PD.

[0067] Then, before transferring the charge accumulated in the photodiode PD to the charge retention portion MEM, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the transfer transistors TRG and DMG and the reset transistor RST to discharge the excess charge remaining in each of the charge retention portion MEM and the floating diffusion portion FD to the outside. Next, before the photoelectric conversion at the photodiode PD is completed, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the transfer transistor TRX and deepens the potential of the charge retention portion MEM, thereby transferring the charge accumulated in the photodiode PD to the charge retention portion MEM. At this time, the solid-state imaging device 1 (specifically, the system control circuit 24) performs this transfer operation on all sensor pixels 11 at the same time.

[0068] After the photoelectric conversion at the photodiode PD is completed, the solid-state imaging device 1 (specifically, the system control circuit 24) turns off the transfer transistor TRX and confines the charge generated by the current frame imaging in the charge holding portion MEM. Then, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the reset transistor RST and discharges the excess charge remaining in the floating diffusion portion FD to the outside again.

[0069] Next, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the transfer transistor DMG and discharges (transfers) the charge accumulated in the charge holding portion DM to the floating diffusion portion FD. At this time, the solid-state imaging device 1 (specifically, the system control circuit 24) keeps the selection transistor SEL turned on. Through this step, a noise signal at a signal level corresponding to the potential of the floating diffusion portion FD is generated at the amplifier transistor AMP, and the generated noise signal is output to the vertical signal line VSL via the selection transistor SEL. The noise signal is generated based on the noise charge having a correlation with the noise charge to be superimposed on the signal charge accumulated in the charge holding portion MEM. The solid-state imaging device 1 (specifically, the system control circuit 24) performs this reading operation for each predetermined pixel row unit.

[0070] Next, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the transfer transistor TRG, and discharges (transfers) the charge accumulated in the charge holding portion MEM to the floating diffusion portion FD. At this time, the solid-state imaging device 1 (specifically, the system control circuit 24) keeps the selection transistor SEL turned on. Through this step, a pixel signal at a signal level corresponding to the potential of the floating diffusion portion FD is generated at the amplifier transistor AMP, and the generated pixel signal is output to the vertical signal line VSL via the selection transistor SEL. The solid-state imaging device 1 (specifically, the system control circuit 24) performs this reading operation for each predetermined pixel row unit. In this way, the imaging operation of the solid-state imaging device 1 according to the present embodiment is performed.

[0071] It should be noted that, for example, Figure 6 As shown, the solid-state imaging device 1 (specifically, the system control circuit 24 ) may perform an operation of reading charges from the charge holding portion MEM before an operation of reading charges from the charge holding portion DM.

[0072] [Effect]

[0073] Next, the effects of the solid-state imaging device 1 according to the present embodiment will be described.

[0074] In a CMOS image sensor with a global shutter function, a charge accumulation section is provided in each pixel. Since the signal of the previous frame is retained in the charge accumulation section, it is necessary to provide a structure for shielding the charge accumulation section from light to prevent the signal of the next frame from entering the charge accumulation section. However, by simply providing such a structure, it is difficult to fully prevent light from leaking into the charge accumulation section. In view of this situation, for example, the methods described in the aforementioned patent documents 1 and 2 can be considered as a countermeasure to this problem.

[0075] In Patent Document 1, one of the pixels shared by two or more pixels is used as a PLS correction pixel. However, in this case, since the PLS correction pixel is buried in the pixel array, the resolution is greatly reduced.

[0076] In Patent Document 2, similar to the present embodiment, a charge accumulation portion for PLS correction is provided. However, in Patent Document 2, the charge accumulation portion for PLS correction is configured to be close to the floating diffusion portion. This makes it difficult to accurately eliminate the PLS component caused by oblique incidence. For example, in a case where a photodiode is formed adjacent to a charge accumulation portion for PLS correction and a floating diffusion portion, if light is obliquely incident on the photodiode from the side of the charge accumulation portion for PLS correction, more noise charges are accumulated in the floating diffusion portion than in the charge accumulation portion for PLS correction. Conversely, in a case where light is obliquely incident on the photodiode from the side of the floating diffusion portion, more noise charges are accumulated in the charge accumulation portion for PLS correction than in the floating diffusion portion. Therefore, the ratio between the noise charges accumulated in the floating diffusion portion and the noise charges accumulated in the charge accumulation portion for PLS correction varies depending on the direction of light incidence. Therefore, it is difficult to accurately remove the noise component from the pixel signal using the method described in Patent Document 2. In addition, in Patent Document 2, a switch element is provided between the floating diffusion and the amplifier transistor, and in addition, a switch element is provided between the charge accumulation section for PLS correction and the amplifier transistor. Therefore, when reading charge from the floating diffusion, it is necessary to keep the switch between the floating diffusion and the amplifier transistor turned on. As a result, the reading operation is performed in a state with low conversion efficiency.

[0077] In contrast, in the present embodiment, a charge retention unit MEM for retaining the charge transferred from the photodiode PD and a charge retention unit DM formed to be non-conductive with the charge retention unit MEM are provided. This makes it possible to reduce the PLS component contained in the signal charge based on the signal charge read from the charge retention unit MEM and the noise charge read from the charge retention unit DM. In addition, in the present embodiment, all or part of the charge retention unit DM is arranged at a position overlapping with the charge retention unit MEM in the planar layout. This enables more accurate estimation of the PLS component caused by oblique incidence compared to the case where the charge retention unit MEM and the charge retention unit DM are arranged in parallel with each other in the planar layout. In addition, in the present embodiment, the transfer transistor TRG is used to read the charge from the charge retention unit MEM, and the transfer transistor DMG is used to read the charge from the charge retention unit DM. As a result, a higher conversion efficiency is achieved compared to the case where the switch element is kept turned on when the charge is read from the charge retention unit MEM. Therefore, while suppressing the reduction in resolution and the reduction in conversion efficiency, the influence of oblique incident light leaking into the charge accumulation unit can be accurately eliminated.

[0078] In addition, in the present embodiment, the charge retention portion MEM, the charge retention portion DM, and the floating diffusion portion FD all include an impurity semiconductor region of a common conductivity type. In addition, the impurity concentration of the charge retention portion MEM and the charge retention portion DM is lower than the impurity concentration of the floating diffusion portion FD. This allows the charge retention portion MEM and the charge retention portion DM to have a potential difference with the floating diffusion portion FD, thereby enabling the charge to be completely discharged from the charge retention portion MEM and the charge retention portion DM, respectively.

[0079] In addition, in the present embodiment, the transfer transistor DMG includes a vertical gate VG reaching the charge holding portion DM. This enables reliable charge transfer from the charge holding portion DM.

[0080] In addition, in the present embodiment, the photodiode PD is arranged at a position adjacent to the charge holding portion MEM and the charge holding portion DM in the planar layout. In addition, in terms of the positional relationship with the photodiode PD, the light receiving surface 10A is formed at a position on the side of the transfer transistor DMG. In other words, the solid-state imaging device 1 according to the present embodiment is a top-irradiation type image sensor. Therefore, the present invention is also applicable to a top-irradiation type image sensor.

[0081] In addition, in the present embodiment, each sensor pixel 11 includes a light shielding layer 36 arranged around the light receiving surface 10A and at a position opposite to the charge holding portion DM. This makes it possible to suppress external light from directly entering the charge holding portion DM without passing through the light receiving surface 10A. As a result, it is possible to reduce the mixing of noise components into the charge to be read from the charge holding portion DM.

[0082] <2. Modifications>

[0083] Modifications of the solid-state imaging device 1 according to the above-described embodiment will be described below.

[0084] [Variation A]

[0085] In the above-described embodiment, the light receiving surface 10A may be provided on the back surface of the semiconductor substrate 30 . Figure 7 A modification example of the planar structure of the sensor pixel 11 is shown. Figure 8 Shown along Figure 7 An example of a cross-sectional structure along line AA. Figure 7 and Figure 8 are schematic and not necessarily drawn to scale. Figure 8In the figure, the density of the impurity concentration is represented by symbols including "P+", "N-", "N+", and "N++". Here, in the position represented as "P+", the value of the concentration of the p-type impurity (acceptor) is higher than the value in the range of 1×1016 cm-3 to 5×1018 cm-3. "N+" means that the concentration of the n-type impurity (donor) is higher than that of "N-". "N++" means that the concentration of the n-type impurity (donor) is higher than that of "N+". For example, in the position represented as "N-", the concentration of the n-type impurity (donor) has a value in the range of 1×1016 cm-3 to 5×1018 cm-3.

[0086] The sensor pixel 11 is formed on a semiconductor substrate 30. For example, the semiconductor substrate 30 is a silicon substrate. The semiconductor substrate 30 includes a p-well layer 32 located on the upper surface of the semiconductor substrate 30 and in the vicinity thereof, and includes an n-type semiconductor layer 31 located at a position deeper than the p-well layer 32. The p-well layer 32 is a p-type semiconductor region formed at and around the upper surface of the semiconductor substrate 30. In the p-well layer 32, a photodiode PD is formed. The photodiode PD includes, for example, an n-type semiconductor region formed in the p-well layer 32. The photodiode PD is arranged at a position where a part of the photodiode PD overlaps with the charge retention portion MEM and the charge retention portion DM in a planar layout. The area opposite to the photodiode PD on the back side of the semiconductor substrate 30 is a light receiving surface 10A. In terms of the positional relationship with the photodiode PD, the light receiving surface 10A is formed at a position on the opposite side of the transfer transistor TRX.

[0087] The charge retention portion MEM is formed at a position opposite to the gate of the transfer transistor TRX in the p-well layer 32. The charge retention portion MEM is formed at a predetermined depth from the upper surface of the semiconductor substrate 30. The charge retention portion MEM includes a semiconductor region of n-type impurities formed in the p-well layer 32. A p-type semiconductor region 35 is formed between the upper surface of the semiconductor substrate 30 and the charge retention portion MEM.

[0088] The charge retention portion DM is formed at a position where all or part of the charge retention portion DM in the p-well layer 32 overlaps with the charge retention portion MEM in the planar layout. In other words, the sensor pixel 11 includes the charge retention portion DM at a position where all or part of the charge retention portion DM in the p-well layer 32 overlaps with the charge retention portion MEM in the planar layout. In addition, the photodiode PD is arranged at a position where a part of the photodiode PD overlaps with the charge retention portion MEM and the charge retention portion DM in the planar layout. Therefore, the photodiode PD, the charge retention portion DM, the charge retention portion MEM, and the p-type semiconductor region 35 are arranged in the p-well layer 32 in order from the back side (light receiving surface 10A) of the semiconductor substrate. The charge retention portion DM includes a semiconductor region of n-type impurities formed in the p-well layer 32. The charge retention portion DM is formed to be non-conductive with the charge retention portion MEM. The n-type impurity (donor) concentration of each of the charge retention portion MEM and the charge retention portion DM is lower than the n-type impurity (donor) concentration of the floating diffusion FD.

[0089] The floating diffusion FD and the exhaust floating diffusion OFD are formed to surround the region including the photodiode PD, the charge retention portion DM, the charge retention portion MEM, and the p-type semiconductor region 35. In other words, the sensor pixel 11 has the floating diffusion FD and the exhaust floating diffusion OFD surrounding the region including the photodiode PD, the charge retention portion DM, the charge retention portion MEM, and the p-type semiconductor region 35. The floating diffusion FD and the exhaust floating diffusion OFD each include a semiconductor region formed in the p-well layer 32 and having an n-type high impurity concentration.

[0090] The transfer transistor DMG is formed near the floating diffusion portion FD. In other words, the sensor pixel 11 includes the transfer transistor DMG located near the floating diffusion portion FD. The transfer transistor DMG includes a vertical gate VG1 reaching the charge holding portion DM. For example, the vertical gate VG1 includes a metal material.

[0091] The drain transistor OFG is formed near the drain floating diffusion OFD. In other words, the sensor pixel 11 includes the drain transistor OFG located near the drain floating diffusion OFD. The drain transistor OFG includes a vertical gate VG2 reaching the photodiode PD. For example, the vertical gate VG2 includes a metal material.

[0092] The sensor pixel 11 includes a transfer transistor TRX located at a position opposite to the charge holding portion MEM. The transfer transistor TRX includes a vertical gate VG3 reaching the photodiode PD. For example, the vertical gate VG3 includes a metal material.

[0093] The sensor pixel 11 includes a light shielding layer 37 on the semiconductor substrate 30. The light shielding layer 37 is disposed at a position at least opposite to the charge retention portion MEM. For example, the light shielding layer 37 includes a metal material. The sensor pixel 11 also includes a light shielding layer 38 between the photodiode PD and the charge retention portion DM. For example, the light shielding layer 38 is disposed at a position opposite to the charge retention portion MEM and the charge retention portion DM. For example, the light shielding layers 37 and 38 include a metal material. It should be noted that, for example, Fig. 9 As shown, the light shielding layer 38 can be omitted as needed.

[0094] In this modification, as in the aforementioned embodiment, a charge retention unit MEM that retains the charge transferred from the photodiode PD, and a charge retention unit DM that is formed to be non-conductive with the charge retention unit MEM are provided. This makes it possible to reduce the PLS component contained in the signal charge based on the signal charge read from the charge retention unit MEM and the noise charge read from the charge retention unit DM. In addition, in this modification, all or part of the charge retention unit DM is arranged at a position overlapping with the charge retention unit MEM in the planar layout. Compared with the case where the charge retention unit MEM and the charge retention unit DM are arranged in parallel with each other in the planar layout, this can more accurately estimate the PLS component caused by oblique incidence. In addition, in this embodiment, the transfer transistor TRG is used to read the charge from the charge retention unit MEM, and the transfer transistor DMG is used to read the charge from the charge retention unit DM. As a result, a higher conversion efficiency is achieved compared with the case where the switch element is kept turned on during the charge reading from the charge retention unit MEM. Therefore, while suppressing the reduction in resolution and the reduction in conversion efficiency, the influence of oblique incident light leaking into the charge accumulation unit can be accurately eliminated.

[0095] In addition, in the present modification, the transfer transistor DMG includes a vertical gate VG1 reaching the charge holding portion DM. This enables reliable charge transfer from the charge holding portion DM.

[0096] In addition, in this modification, the photodiode PD is arranged at a position where a part of the photodiode PD overlaps with the charge retention unit MEM and the charge retention unit DM in the planar layout. In addition, in terms of the positional relationship with the photodiode PD, the light receiving surface 10A is formed at a position on the opposite side of the transfer transistor DMG. In other words, the solid-state imaging device 1 according to this modification is a back-illuminated image sensor. Therefore, the present invention is also applicable to a back-illuminated image sensor.

[0097] In addition, in the present modification, each sensor pixel 11 includes a light shielding layer 38 between the photodiode PD and the charge holding portion DM. This makes it possible to suppress external light from directly entering the charge holding portion DM without passing through the light receiving surface 10A. As a result, it is possible to reduce the mixing of noise components into the charge to be read from the charge holding portion DM.

[0098] [Variation Example B]

[0099] In the aforementioned embodiments, for example, Fig.10 As shown, the vertical gate VG may be omitted. In this case, instead of the vertical gate VG, an n-type semiconductor region 39 reaching the charge retention portion DM and having an impurity concentration higher than that of the charge retention portion DM is formed in the p-well layer 32. In other words, in this modification, each sensor pixel 11 includes an n-type semiconductor region 39 reaching the charge retention portion DM and having an impurity concentration higher than that of the charge retention portion DM. Even in this case, charge transfer can be reliably performed from the charge retention portion DM.

[0100] <3. Application examples>

[0101] The present invention is not limited to application to solid-state imaging devices. More specifically, the present technology is applicable not only to solid-state imaging devices but also to any electronic device including a solid-state imaging device, such as a camera module including an optical lens system, an imaging unit such as a digital camera or a video camera, a mobile terminal unit having an imaging function (e.g., a smartphone or a tablet terminal), or a copier using a solid-state imaging device in an image reading unit.

[0102] Fig.11 : is a block diagram showing a configuration example of an electronic device 2 including the solid-state imaging device 1 according to any of the foregoing embodiments and their modified examples.

[0103] The electronic device 2 is, for example, any electronic device including an imaging unit such as a digital camera or a video camera and a mobile terminal unit such as a smartphone or a tablet terminal. The electronic device 2 includes, for example, a solid-state imaging device 1 according to any of the aforementioned embodiments and their modified examples, a DSP circuit 210, a frame memory 220, a display unit 230, a storage unit 240, an operation unit 250, and a power supply unit 260. The DSP circuit 210 corresponds to a specific example of the “signal processing circuit” of the present invention. In the electronic device 2, the DSP circuit 210, the frame memory 220, the display unit 230, the storage unit 240, the operation unit 250, and the power supply unit 260 are connected to each other via a bus 270.

[0104] The solid-state imaging device 1 according to any one of the aforementioned embodiments and their modified examples outputs image data corresponding to incident light. The DSP circuit 210 is a signal processing circuit that processes a signal (image data) output from the solid-state imaging device 1 according to any one of the aforementioned embodiments and their modified examples. The frame memory 220 temporarily holds the image data processed by the DSP circuit 210 in units of frames. The display section 230 includes, for example, a panel-type display such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state imaging device 1 according to any one of the aforementioned embodiments and their modified examples. The storage section 240 stores image data of a moving image or a still image captured by the solid-state imaging device 1 according to any one of the aforementioned embodiments and their modified examples in a storage medium such as a semiconductor memory or a hard disk. The storage section 240 also stores a correction coefficient α described later in a storage medium such as a semiconductor memory or a hard disk. The operation section 250 outputs operation instructions for various functions of the electronic device 2 according to the user's operation. The power supply section 260 appropriately supplies various types of power used as operation power for the DSP circuit 210 , the frame memory 220 , the display section 230 , the storage section 240 , and the operation section 250 to these power supply objects.

[0105] Next, the imaging procedure of the electronic device 2 will be described.

[0106] Fig.12 An example of a flowchart of an imaging operation of the electronic device 2 is shown. The user operates the operation unit 250 to instruct the start of imaging (step S101). The operation unit 250 then sends an imaging instruction to the solid-state imaging device 1 (step S102). After receiving the imaging instruction, the solid-state imaging device 1 (specifically, the system control circuit 24) performs imaging under the global shutter operation (step S103).

[0107] The solid-state imaging device 1 outputs image data I1 and noise image data I2 obtained by imaging to the DSP circuit 210. Here, the image data I1 is data of pixel signals for all pixels, and the pixel signals are generated based on the charges accumulated in the charge holding portion MEM. The noise image data I2 is data of noise signals for all pixels, and the noise signals are generated based on the charges accumulated in the charge holding portion DM.

[0108] The DSP circuit 210 performs a predetermined noise reduction process based on the image data I1 and the noise image data I2 input from the solid-state imaging device 1 (step S104). The DSP circuit 210 performs the above-mentioned noise reduction process using the correction coefficient α stored in the storage unit 240. The DSP circuit 210 causes the frame memory 220 to hold the image data Ic obtained by the noise reduction process, and the frame memory 220 causes the storage unit 240 to store the image data Ic (step S105). In this way, imaging is performed by the electronic device 2.

[0109] Fig.13 and Fig.14 Examples of correction coefficients for respective pixels used in the above-described noise reduction processing are shown respectively.

[0110] For example, Fig.13 As shown, in the case where the two or more sensor pixels 11 include two or more sensor pixels 11R for red light, two or more sensor pixels 11G for green light, and two or more sensor pixels 11B for blue light, a correction coefficient α for red light can be set for each color of the sensor pixels 11. It should be noted that Fig.13 As an example, a case is shown where the correction coefficient αR is set for the sensor pixel 11R for red light, the correction coefficient αG is set for the sensor pixel 11G for green light, and the correction coefficient αB is set for the sensor pixel 11B for blue light. Fig.13 The state in which one color sensor pixel is constituted by one sensor pixel 11R, two sensor pixels 11G, and one sensor pixel 11B is schematically shown. The correction coefficient αR, the correction coefficient αG, and the correction coefficient αB are, for example, values ​​corresponding to the wavelength, and are different values ​​from each other.

[0111] In addition, for example, Fig.14 As shown, the correction coefficient α can be set corresponding to the position in the pixel array unit 10. It should be noted that Fig.14As an example, the case is shown in which the correction coefficient αa is set for the center portion of the pixel array section 10, the correction coefficient αb is set for the center upper portion of the pixel array section 10, the correction coefficient αc is set for the center lower portion of the pixel array section 10, the correction coefficient αd is set for the center left portion of the pixel array section 10, the correction coefficient αe is set for the upper left portion of the pixel array section 10, the correction coefficient αf is set for the lower left portion of the pixel array section 10, the correction coefficient αg is set for the center right portion of the pixel array section 10, the correction coefficient αh is set for the upper right portion of the pixel array section 10, and the correction coefficient αi is set for the lower right portion of the pixel array section 10. The correction coefficient αa, the correction coefficient αb, the correction coefficient αc, the correction coefficient αd, the correction coefficient αe, the correction coefficient αf, the correction coefficient αg, the correction coefficient αh, and the correction coefficient αi are, for example, values ​​corresponding to positions in the pixel array section 10, and are different values ​​from each other.

[0112] The DSP circuit 210 performs a predetermined noise reduction process based on the image data I1 and the noise image data I2 input from the solid-state imaging device 1, thereby obtaining the image data Ic with reduced PLS noise. The DSP circuit 210 subtracts, for example, image data (αI2) obtained by multiplying the noise image data I2 by a predetermined correction coefficient α from the image data I1, thereby reducing the noise included in the image data I1. For example, the DSP circuit 210 obtains the image data Ic according to the following equation (1).

[0113] Ic = I1 −αI2 (1)

[0114] In the electronic device 2, the solid-state imaging device 1 according to any of the aforementioned embodiments and their modified examples is used, and the above-mentioned noise reduction processing is performed at the DSP circuit 210. This makes it possible to accurately eliminate the influence of oblique incident light leaking into the charge accumulation portion while suppressing a reduction in resolution and a reduction in conversion efficiency.

[0115] <4. Application examples>

[0116] The technology according to the present invention (the present invention) can be applied to various products. For example, the technology according to the embodiments of the present invention can be implemented as a device installed on any type of mobile body such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, or a robot.

[0117] Fig.15 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present invention can be applied.

[0118] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.15In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F: interface) 12053 are shown.

[0119] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various types of programs. For example, the drive system control unit 12010 functions as a control device for the following devices: a drive force generating device for generating a vehicle drive force such as an internal combustion engine, a drive motor, etc., a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a vehicle braking force.

[0120] The body system control unit 12020 controls the operation of various types of devices provided on the body according to various types of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as headlights, reverse lights, brake lights, turn signals, fog lights, etc. In this case, radio waves transmitted from a mobile device as a substitute key or signals of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, power window device, and lights of the vehicle, etc.

[0121] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected with a camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection processing such as a person, a vehicle, an obstacle, a sign, characters on the road surface, etc., or distance measurement processing from these objects.

[0122] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about distance measurement. In addition, the light received by the imaging unit 12031 may be visible light or may be invisible light such as infrared rays.

[0123] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 for detecting the driver's state. The driver state detection unit 12041 includes, for example, a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0124] The microcomputer 12051 calculates a control target value for a driving force generating device, a steering mechanism, or a braking device based on information about the inside and outside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, and outputs a control command to the drive system control unit 12010. For example, the microcomputer 12051 may perform cooperative control aimed at realizing functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation of the vehicle, following driving based on a following distance, speed maintenance driving, vehicle collision warning, or vehicle lane departure warning, etc.

[0125] In addition, based on the information about the inside and outside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, the microcomputer 12051 can perform collaborative control such as automatic driving aimed at enabling the vehicle to drive autonomously without relying on the driver's operation by controlling the driving force generating device, steering mechanism or braking device, etc.

[0126] Furthermore, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 may output a control command to the body system control unit 12020. For example, the microcomputer 12051 may control the headlights to switch from high beam to low beam according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, thereby performing cooperative control aimed at preventing glare.

[0127] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle passengers or the outside of the vehicle of information. Fig.15 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display or a head-up display.

[0128] Fig.16 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0129] exist Fig.16 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0130] The camera unit 12031 includes cameras 12101, 12102, 12103, 12104 and 12105, which are arranged at the front nose, side mirrors, rear bumper and rear door of the vehicle 12100 and the upper position of the windshield in the vehicle. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle mainly obtain the front image of the vehicle 12100. The camera unit 12102 and the camera unit 12103 arranged at the side mirror mainly obtain the side image of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or rear door mainly obtains the rear image of the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle is mainly used to detect the preceding vehicle, pedestrians, obstacles, signal lights, traffic signs or lanes, etc.

[0131] By the way, Fig.16 An example of the photographing range of the camera units 12101 to 12104 is shown. The photographing range 12111 represents the photographing range of the camera unit 12101 provided at the front nose. The photographing ranges 12112 and 12113 respectively represent the photographing ranges of the camera units 12102 and 12103 provided at the side mirrors. The photographing range 12114 represents the photographing range of the camera unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 observed from above is obtained by superimposing the image data photographed by the camera units 12101 to 12104.

[0132] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements or may be an imaging element having pixels for phase difference detection.

[0133] For example, based on the distance information acquired from the imaging units 12101 to 12104, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal variation of the distance (relative speed to the vehicle 12100), and thereby specifically extract the following three-dimensional object as the preceding vehicle: the closest three-dimensional object that is located on the driving path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the front following distance to be maintained with the preceding vehicle and perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform cooperative control of automatic driving that aims to make the vehicle travel automatically without relying on the operation of the driver.

[0134] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12501 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually identify and obstacles that the driver of the vehicle 12100 is difficult to visually identify. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the drive system control unit 12010. The microcomputer 12051 can thus assist driving to avoid collisions.

[0135] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the camera units 12101 to 12104. For example, such identification of a pedestrian may be performed by the following steps: a step of extracting feature points in the captured images of the camera units 12101 to 12104 as infrared cameras; and a step of determining whether the object is a pedestrian by pattern matching a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 in such a manner that an emphasis rectangular contour line is superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 in such a manner that an icon representing a pedestrian or the like is displayed at a desired position.

[0136] An example of a mobile body control system to which the technology of the present invention can be applied has been described above. The technology according to the present invention can be applied to the imaging unit 12031 in the above-mentioned configuration. Specifically, the solid-state imaging device 1 according to any one of the aforementioned embodiments and their modified examples can be applied to the imaging unit 12031. Applying the technology according to the present invention to the imaging unit 12031 enables obtaining a high-definition captured image with less noise. Therefore, it is possible to perform high-precision control using the captured image in the mobile body control system.

[0137] The present invention has been described above with reference to the embodiments, variations, applicable examples and application examples of the present invention. However, the present invention is not limited to the above-mentioned embodiments, etc., and various variations are possible. It should be noted that the effects described herein are merely examples. The effects of the present invention are not limited to the effects described herein. The present invention may have any effects other than the effects described herein.

[0138] Furthermore, the present invention may also have the following configurations.

[0139] (1) A solid-state imaging device comprising:

[0140] light-receiving surface;

[0141] Two or more pixels are opposite to the light receiving surface, wherein:

[0142] Each of the pixels comprises:

[0143] a photoelectric conversion unit that performs photoelectric conversion on the light incident through the light receiving surface,

[0144] a first charge holding portion that holds the charge transferred from the photoelectric conversion portion,

[0145] a second charge holding portion, which is arranged at a position where all or a part of the second charge holding portion overlaps with the first charge holding portion in a planar layout and is formed to be non-conductive with the first charge holding portion,

[0146] a first transfer transistor that transfers the charge held by the first charge holding portion to a floating diffusion portion, and

[0147] A second transfer transistor transfers the charge held by the second charge holding portion to the floating diffusion portion.

[0148] (2) The solid-state imaging device according to (1), wherein:

[0149] The first charge holding portion, the second charge holding portion, and the floating diffusion each include an impurity semiconductor region of a common conductivity type, and

[0150] The impurity concentration of each of the first charge holding portion and the second charge holding portion is lower than the impurity concentration of the floating diffusion portion.

[0151] (3) The solid-state imaging device according to (2), wherein the second transfer transistor includes a vertical gate that reaches the second charge holding portion.

[0152] (4) The solid-state imaging device according to (2), wherein the second transfer transistor is electrically connected to the second charge holding portion through an impurity semiconductor region reaching the second charge holding portion and having an impurity concentration higher than the impurity concentration of the second charge holding portion.

[0153] (5) The solid-state imaging device according to any one of (1) to (4), wherein:

[0154] Each of the pixels further includes a third transfer transistor that transfers the charge accumulated in the photoelectric conversion portion to the first charge holding portion,

[0155] The photoelectric conversion portion is arranged at a position adjacent to the first charge holding portion and the second charge holding portion in the planar layout, and

[0156] The light receiving surface is formed at a position on the third transfer transistor side in terms of positional relationship with the photoelectric conversion portion.

[0157] (6) The solid-state imaging device according to (5), wherein each of the pixels includes a light shielding layer disposed around the light receiving surface at least at a position opposing the first charge holding portion.

[0158] (7) The solid-state imaging device according to any one of (1) to (4), wherein:

[0159] Each of the pixels further includes a third transfer transistor that transfers the charge accumulated in the photoelectric conversion portion to the first charge holding portion,

[0160] The photoelectric conversion unit is arranged at a position where a part of the photoelectric conversion unit overlaps with the first charge holding unit and the second charge holding unit in the planar layout, and

[0161] The light receiving surface is formed at a position on the opposite side of the third transfer transistor in terms of positional relationship with the photoelectric conversion unit.

[0162] (8) The solid-state imaging device according to (7), wherein each of the pixels includes a light shielding layer between the photoelectric conversion portion and the second charge holding portion.

[0163] (9) An electronic device comprising:

[0164] a solid-state imaging device that outputs image data corresponding to incident light; and

[0165] a signal processing circuit that processes the image data,

[0166] The solid-state imaging device comprises:

[0167] light-receiving surface;

[0168] Two or more pixels are opposite to the light receiving surface, wherein:

[0169] Each of the pixels comprises:

[0170] a photoelectric conversion unit that performs photoelectric conversion on the light incident through the light receiving surface,

[0171] a first charge holding portion that holds the charge transferred from the photoelectric conversion portion,

[0172] a second charge holding portion, which is arranged at a position where all or a part of the second charge holding portion overlaps with the first charge holding portion in a planar layout and is formed to be non-conductive with the first charge holding portion,

[0173] a first transfer transistor that transfers the charge held by the first charge holding portion to a floating diffusion portion, and

[0174] a second transfer transistor that transfers the charge held by the second charge holding portion to the floating diffusion portion, and

[0175] The signal processing circuit reduces noise included in the first image data based on first image data generated based on the charge held by the first charge holding portion and second image data generated based on the charge held by the second charge holding portion.

[0176] (10) The electronic device according to (9), wherein the signal processing circuit reduces noise included in the first image data by subtracting third image data from the first image data, the third image data being obtained by multiplying the second image data by a predetermined correction coefficient.

[0177] According to the solid-state imaging device and the electronic device of each embodiment of the present invention, there is provided: a first charge holding portion, which holds the charge transferred from the photoelectric conversion portion, and a second charge holding portion, which is formed to be non-conductive with the first charge holding portion. All or part of the second charge holding portion is arranged at a position overlapping with the first charge holding portion in the planar layout. The first transfer transistor is used to read the charge from the first charge holding portion, and the second transfer transistor is used to read the charge from the second charge holding portion. Therefore, it is possible to accurately eliminate the influence of oblique incident light leaking into the charge accumulation portion while suppressing the reduction in resolution and the reduction in conversion efficiency.

[0178] This application claims priority based on Japanese Patent Application No. 2018-175983 filed with the Japan Patent Office on September 20, 2018, the entire contents of which are incorporated herein by reference.

[0179] It should be understood that various modifications, combinations, sub-combinations and substitutions may occur to those skilled in the art according to design requirements and other factors, and they are within the scope of the appended claims or the equivalents thereof.

Claims

1. An imaging element, comprising: Photodiode; a transfer transistor connected to the photodiode; a first transistor, wherein an output of the pass transistor is connected to an input of the first transistor; a second transistor, wherein the output of the first transistor is connected to the input of the second transistor, Wherein, in a plan view, the gate of the first transistor and the gate of the second transistor are arranged along a first direction, Wherein, in the plan view, the gate of the reset transistor, the gate of the amplification transistor and the gate of the selection transistor are arranged along the second direction, and, The first direction and the second direction are perpendicular.

2. The imaging device according to claim 1, further comprising: A third transistor is electrically connected to the power supply line and the photodiode.

3. The imaging element according to claim 1, wherein: The second transistor is electrically connected to the first charge holding portion.

4. The imaging element according to claim 1, wherein: In the plan view, the gate of the first transistor and the gate of the second transistor are arranged along one side of the photodiode, and the gate of the reset transistor, the gate of the amplification transistor and the gate of the selection transistor are arranged along the other side of the photodiode perpendicular to the one side.

5. The imaging element according to claim 1, wherein: In the plan view, a portion of the photodiode overlaps with the gate of the transfer transistor.

6. The imaging element according to claim 3, wherein: In the plan view, a portion of the photodiode overlaps with the first charge holding portion.

7. The imaging device according to claim 3, further comprising: A second charge holding unit holds the charge transferred from the photodiode, wherein In the plan view, a portion of the first charge holding portion overlaps with the second charge holding portion.

8. The imaging element according to claim 1, wherein: The gate of the amplifying transistor is connected to the drain of the first transistor.

9. The imaging element according to claim 2, wherein: In the plan view, an extension direction of the gate of the third transistor is parallel to the second direction.

10. The imaging element according to claim 2, wherein: In the plan view, the gate of the amplifying transistor and the gate of the third transistor are arranged along the first direction.

11. The imaging element according to claim 1, wherein: The gate of the amplifying transistor is electrically connected to the first transistor.

12. The imaging element according to claim 1, wherein: In the plan view, a gate of the transfer transistor has a size larger than a gate of the first transistor or a gate of the second transistor.

13. The imaging element according to claim 1, wherein: In the plan view, the gate of the transfer transistor has a size larger than a size of a gate of the amplification transistor, a gate of the selection transistor, or a gate of the reset transistor.

14. An electronic device, comprising: The imaging element according to any one of claims 1 to 13; as well as The signal processing circuit processes the signal output by the imaging element.

Images