Electroplated electrode-based HJT battery piece and preparation method thereof

Abstract

The invention discloses an electroplating electrode-based HJT battery piece and a preparation method thereof. The preparation method comprises the following steps of providing an N-type monocrystalline silicon piece; performing double-sided cleaning and texturing on the N-type silicon wafer; depositing intrinsic amorphous silicon layers on the front surface and the back surface of the N-type silicon wafer respectively; amorphous silicon film layers with different conduction types are formed on the surface of the intrinsic amorphous silicon layer; respectively forming transparent conductive films on the surface of the amorphous silicon film layer, leaving an edge between at least one transparent conductive film and the edge of the amorphous silicon film layer, and exposing the amorphous silicon film layer in an edge leaving area; oxidizing the exposed amorphous silicon film layer to form a silicon dioxide layer; respectively depositing seed layers on the surfaces of the transparent conductive films; forming a copper grid line electrode on the seed layer; and etching the seed layer which is not covered by the copper grid line electrode to obtain the HJT battery piece based on the electroplated electrode. The method has the beneficial effects that the doped amorphous silicon layer can be prevented from being in contact with alkali liquor to be corroded, and the battery efficiency is remarkably improved.

Description

Technical Field

[0001] The present application belongs to the technical field of solar cells, and in particular, relates to an HJT cell based on electroplating electrodes and a preparation method thereof. Background Art

[0002] The new energy industry represented by solar power generation is developing rapidly and is moving forward at a foreseeable faster speed. How to further improve the efficiency of solar cells and reduce the production cost of solar cells has become an important issue in the industry. Solar cells have developed from the earliest aluminum back field cells to PERC cells and then to the current mainstream TOPCON / HIT cells. The cell efficiency has increased from about 16% to the current cell efficiency of nearly 26%. Electroplating copper technology uses the principle of electrolysis to deposit copper on the surface of the conductive layer to achieve "silver removal". It is an important technical route for HJT cells to reduce costs and increase efficiency. HJT (Heterojunction with Intrinsic Thin layer) solar cells, referred to as HJT cells, are solar cells with amorphous silicon / crystalline silicon heterojunctions. They are hybrid solar cells made of crystalline silicon substrates, amorphous silicon thin films, TCO thin films and metal grid lines. The advantage of HJT cells combined with electroplating copper technology is that electroplating copper technology uses low-cost metal copper to replace expensive metal silver, while achieving double-sided metalization, further reducing the cost of heterojunction cells. Compared with the traditional HJT screen printing process, the cost is greatly reduced. For example, a Chinese patent for a HJT battery and its preparation method (application number 202111399527.2), the HJT battery of this patent is prepared by setting a silver nanowire layer on the TCO conductive layer. The setting method is to apply the silver nanowire silver paste on the surface of the EVA or POE substrate, and then hot-melt it on the surface of the TCO conductive layer to prepare the silver nanowire layer. Another example is a Chinese patent for a HJT battery structure (application number 202321340323.6). In this application, the second metal electrode is prepared on the surface of the transparent conductive film by screen printing or electroplating. Although the above method improves the conductivity of the TCO conductive layer, the electron collection rate and the conductivity of the entire path, the application uses silver nanowires on the one hand, which are expensive and have high production costs; secondly, compared with the original silver grid wire, the pure copper grid wire ensures high conductivity, and the low line width also reduces power loss. However, there is a problem in the above-mentioned manufacturing process if electroplating is used: there is a doped amorphous silicon layer with a width of about 0.75 mm at the edge of the battery that is not covered by the TCO film and the copper seed layer. The mask material used in the electroplating process must be removed with an alkaline solution, which directly leads to the doped amorphous silicon layer with a width of about 0.75 mm at the edge of the battery being inevitably corroded by the alkaline solution. The doped amorphous silicon layer is corroded by contact with the alkali, thereby reducing the efficiency of the manufactured battery. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a HJT cell based on electroplating electrodes and a preparation method thereof, so as to solve the problem of low cell efficiency caused by corrosion of the doped amorphous silicon layer at the edge of the cell.

[0004] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for preparing a HJT cell based on electroplating electrodes, which is characterized by comprising the following steps: Providing an N-type single crystal silicon wafer; Double-sided cleaning and texturing of N-type silicon wafers are performed to form undulating texturing surfaces on both sides of the N-type silicon wafers; Depositing intrinsic amorphous silicon layers on the front and back of an N-type silicon wafer; Forming amorphous silicon film layers with different conductivity types on the surfaces of the intrinsic amorphous silicon layers on the front and back sides of the N-type silicon wafer; Transparent conductive films are formed on the surfaces of the amorphous silicon film layers on the front and back sides of the N-type silicon wafer, and margins are left between at least one transparent conductive film and the edge of the amorphous silicon film layer connected thereto to expose the amorphous silicon film layer in the margin area; Oxidizing the exposed amorphous silicon film layer to form a silicon dioxide layer; Depositing seed layers on the surfaces of the transparent conductive films on the front and back sides of the N-type silicon wafer respectively; forming a copper gate electrode on the seed layer; The seed layer not covered by the copper grid electrode is etched to obtain a HJT cell based on electroplating electrodes.

[0005] As a preferred embodiment of the present application, the step of forming an electroplated copper gate electrode on the seed layer includes: forming a patterned mask layer on the seed layer to expose the seed layer in the patterned area; Electroplating the surface of the seed layer in the pattern area to form a patterned electroplated copper grid electrode; The mask layer is removed to expose the seed layer not covered by the electroplated copper gate electrode.

[0006] As a preferred embodiment of the present application, the step of removing the mask layer includes: removing the mask layer on the surface of the seed layer using an alkaline solution at a stripping temperature of 10 to 40°C; the mass concentration of KOH in the alkaline solution is 10 to 50 g / L, the volume concentration of diethylene glycol monobutyl ether (BDG for short) is 50 to 200 mL / L, and the solvent in the alkaline solution is water.

[0007] As a preferred embodiment of the present application, the step of removing the mask layer includes: the alkaline solution also includes hydrogen peroxide, and the volume concentration of the hydrogen peroxide is 10~200mL / L.

[0008] As a preference of the present application, the mass concentration of KOH in the alkali solution is 25 g / L, the volume concentration of BDG is 100 mL / L, and the volume concentration of hydrogen peroxide is 144 mL / L.

[0009] As a preference of the present application, the peeling temperature is 13°C.

[0010] As a preferred embodiment of the present application, after forming the electroplated copper gate line electrode on the seed layer, the silicon dioxide layer is chemically etched.

[0011] As a preferred embodiment of the present application, before etching the seed layer by chemical etching, the silicon dioxide layer in the margin area is etched.

[0012] As a preferred embodiment of the present application, the seed layer is etched by a chemical etching method.

[0013] When transparent conductive films are formed on the surfaces of the amorphous silicon film layers on the front and back sides of the N-type silicon wafer, margins are left between the transparent conductive film and the edge of the amorphous silicon film layer on the back side of the N-type silicon wafer.

[0014] The specific edge retention methods are as follows: When transparent conductive films are formed on the surfaces of the amorphous silicon film layers on the front and back sides of the N-type silicon wafer, the target material is placed underneath and the N-type silicon wafer is placed on a hollow carrier for deposition. The carrier is shielded to leave a margin, so that a circle of exposed amorphous silicon layer is formed around the intrinsic amorphous silicon on the back side of the N-type silicon wafer.

[0015] As a preferred embodiment of the present application, the width of the margin area is 0.5~1mm.

[0016] As a preferred embodiment of the present application, the width of the margin area is 0.75 mm.

[0017] The present invention also provides an HJT cell manufactured based on the HJT cell manufacturing method based on electroplating electrodes.

[0018] As a preferred embodiment of the present application, the HJT cell comprises: N-type monocrystalline silicon wafer; Amorphous silicon intrinsic layers formed on the front and back sides of an N-type single crystal silicon wafer; Amorphous silicon film layers are formed on the amorphous silicon intrinsic layers on the front and back sides of the N-type single crystal silicon wafer respectively; A transparent conductive film is formed on the surface of the amorphous silicon film layer, and a margin area arranged along the circumference of the amorphous silicon film layer is provided between at least one transparent conductive film and the edge of the amorphous silicon film layer connected thereto; A seed layer formed on the surface of the transparent conductive film on the front and back sides of the N-type single crystal silicon wafer; and Copper gate line electrodes are respectively formed on the seed layer.

[0019] As a preferred embodiment of the present application, the types of amorphous silicon film layers on the amorphous silicon intrinsic layers on the front and back sides of the N-type single crystal silicon wafer are different.

[0020] As a preferred embodiment of the present application, the amorphous silicon film layer on the amorphous silicon intrinsic layer on the front side of the N-type single crystal silicon wafer is an N-type doped amorphous silicon film layer, and the amorphous silicon film layer on the amorphous silicon intrinsic layer on the back side of the N-type single crystal silicon wafer is a P-type doped amorphous silicon film layer.

[0021] Alternatively, the amorphous silicon film layer on the amorphous silicon intrinsic layer on the front side of the N-type single crystal silicon wafer is a P-type doped amorphous silicon film layer, and the amorphous silicon film layer on the amorphous silicon intrinsic layer on the back side of the N-type single crystal silicon wafer is an N-type doped amorphous silicon film layer.

[0022] Compared with the prior art, the beneficial effects of this application are: (1) In the present application, when preparing a transparent conductive film on an amorphous silicon layer, a 0.75 mm edge is reserved for hydrogen peroxide or ozone oxidation of the amorphous silicon to form a silicon dioxide layer that is not easily reactive with alkaline solution. The purpose of this step is to prevent the alkali in the solution from damaging the amorphous silicon layer when removing the mask layer, and to prevent the doped amorphous silicon from being corroded by contact with the alkali, thereby significantly improving the battery efficiency. (2) The process of removing the mask layer is optimized, from the original 55~65℃ to 10~40℃. Under low temperature conditions, the alkaline solution composed of alkali and BDG hydrogen peroxide reduces the reaction rate while further inhibiting the reaction between the alkali and amorphous silicon and silicon dioxide through the oxidation effect of hydrogen peroxide, so that the effective contact time between amorphous silicon and the alkaline solution is only tens of seconds, which greatly reduces the reaction rate and can protect the oxidized amorphous silicon layer at the edge of the battery cell from being etched, that is, slowing down the reaction rate again; when the traditional process is used, that is, the amorphous silicon layer is not oxidized, in the traditional alkaline solution, the minority carrier lifetime of the middle silicon wafer is almost annihilated, only 60~70μs, and the passivation effect is almost completely lost; while the method of the present application is used to first oxidize the amorphous silicon layer After that, the minority carrier lifetime in the traditional alkaline solution is significantly improved and can reach 684μs; further, the process involved in removing the mask layer is improved (such as the composition of the alkaline solution, the stripping temperature, etc.), the amorphous silicon layer is first oxidized, and then the oxidized battery cell is placed in the improved alkaline solution (the alkaline solution is made of alkali and BDG hydrogen peroxide) for treatment, and the stripping temperature is reduced from the original 55~65℃ to 10~40℃, the minority carrier lifetime of the middle silicon wafer can reach more than 3000μs, compared with the minority carrier lifetime of 3200μs before treatment, there is almost no loss, which can prove that the HJT battery cell prepared by the method of the present application can well maintain the performance of the battery, and save energy and reduce energy consumption; (3) The process is highly selective. Manufacturers can selectively remove the silicon dioxide layer based on the performance and production cost of the battery to be achieved, so as to meet the needs of different manufacturers. From the perspective of cost control, the silicon dioxide layer can be retained. Since the silicon dioxide layer is generally very thin (about 3nm) and also has a certain passivation effect, this can simplify the production steps and control production costs. If the performance requirements of the product are high, the silicon dioxide layer needs to be removed when producing the battery. The reason is that the etching solution used for subsequent etching of the seed layer is usually an alkaline solution, and the reaction rate between the seed layer and the alkali is significantly faster than the reaction rate between the silicon dioxide layer and the alkali. If the silicon dioxide layer is not treated when etching the seed layer, the silicon dioxide layer will not be completely etched after the seed layer is completely etched, and the remaining silicon dioxide layer will affect the lateral transport of photogenerated carriers in the battery cell, thereby affecting the battery efficiency. Therefore, for products with higher performance requirements, manufacturers need to etch the silicon dioxide layer. Since silicon dioxide reacts very quickly with HF, this step can use a mixture of HF / HF+dilute sulfuric acid to etch the oxidized silicon dioxide layer at the edge of the cell. In addition, since the exposed seed layer may be oxidized after the mask layer is removed, a copper oxide layer is formed on the surface of the seed layer. Since copper oxide basically does not react in alkaline etching solution, but can react with dilute sulfuric acid, dilute sulfuric acid can be added to HF to remove the copper oxide layer while removing the silicon dioxide layer, so that the subsequent etching of the seed layer can proceed smoothly. (4) Adapt to the needs of different manufacturers, reduce equipment investment, production costs, factory investment, and improve battery yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a schematic diagram of the HJT cell manufacturing process according to an embodiment of the present application.

[0024] Figure 2 and Figure 3 Shown is a schematic diagram of the HJT cell manufacturing process according to an embodiment of the present application.

[0025] Figure 4 Shown is a schematic structural diagram of an HJT cell according to an embodiment of the present application.

[0026] Figure 5 Shown is a schematic structural diagram of an HJT cell according to another embodiment of the present application.

[0027] Figure 6 Shown is a schematic structural diagram of etching the seed layer not covered by the copper grid electrode during the HJT cell process according to an embodiment of the present application.

[0028] In the figure: N-type single crystal silicon wafer 1, amorphous silicon intrinsic layer 2, amorphous silicon film layer 3, transparent conductive film 4, edge region 41, seed layer 5, copper gate electrode 6. DETAILED DESCRIPTION

[0029] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0030] It should be noted that the process equipment or devices not specifically specified in the following embodiments are all conventional equipment or devices in the art.

[0031] In addition, it should be understood that one or more method steps mentioned in this application do not exclude the existence of other method steps before or after the combination step or the insertion of other method steps between these explicitly mentioned steps, unless otherwise specified; it should also be understood that the combination connection relationship between one or more devices / apparatuses mentioned in this application does not exclude the existence of other devices / apparatuses before or after the combination device / apparatus or the insertion of other devices / apparatuses between these explicitly mentioned two devices / apparatuses, unless otherwise specified. Moreover, unless otherwise specified, the numbering of each method step is only a convenient tool for identifying each method step, and is not intended to limit the order of arrangement of each method step or the scope of implementation of this application. Changes or adjustments in their relative relationships shall also be regarded as the scope of implementation of this application without substantial changes in the technical content.

[0032] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0033] In the description of the present application, it should be understood that the terms "upper", "lower", "left", "right", "inner", "outer", "axial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more.

[0034] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0035] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0036] The present application is further described below in conjunction with specific embodiments, but the protection scope of the present application is not limited thereto.

[0037] See also Figure 1~Figure 3 , Figure 1 This is a flow chart of an embodiment of the HJT cell based on electroplating electrodes of the present application. It should be noted that if there are substantially the same results, the method of the present application is not limited to Figure 1 The process sequence shown is limited.

[0038] See also Figure 1 The present application provides a method for preparing a HJT cell based on electroplating electrodes, comprising the following steps: S1 provides an N-type single crystal silicon wafer; This step can be obtained by cutting the original silicon wafer, and the wafers are separated from each other after cutting. The silicon wafer in this application can be manufactured using previously known materials without special restrictions.

[0039] S2 performs double-sided cleaning and texturing on the N-type silicon wafer, forming an undulating texturing surface on both sides of the N-type silicon wafer; The N-type silicon wafer is pre-cleaned with a pre-cleaning solution composed of potassium hydroxide and hydrogen peroxide to remove organic matter and metal impurities remaining on the surface of the N-type silicon wafer from cutting, to ensure the cleanliness and flatness of the silicon wafer surface, and to facilitate subsequent operations on the silicon wafer; in the pre-cleaning solution, the volume proportion of potassium hydroxide is 1-3% (optimal 2%), the volume proportion of hydrogen peroxide is 3-5% (optimal 4%), and the rest is deionized water; the pre-cleaning temperature is 60-70°C (optimal 65°C), and the time is 120-240s (optimal 200s). The silicon wafer is texturized with a texturing solution composed of potassium hydroxide and a texturing additive to form a pyramid texturing surface. In the texturing solution, the volume proportion of potassium hydroxide is 4~5% (the optimal is 4.5%), the volume proportion of the texturing additive is 0.1~0.4% (the optimal is 0.2%), and the rest is deionized water; the temperature of the texturing treatment is 70~85℃ (the optimal is 80℃), and the time is 600~850s (the optimal is 700s).

[0040] S3 deposits intrinsic amorphous silicon layers on the front and back sides of the N-type silicon wafer respectively; like Figure 2 As shown in (b), the deposition of the amorphous silicon film layer of the HJT cell is completed by using plasma enhanced chemical vapor deposition or catalytic chemical vapor deposition, and the amorphous silicon film layer is deposited on the front and back sides of the silicon wafer. The thickness of the intrinsic amorphous silicon film layer is 10~20nm (optimal is 15nm).

[0041] S4 forms amorphous silicon film layers with different conductivity types on the surfaces of the intrinsic amorphous silicon layers on the front and back sides of the N-type silicon wafer; like Figure 2 As shown in (c), the types of amorphous silicon film layers on the front and back of the N-type silicon wafer are different, that is, if the amorphous silicon film layer on the front of the N-type silicon wafer is a P-type amorphous silicon film layer, the amorphous silicon film layer on the back of the N-type silicon wafer is an N-type amorphous silicon film layer; if the amorphous silicon film layer on the front of the N-type silicon wafer is an N-type amorphous silicon film layer, the amorphous silicon film layer on the back of the N-type silicon wafer is a P-type amorphous silicon film layer. Among them, the thickness of the P-type doped amorphous silicon film layer is 15~35nm (optimal 25nm), the thickness of the N-type doped amorphous silicon film layer is 15~35nm (optimal 25nm), the process temperature is 180~250℃, and the process time is 3~10min.

[0042] S5 forms transparent conductive films (also called TCO layers) on the surfaces of the amorphous silicon film layers on the front and back sides of the N-type silicon wafer, respectively, and leaves margins between the transparent conductive film on the back side of the N-type silicon wafer and the edge of the amorphous silicon film layer connected thereto, exposing the amorphous silicon film layer in the margin area; TCO layer (TCO-Transprant Conductive Oxide), also known as transparent conductive oxide film, is currently mainly ITO-indium tin oxide, but is not limited to ITO. Other types of transparent conductive thin films such as AZO aluminum zinc oxide can be selected, such as Figure 2 As shown in (d), this embodiment takes ITO as an example to illustrate that a transparent conductive film is formed on the surface of an amorphous silicon film by evaporation, including: Place the N-type silicon wafer under the target of the magnetron sputtering equipment, and place a hollow carrier on the back of the N-type silicon wafer; The temperature of the magnetron sputtering equipment is adjusted to 150~250℃, and Ar is sputtered by 9.3kw RF power to generate argon plasma. The target atoms generated by the argon plasma bombard the target material and combine with O2. The resulting combination is deposited on the front and back sides of the silicon wafer with amorphous silicon film deposited, forming a transparent conductive film. When the PVD forms the ITO layer, a 0.75mm ITO-free margin area is left on the four sides of the cell, so that the underlying amorphous silicon layer is exposed.

[0043] S6 oxidizes the exposed amorphous silicon film layer to form a silicon dioxide layer; like Figure 2 As shown in (e), in this step, the amorphous silicon layer on the back side of the N-type silicon wafer that is not covered by the ITO layer is oxidized into silicon dioxide. The oxidation process of the amorphous silicon layer in this step adopts hydrogen peroxide or ozone. This embodiment is explained by taking hydrogen peroxide as an example. The amorphous silicon layer on the back side of the N-type silicon wafer of the oxidation cell that is not covered by the ITO layer is oxidized by 50~500mL / L of hydrogen peroxide for 2~20min, which can reduce the subsequent alkali solution The further etching of the amorphous silicon.

[0044] S7 deposits seed layers on the surfaces of the transparent conductive films on the front and back sides of the N-type silicon wafer respectively; like Figure 2 As shown in (f), a seed layer is deposited on the surface of the transparent conductive film using a PVD device according to a normal process. The seed layer in the present application can be made of previously known materials without special restrictions, and can be copper, gold, titanium, nickel, silver, platinum, chromium or alloys, etc., but is not limited to these metals; copper is preferred in the present application. In terms of comprehensive resistivity, production cost, physical stability, etc., copper is considered to be the most suitable material for the circuit, but the present application is not limited to copper for production.

[0045] S8 forming a copper gate electrode on the seed layer; like Figure 3 (g) ~ Figure 3 As shown in (i), in this step, an electroplated copper gate electrode is formed on the seed layer, comprising: forming a patterned mask layer on the seed layer to expose the seed layer in the patterned area; Electroplating the surface of the seed layer in the pattern area to form a patterned electroplated copper grid electrode; The mask layer is removed to expose the seed layer not covered by the electroplated copper gate electrode.

[0046] Specifically, the mask layer can be made of any material known in the past without any particular restrictions, and can be photoresist, ink, stearic acid, epoxy material, hot melt wax and other materials, but not limited to these. However, whether it is photoresist or ink, alkaline solution is required for removal, and alkaline solution is corrosive to amorphous silicon. In order to prevent it from being rapidly corroded in the alkali, the oxidation of the exposed amorphous silicon layer in the margin area is completed before the copper grid electrode is formed on the seed layer, thereby forming a layer of silicon dioxide on the surface of the amorphous silicon layer. The corrosion rate of silicon dioxide in alkaline solution is low, and it can be tolerated in a normal wax removal alkali tank, which means that in an alkaline environment, a protective film is formed on the surface of the amorphous silicon layer, and the protective film can significantly reduce the effective contact time between the amorphous silicon layer and the alkaline solution, thereby significantly slowing down the corrosion of the amorphous silicon layer by the alkaline solution. In addition, in the traditional mask removal step, the temperature of the alkali solution is 55~65℃. Studies have shown that high temperature will accelerate the reaction rate of the amorphous silicon layer and the alkali solution. Therefore, in this embodiment, the mask layer is removed in the alkali solution system of low-temperature alkali solution + BDG + hydrogen peroxide, while slowing down or avoiding the reaction between the alkali solution and the amorphous silicon layer. Specifically, the preferred process in this embodiment is: using alkali solution to remove the mask layer on the surface of the seed layer under the condition of 10~40℃; the mass concentration of KOH in the alkali solution is 10~50g / L, the volume concentration of BDG is 50~200mL / L, the volume concentration of hydrogen peroxide is 10~200mL / L, the solvent in the alkali solution is water, and the processing time is 1~8min; the optimal process is: the mass concentration of KOH in the alkali solution is 25g / L, the volume concentration of BDG is 100mL / L, and the volume concentration of hydrogen peroxide is 144mL / L solution for 5min, which can completely remove the mask layer on the surface of the silicon wafer.

[0047] The alkali solution prepared by alkali and BDG can dissolve the mask layer. The mask layer is directly stripped with the alkali solution prepared by alkali and BDG. The traditional process time is 2 minutes. During this time, the amorphous silicon layer will be completely destroyed by the alkali solution, and the minority carrier lifetime is almost eliminated, only 60~70μs, and the passivation effect is almost lost; and after the amorphous silicon layer is first oxidized by the method of the present application, the minority carrier lifetime in the traditional alkali solution is significantly improved, which can reach 684μs; in order to better improve the performance of the battery, hydrogen peroxide is added to the alkali solution, and the stripping temperature is reduced from the original stripping temperature of 55~65℃ to 10~40℃. Even if the process time is extended to 5 minutes, the minority carrier lifetime of the intermediate silicon wafer can still reach more than 3000μs, compared with the original 3200μs, there is no significant decrease, and there is almost no loss; it can be proved that the preparation of HJT battery cells by the method of the present application can well maintain the performance of the battery, save energy, and reduce energy consumption. The possible reason is that alkali will react with silicon dioxide and amorphous silicon to corrode. During the reaction, the dangling bonds of silicon atoms combine with OH-, injecting electrons into the conduction band to form hydroxide ions that diffuse to the surface of the wafer. Subsequently, the OH groups on the silicon surface reduce the back bond strength, resulting in the breakage of Si-O bonds and Si-Si bonds, and the formation of silicon hydroxide complexes. These complexes further react with hydroxide to generate orthosilicic acid, which eventually decomposes into metasilicate ions and water, while releasing hydrogen ions and hydroxide ions to generate water. However, the reaction rate of silicon dioxide and alkali is significantly lower than that of amorphous silicon and alkali. Therefore, the present application forms a silicon dioxide layer on the surface of amorphous silicon, which can significantly reduce the corrosion rate of amorphous silicon. In addition, the present application reduces the reaction temperature from 55~65℃ to 10~40℃ (optimum 13℃) for film stripping operation, which further slows down the corrosion rate of silicon dioxide. Then, by adding hydrogen peroxide to the alkaline solution and utilizing the oxidizing effect of hydrogen peroxide, the reaction of alkali with amorphous silicon and silicon dioxide is inhibited, so that the effective contact time between amorphous silicon and alkaline solution is only tens of seconds, which greatly reduces the reaction rate. The oxidized amorphous silicon layer at the edge of the battery cell can be protected from being etched, that is, the reaction rate is slowed down again, which can widen the process window, but it will increase a certain cost. Therefore, whether to increase is comprehensively evaluated based on production capacity, process beat, and cost.

[0048] In order to verify the effect of the alkaline solution prepared in this step, the intermediate product prepared in step S4 is measured (because the entire surface of the product obtained in step S4 is amorphous silicon). If this product can have a good effect, then after the transparent conductive layer and the seed layer are formed on the subsequent amorphous silicon layer, the retained amorphous silicon layer is only about 0.75mm of amorphous silicon layer (a margin is left between the edge of the transparent conductive film and the amorphous silicon film layer connected to it, and the width of the amorphous silicon film layer in the exposed margin area). Due to its smaller area and narrower width, it should be less affected by corrosion. Therefore, the present application forms a patterned mask layer on the surface of the amorphous silicon layer of the intermediate product prepared in step S4, and then processes it in the mask removal layer. The entire surface of the amorphous silicon is placed in the solution of the mask removal layer. Before treatment, the minority carrier lifetime of the product is 3200μs; after the intermediate product is immersed in a traditional alkaline solution for treatment, the minority carrier lifetime of the product is measured to be 684μs, and after the intermediate product is treated with the alkaline solution of the present application, the minority carrier lifetime of the product is 3000μs. It can be seen that the minority carrier lifetime of the product prepared by the method of the present application will hardly be affected, so the amorphous silicon layer reserved at the edge without ITO and seed layer protection will not be damaged.

[0049] S9 etches the silicon dioxide layer in the edge area; This step is optional. If you choose to retain the silicon dioxide layer, since the silicon dioxide layer is generally very thin (about 3nm) and also has a certain passivation effect, this can simplify the production steps and control production costs. If the product performance requirements are high, the silicon dioxide layer needs to be removed when producing the battery. The reason is that the etching solution used for the subsequent etching of the seed layer is usually an alkaline solution, and the reaction rate between the seed layer and the alkali is significantly faster than the reaction rate between the silicon dioxide layer and the alkali. If the silicon dioxide layer is not processed when etching the seed layer, the silicon dioxide layer will not be completely etched after the seed layer is completely etched, and the remaining silicon dioxide layer will affect the lateral transport of photogenerated carriers in the battery cell, thereby affecting the battery efficiency. Therefore, for products with higher performance requirements, manufacturers need to etch the silicon dioxide layer. The reaction rate of silicon dioxide and HF is very fast, so this step can use HF / HF+dilute sulfuric acid mixture to etch the silicon dioxide layer after oxidation at the edge of the cell; in addition, the exposed seed layer after removing the mask layer may be oxidized, forming a copper oxide layer on the surface of the seed layer. Since copper oxide basically does not react in alkaline etching solution, but can react with dilute sulfuric acid, dilute sulfuric acid can be added to HF to remove the copper oxide layer while removing the silicon dioxide layer, so as to prepare for the subsequent etching of the seed layer; S10 etches the seed layer not covered by the copper grid electrode to obtain a HJT cell based on the electroplating electrode.

[0050] like Figure 3 (j) and Figure 3As shown in (k), the seed layer is etched by chemical etching. Specifically, the etching solution used in this step can be any conventional solution used to etch the seed layer without any special restrictions, such as an alkaline mixed aqueous solution of copper chloride-ammonia-ammonium chloride, or an H2SO4-H2O2 mixed system or other conventional etching solutions, so that an HJT cell with no edge plating can be obtained.

[0051] The present invention also provides an HJT cell manufactured based on the HJT cell manufacturing method based on electroplating electrodes.

[0052] In some embodiments of the present application, the HJT cell comprises: N-type single crystal silicon wafer 1; An amorphous silicon intrinsic layer 2 is formed on the front and back sides of an N-type single crystal silicon wafer 1 respectively; An amorphous silicon film layer 3 is formed on the amorphous silicon intrinsic layer 2 on the front and back sides of the N-type single crystal silicon wafer 1 respectively; A transparent conductive film 4 is formed on the surface of the amorphous silicon film layer, and a margin area 41 arranged along the circumference of the amorphous silicon film layer is provided between at least one transparent conductive film and the edge of the connected amorphous silicon film layer; A seed layer 5 formed on the surface of the transparent conductive film 4 on the front and back sides of the N-type single crystal silicon wafer 1; and Copper gate electrodes 6 are formed on the seed layers 5 .

[0053] In some embodiments of the present application, the amorphous silicon film layer on the amorphous silicon intrinsic layer on the front side of the N-type single crystal silicon wafer is a P-type doped amorphous silicon film layer, and the amorphous silicon film layer on the amorphous silicon intrinsic layer on the back side of the N-type single crystal silicon wafer is an N-type doped amorphous silicon film layer.

[0054] In other embodiments of the present application, the amorphous silicon film layer on the amorphous silicon intrinsic layer on the front side of the N-type single crystal silicon wafer is an N-type doped amorphous silicon film layer, and the amorphous silicon film layer on the amorphous silicon intrinsic layer on the back side of the N-type single crystal silicon wafer is a P-type doped amorphous silicon film layer.

[0055] This patented technology can leave a 0.75mm edge for hydrogen peroxide / ozone oxidation of amorphous silicon when preparing ITO on the amorphous silicon layer. This step is to prevent the alkali in the solution from damaging the amorphous silicon when removing the mask layer (wax). Before etching the seed copper layer, the amorphous silicon is oxidized to silicon dioxide and reacts with HF for removal. The above process steps avoid the risk of low efficiency of the cell due to PVD deposition of ITO / copper layer to the edge of the cell, and the front and back sides are turned on after electroplating. In addition, the method of this application can reduce equipment investment, production cost, plant investment, and improve yield.

[0056] The above examples are for the purpose of illustrating the embodiments disclosed in the present application and should not be construed as limiting the present application. In addition, the various modifications listed herein and the changes in the methods and compositions in the application are obvious to those skilled in the art without departing from the scope and spirit of the present application. Although the present application has been specifically described in conjunction with a variety of specific preferred embodiments of the present application, it should be understood that the present application should not be limited to these specific embodiments. In fact, various modifications as described above that are obvious to those skilled in the art to obtain the application should be included in the scope of the present application.

Claims

1. A method for preparing a HJT cell based on electroplating electrodes, characterized in that: The following steps are involved: Providing an N-type single crystal silicon wafer; Double-sided cleaning and texturing of N-type silicon wafers are performed to form undulating texturing surfaces on both sides of the N-type silicon wafers; Depositing intrinsic amorphous silicon layers on the front and back of the N-type silicon wafer respectively; Forming amorphous silicon film layers with different conductivity types on the surfaces of the intrinsic amorphous silicon layers on the front and back sides of the N-type silicon wafer; Forming transparent conductive films on the surfaces of the amorphous silicon film layers on the front and back sides of the N-type silicon wafer, respectively, leaving a margin between at least one transparent conductive film and the edge of the amorphous silicon film layer connected thereto, exposing the amorphous silicon film layer in the margin area; Oxidizing the exposed amorphous silicon film layer to form a silicon dioxide layer; Depositing seed layers on the surfaces of the transparent conductive films on the front and back sides of the N-type silicon wafer respectively; forming a copper gate electrode on the seed layer; The seed layer not covered by the copper grid electrode is etched to obtain a HJT cell based on electroplating electrodes.

2. The method for preparing a HJT cell based on electroplating electrodes according to claim 1, characterized in that: The step of forming an electroplated copper gate electrode on the seed layer comprises: forming a patterned mask layer on the seed layer to expose the seed layer in the patterned area; Electroplating the surface of the seed layer in the pattern area to form a patterned electroplated copper grid electrode; The mask layer is removed to expose the seed layer not covered by the electroplated copper gate electrode.

3. The method for preparing a HJT cell based on electroplating electrodes according to claim 2, characterized in that: The step of removing the mask layer includes: removing the mask layer on the surface of the seed layer using an alkaline solution at a stripping temperature of 10-40° C.; the mass concentration of KOH in the alkaline solution is 10-50 g / L, the volume concentration of BDG is 20-200 mL / L, and the solvent in the alkaline solution is water.

4. The method for preparing a HJT cell based on electroplating electrodes according to claim 2, characterized in that: The alkali solution also includes hydrogen peroxide, and the volume concentration of the hydrogen peroxide is 10-200 mL / L.

5. The method for preparing a HJT cell based on electroplating electrodes according to claim 4, characterized in that: The mass concentration of KOH in the alkali solution is 25 g / L, the volume concentration of BDG is 100 mL / L, and the volume concentration of hydrogen peroxide is 144 mL / L.

6. The method for preparing a HJT cell based on electroplating electrodes according to claim 3, characterized in that: The peeling temperature was 13°C.

7. The method for preparing a HJT cell based on electroplating electrodes according to claim 1, characterized in that: Before forming the electroplated copper gate line electrode on the seed layer, the silicon dioxide layer is chemically etched.

8. The method for preparing a HJT cell based on electroplating electrodes according to claim 3, characterized in that: The seed layer is etched by a chemical etching method.

9. The method for preparing a HJT cell based on electroplating electrodes according to claim 1, characterized in that: When transparent conductive films are formed on the surfaces of the amorphous silicon film layers on the front and back sides of the N-type silicon wafer, margins are left between the transparent conductive film on the amorphous silicon film layer on the back side of the N-type silicon wafer and the edge of the connected amorphous silicon film layer.

10. A HJT cell manufactured by the HJT cell manufacturing method based on electroplating electrodes according to any one of claims 1 to 9.

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