Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module, and the solar cell comprises a semiconductor substrate which is provided with a first surface and a second surface which are opposite to each other; the first doped semiconductor layer is arranged on the first surface; the first electrode layer is arranged on one side, deviating from the semiconductor substrate, of the first doped semiconductor layer; in the width direction of the first electrode layer, the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is larger than or equal to 0.1 and smaller than or equal to 1.1. The reflectivity of the first electrode layer reflecting the light penetrating through the semiconductor substrate back to the semiconductor substrate is higher, so that the absorption and utilization rate of the solar cell on the light incident from the second surface is improved, and the photoelectric conversion efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Solar cells are now being used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

[0003] However, during actual use of solar cells, part of the light irradiated to the semiconductor substrate will pass through the semiconductor substrate back to the environment, reducing the light absorption utilization rate of the solar cell and affecting the photoelectric conversion efficiency of the solar cell. Summary of the invention

[0004] The purpose of the present application is to provide a solar cell and a photovoltaic module to improve the light absorption utilization rate of the solar cell.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell, comprising:

[0007] A semiconductor substrate having a first surface and a second surface opposite to each other;

[0008] A first doped semiconductor layer, disposed on the first surface;

[0009] The first electrode layer is arranged on a side of the first doped semiconductor layer away from the semiconductor substrate; along the width direction of the first electrode layer, the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is greater than or equal to 0.1 and less than or equal to 1.1.

[0010] By adopting the above technical scheme, the light irradiated from the second surface to the semiconductor substrate will be reflected back to the semiconductor substrate by the first electrode layer when passing through the semiconductor substrate to irradiate the first electrode layer, so that the semiconductor substrate absorbs the light again. In this scheme, since the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is greater than or equal to 0.1 and less than or equal to 1.1, the area covered by the first electrode layer is larger. Therefore, compared with the case where the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is less than 0.1, the reflectivity of the first electrode layer in this application that reflects the light passing through the semiconductor substrate back to the semiconductor substrate is greater, thereby improving the absorption utilization rate of the solar cell for the light incident from the second surface and improving the photoelectric conversion efficiency. Moreover, since the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer in the present application is greater than or equal to 0.1 and less than or equal to 1.1, when the width of the first doped semiconductor layer is constant, the width of the first electrode layer in the present application accounts for a larger proportion, that is, the width of the first battery layer is larger. Under the premise that the thickness of the first electrode layer remains unchanged, the wider the first electrode layer, the lower the transmission resistance and the lower the series resistance, thereby increasing the fill factor FF to improve the efficiency of the back contact battery; or, under the premise that the resistance of the first electrode layer remains unchanged, the thickness of the first electrode layer can be reduced due to the increase in the width of the first electrode layer, and the reduction in the thickness of the first electrode layer is beneficial to improving the manufacturing efficiency of the first electrode layer.

[0011] In one implementation, the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is 0.6-1.1. In this way, the first electrode layer covers a larger area of ​​the first doped semiconductor layer, and when the light passing through the semiconductor substrate is irradiated to the first electrode layer, it will be reflected back to the semiconductor substrate by the first electrode layer, causing the semiconductor substrate to absorb the light for a second time, thereby further improving the absorption and utilization rate of the solar cell for light and improving the photoelectric conversion efficiency.

[0012] In one implementation, a ratio of a width of the first electrode layer to a width of the first doped semiconductor layer is less than or equal to 1;

[0013] The orthographic projection of the first electrode layer on the first doped semiconductor layer is located within the boundary of the first doped semiconductor layer, and along the width direction of the first electrode layer, the distance between the edge of the first electrode layer and the edge of the first doped semiconductor layer on the same side is 0 to 40 μm. This arrangement can prevent the first electrode layer from being too wide and contacting another doped semiconductor layer of opposite conductivity type, resulting in leakage.

[0014] In one implementation, along the width direction of the first electrode layer, the absolute value of the difference between the distance between any two points on the edge of the first electrode layer and the edge of the first doped semiconductor layer on the same side is ΔD1, 0≤ΔD1≤40μm. This ensures that the distance between any two points on the edge of the first electrode layer and the edge of the first doped semiconductor layer is close, so that the shape of the edge of the first electrode layer is similar to that of the edge of the first doped semiconductor layer. Based on this, the first electrode layer covers a larger area of ​​the first doped semiconductor layer, thereby further improving the absorption and utilization rate of light by the solar cell and improving the photoelectric conversion efficiency.

[0015] In one implementation, a ratio of a width of the first electrode layer to a width of the first doped semiconductor layer is greater than 1 and less than or equal to 1.1;

[0016] The orthographic projection of the first doped semiconductor layer on the first surface is located inside the orthographic projection of the first electrode layer on the first surface. With this technical solution, the first electrode layer will extend into the isolation region, and can also reflect the light in the isolation region back to the semiconductor substrate, further improving the absorption and utilization rate of the solar cell for light.

[0017] In one implementation, along the width direction of the first doped semiconductor layer, the edge of the first electrode layer exceeds the edge of the first doped semiconductor layer on the same side by a distance of 0 to 10 μm. This technical solution ensures that a safe distance is reserved between the edge of the first electrode layer and the second doped semiconductor layer, further reducing the risk of leakage.

[0018] In one implementation, the solar cell further includes a second doped semiconductor layer and a second electrode layer, wherein the second electrode layer is disposed on a side of the second doped semiconductor layer away from the semiconductor substrate; the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer;

[0019] The second doped semiconductor layers and the first doped semiconductor layers are alternately arranged on the first surface;

[0020] Among them, the ratio of the width of the second electrode layer to the width of the second doped semiconductor layer is greater than or equal to 0.1, and less than or equal to 1.1. With the above technical solution, the light irradiated from the second surface to the semiconductor substrate will be reflected back to the semiconductor substrate by the second electrode layer when passing through the semiconductor substrate to the second electrode layer, so that the semiconductor substrate absorbs the light twice. In this solution, since the ratio of the width of the second electrode layer to the width of the second doped semiconductor layer is greater than or equal to 0.1, and less than or equal to 1.1, the area of ​​the second doped semiconductor layer covered by the second electrode layer is larger. Therefore, compared with the case where the ratio of the width of the second electrode layer to the width of the second doped semiconductor layer is less than 0.1, the reflectivity of the second electrode layer reflecting the light passing through the semiconductor substrate back to the semiconductor substrate in this application is greater, thereby improving the absorption and utilization rate of the solar cell for the light incident from the second surface and improving the photoelectric conversion efficiency. Moreover, since the ratio of the width of the second electrode layer to the width of the second doped semiconductor layer in the present application is greater than or equal to 0.1 and less than or equal to 1.1, when the width of the second doped semiconductor layer is constant, the width of the second electrode layer in the present application accounts for a larger proportion, that is, the width of the second battery layer is larger. On the premise that the thickness of the second electrode layer remains unchanged, the wider the second electrode layer, the lower the transmission resistance and the lower the series resistance, thereby increasing the fill factor FF to improve the efficiency of the back contact battery; or, on the premise that the resistance of the second electrode layer remains unchanged, the thickness of the second electrode layer can be reduced due to the increase in the width of the second electrode layer, and the reduction in the thickness of the second electrode layer is beneficial to improving the manufacturing efficiency of the second electrode layer.

[0021] In one implementation, the ratio of the width of the second electrode layer to the width of the second doped semiconductor layer is 0.6-1.1. In this way, the second electrode layer covers a larger area of ​​the second doped semiconductor layer, and when the light passing through the semiconductor substrate is irradiated to the second electrode layer, it will be reflected back to the semiconductor substrate by the second electrode layer, causing the semiconductor substrate to absorb the light for a second time, thereby further improving the absorption and utilization rate of the solar cell for light and improving the photoelectric conversion efficiency.

[0022] In one implementation, a ratio of a width of the second electrode layer to a width of the second doped semiconductor layer is less than or equal to 1;

[0023] The projection of the second electrode layer on the second doped semiconductor layer is located within the boundary of the second doped semiconductor layer, and along the width direction of the second electrode layer, the distance between the edge of the second electrode layer and the edge of the second doped semiconductor layer on the same side is 0 to 40 μm. In this way, the width of the second electrode layer can be prevented from being too wide and contacting another doped semiconductor layer of opposite conductivity type, resulting in leakage.

[0024] In one implementation, along the width direction of the second electrode layer, the absolute value of the difference between the distance between any two points on the edge of the second electrode layer and the edge of the second doped semiconductor layer on the same side is ΔD2, 0≤ΔD2≤40μm. This ensures that the distance between any two points on the edge of the second electrode layer and the edge of the second doped semiconductor layer is close, so that the shape of the edge of the second electrode layer is similar to that of the edge of the second doped semiconductor layer. Based on this, the second electrode layer covers a larger area of ​​the second doped semiconductor layer, thereby further improving the absorption and utilization rate of light by the solar cell and improving the photoelectric conversion efficiency.

[0025] In one implementation, a ratio of a width of the second electrode layer to a width of the second doped semiconductor layer is greater than 1 and less than or equal to 1.1;

[0026] The orthographic projection of the second doped semiconductor layer on the first surface is located inside the orthographic projection of the second electrode layer on the first surface. With this technical solution, the second electrode layer will extend into the isolation region, and can also reflect the light in the isolation region back to the semiconductor substrate, further improving the absorption and utilization rate of the solar cell for light.

[0027] In one implementation, along the width direction of the second doped semiconductor layer, the distance that the edge of the second electrode layer exceeds the edge of the second doped semiconductor layer on the same side is 0 to 10 μm. This technical solution ensures that a safe distance is reserved between the edge of the second electrode layer and the first doped semiconductor layer, further reducing the risk of leakage.

[0028] In one implementation, a ratio of a width of the first electrode layer to a width of the first doped semiconductor layer is different from a ratio of a width of the second electrode layer to a width of the second doped semiconductor layer;

[0029] Or, the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is less than 1, and along the width direction of the first electrode layer, the distance between the edge of the first electrode layer and the edge of the first doped semiconductor layer is different from the distance between the edge of the second electrode layer and the edge of the second doped semiconductor layer;

[0030] Or, the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is greater than 1 and less than or equal to 1.1, and along the width direction of the first electrode layer, the distance that the edge of the first electrode layer exceeds the edge of the first doped semiconductor layer on the same side is different from the distance that the edge of the second electrode layer exceeds the edge of the second doped semiconductor layer on the same side;

[0031] Or, the width of the first electrode layer is different from the width of the second electrode layer; when the second doped semiconductor layer and the second electrode layer are both of opposite conductivity type to the semiconductor substrate, the width of the first electrode layer is smaller than the width of the second electrode layer. The second electrode layer is of opposite conductivity type to the semiconductor substrate, so the second electrode layer is used to extract minority carriers in the semiconductor substrate, and the larger the width of the second electrode layer, the more conducive it is to extract minority carriers, and the more minority carriers are extracted, the higher the minority carrier collection efficiency is, and the more conducive it is to reducing recombination, which is conducive to improving the efficiency of solar cells.

[0032] Or, the width of the first doped semiconductor layer is different from the width of the second doped semiconductor layer. The second doped semiconductor has an opposite conductivity type to the semiconductor substrate, so the second doped semiconductor is used to collect minority carriers in the semiconductor substrate, and the larger the width of the second doped semiconductor is, the more conducive it is to the collection of minority carriers, and the more minority carriers are collected, the higher the minority carrier collection efficiency is, and the more conducive it is to reducing recombination, thereby facilitating improving the efficiency of solar cells.

[0033] In one implementation, the second doped semiconductor layer has a conductivity type opposite to that of the semiconductor substrate;

[0034] Along the width direction of the first electrode layer or the second electrode layer, the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is smaller than the ratio of the width of the second electrode layer to the width of the second doped semiconductor layer;

[0035] and / or, the width of the first electrode layer is smaller than the width of the second electrode layer;

[0036] and / or, the width of the first doped semiconductor layer is smaller than the width of the second doped semiconductor layer;

[0037] And / or, when the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is greater than 1 and less than or equal to 1.1, along the width direction of the first doped semiconductor layer or the second doped semiconductor layer, the distance that the edge of the second electrode layer exceeds the edge of the second doped semiconductor layer on the same side is greater than the distance that the edge of the first electrode layer exceeds the edge of the first doped semiconductor layer on the same side.

[0038] In each of the above schemes, the second electrode layer and the second doped semiconductor layer have opposite conductivity types to the semiconductor substrate, and thus the second electrode layer and the second doped semiconductor layer are used to extract minority carriers in the semiconductor substrate. The larger the width of the second electrode layer or the second doped semiconductor layer, the more conducive it is to the extraction of minority carriers. The more minority carriers are extracted, the higher the minority carrier collection efficiency is, and the more conducive it is to reducing recombination, which in turn helps to improve the efficiency of solar cells.

[0039] When the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is less than 1, the distance between the edge of the first electrode layer and the edge of the first doped semiconductor layer is less than the distance between the edge of the second electrode layer and the edge of the second doped semiconductor layer. The width of the second electrode layer is appropriately reduced compared to the width of the first electrode layer, and while ensuring the minority carrier collection efficiency, the light blocking area can be reduced, so that more light is incident from the surface where the second electrode layer is located into the semiconductor substrate.

[0040] In one implementation, along the width direction of the first doped semiconductor layer, the width of the first electrode layer accounts for 80% to 100% of the width of the first doped semiconductor layer; such a configuration can not only ensure that the first electrode layer reflects light passing through the semiconductor substrate back into the semiconductor substrate, but also prevent the first electrode layer from contacting the second doped semiconductor layer or the second electrode with the opposite conductivity type and leaking electricity.

[0041] And / or, the thickness of the first electrode layer is 0.5 μm to 20 μm, which can not only ensure the efficiency of extracting carriers by using the first electrode layer, but also prevent the first electrode layer from being too thick and causing a waste of raw materials.

[0042] And / or, the width of the first electrode layer is 40 μm-350 μm. This ensures that the contact area between the first electrode layer and the first doped semiconductor layer is large, reduces the contact resistance between the first electrode layer and the first doped semiconductor layer, and prevents the first electrode layer from being too wide and contacting another doped semiconductor layer of opposite conductivity type, causing leakage.

[0043] And / or, the width of the first doped semiconductor layer is 50 μm-350 μm.

[0044] In one implementation, the solar cell further includes a dielectric layer located between the first doped semiconductor layer and the first electrode layer, the dielectric layer is provided with an opening penetrating the thickness thereof, and the first electrode layer is electrically connected to the first doped semiconductor layer through the opening;

[0045] The total area of ​​the openings corresponding to the dielectric layer and the first electrode layer accounts for 1% to 10% of the area of ​​the first electrode layer, thereby reducing the contact resistance between the first electrode layer and the first doped semiconductor layer, reducing the damage of the laser to the battery, and reducing recombination.

[0046] In one implementation, the second doped semiconductor layer and the first doped semiconductor layer are alternately arranged on the first surface, and the conductivity type of the second doped semiconductor layer is opposite to that of the semiconductor substrate.

[0047] The solar cell further includes a dielectric layer covering the first surface, the dielectric layer is located between the first doped semiconductor layer and the first electrode layer and between the second doped semiconductor layer and the second electrode layer, the dielectric layer is provided with an opening penetrating through the thickness thereof, the first electrode layer is electrically connected to the first doped semiconductor layer through the opening, and the second electrode layer is electrically connected to the second doped semiconductor layer through the opening;

[0048] The total area of ​​the openings corresponding to the dielectric layer and the first electrode layer is smaller than the total area of ​​the openings corresponding to the dielectric layer and the second electrode layer. By adopting the above technical solution, the total area of ​​the openings corresponding to the narrower first electrode layer is smaller, thereby improving the passivation effect, and the total area of ​​the openings corresponding to the wider first electrode layer is larger, thereby reducing the contact resistance between the first electrode layer and the first doped semiconductor layer, and also ensuring that the total area of ​​the openings between the dielectric layer and any one of the electric electrode layers can ensure the normal transmission of current, and will not be too large to cause laser damage to the substrate.

[0049] In one implementation, the solar cell further includes a dielectric layer located between the first doped semiconductor layer and the first electrode layer, and between the second doped semiconductor layer and the second electrode layer, the dielectric layer is provided with an opening penetrating the thickness thereof, the first electrode layer is electrically connected to the first doped semiconductor layer through the opening, and the second electrode layer is electrically connected to the second doped semiconductor layer through the opening;

[0050] The second doped semiconductor layer and the first doped semiconductor layer are alternately arranged on the first surface, an isolation region is provided between the first doped semiconductor layer and the second doped semiconductor layer, and the portion of the dielectric layer covering the isolation region includes at least one metal element in the first electrode layer, and / or includes at least one metal element in the second electrode layer. In this way, the metal elements located in the isolation region can also reflect the light back to the semiconductor substrate for secondary absorption, further improving the absorption and utilization rate of the solar cell for light.

[0051] In one implementation, the second doped semiconductor layer and the first doped semiconductor layer are alternately arranged on the first surface, an isolation groove is provided between the first doped semiconductor layer and the second doped semiconductor layer, the solar cell further comprises a dielectric layer, the dielectric layer is located between the first doped semiconductor layer and the first electrode layer and between the second doped semiconductor layer and the second electrode layer, and covers the isolation groove, the dielectric layer is provided with an opening penetrating the thickness thereof, the first electrode layer is electrically connected to the first doped semiconductor layer through the opening, and the second electrode layer is electrically connected to the second doped semiconductor layer through the opening;

[0052] The first electrode layer covers at least part of the dielectric layer on the side wall of the isolation groove; and / or the second electrode layer covers at least part of the dielectric layer on the side wall of the isolation groove. With this technical solution, light directed toward the side of the isolation groove can be reflected back to the semiconductor substrate by the first electrode layer or the second electrode layer, further improving the absorption and utilization rate of the solar cell for light.

[0053] In one implementation, the first electrode layer includes a first metal layer and a second metal layer stacked in sequence along the thickness direction of the semiconductor substrate, the first metal layer is closer to the semiconductor substrate relative to the second metal layer; and the width of the second metal layer is greater than the width of the first metal layer; this ensures that during the welding process, there is a larger contact area between the second metal layer and the welding strip or other interconnecting parts, thereby improving the welding efficiency.

[0054] The portion of the second metal layer extending beyond the first metal layer is parallel to the first surface; or, the portion of the second metal layer extending beyond the first metal layer gradually tilts toward the first surface; or, the portion of the second metal layer extending beyond the first metal layer gradually warps away from the first surface.

[0055] In one implementation, along the extension direction of the first electrode layer, the side surface of the first metal layer includes multiple concave surfaces; the concave surfaces are more conducive to reflecting the light irradiated to the side surface of the first metal layer to the semiconductor substrate, which is beneficial for the semiconductor substrate surface to receive more reflected light, thereby improving the utilization rate of light.

[0056] The concave curved surface includes an edge line, that is, the position where two adjacent concave curved surfaces meet is an edge line, and the edge line can increase the contact area with the encapsulation film during the encapsulation process, thereby increasing the adhesion between the encapsulation film and the solar cell, and improving the structural stability of the encapsulation component.

[0057] In one implementation, the first electrode layer includes a first middle region and two first edge regions located on both sides of the first middle region along the width direction, the reflectivity of the first edge region is less than the reflectivity of the first middle region, and / or the roughness of the first edge region is less than the roughness of the first middle region. During the packaging process, the contact area between the first edge region of the first electrode layer and the packaging material can be increased, the adhesion between the first electrode layer and the packaging material can be improved, and thus the firmness of the packaging of the first electrode layer can be improved.

[0058] In one implementation, along the extension direction of the first electrode layer, the boundary of the first electrode layer is wavy;

[0059] And / or, the boundary of the first doped semiconductor layer is wavy. With this technical solution, the overall extension length of the first electrode layer or the first doped semiconductor layer can be increased, thereby increasing the transmission path and area of ​​carriers in the first electrode layer or the first doped semiconductor layer, which is beneficial to reducing contact resistance.

[0060] A photovoltaic assembly comprises a plurality of solar cells as described above.

[0061] Compared with the prior art, the beneficial effects of the photovoltaic module provided in the present application are the same as the beneficial effects of the above-mentioned solar cells, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0063] Figure 1 A schematic diagram of a photovoltaic module provided in an embodiment of the present application;

[0064] Figure 2 A partial cross-sectional view of a solar cell provided in an embodiment of the present application;

[0065] Figure 3 A partial cross-sectional view of another solar cell provided in an embodiment of the present application;

[0066] Figure 4 A partial top view of a solar cell provided in an embodiment of the present application;

[0067] Figure 5 for Figure 4 A partial enlarged view of the middle A area;

[0068] Figure 6 A top view SEM image of a part of a solar cell provided in an embodiment of the present application;

[0069] Figure 7 A partial cross-sectional view of another solar cell provided in an embodiment of the present application;

[0070] Figure 8 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0071] Fig. 9 A partial enlarged view of a solar cell provided in another embodiment of the present application;

[0072] Fig.10 A local enlarged view of the first electrode layer of the solar cell provided in an embodiment of the present application;

[0073] Fig.11 A local enlarged view of the second electrode layer of the solar cell provided in an embodiment of the present application;

[0074] Fig.12 A SEM image of the side of a solar cell provided in an embodiment of the present application;

[0075] Fig.13 for Fig.12 A partial enlarged view of the middle B area;

[0076] Fig.14 A SEM image of a side surface of a solar cell provided in another embodiment of the present application;

[0077] Fig.15 A SEM image of a side surface of a solar cell provided in another embodiment of the present application;

[0078] Fig.16 A SEM image of a side surface of a solar cell provided in another embodiment of the present application;

[0079] Fig.17 This is a local cross-sectional SEM image of the solar cell provided in an embodiment of the present application.

[0080] Reference numerals:

[0081] 1-semiconductor substrate, 2-dielectric layer, 3-first doped semiconductor layer, 4-first interface layer, 5-first electrode layer, 5a-first edge region, 5b-first middle region, 6-second electrode layer, 6a-second edge region, 6b-second middle region, 7-second doped semiconductor layer, 8-second interface layer, 9-isolation region, 10-passivation layer, 11-anti-reflection layer, 12-transparent conductive layer, a-first metal layer, b-second metal layer, c-vertical stripes, d-ridges, e-holes. DETAILED DESCRIPTION

[0082] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0083] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0084] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0085] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0086] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0087] The present application embodiment provides a photovoltaic module, which includes a plurality of solar cells, and the plurality of solar cells are electrically connected in series and / or in parallel. For example, Figure 1 A schematic diagram of a plurality of solar cells electrically connected together is provided. Figure 1 As shown, multiple solar cells are arranged in sequence along a first direction to form a battery string, and multiple solar cells in the battery string are connected in series in sequence. Two or more battery strings are arranged in sequence along the first direction to form a group of battery strings, and multiple groups of battery strings are arranged in sequence along the second direction.

[0088] During the actual use of solar cells, part of the light irradiated to the semiconductor substrate 1 will pass through the semiconductor substrate 1 back to the environment, which reduces the absorption and utilization rate of light by the solar cell and affects the photoelectric conversion efficiency of the solar cell. For example, for distributed products, when photovoltaic modules are applied to roofs, since sunlight cannot be incident from the back of the solar cell to be absorbed by the solar cell, in this case, the solar cell does not pay attention to the bifaciality, but pays more attention to the absorption rate of light incident from the front of the cell. The higher the absorption rate of light incident from the front, the more conducive it is to improving the photoelectric conversion efficiency of the solar cell.

[0089] In view of the above situation, in order to improve the absorption and utilization rate of light by solar cells, the present application also provides a variety of solar cells, which can be applied to the above photovoltaic modules.

[0090] A solar cell provided in an embodiment of the present application includes: a semiconductor substrate 1, the semiconductor substrate 1 having a first surface and a second surface relative to each other; a first doped semiconductor layer 3, arranged on the first surface; a first electrode layer 5, arranged on a side of the first doped semiconductor layer 3 away from the semiconductor substrate 1; along the width direction of the electrode layer, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is greater than or equal to 0.1, and less than or equal to 1.1.

[0091] Another solar cell provided in an embodiment of the present application includes: a semiconductor substrate 1, the semiconductor substrate 1 has a first surface and a second surface opposite to each other; a first doped semiconductor layer 3, arranged on the first surface; a first electrode layer 5, arranged on the side of the first doped semiconductor layer 3 away from the semiconductor substrate 1; along the width direction of the electrode layer, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is greater than or equal to 0.1, and less than or equal to 1.1. The solar cell also includes a second doped semiconductor layer 7 and a second electrode layer 6, the second electrode layer 6 is arranged on the side of the second doped semiconductor layer 7 away from the semiconductor substrate 1; the conductivity type of the second doped semiconductor layer 7 is opposite to the conductivity type of the first doped semiconductor layer 3; the second doped semiconductor layer 7 and the first doped semiconductor layer 3 are alternately arranged on the first surface, wherein the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 is greater than or equal to 0.1, and less than or equal to 1.1.

[0092] Another solar cell provided in an embodiment of the present application includes: a semiconductor substrate 1, the semiconductor substrate 1 has a first surface and a second surface opposite to each other; a first doped semiconductor layer 3, arranged on the first surface; a first electrode layer 5, arranged on the side of the first doped semiconductor layer 3 away from the semiconductor substrate 1; along the width direction of the electrode layer, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is greater than or equal to 0.1, and less than or equal to 1.1. The solar cell also includes a second doped semiconductor layer 7 and a second electrode layer 6, the second electrode layer 6 is arranged on the side of the second doped semiconductor layer 7 away from the semiconductor substrate 1; the conductivity type of the second doped semiconductor layer 7 is opposite to the conductivity type of the first doped semiconductor layer 3; the second doped semiconductor layer 7 is arranged on the second surface, and the second doped semiconductor layer 7 can be arranged on the second surface as a whole layer, or can be arranged on the second surface partially, such as being arranged on the second surface in a strip shape.

[0093] The solar cell provided in the present application is described in detail below through several specific embodiments.

[0094] Embodiment 1:

[0095] like Figure 2As shown, the solar cell provided in the first embodiment of the present application includes a semiconductor substrate 1, a first doped semiconductor layer 3, a first interface layer 4, a first electrode layer 5, a second doped semiconductor layer 7, a second interface layer 8 and a second electrode layer 6. The semiconductor substrate 1 has a first surface and a second surface relative to each other, that is, the two surfaces relative to each other along the thickness direction of the semiconductor substrate 1 are the first surface and the second surface respectively. In actual use, the first surface may correspond to the backlight side of the solar cell, and the second surface may correspond to the light-facing side of the solar cell; or, the second surface may correspond to the backlight side of the solar cell, and the first surface may correspond to the light-facing side of the solar cell.

[0096] In the actual application process, the embodiment of the present invention does not specifically limit the material and conductivity type of the semiconductor substrate 1. For example, the semiconductor substrate 1 can be a silicon substrate. Alternatively, the semiconductor substrate 1 can also be a substrate made of any semiconductor material such as a germanium silicon substrate, a germanium substrate or a gallium arsenide substrate. The conductivity type of the semiconductor substrate 1 can be an N-type semiconductor substrate 1, a P-type semiconductor substrate 1 or an intrinsic semiconductor substrate 1.

[0097] like Figure 2 As shown, the first doped semiconductor layer 3 is disposed on the first surface, wherein the first doped semiconductor layer 3 can be additionally formed on the semiconductor substrate 1 by a deposition technique, or can be formed in the semiconductor substrate 1 by diffusion, ion implantation, or the like.

[0098] like Figure 2 and Figure 3As shown, the first electrode layer 5 is disposed on the side of the first doped semiconductor layer 3 away from the semiconductor substrate 1. Along the width direction of the first electrode layer 5, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is greater than or equal to 0.1 and less than or equal to 1.1. That is, along the direction perpendicular to the extension of the first doped semiconductor layer 3, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is in the range of 0.1 to 1.1. By adopting the above technical scheme, the light irradiated from the second surface to the semiconductor substrate 1 will be reflected back to the semiconductor substrate 1 by the first electrode layer 5 when passing through the semiconductor substrate 1 to the first electrode layer 5, so that the semiconductor substrate 1 absorbs the light again. In this scheme, since the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is greater than or equal to 0.1 and less than or equal to 1.1, the area of ​​the first doped semiconductor layer 3 covered by the first electrode layer 5 is larger. Therefore, compared with the case where the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is less than 0.1, the reflectivity of the first electrode layer 5 in this application that reflects the light passing through the semiconductor substrate 1 back to the semiconductor substrate 1 is greater, thereby improving the absorption utilization rate of the solar cell for the light incident from the second surface and improving the photoelectric conversion efficiency. Moreover, since the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 in the present application is greater than or equal to 0.1 and less than or equal to 1.1, when the width of the first doped semiconductor layer 3 is constant, the width of the first electrode layer 5 in the present application accounts for a large proportion, that is, the width of the first electrode layer 5 is large. On the premise that the thickness of the first electrode layer 5 remains unchanged, the wider the first electrode layer 5, the lower the transmission resistance, and the lower the series resistance, thereby improving the fill factor FF to improve the efficiency of the solar cell; or, on the premise that the resistance of the first electrode layer 5 remains unchanged, the thickness of the first electrode layer 5 can be reduced due to the increase in the width of the first electrode layer 5, and the reduction in the thickness of the first electrode layer 5 is beneficial to improving the manufacturing efficiency of the first electrode layer 5.

[0099] Exemplarily, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1 or 1.1.

[0100] In the case where the first surface is the backlight surface, the light irradiated from the second surface to the semiconductor substrate 1 will pass through the semiconductor substrate 1 and return to the environment, reducing the absorption and utilization rate of the light. Therefore, in some embodiments, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is 0.6-1.1, so that the first electrode layer 5 covers a larger area of ​​the first doped semiconductor layer 3, and the light passing through the semiconductor substrate 1 will be reflected back to the semiconductor substrate 1 by the first electrode layer 5 when irradiating the first electrode layer 5, so that the semiconductor substrate 1 absorbs the light twice, thereby further improving the absorption and utilization rate of the solar cell for light and improving the photoelectric conversion efficiency. Exemplarily, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is 0.65, 0.75, 0.85, 0.88, 0.92, 0.95, 0.98, 1.02 or 1.08.

[0101] In some embodiments, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is 0.1-0.2, so that the area of ​​the first electrode layer 5 covering the first doped semiconductor layer 3 is small, which further saves the raw materials of the first electrode layer 5; in addition, more light can be incident from the first surface to the semiconductor substrate. Exemplarily, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is 0.15, 0.25, 0.35, 0.45, 0.55, 0.65, 0.75, 0.85 or 0.95.

[0102] In some embodiments, when the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is less than or equal to 1, the orthographic projection of the first electrode layer 5 on the first doped semiconductor layer 3 is located within the boundary of the first doped semiconductor layer 3, such as Figure 6 As shown, along the width direction of the first electrode layer 5, the distance D1 between the edge of the first electrode layer 5 and the edge of the first doped semiconductor layer 3 on the same side is 0-40 μm. That is, the width of the first electrode layer 5 is less than or equal to the width of the first doped semiconductor layer 3, and along the width direction of the first electrode layer 5, at least one side edge of the first electrode layer 5 is between the two side edges of the first doped semiconductor layer 3. In addition, along the width direction of the first electrode layer 5, the distance D1 between the edge of the first electrode layer 5 on the same side and the edge of the first doped semiconductor layer 3 is set within a reasonable range of 0-40 μm, which can ensure that the width of the first electrode layer 5 is relatively wide while preventing the width of the first electrode layer 5 from being too wide and contacting another doped semiconductor layer of the opposite conductive type, resulting in leakage. Among them, the edge of the first electrode layer 5 and / or the edge of the first doped semiconductor layer 3 can extend along a straight line, a regular curve or an irregular curve, for example, the edge of the first electrode layer 5 and / or the edge of the first doped semiconductor layer 3 extends along a wavy line.

[0103] Exemplarily, the distance D1 between the edge of the first electrode layer 5 and the edge of the first doped semiconductor layer 3 on the same side is 0, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm or 40 μm. Optionally, D1 is 0-20 μm.

[0104] In some embodiments, Figure 5 As shown, along the width direction of the first electrode layer 5, the absolute value of the difference between the distance between any two points on the edge of the first electrode layer 5 and the edge of the first doped semiconductor layer 3 on the same side is ΔD1, 0≤ΔD1≤40μm. Exemplarily, take any two points A and B on the same side of the edge of the first electrode layer 5, and along the width direction of the first electrode layer 5, the distance between point A and the edge of the first doped semiconductor layer 3 on the same side is the distance D between A-A'. A The distance between point B and the edge of the first doped semiconductor layer 3 on the same side is the distance D between point B-B'. B , D A With D B The absolute value of the difference is ΔD1, that is, ΔD1 = |D A -D B |. In this technical solution, ΔD1 is set within a reasonable range of 0 to 40 μm to ensure that the distances between any two points on the edge of the first electrode layer 5 and the edge of the first doped semiconductor layer 3 are close, so that the shape of the edge of the first electrode layer 5 is similar to that of the edge of the first doped semiconductor layer 3. Based on this, the first electrode layer 5 covers a larger area of ​​the first doped semiconductor layer 3, thereby further improving the absorption and utilization rate of the solar cell for light and improving the photoelectric conversion efficiency.

[0105] Illustratively, ΔD1 may be 0, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, or 40 μm.

[0106] like Figure 2 As shown, the solar cell further includes a second doped semiconductor layer 7 and a second electrode layer 6. The conductivity type of the second doped semiconductor layer 7 is opposite to that of the first doped semiconductor layer 3, so as to collect and extract electrons and holes respectively, which is conducive to the formation of photocurrent. The second electrode layer 6 is arranged on the side of the second doped semiconductor layer 7 away from the semiconductor substrate 1, so as to utilize the second electrode layer 6 to extract the carriers collected by the second doped semiconductor layer 7. The solar cell can be a back contact cell or a bifacial cell.

[0107] When the solar cell is a back contact cell, the second doped semiconductor layer 7 and the first doped semiconductor layer 3 are alternately arranged on the first surface. Specifically, the second doped semiconductor layer 7 and the first doped semiconductor layer 3 can be arranged alternately in strips or in a cross-shaped V-shaped distribution.

[0108] like Figure 3 As shown, in the case where the solar cell is a bifacial cell, the second doped semiconductor layer 7 is arranged on the second surface.

[0109] In the case where the solar cell is a back contact cell, in some embodiments, along the width direction of the second electrode layer 6, the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 is greater than or equal to 0.1, and less than or equal to 1.1. In the case where the second doped semiconductor layer 7 is arranged on the first surface, the above technical solution is adopted, and the light irradiated from the second surface to the semiconductor substrate 1 is reflected back to the semiconductor substrate 1 by the second electrode layer 6 when passing through the semiconductor substrate 1 to the second electrode layer 6, so that the semiconductor substrate 1 absorbs the light twice. In this solution, since the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 is greater than or equal to 0.1, and less than or equal to 1.1, the area of ​​the second doped semiconductor layer 7 covered by the second electrode layer 6 is larger. Therefore, compared with the case where the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 is less than 0.1, the reflectivity of the second electrode layer 6 reflecting the light passing through the semiconductor substrate 1 back to the semiconductor substrate 1 in this application is greater, thereby improving the absorption and utilization rate of the solar cell for the light incident from the second surface, and improving the photoelectric conversion efficiency. Moreover, since the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 in the present application is greater than or equal to 0.1 and less than or equal to 1.1, when the width of the second doped semiconductor layer 7 is constant, the width of the second electrode layer 6 in the present application accounts for a large proportion, that is, the width of the second battery layer is large. On the premise that the thickness of the second electrode layer 6 remains unchanged, the wider the second electrode layer 6 is, the lower the transmission resistance is, and the lower the series resistance is, thereby improving the fill factor FF to improve the efficiency of the solar cell; or, on the premise that the resistance of the second electrode layer 6 remains unchanged, the thickness of the second electrode layer 6 can be reduced due to the increase in the width of the second electrode layer 6, and the reduction in the thickness of the second electrode layer 6 is beneficial to improving the manufacturing efficiency of the second electrode layer 6.

[0110] When the second doped semiconductor layer 7 is disposed on the second surface, the second doped semiconductor layer 7 and the first doped semiconductor layer 3 are disposed on the first surface and the second surface of the semiconductor substrate 1 respectively, which can reduce leakage risk and current loss.

[0111] Exemplarily, the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 is 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1 or 1.1. Optionally, the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 is 0.1-0.2 or 0.6-1.1, and the effect can refer to the beneficial effect corresponding to the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 in this range.

[0112] In some embodiments, when the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 is less than or equal to 1, the projection of the second electrode layer 6 on the second doped semiconductor layer 7 is located within the boundary of the second doped semiconductor layer 7. Figure 2 As shown, along the width direction of the second electrode layer 6, the distance D2 between the edge of the second electrode layer 6 and the edge of the second doped semiconductor layer 7 on the same side is 0-40 μm. That is, the width of the second electrode layer 6 is less than or equal to the width of the second doped semiconductor layer 7, and along the width direction of the second electrode layer 6, at least one side edge of the second electrode layer 6 is between the two side edges of the second doped semiconductor layer 7. In addition, along the width direction of the second electrode layer 6, the distance D2 between the edge of the second electrode layer 6 on the same side and the edge of the second doped semiconductor layer 7 is set within a reasonable range of 0-40 μm, which can ensure that the width of the second electrode layer 6 is wide while preventing the width of the second electrode layer 6 from being too wide and contacting another doped semiconductor layer of the opposite conductive type, resulting in leakage. Among them, the edge of the second electrode layer 6 and / or the edge of the second doped semiconductor layer 7 can extend along a straight line, a regular curve or an irregular curve, for example, the edge of the second electrode layer 6 and / or the edge of the second doped semiconductor layer 7 extends along a wavy line.

[0113] Exemplarily, the distance D2 between the edge of the second electrode layer 6 and the edge of the second doped semiconductor layer 7 on the same side is 0, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm or 40 μm. Optionally, D2 is 0-20 μm.

[0114] In some embodiments, along the width direction of the second electrode layer 6, the absolute value of the difference between the distance between any two points on the edge of the second electrode layer 6 and the edge of the second doped semiconductor layer 7 on the same side is ΔD2, 0≤ΔD2≤40μm. Exemplarily, take any two points C and E on the same side of the edge of the second electrode layer 6, and along the width direction of the second electrode layer 6, the distance between point C and the edge of the second doped semiconductor layer 7 on the same side is the distance D between C-C'. C The distance between point E and the edge of the second doped semiconductor layer 7 on the same side is the distance D between point E-E'. E , D C With DE The absolute value of the difference is ΔD2, that is, ΔD2 = |D C -D E |. In this technical solution, ΔD2 is set within a reasonable range of 0 to 40 μm to ensure that the distances between any two points on the edge of the second electrode layer 6 and the edge of the second doped semiconductor layer 7 are close, so that the shape of the edge of the second electrode layer 6 is similar to that of the edge of the second doped semiconductor layer 7. Based on this, the second electrode layer 6 covers a larger area of ​​the second doped semiconductor layer 7, thereby further improving the absorption and utilization rate of the solar cell for light and improving the photoelectric conversion efficiency.

[0115] Illustratively, ΔD2 may be 0, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, or 40 μm.

[0116] In some embodiments, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 and the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 are different.

[0117] In some embodiments, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is less than 1, and along the width direction of the first electrode layer 5, the distance between the edge of the first electrode layer 5 and the edge of the first doped semiconductor layer 3 is different from the distance between the edge of the second electrode layer 6 and the edge of the second doped semiconductor layer 7.

[0118] The ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3, the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7, the distance between the edge of the first electrode layer 5 and the edge of the first doped semiconductor layer 3, and the distance between the edge of the second electrode layer 6 and the edge of the second doped semiconductor layer 7 can be set according to the actual application scenario. For example, it can be adjusted according to the conductivity type of the first doped semiconductor layer 3 and the second doped semiconductor layer 7 and the width of the first doped semiconductor layer 3 and the second doped semiconductor layer 7. Of course, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 and the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 are the same; and / or, along the width direction of the first electrode layer 5, the distance between the edge of the first electrode layer 5 and the edge of the first doped semiconductor layer 3 and the distance between the edge of the second electrode layer 6 and the edge of the second doped semiconductor layer 7 are the same, which is also within the protection scope of the present application.

[0119] In some embodiments, the width of the first electrode layer 5 is different from the width of the second electrode layer 6. Specifically, the second electrode layer 6 is used to extract the carriers collected by the second doped semiconductor layer 7, so it can be considered that the conductivity type of the second electrode layer 6 is the same as the conductivity type of the second doped semiconductor layer 7. In some embodiments, when the second doped semiconductor layer 7 and the second electrode layer 6 are both opposite to the conductivity type of the semiconductor substrate 1, the width of the first electrode layer 5 is less than the width of the second electrode layer 6. Among them, the second electrode layer 6 is opposite to the conductivity type of the semiconductor substrate 1, so the second electrode layer 6 is used to extract the minority carriers in the semiconductor substrate 1, and the larger the width of the second electrode layer 6, the more conducive to the extraction of minority carriers, and the more minority carriers are extracted, the more minority carrier collection efficiency is improved, and the more conducive to reducing recombination, which is conducive to improving the efficiency of solar cells.

[0120] Of course, the situation where the width of the first electrode layer 5 is the same as the width of the second electrode layer 6 is also within the protection scope of the present application.

[0121] In some embodiments, the width of the first doped semiconductor layer 3 is different from the width of the second doped semiconductor layer 7. In other embodiments, the second doped semiconductor layer 7 is of opposite conductivity type to the semiconductor substrate 1, and the width of the first doped semiconductor layer 3 is smaller than the width of the second doped semiconductor layer 7, that is, the width of the doped semiconductor layer of opposite type to the semiconductor substrate 1 is larger. Among them, the second doped semiconductor is of opposite conductivity type to the semiconductor substrate 1, so the second doped semiconductor is used to collect minority carriers in the semiconductor substrate 1, and the larger the width of the second doped semiconductor, the more conducive to the collection of minority carriers, and the more minority carriers are collected, the higher the minority carrier collection efficiency, which is more conducive to reducing recombination, and thus conducive to improving the efficiency of solar cells.

[0122] Of course, the situation where the width of the first doped semiconductor layer 3 is the same as the width of the second doped semiconductor layer 7 is also within the protection scope of the present application.

[0123] In the case where the conductivity type of the second doped semiconductor layer 7 is opposite to that of the semiconductor substrate 1, and the conductivity type of the first doped semiconductor layer 3 is the same as that of the semiconductor substrate 1, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is less than 1, and the distance between the edge of the first electrode layer 5 and the edge of the first doped semiconductor layer 3 is less than the distance between the edge of the second electrode layer 6 and the edge of the second doped semiconductor layer 7. In this way, the width of the second electrode layer 6 is smaller, that is, when the widths of the first electrode layer 5 and the second electrode layer 6 are equal, the width of the second electrode layer 6 is less than the width of the first doped semiconductor layer 3. Among them, the conductivity type of the second electrode layer 6 is opposite to that of the semiconductor substrate 1, so the second electrode layer 6 is used to extract minority carriers in the semiconductor substrate 1, and the width of the second electrode layer 6 is appropriately reduced compared to the width of the first electrode layer 5, while ensuring the minority carrier collection efficiency, the light blocking area can be reduced, so that more light is incident from the surface where the second electrode layer 6 is located into the semiconductor substrate 1.

[0124] Exemplarily, the distance between the edge of the first electrode layer 5 and the edge of the first doped semiconductor layer 3 is 0-20 μm; the distance between the edge of the second electrode layer 6 and the edge of the second doped semiconductor layer 7 is 0-40 μm.

[0125] In addition, along the width direction of the second doped semiconductor layer 7, the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 is 0.6-1.1. In this way, the second electrode layer 6 covers a larger area of ​​the second doped semiconductor layer 7, and when the light passing through the semiconductor substrate 1 is irradiated to the second electrode layer 6, it will be reflected back to the semiconductor substrate 1 by the second electrode layer 6, so that the semiconductor substrate 1 absorbs the light for the second time, thereby further improving the absorption and utilization rate of the solar cell for light and improving the photoelectric conversion efficiency. Exemplarily, the ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 is 0.65, 0.75, 0.85, 0.88, 0.92, 0.95, 0.98, 1.02 or 1.08.

[0126] The width of the first electrode layer 5 and the second electrode layer 6 and the width of the first doped semiconductor layer 3 and the second doped semiconductor layer 7 can be set according to the actual application scenario. For example, the width of the first doped semiconductor layer 3 and the second doped semiconductor layer 7 can be 50um-900um, and the width of the first electrode layer 5 and the second electrode layer 6 can be 40um-900um.

[0127] In some embodiments, the thickness of the second electrode layer 6 is 0.5 μm to 20 μm; and / or, the width of the second electrode layer 6 is 30 μm-450 μm. With this technical solution, the thickness of the second electrode layer 6 is set within a reasonable range of 0.5 μm to 20 μm, which can not only ensure the efficiency of extracting carriers using the second electrode layer 6, but also prevent the second electrode layer 6 from being too thick and causing waste of raw materials. In addition, the width of the second electrode layer 6 is set within a reasonable range of 30 μm-450 μm, which ensures that the contact area between the second electrode layer 6 and the second doped semiconductor layer 7 is large, reduces the contact resistance between the second electrode layer 6 and the second doped semiconductor layer 7, and prevents the width of the second electrode layer 6 from being too wide and contacting another doped semiconductor layer of the opposite conductivity type, resulting in leakage. When the thickness of the second electrode layer 6 is 0.5 μm to 20 μm, and the width of the second electrode layer 6 is 30 μm-450 μm, the second electrode layer 6 is wider and thinner, which can maximize the area of ​​the second electrode layer 6 without increasing the cost of raw materials, thereby reducing the transmission resistance. Exemplarily, the thickness of the second electrode layer 6 is 0.5 μm, 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 12 μm, 15 μm, 18 μm or 20 μm. The width of the second electrode layer 6 is 30 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 350 μm, 380 μm, 400 μm, 420 μm or 450 μm.

[0128] In addition, illustratively, the width of the second doped semiconductor layer 7 is 50 μm-450 μm. The width of the first doped semiconductor layer 3 is 50 μm-350 μm. With this technical solution, the second doped semiconductor layer 7 has a conductivity type opposite to that of the semiconductor substrate 1, and the width of the second doped semiconductor layer 7 can be wider than the width of the first doped semiconductor layer 3, that is, the second doped semiconductor layer 7 having a conductivity type opposite to that of the semiconductor substrate 1 has a larger contact area with the semiconductor substrate 1, so that the number of carriers collected by the first doped semiconductor layer 3 and the second doped semiconductor layer 7 can be balanced, current loss can be reduced, and photoelectric conversion efficiency can be improved.

[0129] For example, the width of the second doped semiconductor layer 7 is 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 350 μm, 380 μm, 400 μm, 420 μm or 450 μm. The width of the first doped semiconductor layer 3 can be 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm or 350 μm.

[0130] In other embodiments, along the width direction of the first doped semiconductor layer 3, the width of the first electrode layer 5 accounts for 80% to 100% of the width of the first doped semiconductor layer 3. Such a configuration can ensure that the first electrode layer 5 reflects the light passing through the semiconductor substrate 1 back into the semiconductor substrate 1, and can prevent the first electrode layer 5 from contacting with the second doped semiconductor layer 7 or the second electrode of the opposite conductivity type and causing leakage.

[0131] In addition, the thickness of the first electrode layer 5 is 0.5 μm to 20 μm; and / or, the width of the first electrode layer 5 is 40 μm-350 μm. With this technical solution, the thickness of the first electrode layer 5 is set within a reasonable range of 0.5 μm to 20 μm, which can not only ensure the efficiency of extracting carriers using the first electrode layer 5, but also prevent the first electrode layer 5 from being too thick and causing waste of raw materials. In addition, the width of the first electrode layer 5 is set within a reasonable range of 40 μm-350 μm, which ensures that the contact area between the first electrode layer 5 and the first doped semiconductor layer 3 is large, reduces the contact resistance between the first electrode layer 5 and the first doped semiconductor layer 3, and prevents the first electrode layer 5 from being too wide and contacting another doped semiconductor layer of the opposite conductive type, resulting in leakage. When the thickness of the first electrode layer 5 is 0.5 μm to 20 μm, and the width of the first electrode layer 5 is 40 μm-350 μm, the first electrode layer 5 is wider and thinner, which can maximize the area of ​​the first electrode layer 5 without increasing the cost of raw materials, thereby reducing the transmission resistance. Exemplarily, the thickness of the first electrode layer 5 is 0.5 μm, 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 12 μm, 15 μm, 18 μm or 20 μm. The width of the first electrode layer 5 is 30 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm or 350 μm.

[0132] In some examples, such as Figure 2 As shown, the solar cell also includes a dielectric layer 2 located between the first doped semiconductor layer 3 and the first electrode layer 5, and the dielectric layer 2 is provided with an opening that runs through its thickness, and the first electrode layer 5 is electrically connected to the first doped semiconductor layer 3 through the opening. On the one hand, the dielectric layer 2 can protect the surface of the cell and prevent water vapor and oxygen from penetrating into the interior of the cell, thereby avoiding the performance degradation of the cell due to oxidation or hydrolysis; on the other hand, the setting of the dielectric layer 2 can improve the utilization rate of light and reduce the surface recombination rate of the cell, thereby improving the photoelectric conversion efficiency of the cell. Among them, the opening of the dielectric layer 2 can be of any shape, such as square, circular, elliptical, etc.

[0133] The total area of ​​the openings corresponding to the dielectric layer 2 and the first electrode layer 5 accounts for 1% to 10% of the area of ​​the first electrode layer 5. Considering that if the total area of ​​the openings corresponding to the first electrode layer 5 is too small, the contact resistance between the first electrode layer 5 and the first doped semiconductor layer 3 increases, and the current loss is relatively large; if the total area of ​​the openings corresponding to the first electrode layer 5 is too large, the battery is easily damaged during the laser grooving process, and the more the first doped semiconductor layer 3 is exposed, the easier it is to recombine. Therefore, in this technical solution, the ratio of the total area of ​​the openings corresponding to the dielectric layer 2 and the first electrode layer 5 to the area of ​​the first electrode layer 5 is set within a reasonable range of 1% to 10%, so as to reduce the contact resistance between the first electrode layer 5 and the first doped semiconductor layer 3, reduce the damage of the laser to the battery, and reduce recombination. Exemplarily, the total area of ​​the openings corresponding to the dielectric layer 2 and the first electrode layer 5 accounts for 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, or 10% of the area of ​​the first electrode layer 5.

[0134] When the solar cell is a back contact cell, the second doped semiconductor layer 7 is also located on the second surface, and the dielectric layer 2 is also located between the second doped semiconductor layer 7 and the second electrode layer 6, that is, the dielectric layer 2 covers the entire first surface of the semiconductor substrate 1. The dielectric layer 2 and the second doped semiconductor layer 7 The corresponding area also has an opening, and the second electrode layer 6 is electrically connected to the second doped semiconductor layer 7 through the opening. The total area of ​​the openings corresponding to the dielectric layer 2 and the second doped semiconductor layer 7 is larger than the total area of ​​the openings corresponding to the dielectric layer 2 and the first doped semiconductor layer 3. In view of the different conductivity of the first doped semiconductor layer 3 and the second doped semiconductor layer 7, in this solution, the total area of ​​the openings corresponding to the second doped semiconductor layer 7 with smaller conductivity is set to be larger, so that the contact area between the second electrode layer 6 and the second doped semiconductor layer 7 is larger than the contact area between the first electrode layer 5 and the first doped semiconductor layer 3, thereby making the contact resistance between the second electrode layer 6 and the second doped semiconductor layer 7 equal to or closer to the contact resistance between the first electrode layer 5 and the first doped semiconductor layer 3, thereby reducing the current difference between the second electrode layer 6 and the second doped semiconductor layer 7 and between the first electrode layer 5 and the first doped semiconductor layer 3, reducing the current loss of the battery, and ensuring the performance of the battery.

[0135] In some examples, the total area of ​​the openings corresponding to the dielectric layer 2 and the second electrode layer 6 accounts for 1% to 10% of the area of ​​the second electrode layer 6. Considering that if the total area of ​​the openings corresponding to the second electrode layer 6 is too small, the contact resistance between the second electrode layer 6 and the second doped semiconductor layer 7 increases, and the current loss is relatively large; if the total area of ​​the openings corresponding to the second electrode layer 6 is too large, the battery is easily damaged during the laser grooving process, and the more the second doped semiconductor layer 7 is exposed, the easier it is to recombine. Therefore, in this technical solution, the ratio of the total area of ​​the openings corresponding to the dielectric layer 2 and the second electrode layer 6 to the area of ​​the second electrode layer 6 is set within a reasonable range of 1% to 10%, so as to reduce the contact resistance between the second electrode layer 6 and the second doped semiconductor layer 7, reduce the damage of the laser to the battery, and reduce recombination. Exemplarily, the total area of ​​the openings corresponding to the dielectric layer 2 and the second electrode layer 6 accounts for 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, or 10% of the area of ​​the second electrode layer 6.

[0136] When the solar cell is a back contact cell, the back contact cell may be a TBC (Tunnel Oxide Passivated Contact Back Contact), HPBC (Hybrid Passivated Back Contact) or a hybrid back contact cell. The light-facing surface of the back contact cell may be provided with a stacked passivation layer 10 and an anti-reflection layer 11, and the anti-reflection layer 11 is located on the side of the passivation layer 10 away from the semiconductor substrate 1. When the solar cell is a bifacial solar cell, the bifacial solar cell may be a TOPCon (Tunnel Oxide Passivated Contact) solar cell or a bifacial hybrid cell.

[0137] In some embodiments, a first interface layer 4 is disposed between the first doped semiconductor layer 3 and the semiconductor substrate 1 , and a second interface layer 8 is disposed between the second doped semiconductor layer 7 and the semiconductor substrate 1 .

[0138] For example, the first doped semiconductor layer 3 may be a doped polysilicon layer, and the first interface layer 4 may be a tunneling oxide layer. The second doped semiconductor layer 7 may be a doped polysilicon layer, and the second interface layer 8 may be a tunneling oxide layer.

[0139] Of course, the second doped semiconductor layer 7 may also include one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. In this case, the second interface layer 8 includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon layer. For example, Figure 7As shown, the first doped semiconductor layer 3 is a polycrystalline silicon layer, the first interface layer 4 is a tunneling oxide layer, the second doped semiconductor layer 7 is doped amorphous silicon, and the second interface layer 8 is an intrinsic amorphous silicon layer. In this solution, a transparent conductive layer 12 is further provided on the side of the first doped semiconductor layer 3 and the second doped semiconductor layer 7 away from the semiconductor substrate 1, and the transparent conductive layer 12 has an opening that penetrates the thickness thereof to prevent leakage between the first doped semiconductor layer 3 and the second doped semiconductor layer 7 through the transparent conductive layer 12. The first electrode layer 5 is provided on the side of the transparent conductive layer 12 away from the first doped semiconductor layer 3, and the second electrode layer 6 is provided on the side of the transparent conductive layer 12 away from the second doped semiconductor layer 7.

[0140] Embodiment 2:

[0141] like Figure 8 As shown, the second embodiment of the present application also provides another solar cell, which includes a semiconductor substrate 1, a first doped semiconductor layer 3, a first electrode layer 5, a second doped semiconductor layer 7 and a second electrode layer 6. The semiconductor substrate 1 has a first surface and a second surface relative to each other, and the first surface includes an alternately distributed first region, a second region and an isolation region 9 arranged between the first region and the second region. The first region and the second region can be alternately distributed in strips, or can be cross-distributed in a "F" shape. The first doped semiconductor layer 3 is arranged in the first region, and the first electrode layer 5 is arranged on the side of the first doped semiconductor layer 3 away from the semiconductor substrate 1. The second doped semiconductor layer 7 is at least arranged in the second region, and the second electrode layer 6 is arranged on the side of the second doped semiconductor layer 7 away from the semiconductor substrate 1. The second doped semiconductor layer 7 and the first doped semiconductor layer 3 have opposite conductivity types, so as to collect and guide out electrons and holes respectively, which is conducive to the formation of photocurrent.

[0142] Among them, along the width direction of the first electrode layer 5, the width of the first electrode layer 5 is greater than the width of the first doped semiconductor layer 3. And / or, along the width direction of the second doped semiconductor layer 7, the width of the second electrode layer 6 is greater than the width of the second doped semiconductor layer 7. With the above technical solution, the first electrode layer 5 can cover more of the first doped semiconductor layer 3, and / or, the second electrode layer 6 can cover more of the second doped semiconductor layer 7, and the light irradiated from the second surface to the semiconductor substrate 1 will have more light reflected back to the semiconductor substrate 1 when passing through the semiconductor substrate 1 to irradiate the first electrode layer 5 and the second electrode layer 6, so that the semiconductor substrate 1 absorbs more light for a second time, thereby improving the absorption and utilization rate of the solar cell for light.

[0143] In some embodiments, the ratio of the width of the first electrode layer 5 to the width of the first doped semiconductor layer 3 is greater than 1 and less than or equal to 1.1, and the orthographic projection of the first doped semiconductor layer 3 on the first surface is located inside the orthographic projection of the first electrode layer 5 on the first surface, that is, the edge of the first doped semiconductor layer 3 is located inside the edge of the first electrode layer 5. The ratio of the width of the second electrode layer 6 to the width of the second doped semiconductor layer 7 is greater than 1 and less than or equal to 1.1, and the orthographic projection of the second doped semiconductor layer 7 on the first surface is located inside the orthographic projection of the second electrode layer 6 on the first surface, that is, the edge of the second doped semiconductor layer 7 is located inside the edge of the second electrode layer 6. With this technical solution, the first electrode layer 5 can completely cover the first doped semiconductor layer 3, the second electrode layer 6 can completely cover the second doped semiconductor layer 7, the first electrode layer 5 and / or the second electrode layer 6 will extend into the isolation region 9, and can also reflect the light in the isolation region 9 back to the semiconductor substrate 1, further improving the absorption and utilization rate of the solar cell for light.

[0144] In another embodiment, the conductivity type of the second doped semiconductor layer 7 and the second electrode layer 6 is opposite to that of the semiconductor substrate 1, and along the width direction of the first doped semiconductor layer 3 or the second doped semiconductor layer 7, the distance that the edge of the second electrode layer 6 exceeds the edge of the second doped semiconductor layer 7 on the same side is greater than the distance that the edge of the first electrode layer 5 exceeds the edge of the first doped semiconductor layer 3 on the same side. In this way, the width of the second electrode layer 6 is made wider, wherein the conductivity type of the second electrode layer 6 is opposite to that of the semiconductor substrate 1, so the second electrode layer 6 is used to extract minority carriers in the semiconductor substrate 1, and the larger the width of the second electrode layer 6, the more conducive it is to extract minority carriers, and the more minority carriers are extracted, the more minority carrier collection efficiency is improved, and the more conducive it is to reduce recombination, thereby facilitating the improvement of the efficiency of solar cells.

[0145] Exemplarily, along the width direction of the first doped semiconductor layer 3, the distance that the edge of the first electrode layer 5 exceeds the edge of the first doped semiconductor layer 3 on the same side is 0 to 10 μm. Along the width direction of the second doped semiconductor layer 7, the distance that the edge of the second electrode layer 6 exceeds the edge of the second doped semiconductor layer 7 on the same side is 0 to 10 μm. Considering that the greater the distance that the edge of the first electrode layer 5 exceeds the edge of the first doped semiconductor layer 3 on the same side and the distance that the edge of the second electrode layer 6 exceeds the edge of the second doped semiconductor layer 7 on the same side, the closer the edge of the first electrode layer 5 is to the second doped semiconductor layer 7, and the closer the edge of the second electrode layer 6 is to the first doped semiconductor layer 3, it is easy to cause leakage. Therefore, this technical solution is adopted to ensure that a safe distance is reserved between the edge of the second electrode layer 6 and the first doped semiconductor layer 3 and between the edge of the first electrode layer 5 and the second doped semiconductor layer 7, so as to further reduce the risk of leakage. Optionally, the distance that the edge of the first electrode layer 5 exceeds the edge of the first doped semiconductor layer 3 on the same side is 0 to 6 μm.

[0146] For example, the edge of the first electrode layer 5 exceeds the edge of the first doped semiconductor layer 3 on the same side by a distance of 0, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm. The edge of the second electrode layer 6 exceeds the edge of the second doped semiconductor layer 7 on the same side by a distance of 0, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm.

[0147] In some embodiments, the width of the first electrode layer 5 is 50 μm-456 μm, so that the area of ​​the first electrode layer 5 is maximized, thereby reducing the transmission resistance. The width of the second electrode layer 6 is 50 μm-360 μm, so that the area of ​​the second electrode layer 6 is maximized, thereby reducing the transmission resistance. Exemplarily, the width of the first electrode layer 5 is 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 350 μm, 380 μm, 400 μm, 420 μm, 450 μm or 456 μm. The width of the first electrode layer 5 is 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 350 μm or 360 μm.

[0148] In addition, the width of the first doped semiconductor layer 3 and the second doped semiconductor layer 7 can be set according to the actual application scenario. Exemplarily, the width of the second doped semiconductor layer 7 is 50μm-450μm; the width of the first doped semiconductor layer 3 is 50μm-350μm. Among them, the width of the first doped semiconductor layer 3 is smaller than the width of the second doped semiconductor layer 7, and the second doped semiconductor is of opposite conductivity type to the semiconductor substrate 1, so the second doped semiconductor is used to collect minority carriers in the semiconductor substrate 1, and the larger the width of the second doped semiconductor, the more conducive to the collection of minority carriers, and the more minority carriers are collected, the higher the minority carrier collection efficiency, which is more conducive to reducing recombination, and thus conducive to improving the efficiency of solar cells.

[0149] For example, the width of the second doped semiconductor layer 7 is 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 350 μm, 380 μm, 400 μm, 420 μm or 450 μm. The width of the first doped semiconductor layer 3 can be 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm or 350 μm.

[0150] In some embodiments, the solar cell further includes a dielectric layer 2, which is located between the first doped semiconductor layer 3 and the first electrode layer 5 and between the second doped semiconductor layer 7 and the second electrode layer 6, and the dielectric layer 2 also covers the isolation region 9. The dielectric layer 2 is provided with an opening that runs through its thickness, the first electrode layer 5 is electrically connected to the first doped semiconductor layer 3 through the opening, the second electrode layer 6 is electrically connected to the second doped semiconductor layer 7 through the opening, and the isolation region 9 includes an isolation groove and a dielectric layer 2 covering the isolation groove, and the isolation groove is used to isolate the first doped semiconductor layer 3 and the second doped semiconductor layer 7 to prevent leakage. The function of the dielectric layer 2 and the shape of the opening are the same as those in the previous text and will not be repeated here.

[0151] Among them, Fig. 9 As shown, the first electrode layer 5 covers at least a portion of the dielectric layer 2 on the side wall of the isolation groove. The second electrode layer 6 covers at least a portion of the dielectric layer 2 on the side wall of the isolation groove. Specifically, the first electrode layer 5 extends continuously along the width direction to cover a portion of the dielectric layer 2 on the side wall of the isolation groove, and the second electrode layer 6 extends continuously along the width direction to cover a portion of the dielectric layer 2 on the side wall of the isolation groove. The distance W that the first electrode layer 5 extends along the side wall of the isolation groove, and the distance that the second electrode layer 6 extends along the side wall of the isolation groove can be set according to actual conditions. With this technical solution, light directed toward the side of the isolation groove can be reflected back to the semiconductor substrate 1 by the first electrode layer 5 or the second electrode layer 6, further improving the light absorption and utilization rate of the solar cell.

[0152] In some embodiments, a first interface layer 4 is disposed between the first doped semiconductor layer 3 and the semiconductor substrate 1 , and a second interface layer 8 is disposed between the second doped semiconductor layer 7 and the semiconductor substrate 1 .

[0153] In the case where the solar cell provided in the present application is a TBC cell, the semiconductor substrate 1 is an N-type substrate, the first doped semiconductor layer 3 includes N-type polycrystalline silicon, and a first tunneling oxide layer is provided between the first doped semiconductor layer 3 and the semiconductor substrate 1; the second doped semiconductor layer 7 includes P-type polycrystalline silicon, and a second tunneling oxide layer is provided between the second doped semiconductor layer 7 and the semiconductor substrate 1. In this way, the first doped semiconductor layer 3 and the first interface layer 4 form a tunneling oxide layer passivation contact, and the second doped semiconductor layer 7 and the second interface layer 8 also form a tunneling oxide layer passivation contact. The tunneling oxide layer passivation technology can form a tunneling film between the electrode layer and the semiconductor substrate 1, isolate the electrode layer from the semiconductor substrate 1, reduce the contact recombination loss, and the electron energy tunneling film will not affect the current transfer. At the same time, the passivation can bend the surface energy band, reduce the surface recombination loss of the silicon wafer, and can effectively improve the front passivation and metal contact problems.

[0154] Of course, the second doped semiconductor layer 7 may also include one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. In this case, the second interface layer 8 includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon layer. For example, Figure 7 As shown, the first doped semiconductor layer 3 is a polycrystalline silicon layer, the first interface layer 4 is a tunneling oxide layer, the second doped semiconductor layer 7 is doped amorphous silicon, and the second interface layer 8 is an intrinsic amorphous silicon layer. In this solution, a transparent conductive layer 12 is further provided on the side of the first doped semiconductor layer 3 and the second doped semiconductor layer 7 away from the semiconductor substrate 1, and the transparent conductive layer 12 has an opening that penetrates the thickness thereof to prevent leakage between the first doped semiconductor layer 3 and the second doped semiconductor layer 7 through the transparent conductive layer 12. The first electrode layer 5 is provided on the side of the transparent conductive layer 12 away from the first doped semiconductor layer 3, and the second electrode layer 6 is provided on the side of the transparent conductive layer 12 away from the second doped semiconductor layer 7.

[0155] The above is an introduction to Embodiment 1 and Embodiment 2. The following content is applicable to Embodiment 1 and Embodiment 2 and other embodiments.

[0156] On the premise that the solar cell is a back contact cell, the total area of ​​the openings corresponding to the dielectric layer 2 and the first electrode layer 5 is different from the total area of ​​the openings corresponding to the dielectric layer 2 and the second electrode layer 6. Specifically, the total area of ​​the openings corresponding to the dielectric layer 2 and the first electrode layer 5 can be greater than, equal to, or less than the total area of ​​the openings corresponding to the dielectric layer 2 and the second electrode layer 6. In this way, the number, shape, etc. of the openings corresponding to the dielectric layer 2 and the first electrode layer 5, and the number, shape, etc. of the openings corresponding to the dielectric layer 2 and the second electrode layer 6 can be set according to actual conditions.

[0157] In the case where the solar cell provided in the present application is a TBC cell, the conductivity type of the second doped semiconductor layer 7 is opposite to that of the semiconductor substrate 1. For example, the semiconductor substrate 1 is an N-type substrate, the first doped semiconductor layer 3 includes N-type polycrystalline silicon, and a first tunneling oxide layer is provided between the first doped semiconductor layer 3 and the semiconductor substrate 1; the second doped semiconductor layer 7 includes P-type polycrystalline silicon, and a second tunneling oxide layer is provided between the second doped semiconductor layer 7 and the semiconductor substrate 1. The TBC cell also includes a dielectric layer 2, which is located between the first electrode layer 5 and the first doped semiconductor layer 3 and between the second electrode layer 6 and the second doped semiconductor layer 7. The dielectric layer 2 is provided with an opening that penetrates its thickness, and the first electrode layer 5 is electrically connected to the first doped semiconductor layer 3 through the opening, and the second electrode layer 6 is electrically connected to the second doped semiconductor layer 7 through the opening. The total area of ​​the openings corresponding to the dielectric layer 2 and the first electrode layer 5 is smaller than the total area of ​​the openings corresponding to the dielectric layer 2 and the second electrode layer 6. By adopting the above technical solution, the total opening area corresponding to the narrower first electrode layer 5 is smaller, thereby improving the passivation effect, and the total opening area corresponding to the wider first electrode layer 5 is larger, thereby reducing the contact resistance between the first electrode layer 5 and the first doped semiconductor layer 3.

[0158] In some embodiments, an isolation region 9 is provided between the first doped semiconductor layer 3 and the second doped semiconductor layer 7 to prevent the first doped semiconductor layer 3 and the second doped semiconductor layer 7 from contacting and leaking electricity. The dielectric layer 2 is located between the first electrode layer 5 and the first doped semiconductor layer 3 and between the second electrode layer 6 and the second doped semiconductor layer 7, and the dielectric layer 2 covers the isolation region 9. The portion of the dielectric layer 2 covering the isolation region 9 includes at least one metal element in the first electrode layer 5 and / or includes at least one metal element in the second electrode layer 6, so that the metal elements located in the isolation region 9 can also reflect the light back to the semiconductor substrate 1 for secondary absorption, further improving the absorption and utilization rate of the solar cell for light.

[0159] In addition, the dielectric layer 2 is a composite film formed by stacking one or more of an aluminum oxide layer, a silicon nitride layer, and a silicon dioxide layer. For example, the dielectric layer 2 is a double-layer composite film formed by stacking an aluminum oxide layer and a silicon dioxide layer, or the dielectric layer 2 is a three-layer composite film formed by stacking an aluminum oxide layer, a silicon nitride layer, and a silicon dioxide layer in sequence in a direction away from the semiconductor substrate 1, or the dielectric layer 2 is a single-layer film.

[0160] When the dielectric layer 2 includes a silicon dioxide layer, the silicon dioxide layer can increase the short-circuit current Isc of the battery. The thickness of the silicon dioxide layer can be set according to actual conditions. Optionally, the thickness of the silicon dioxide layer is 50nm to 200nm, for example, 50nm, 50nm, 50nm, 50nm, 50nm, 50nm, 50nm, 50nm, 50nm, 50nm, 50nm, 50nm, 50nm, 200nm.

[0161] In another embodiment, if Fig.10 As shown, the first electrode layer 5 includes a first middle region 5b and two first edge regions 5a located on both sides of the first middle region 5b along the width direction. The reflectivity of the first edge region 5a is less than the reflectivity of the first middle region 5b. In this way, the light reflected by the first edge region 5a can be reduced, which is beneficial to further improve the absorption and utilization rate of light by the solar cell.

[0162] In addition, the roughness of the first edge region 5a is greater than the roughness of the first middle region 5b, that is, the roughness of the edges on both sides of the first electrode layer 5 is greater. During the packaging process, the contact area between the first edge region 5a of the first electrode layer 5 and the packaging material can be increased, and the adhesion between the first electrode layer 5 and the packaging material can be improved, thereby improving the firmness of the packaging of the first electrode layer 5.

[0163] Among them, the width of the first edge area 5a can be 0 to 100μm, for example, the width of the first edge area 5a is 0, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm or 100μm.

[0164] like Fig.11 As shown, the second electrode layer 6 includes a second middle region 6b and two second edge regions 6a located on both sides of the second middle region 6b along the width direction. The reflectivity of the second edge region 6a is less than the reflectivity of the second middle region 6b. In this way, the light reflected by the second edge region 6a can be reduced, which is beneficial to further improve the absorption and utilization rate of light by the solar cell.

[0165] In addition, the roughness of the second edge region 6a is greater than the roughness of the second middle region 6b, that is, the roughness of the edges on both sides of the second electrode layer 6 is greater. During the packaging process, the contact area between the second edge region 6a of the second electrode layer 6 and the packaging material can be increased, and the adhesion between the second electrode layer 6 and the packaging material can be improved, thereby improving the firmness of the second electrode layer 6 packaging.

[0166] Among them, the width of the second edge area 6a can be 0 to 200μm, for example, the width of the second edge area 6a is 0, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm or 200μm.

[0167] In other embodiments, the first electrode layer 5 and / or the second electrode layer 6 may include a first metal layer a and a second metal layer b, and the first metal layer a and the second metal layer b are stacked in sequence along the thickness direction of the semiconductor substrate 1, that is, the first metal layer a is located between the second metal layer b and the semiconductor substrate 1. In this way, a lower-priced material can be selected according to the functions required by the first metal layer a and the second metal layer b, thereby reducing costs. Among them, the second metal layer b can be used as a welding layer, and the second metal layer b can be made of a weldable metal material, and the first metal layer a can be made of a metal material with low cost and good conductivity. Compared with the prior art in which the electrode layer is an integrated structure, since the first metal layer a and the second metal layer b can be made of different materials as needed, different functions can be achieved.

[0168] It should be noted that, when the first electrode layer 5 and / or the second electrode layer 6 include a first metal layer a and a second metal layer b, the width of the first electrode layer 5 and / or the second electrode layer 6 described above refers to the width of the first metal layer a.

[0169] At the opening of the dielectric layer 2, the first metal layer a includes a hole e, and the hole e can be located near the boundary of the opening or inside the opening, that is, the first metal layer a is missing at the hole e. In this technical solution, the hole e included in the first metal layer a can release stress, preventing problems such as loose welding and warping of the battery cell caused by the release of stress from the electrode layer when welding the electrode layer to the interconnection, while saving the raw materials for forming the first metal layer a.

[0170] The roughness of the first electrode layer 5 and / or the second electrode layer 6 at the opening is greater than the roughness of the electrode layer at other positions. In this technical solution, the roughness of the electrode layer at the opening is larger. During the packaging process, the contact area between the electrode layer at the opening and the packaging material can be increased, and the adhesion between the electrode layer at the opening and the packaging material can be improved, thereby improving the firmness of the electrode layer packaging.

[0171] In addition, if Fig.13 , 14 and Fig.15As shown, along the extension direction of the first metal layer a, the side of the first metal layer a includes a plurality of concave curved surfaces, and the plurality of concave curved surfaces can be connected in sequence along the extension direction of the first metal layer a or can be arranged arbitrarily, that is, the plurality of concave curved surfaces can be located at any position of the side of the first metal layer a along the extension direction of the first metal layer a. The dimensions of the plurality of concave curved surfaces along the extension direction of the first metal layer a and the recessed depths of the plurality of concave curved surfaces can be the same or different. In the case of adopting the above technical solution, the concave curved surface is more conducive to reflecting the light irradiated to the side of the first metal layer a to the semiconductor substrate 1, which is conducive to the surface of the semiconductor substrate 1 receiving more reflected light, thereby improving the utilization rate of light. In addition, the edge where the concave curved surface is connected to the semiconductor substrate 1 is an arc edge, and the arc edges of the plurality of concave curved surfaces can increase the length of the bottom edge of the side of the first metal layer a, and can increase the transmission path and area of ​​the carriers at the bottom edge of the first metal layer a, thereby helping to reduce the contact resistance.

[0172] The concave curved surface includes an edge line d, that is, the position where two adjacent concave curved surfaces meet is the edge line d, and the edge line d can increase the contact area with the packaging film during the packaging process, thereby increasing the adhesion between the packaging film and the solar cell, and improving the structural stability of the packaging component. The orthographic projection of the edge line d on a plane perpendicular to the first surface and perpendicular to the extension direction of the first electrode layer 5 can be a straight line, a broken line, a curve or an irregular line.

[0173] Along the extension direction of the second electrode layer 6 , the side surface of the second electrode layer 6 may also include multiple concave curved surfaces. The arrangement and effect of the concave curved surfaces of the second electrode layer 6 are the same as those of the concave curved surfaces of the first electrode layer 5 , and will not be repeated here.

[0174] In the above embodiments, the concave curved surface may include a texture structure, and the texture structure may include stripes, arcs, circles, ellipses and / or polygons. The texture structure can increase the surface area of ​​the side wall of the electrode layer, thereby increasing the contact area with the EVA film and improving the bonding effect. Exemplarily, the texture structure may include vertical stripes c, and the angle between the vertical stripes c and the direction perpendicular to the first surface is 0° to 45°, for example, 0°, 5°, 10°, 15°, 20°, 25°, 30°, 35°, 40° or 45°. The orthographic projection of the stripes on a plane perpendicular to the first surface and parallel to the extension direction of the metal electrode is a straight line or a curve.

[0175] like Figure 4As shown, along the extension direction of the first electrode layer 5, the boundary of the first electrode layer 5 is wavy. It can be understood that the surface of the first electrode layer 5 close to the semiconductor substrate 1 and the surface of the first electrode layer 5 away from the semiconductor substrate 1 appear to extend along the wavy line as a whole in the orthographic projection on the semiconductor substrate 1. In this way, the boundary of the first electrode layer 5 includes a plurality of arcs, and the plurality of arcs are connected in sequence and extend in the direction of the wavy line. By adopting this technical solution, the overall extension length of the first electrode layer 5 can be increased, thereby increasing the transmission path and area of ​​the carriers in the first electrode layer 5, which is conducive to reducing the contact resistance.

[0176] The boundary of the first doped semiconductor layer 3 may also be wavy, that is, the surface of the first doped semiconductor layer 3 close to the semiconductor substrate 1 and the surface of the first doped semiconductor layer 3 away from the semiconductor substrate 1 appear to extend along the wavy line in the orthographic projection on the semiconductor substrate 1. By adopting this technical solution, the overall extension length of the first doped semiconductor layer 3 can be increased, thereby increasing the transmission path and area of ​​the carriers in the first doped semiconductor layer 3, which is conducive to reducing the contact resistance.

[0177] Of course, the boundary of the second electrode layer 6 may also be wavy, and the boundary of the second doped semiconductor layer 7 may also be wavy, and their functions are the same as the wavy boundary of the first electrode layer 5 and the second doped semiconductor layer 7, which will not be repeated here.

[0178] Along the width direction of the first electrode layer 5, the width of the second metal layer b is greater than the width of the surface of the first metal layer a away from the semiconductor substrate 1, that is, the width of the second metal layer b is greater than the width of the upper surface of the first metal layer a. This arrangement can ensure that there is a larger contact area between the second metal layer b and the welding strip or other interconnects during the welding process, thereby improving the welding efficiency. Alternatively, the width of the second metal layer b is equal to the width of the surface of the first metal layer a away from the semiconductor substrate 1, that is, the width of the second metal layer b is equal to the width of the upper surface of the first metal layer a. This arrangement can prevent the second metal layer b from blocking the first metal layer a, avoid affecting the absorption of light by the first metal layer a, and avoid the first metal layer a reflecting light to the semiconductor substrate 1. Of course, the width of the second metal layer b can also be less than the width of the surface of the first metal layer a away from the semiconductor substrate 1, that is, the width of the second metal layer b is less than the width of the upper surface of the first metal layer a, which is not limited here.

[0179] In the case where the width of the second metal layer b is greater than the width of the first metal layer a away from the surface of the semiconductor substrate 1, the portion of the second metal layer b that exceeds the first metal layer a is parallel to the first surface; or Fig.12 As shown, the portion of the second metal layer b that exceeds the first metal layer a gradually tilts toward the direction close to the first surface; or, as Figure 14-16As shown, the portion of the second metal layer b that exceeds the first metal layer a gradually rises in a direction away from the first surface.

[0180] Along the direction close to the semiconductor substrate 1, the width of the first metal layer a gradually increases, the width of the lower surface of the first metal layer a close to the semiconductor substrate 1 is the largest, and the width of the upper surface of the first metal layer a away from the semiconductor substrate 1 is the smallest. In this way, the contact area between the first metal layer a and the semiconductor substrate 1 is large, which increases the adhesion between the first metal layer a and the semiconductor substrate 1 and helps to reduce the contact resistance. In addition, the side of the first metal layer a will not be blocked by the upper surface of the first metal layer a, so that more light can be irradiated to the side of the first metal layer a, and then more light can be reflected to the semiconductor substrate 1, thereby improving the utilization rate of light.

[0181] In some embodiments, the difference between the standard electrode potential of the first metal layer a and the standard electrode potential of the second metal layer b is 0.1V to 3.5V, and the standard electrode potential of the first metal layer a is less than the standard electrode potential of the second metal layer b. In this way, during the wet etching process, the etching solution preferentially corrodes the first metal layer a, forming the shape of the side surface of the first metal layer a while ensuring that the second metal layer b is not severely corroded.

[0182] From the material point of view, the first metal layer a may include one or more of Al, Zn, Fe, Co, Mg, Cu, Ag and their alloys. The second metal layer b may include one or more of Cu, Ni, Cr, Ti, W, Mo, Ag, Sn and their alloys. It can be understood that the materials of the first metal layer a and the second metal layer b are different, and the materials of the first metal layer a and the second metal layer b cannot be Cu or Ag at the same time.

[0183] In terms of manufacturing process, the first metal layer a and the second metal layer b can be formed by LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), etc., so that the first metal layer a and the second metal layer b have a high density, which is beneficial to improve the welding effect of the second metal layer b when the second metal layer b is used as a welding layer. Compared with the electrodes formed by printing in the prior art, the first metal layer a and the second metal layer b in the electrode layer formed by the above method have clear edges of the electrode layer and less conductive waste, which avoids the conductive waste blocking the light and affecting the collection of carriers. The above-mentioned methods can be used to first form a first metal layer a and a second metal layer b that are set as a whole layer, and then a wet etching process can be used to etch to form a patterned first metal layer a and a second metal layer b, and the side of the first metal layer a can be processed to form multiple concave surfaces.

[0184] It can be understood that the first metal layer a and the second metal layer b can be formed by the same process. For example, the first metal layer a and the second metal layer b can be both formed by magnetron sputtering or both formed by evaporation; alternatively, the first metal layer a and the second metal layer b can be formed by different processes. For example, the first metal layer a is formed by magnetron sputtering and the second metal layer b is formed by evaporation, or the first metal layer a is formed by evaporation and the second metal layer b is formed by magnetron sputtering.

[0185] The thickness of the second metal layer b is less than or equal to 10% of the thickness of the first metal layer a, so as to ensure that the second metal layer b is firmly welded to the welding strip or the interconnection part, and to facilitate patterning of the second metal layer b, for example, to make the laser selectivity used for laser patterning of the second metal layer b more. For example, the thickness of the second metal layer b is 10%, 9%, 8%, 7%, 6% or 5% of the thickness of the first metal layer a.

[0186] In another specific embodiment, the first metal layer a may include multiple first sub-metal layers stacked along the thickness direction of the semiconductor substrate 1. In this way, multiple first sub-metal layers can be processed in sequence. The materials of the multiple first sub-metal layers can be different, and the thicknesses of the multiple first sub-metal layers can be the same or different. The number of layers, thickness and material of the first sub-metal layer can be set according to actual conditions. Specifically, the first sub-metal layer can be 2 layers, 3 layers, 4 layers or more layers. With this technical solution, different purposes can be achieved by reasonably selecting the materials of each first sub-metal layer in the first metal layer a. For example, by selecting the first sub-metal layer, the metal in the second metal layer b is prevented from diffusing into the semiconductor substrate 1, resulting in a decrease in the short-circuit current density (Jsc); at the same time, multiple first sub-metal layers can reduce the stress of the entire electrode layer and reduce the warpage.

[0187] As a possible implementation, the solar cell further includes a buffer layer between the first electrode layer 5 and / or the second electrode layer 6 and the semiconductor substrate 1 , wherein the buffer layer facilitates the deposition of the first metal layer a and improves the adhesion between the electrode layer and the semiconductor substrate 1 .

[0188] In terms of materials, the buffer layer may include one or more of metal oxides, metal nitrides, metal fluorides, metal silicides and metals. Among them, metal oxides include AZO, TiO X 、Cu2O、MgO X 、TaO X , VO X CrO X , SnO2, B:ZnO (boron-doped zinc oxide), CdO X and MoO X One or more of. Metal nitrides include TiN X and TiO X The metal fluoride includes one or more of MgF2, LiF, YF3 and CeF3. The metal silicide includes one or more of TiSi2, TaSi2, MOSi2, CoSi2, Ni2Si and WSi2. The metal includes one or more of Ni, Ti, Cr, Cu, W, Mo and Ag. The material of the buffer layer can be selected according to actual needs.

[0189] The buffer layer may be a single-layer structure, or the buffer layer may include multiple sub-buffer layers stacked along the thickness direction of the semiconductor substrate 1. Multiple sub-buffer layers can reduce the stress of the entire electrode layer and reduce the warpage. The materials of the multiple sub-buffer layers may be different, and the thickness, refractive index or conductivity of the sub-buffer layers may be the same or different.

[0190] If the thickness of the buffer layer is too thick, the carrier transmission efficiency may be reduced, so the thickness of the buffer layer is 5nm to 300nm; and / or, the thickness of the buffer layer is less than or equal to 10% of the thickness of the first metal layer a to ensure that the carrier transmission efficiency is reduced. Exemplarily, the thickness of the buffer layer is 5nm, 50nm, 100nm, 150nm, 200nm, 250nm or 300nm. Alternatively, the thickness of the buffer layer is 10%, 9%, 8%, 7% or 6% of the thickness of the first metal layer a, etc.

[0191] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0192] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; A first doped semiconductor layer, disposed on the first surface; A first electrode layer, disposed on a side of the first doped semiconductor layer away from the semiconductor substrate; Along the width direction of the first electrode layer, a ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is greater than or equal to 0.1 and less than or equal to 1.

1.

2. The solar cell according to claim 1, characterized in that The ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is 0.6-1.

1.

3. The solar cell according to claim 1, characterized in that A ratio of a width of the first electrode layer to a width of the first doped semiconductor layer is less than or equal to 1; The orthographic projection of the first electrode layer on the first doped semiconductor layer is located within the boundary of the first doped semiconductor layer, and along the width direction of the first electrode layer, the distance between the edge of the first electrode layer and the edge of the first doped semiconductor layer on the same side is 0 to 40 μm.

4. The solar cell according to claim 3, characterized in that: Along the width direction of the first electrode layer, the absolute value of the difference between the distances between any two points on the edge of the first electrode layer and the edge of the first doped semiconductor layer on the same side is ΔD1, and 0≤ΔD1≤40 μm.

5. The solar cell according to claim 1, characterized in that: A ratio of a width of the first electrode layer to a width of the first doped semiconductor layer is greater than 1 and less than or equal to 1.1; An orthographic projection of the first doped semiconductor layer on the first surface is located inside an orthographic projection of the first electrode layer on the first surface.

6. The solar cell according to claim 5, characterized in that: Along the width direction of the first doped semiconductor layer, the distance that the edge of the first electrode layer exceeds the edge of the first doped semiconductor layer on the same side is 0-10 μm.

7. The solar cell according to claim 1, characterized in that The solar cell further comprises a second doped semiconductor layer and a second electrode layer, wherein the second electrode layer is arranged on a side of the second doped semiconductor layer away from the semiconductor substrate; the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer; The second doped semiconductor layers and the first doped semiconductor layers are alternately arranged on the first surface; Wherein, a ratio of a width of the second electrode layer to a width of the second doped semiconductor layer is greater than or equal to 0.1 and less than or equal to 1.

1.

8. The solar cell according to claim 7, characterized in that: The ratio of the width of the second electrode layer to the width of the second doped semiconductor layer is 0.6-1.

1.

9. The solar cell according to claim 7, characterized in that: A ratio of a width of the second electrode layer to a width of the second doped semiconductor layer is less than or equal to 1; The projection of the second electrode layer on the second doped semiconductor layer is located within the boundary of the second doped semiconductor layer, and along the width direction of the second electrode layer, the distance between the edge of the second electrode layer and the edge of the second doped semiconductor layer on the same side is 0 to 40 μm.

10. The solar cell according to claim 9, characterized in that: Along the width direction of the second electrode layer, the absolute value of the difference in distance between any two points on the edge of the second electrode layer and the edge of the second doped semiconductor layer on the same side is ΔD2, and 0≤ΔD2≤40 μm.

11. The solar cell according to claim 7, characterized in that: A ratio of a width of the second electrode layer to a width of the second doped semiconductor layer is greater than 1 and less than or equal to 1.1; An orthographic projection of the second doped semiconductor layer on the first surface is located inside an orthographic projection of the second electrode layer on the first surface.

12. The solar cell according to claim 11, characterized in that: Along the width direction of the second doped semiconductor layer, the distance that the edge of the second electrode layer exceeds the edge of the second doped semiconductor layer on the same side is 0-10 μm.

13. The solar cell according to claim 7, characterized in that: A ratio of a width of the first electrode layer to a width of the first doped semiconductor layer is different from a ratio of a width of the second electrode layer to a width of the second doped semiconductor layer; Or, the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is less than 1, and along the width direction of the first electrode layer, the distance between the edge of the first electrode layer and the edge of the first doped semiconductor layer is different from the distance between the edge of the second electrode layer and the edge of the second doped semiconductor layer; Or, the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is greater than 1 and less than or equal to 1.1, and along the width direction of the first electrode layer, the distance that the edge of the first electrode layer exceeds the edge of the first doped semiconductor layer on the same side is different from the distance that the edge of the second electrode layer exceeds the edge of the second doped semiconductor layer on the same side; Or, the width of the first electrode layer is different from the width of the second electrode layer; Alternatively, the width of the first doped semiconductor layer is different from the width of the second doped semiconductor layer.

14. The solar cell according to claim 7, characterized in that: The conductivity type of the second doped semiconductor layer is opposite to that of the semiconductor substrate; Along the width direction of the first electrode layer or the second electrode layer, a ratio of a width of the first electrode layer to a width of the first doped semiconductor layer is smaller than a ratio of a width of the second electrode layer to a width of the second doped semiconductor layer; and / or, the width of the first electrode layer is smaller than the width of the second electrode layer; and / or, the width of the first doped semiconductor layer is smaller than the width of the second doped semiconductor layer; And / or, when the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is less than 1, the distance between the edge of the first electrode layer and the edge of the first doped semiconductor layer is smaller than the distance between the edge of the second electrode layer and the edge of the second doped semiconductor layer; when the ratio of the width of the first electrode layer to the width of the first doped semiconductor layer is greater than 1 and less than or equal to 1.1, along the width direction of the first doped semiconductor layer or the second doped semiconductor layer, the distance that the edge of the second electrode layer exceeds the edge of the second doped semiconductor layer on the same side is greater than the distance that the edge of the first electrode layer exceeds the edge of the first doped semiconductor layer on the same side.

15. The solar cell according to claim 1, characterized in that: Along the width direction of the first doped semiconductor layer, the width of the first electrode layer accounts for 80% to 100% of the width of the first doped semiconductor layer; and / or the thickness of the first electrode layer is 0.5μm to 20μm; and / or the width of the first electrode layer is 40μm-350μm; and / or the width of the first doped semiconductor layer is 50μm-350μm.

16. The solar cell according to claim 1, characterized in that The solar cell further comprises a dielectric layer located between the first doped semiconductor layer and the first electrode layer, the dielectric layer is provided with an opening penetrating the thickness thereof, and the first electrode layer is electrically connected to the first doped semiconductor layer through the opening; The total area of ​​the openings corresponding to the dielectric layer and the first electrode layer accounts for 1% to 10% of the area of ​​the first electrode layer.

17. The solar cell according to claim 7, characterized in that: The second doped semiconductor layers and the first doped semiconductor layers are alternately arranged on the first surface, and the conductivity type of the second doped semiconductor layers is opposite to that of the semiconductor substrate; The solar cell further comprises a dielectric layer covering the first surface, the dielectric layer being located between the first doped semiconductor layer and the first electrode layer and between the second doped semiconductor layer and the second electrode layer, the dielectric layer being provided with an opening penetrating the thickness thereof, the first electrode layer being electrically connected to the first doped semiconductor layer through the opening, and the second electrode layer being electrically connected to the second doped semiconductor layer through the opening; A total area of ​​the openings corresponding to the dielectric layer and the first electrode layer is smaller than a total area of ​​the openings corresponding to the dielectric layer and the second electrode layer.

18. The solar cell according to claim 7, characterized in that: The solar cell further comprises a dielectric layer located between the first doped semiconductor layer and the first electrode layer, and between the second doped semiconductor layer and the second electrode layer, the dielectric layer is provided with an opening penetrating the thickness thereof, the first electrode layer is electrically connected to the first doped semiconductor layer through the opening, and the second electrode layer is electrically connected to the second doped semiconductor layer through the opening; The second doped semiconductor layers and the first doped semiconductor layers are alternately arranged on the first surface, an isolation region is provided between the first doped semiconductor layers and the second doped semiconductor layers, and a portion of the dielectric layer covering the isolation region includes at least one metal element in the first electrode layer, and / or includes at least one metal element in the second electrode layer.

19. The solar cell according to claim 7, characterized in that: The second doped semiconductor layers and the first doped semiconductor layers are alternately arranged on the first surface, an isolation groove is provided between the first doped semiconductor layer and the second doped semiconductor layer, the solar cell further comprises a dielectric layer, the dielectric layer is located between the first doped semiconductor layer and the first electrode layer and between the second doped semiconductor layer and the second electrode layer, and covers the isolation groove, the dielectric layer is provided with an opening penetrating the thickness thereof, the first electrode layer is electrically connected to the first doped semiconductor layer through the opening, and the second electrode layer is electrically connected to the second doped semiconductor layer through the opening; The first electrode layer covers at least a portion of the dielectric layer located on the sidewall of the isolation trench; And / or, the second electrode layer covers at least a portion of the dielectric layer located on the sidewall of the isolation trench.

20. The solar cell according to claim 1, characterized in that The first electrode layer includes a first metal layer and a second metal layer stacked in sequence along the thickness direction of the semiconductor substrate, and the first metal layer is closer to the semiconductor substrate than the second metal layer; and the width of the second metal layer is greater than the width of the first metal layer; The portion of the second metal layer extending beyond the first metal layer is parallel to the first surface; or, the portion of the second metal layer extending beyond the first metal layer gradually tilts toward the first surface; or, the portion of the second metal layer extending beyond the first metal layer gradually warps away from the first surface.

21. The solar cell according to claim 20, characterized in that Along the extension direction of the first electrode layer, the side surface of the first metal layer includes a plurality of concave curved surfaces; The concave curved surface includes an edge line.

22. The solar cell according to claim 1, characterized in that The first electrode layer includes a first middle region and two first edge regions located on both sides of the first middle region along the width direction, the reflectivity of the first edge region is smaller than the reflectivity of the first middle region, and / or the roughness of the first edge region is smaller than the roughness of the first middle region.

23. The solar cell according to claim 1, characterized in that Along the extension direction of the first electrode layer, the boundary of the first electrode layer is wavy; And / or, a boundary of the first doped semiconductor layer is wavy.

24. A photovoltaic module, characterized in that: The method comprises a plurality of solar cells according to any one of claims 1 to 23.

Images