Laminated solar cell and preparation method

Abstract

The invention relates to the technical field of solar cells, and particularly provides a laminated solar cell and a preparation method. The laminated solar cell of the present invention comprises: a substrate; the crystalline silicon battery unit is formed on the substrate; and a perovskite cell unit formed on the crystalline silicon cell unit. Wherein the perovskite cell unit comprises a perovskite light absorption layer, and the area of the orthographic projection of the perovskite light absorption layer on the substrate is smaller than the area of the orthographic projection of the crystalline silicon cell unit on the substrate. By improving the quality of the perovskite thin film prepared by a coating method, the overall quality of the perovskite cell unit is improved, the performance of the laminated cell is optimized, and the preparation method is suitable for mass production.

Description

Technical Field

[0001] The invention relates to the technical field of solar cells, and specifically provides a stacked solar cell and a preparation method thereof. Background Art

[0002] Perovskite-crystalline silicon two-terminal tandem solar cells, referred to as tandem cells, are considered to be a new photovoltaic technology that is expected to replace traditional crystalline silicon solar cells in the future due to their high efficiency and low cost. In this cell preparation process, the preparation of a perovskite layer on a silicon wafer is a key step in the manufacture of tandem cells. At present, the coating method is considered to be an effective means to achieve the deposition of a high-quality perovskite layer on a velvet-topographic silicon substrate. However, at the full silicon wafer size, the full-area coating quality of the coating method still needs to be further improved, because some areas may be uneven, thus affecting the efficiency of the overall tandem cell. Specifically, during the coating process, the quality may be poor when the coating blade just starts to contact the substrate and at the end of the coating.

[0003] Currently, full-area perovskite films are prepared by vacuum thermal evaporation or evaporation combined with inkjet printing. However, the vacuum method has high preparation costs, high energy consumption, and low material utilization; while inkjet printing has the problem of material pore blocking, which also affects the quality and production efficiency of preparing full-area films. Therefore, how to use the coating method to efficiently prepare perovskite films and improve the efficiency of stacked cells is a key problem that needs to be solved at present. Summary of the invention

[0004] The present invention provides a tandem solar cell and a preparation method thereof, which improves the quality of a perovskite film prepared by a coating method, thereby improving the overall quality of a perovskite cell unit and optimizing the performance of the tandem cell, and the preparation method is suitable for mass production.

[0005] In a first aspect, the present invention provides a tandem solar cell, comprising:

[0006] substrate;

[0007] A crystalline silicon battery cell formed on the substrate; and

[0008] a perovskite cell formed on the crystalline silicon cell;

[0009] The perovskite battery unit includes a perovskite light absorbing layer, and the area of ​​the orthographic projection of the perovskite light absorbing layer on the substrate is smaller than the area of ​​the orthographic projection of the crystalline silicon battery unit on the substrate.

[0010] Further, there is a first distance between the perovskite light absorption layer and the first side surface of the crystalline silicon battery unit;

[0011] There is a second distance between the perovskite light absorbing layer and the second side of the crystalline silicon battery unit, wherein the second side is opposite to the first side.

[0012] Furthermore, the second spacing is smaller than the first spacing.

[0013] Further, there is a third distance between the perovskite light absorption layer and the third side of the crystalline silicon battery unit, and there is a fourth distance between the perovskite light absorption layer and the fourth side of the crystalline silicon battery unit;

[0014] The third spacing and the fourth spacing are both smaller than the second spacing; wherein the third side surface is opposite to the fourth side surface, the third side surface is adjacent to the first side surface and the second side surface respectively, and the fourth side surface is adjacent to the first side surface and the second side surface respectively.

[0015] Furthermore, the crystalline silicon battery unit is a bottom battery, and the perovskite battery unit is a top battery.

[0016] Furthermore, the crystalline silicon battery unit includes a first electrode layer, a first transparent conductive layer, a first type doped silicon wafer layer, a first intrinsic silicon wafer layer, a single crystal silicon wafer layer, a second intrinsic silicon wafer layer and a second type doped silicon wafer layer, which are formed in sequence from bottom to top; wherein the second type is opposite to the first type; and the single crystal silicon wafer layer is the substrate.

[0017] Furthermore, the perovskite battery unit is formed from bottom to top in sequence of a first charge transport layer, a perovskite light absorption layer, a second charge transport layer, a second transparent conductive layer and a second electrode layer.

[0018] Furthermore, the battery also includes a composite layer formed between the crystalline silicon battery unit and the perovskite battery unit.

[0019] Furthermore, the orthographic projection areas of the perovskite light absorbing layer, the composite layer, the first transparent conductive layer and the second transparent conductive layer on the substrate are the same.

[0020] Furthermore, the orthographic projection areas of the first charge transport layer, the perovskite light absorbing layer, the second charge transport layer, the first transparent conductive layer, the composite layer, the first transparent conductive layer and the second transparent conductive layer on the substrate are the same.

[0021] Furthermore, the perovskite battery cell further includes a buffer layer, which is formed between the second charge transport layer and the second transparent conductive layer.

[0022] In a second aspect, the present invention provides a method for preparing a tandem solar cell, comprising:

[0023] forming a crystalline silicon battery cell on a substrate;

[0024] A perovskite cell unit is formed on the crystalline silicon cell unit; wherein the perovskite light absorption layer in the perovskite cell unit is formed by a coating method, and the area of ​​the orthographic projection of the perovskite light absorption layer on the substrate is smaller than the area of ​​the orthographic projection of the crystalline silicon cell unit on the substrate.

[0025] Further, forming a crystalline silicon battery unit on a substrate comprises:

[0026] Using single crystal silicon wafer as substrate;

[0027] Forming a second intrinsic silicon layer and a second type doped silicon layer on the first surface of the substrate in sequence from bottom to top;

[0028] A first intrinsic silicon layer, a first type doped silicon layer, a first transparent conductive layer and a first electrode layer are sequentially formed on the second surface of the crystalline silicon layer from top to bottom.

[0029] Furthermore, the first type doped silicon wafer layer includes a P-type silicon wafer layer; and the second type doped silicon wafer layer includes an N-type silicon wafer layer.

[0030] Further, forming a perovskite battery cell on the crystalline silicon battery cell comprises:

[0031] On the crystalline silicon battery unit, a first charge transport layer, a perovskite light absorption layer, a second charge transport layer, a second transparent conductive layer and a second electrode layer are formed in sequence from bottom to top.

[0032] Furthermore, the method further comprises:

[0033] A buffer layer is formed between the second charge transport layer and the second transparent conductive layer.

[0034] Furthermore, the method further comprises:

[0035] A composite layer is formed between the crystalline silicon battery unit and the perovskite battery unit.

[0036] Furthermore, the method further comprises:

[0037] The composite layer, the first transparent conductive layer and the second transparent conductive layer are patterned respectively, so that the areas of the orthographic projections of the patterned composite structure, the first transparent conductive structure and the second transparent conductive structure on the substrate overlap.

[0038] The above one or more technical solutions of the present invention have at least one or more of the following beneficial effects:

[0039] In the technical solution of the present invention, by reducing the size of the perovskite light-absorbing layer, it can be effectively ensured that the remaining perovskite layer is the most uniform part during the coating process. In this way, not only the performance of the battery is improved, but also the overall battery structure is optimized, so that the battery can show better stability and efficiency in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The disclosure of the present invention will become more easily understood with reference to the accompanying drawings. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In addition, similar numbers in the figures are used to represent similar components, among which:

[0041] Figure 1 is a schematic diagram of the main structure of a tandem solar cell in which only the area of ​​the perovskite light-absorbing layer is reduced according to an embodiment of the present invention;

[0042] Figure 2 is a schematic diagram of the spacing L1-L4 according to an embodiment of the present invention;

[0043] Figure 3 It is a schematic diagram of the main structure of a tandem solar cell in which the areas of the perovskite light-absorbing layer, the composite layer and the transparent conductive layer are simultaneously reduced according to an embodiment of the present invention;

[0044] Figure 4 It is a schematic diagram of the main structure of a stacked solar cell in which the composite layer to the second transparent conductive layer and the first transparent conductive layer are simultaneously reduced according to an embodiment of the present invention;

[0045] Figure 5 is a schematic diagram of the main steps of a method for preparing a tandem solar cell according to an embodiment of the present invention;

[0046] Figure 6 is a schematic structural diagram of a mask plate according to an embodiment of the present invention;

[0047] Figure 7 Schematic diagram of the structure of a cover plate according to an embodiment of the present invention.

[0048] Reference numerals list

[0049] 1 substrate; 2 second intrinsic silicon wafer layer; 3 second type doped silicon wafer layer; 4 first intrinsic silicon wafer layer; 5 first type doped silicon wafer layer; 6 first transparent conductive layer; 7 first electrode layer; 8 first charge transport layer; 9 perovskite light absorption layer; 10 second charge transport layer; 11 second transparent conductive layer; 12 second electrode layer; 13 composite layer; 14 buffer layer. DETAILED DESCRIPTION

[0050] Some embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present invention and are not intended to limit the protection scope of the present invention.

[0051] Reference Figure 1 and Figure 3-4 The present invention provides a tandem solar cell, comprising:

[0052] Substrate 1;

[0053] A crystalline silicon battery cell formed on the substrate; and

[0054] a perovskite cell formed on the crystalline silicon cell;

[0055] The perovskite battery unit comprises a perovskite light absorbing layer 9, and the area of ​​the orthographic projection of the perovskite light absorbing layer 9 on the substrate is smaller than the area of ​​the orthographic projection of the crystalline silicon battery unit on the substrate.

[0056] The perovskite light absorption layer is the core of the perovskite cell unit, responsible for light absorption and charge generation. The core structure of the perovskite solar cell is composed of perovskite materials. Perovskite is a mineral with a special crystal structure, and its chemical formula is ABX3. In the application of solar cells, A usually represents organic cations, B is metal ions, and X is halogen ions. This structure gives perovskite excellent light absorption and charge transfer properties.

[0057] One of the three major challenges currently hindering the development of perovskite cells is large-scale production. The coating and printing of perovskite materials have made rapid progress, which is of great commercial significance for the large-scale production of perovskite cells.

[0058] The coating process is relatively simple, easy to operate, and suitable for large-scale production. The coating method can quickly deposit perovskite films and improve production efficiency. The coating process does not require complex equipment and high investment, and can significantly reduce production costs compared to other deposition methods. The coating process is suitable for large-area deposition of perovskite films, which is conducive to the preparation of large-size perovskite cells and improves the output power of the cells. The coating process is compatible with existing coating, laser, packaging and other equipment, and can be easily integrated into the production line of perovskite cells.

[0059] Therefore, by adopting the coating method to prepare the perovskite battery unit, the mass production of the stacked battery can be promoted. During the coating process, when the blade moves on the silicon bottom battery and performs coating, the problem of unsatisfactory peripheral coating quality often occurs. In order to solve this problem, the present invention particularly retains the part with better coating effect, so that the orthographic projection area of ​​the perovskite light absorbing layer on the substrate is smaller than the orthographic projection area of ​​the crystalline silicon battery unit on the substrate. In this way, by optimizing the structure of the stacked battery, the quality of the perovskite battery unit can be effectively improved, thereby improving the overall performance and production efficiency of the stacked battery.

[0060] In one embodiment, referring to Figure 2 , there is a first distance L1 between the perovskite light absorption layer and the first side surface of the crystalline silicon battery unit;

[0061] There is a second distance L2 between the perovskite light absorbing layer and the second side surface of the crystalline silicon battery unit, wherein the second side surface is opposite to the first side surface.

[0062] In the process of forming the perovskite light-absorbing layer on the support through the coating process, the coating blade performs coating operation along the X-axis direction. First, the blade contacts the first side of the support, and then continues coating along the X-axis direction until it finally leaves the support. The side where the blade leaves the support is called the second side.

[0063] When coating, especially when coating a large area, the uniformity of the coating at the beginning and end is often poorer than that in the middle. Especially at the beginning of coating, where the blade first contacts the substrate, the quality of the coating at the beginning is often unstable. This may be because at the beginning of coating, the solution has not yet reached a completely uniform distribution state, or the coating equipment has not yet fully entered the optimal working state, resulting in large fluctuations in the quality of the coating at the beginning. At the end of coating, the quality of the coating end may also decrease due to factors such as the gradual reduction in the amount of slurry, possible changes in the coating speed, or inertia when the equipment stops working.

[0064] The stacked battery of the present invention removes the uneven parts in the perovskite coating process, so the battery structure formed is that the area of ​​the orthographic projection of the perovskite light absorbing layer on the substrate is smaller than the area of ​​the orthographic projection of the crystalline silicon battery unit on the substrate.

[0065] In one embodiment, the second distance L2 is smaller than the first distance L1.

[0066] Generally, the coating effect at the initial stage of coating is inferior to that at the end of coating.

[0067] Thus, when it is necessary to remove a portion with poor coating effect, more areas at the beginning of coating will be removed, and the blank gap left on the first coated side will become larger, forming a second spacing L2 smaller than the first spacing L1.

[0068] In one embodiment, there is a third distance L3 between the perovskite light absorption layer and the third side of the crystalline silicon battery unit, and there is a fourth distance L4 between the perovskite light absorption layer and the fourth side of the crystalline silicon battery unit;

[0069] The third spacing L3 and the fourth spacing L4 are both smaller than the second spacing L2; wherein the third side surface is opposite to the fourth side surface, the third side surface is adjacent to the first side surface and the second side surface respectively, and the fourth side surface is adjacent to the first side surface and the second side surface respectively.

[0070] In the present invention, if the coating direction is set to the x direction, then the third side and the fourth side both refer to the side perpendicular to the first side (or the second side), that is, the side in the y direction. During the coating operation, the coating uniformity of the third side and the fourth side is relatively poor. Therefore, in the process of constructing the stacked battery, the perovskite layer on the two sides along the y direction is removed. Through this removal operation, the third spacing L3 and the fourth spacing L4 are formed.

[0071] The purpose of this design is to ensure that the projected area of ​​the perovskite light-absorbing layer is smaller than the projected area of ​​the crystalline silicon battery unit. By reducing the size of the perovskite light-absorbing layer, it can effectively ensure that the remaining perovskite layer is the most uniform part of the coating process. In this way, not only the performance of the battery is improved, but also the overall battery structure is optimized, so that the battery can show better stability and efficiency in practical applications.

[0072] In one embodiment, the crystalline silicon cell unit is a bottom cell, and the perovskite cell unit is a top cell.

[0073] In one embodiment, still referring to Figure 1 and Figure 3-4 The crystalline silicon battery unit includes a first electrode layer 7, a first transparent conductive layer 6, a first type doped silicon wafer layer 5, a first intrinsic silicon wafer layer 4, a substrate 1, a second intrinsic silicon wafer layer 2 and a second type doped silicon wafer layer 3, which are formed in sequence from bottom to top; wherein the second type is opposite to the first type; the single crystal silicon wafer layer 1 is the substrate.

[0074] In one embodiment, the perovskite battery unit comprises a first charge transport layer 8, a perovskite light absorption layer 9, a second charge transport layer 10, a second transparent conductive layer 11 and a second electrode layer 12 formed in sequence from bottom to top.

[0075] In one embodiment, the material of the perovskite light absorbing layer is ABX3, wherein A includes any one of FA, MA, Cs or Rb or a combination of at least two, B includes any one of Pb, Sn or Sr or a combination of at least two, and X includes any one of Br, I or CI or a combination of at least two.

[0076] Optionally, the material of the perovskite light-absorbing layer has a three-dimensional crystal structure.

[0077] Optionally, the band gap of the perovskite light absorbing layer is 1.50-1.75 eV.

[0078] Optionally, the thickness of the perovskite light absorbing layer is 10-3000 nm.

[0079] The perovskite light-absorbing layer can be prepared by solution method, evaporation + solution method, and full evaporation method.

[0080] In one embodiment, the first charge transport layer may be an n-type or p-type layer, having opposite carrier transport properties to the second charge transport layer.

[0081] The n-type layer materials include but are not limited to n-type single crystal silicon, n-type polycrystalline silicon, n-type amorphous silicon, TiO2, SnO2, ZnO, ZrO2, GZO, IZO, FTO, ITO, BaSnO3, TiSnO x SnZnO x , fullerene and derivatives (C 60 , C 70 , PCBM), and the thickness of the n-type region is 0 nm to 100 μm.

[0082] The p-type layer material includes but is not limited to p-type single crystal silicon, p-type polycrystalline silicon, p-type amorphous silicon, and single molecule self-assembled materials, including [2-(9H-carbazole-9-yl)ethyl]phosphonic acid (2PACz), [2-(3,6-dimethoxy-9H-carbazole-9-yl)ethyl]phosphonic acid (MeO-2PACz), [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphonic acid (Me-4PACz), benzoic acid, 4-[bis(2,4-dimethoxybiphenyl-4-yl)amino]-biphenyl-4-carboxylic acid [MC-43] etc., one or more of Spirio-OMeTAD (2,2',7,7'-tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene), PTAA (polyethylene terephthalate), P3HT (polymer of 3-hexylthiophene), PEDOT:PSS, Spiro-TTB, F4-TCNQ, F6TCNNQ, TAPC, NiOx, CuSCN, CuAlO2, V2O5, CdS, CdSe, the thickness of the p-type region is 0nm to 100μm.

[0083] The composite layer material includes but is not limited to ITO, IZO, IWO, FTO, ICO, AZO, BZO, nanocrystalline silicon, TiO2, SnO2, and has a thickness of 0.1-100 nm.

[0084] The first transparent conductive layer includes but is not limited to ITO, IZO, IWO, FTO, ICO, AZO, BZO, nanocrystalline silicon, TiO2, SnO2, and has a thickness of 1-500 nm.

[0085] The second transparent conductive layer includes but is not limited to ITO, IZO, IWO, FTO, ICO, AZO, BZO, nanocrystalline silicon, TiO2, SnO2, and has a thickness of 1-500 nm.

[0086] The electrode material of the first electrode layer includes, but is not limited to, one or more of Au, Ag, Al, Cu, graphene, TCO material, and nanocrystalline silicon, and the electrode preparation method includes, but is not limited to, one or more of spin coating, scraper coating, evaporation, printing, spray coating, spray pyrolysis, and slit coating. The thickness of the electrode layer is 0 nm to 10 μm.

[0087] The electrode material of the second electrode layer includes, but is not limited to, one or more of Au, Ag, Al, Cu, graphene, TCO material, and nanocrystalline silicon, and the electrode preparation method includes, but is not limited to, one or more of spin coating, scraper coating, evaporation, printing, spray coating, spray pyrolysis, and slit coating. The thickness of the electrode layer is 0 nm to 10 μm.

[0088] In one embodiment, the battery further includes a composite layer 13 formed between the crystalline silicon battery unit and the perovskite battery unit.

[0089] In one embodiment, the composite layer 13 is formed between the first charge transport layer 8 and the second type doped silicon layer 3 .

[0090] In one embodiment, referring to Figure 3 , only a spacing of L1-L4 is formed between the perovskite light-absorbing layer and the crystalline silicon battery unit.

[0091] In one embodiment, referring to Figure 4 The orthographic projection areas of the perovskite light absorbing layer 9 , the composite layer 13 , the first transparent conductive layer 6 and the second transparent conductive layer 11 on the substrate 1 are the same.

[0092] In one embodiment, referring to Figure 5 In one embodiment, the orthographic projection areas of the first charge transport layer 8, the perovskite light absorbing layer 9, the second charge transport layer 10, the first transparent conductive layer 6, the composite layer 13, the first transparent conductive layer 6 and the second transparent conductive layer 11 on the substrate are the same.

[0093] In one embodiment, the perovskite battery cell further includes a buffer layer 14 (Buffer layer), and the buffer layer 14 is formed between the second charge transport layer and the second transparent conductive layer.

[0094] The material of the buffer layer 14 includes, but is not limited to, CdS, SnO 2 , and ZnO 2 .

[0095] The present invention cleverly designs the distribution structure of the perovskite layer by sacrificing the active area of ​​the perovskite material with poor coating effect. This design not only greatly improves its applicability in large-scale production, but also provides new ideas and methods for the distribution of the perovskite layer in other related processes. Through this design, while maintaining the material properties, the production process can be optimized, the cost can be reduced, and the efficiency can be improved, so that the perovskite material is more competitive and feasible in the practical application of the stacked battery.

[0096] Reference Figure 5 The present invention also provides a method for preparing a tandem solar cell, comprising:

[0097] S1, forming a crystalline silicon battery unit on a substrate;

[0098] S2, forming a perovskite battery cell on the crystalline silicon battery cell; wherein the perovskite light absorption layer in the perovskite battery cell is formed by a coating method, and the area of ​​the orthographic projection of the perovskite light absorption layer on the substrate is smaller than the area of ​​the orthographic projection of the crystalline silicon battery cell on the substrate.

[0099] In one embodiment, forming a crystalline silicon battery unit on a substrate includes:

[0100] A single crystal silicon wafer c-Si is used as a substrate 1;

[0101] Forming a second intrinsic silicon layer 2 and a second type doped silicon layer 3 on the first surface of the substrate in sequence from bottom to top;

[0102] A first intrinsic silicon layer 4, a first type doped silicon layer 5, a first transparent conductive layer 6 and a first electrode layer 7 are sequentially formed on the second surface of the crystalline silicon layer from top to bottom.

[0103] In one embodiment, the first type doped silicon wafer layer 5 includes a P-type silicon wafer layer; and the second type doped silicon wafer layer includes an N-type silicon wafer layer.

[0104] In one embodiment, forming a perovskite battery cell on the crystalline silicon battery cell comprises:

[0105] On the crystalline silicon battery unit, a first charge transport layer 8, a perovskite light absorption layer 9, a second charge transport layer 10, a second transparent conductive layer 11 and a second electrode layer 12 are formed in sequence from bottom to top.

[0106] In one embodiment, the perovskite light absorbing layer 9 is formed on the first charge transport layer 8 by a coating method.

[0107] In one embodiment, the method further comprises:

[0108] A buffer layer 14 is formed between the second charge transport layer 10 and the second transparent conductive layer 11 .

[0109] In one embodiment, the method further comprises:

[0110] A composite layer 13 is formed between the crystalline silicon battery unit and the perovskite battery unit.

[0111] In one embodiment, the method further comprises:

[0112] The composite layer 13, the first transparent conductive layer and the second transparent conductive layer are patterned respectively so that the areas of the orthographic projections of the patterned composite structure, the first transparent conductive structure and the second transparent conductive structure on the substrate overlap.

[0113] In one application scenario, the patterning process of the first transparent conductive layer is to add the following steps during the deposition of the thin film: Figure 6 The mask plate shown in this example has the hollow portion of the mask plate deposited thereon.

[0114] In one embodiment, the method further comprises:

[0115] The composite layer 13, the first charge transport layer 8, the perovskite light absorption layer 9, the second charge transport layer 10, the buffer layer 14 and the second transparent conductive layer 11 are patterned respectively, so that the areas of the orthographic projections of the patterned composite structure, the first charge transport structure, the perovskite light absorption structure, the second charge transport structure, the buffer structure and the second transparent conductive structure on the substrate overlap. In one embodiment, after coating by full coating, the above layers are patterned by laser method.

[0116] Example 1

[0117] like Figure 1 In the device structure shown, a full-area perovskite light absorption layer 9 is formed on the first charge transport layer 8 by a coating method, and thin films with poor quality in different parts are etched away by laser to form a regional coating, thereby forming a first spacing to a fourth spacing (L1, L2, L3 and L4) between the perovskite light absorption layer and the crystalline silicon battery unit.

[0118] This embodiment uses etching to remove areas with poor coating effects.

[0119] Example 2

[0120] like Figure 1 The device structure shown is based on the four pre-set size parameters of L1, L2, L3, and L4. Figure 7 The customized cover plate has a hollow structure, and the cover plate is covered on the first charge transport layer to ensure that the cover plate can accurately cover the four specific areas of L1, L2, L3, and L4. During the coating operation, the cover plate is laid flat on the surface of the first charge transport layer. Although the coating process is carried out in a full-area coating manner, due to the presence of the cover plate, the edge part is not covered by the coating material on the first charge transport layer. The result of this is that although the edge part is not coated, the middle area is evenly coated. This method can ensure that areas with good coating quality are retained without increasing the complexity of the production line and additional processes. After the coating process is completed, the cover plate is removed from the first charge transport layer.

[0121] Example 3

[0122] like Figure 1 The device structure shown is designed with a coating fixture, which includes an openable and closable fixture and a cover plate fixed to the fixture.

[0123] The cover plate is customized according to four preset size parameters of L1, L2, L3 and L4.

[0124] The clamp is set according to the structure and size of the first charge transport layer and the device below it, and the clamp can be opened and closed by bolts, and is detachably clamped around the lower periphery of the crystalline silicon battery unit and the perovskite battery unit. The clamp plays a role of stability and support.

[0125] When in use, the clamp is clamped on the outer periphery of the lower part of the crystalline silicon battery unit and the perovskite battery unit, and the cover plate is on the surface of the first charge transfer layer. The coating process is carried out in a full-area coating manner, but due to the presence of the cover plate, the edge part is not covered by the coating material on the first charge transfer layer. The middle area is the actually formed perovskite light absorption layer, which has a uniform coating effect, and the peripheral coating part is removed as the clamp is removed.

[0126] Comparative Example 1

[0127] The difference between Comparative Example 1 and Example 1 is that Comparative Example 1 adopts a full-area coating method to form a full-area perovskite light absorption layer on the first charge transport layer. The area of ​​the orthographic projection of the perovskite light absorption layer on the substrate is equal to the area of ​​the orthographic projection of the crystalline silicon battery unit on the substrate.

[0128] The batteries of Example 1 and Comparative Example 1 were tested, and the test results were as follows:

[0129] Table 1 Battery test results of Example 1 and Comparative Example 1

[0130]

[0131] It can be seen from the JV test data in Table 1 that by cleaning the edges of L1-L4, the overall top cell quality is improved, the battery Voc, Jsc, FF and other parameters are improved, and the efficiency is improved. Combined with the overall loss area, the output power of the stacked cell in Example 1 of the present invention is increased from 5.55W to 5.87W compared to the stacked cell with the perovskite light-absorbing layer coated on the entire area without cleaning the edges.

[0132] According to the JV test data provided in Table 1, it can be seen that the quality of the overall top battery has been significantly improved by edge removal of the L1-L4 layers. Specifically, key parameters such as the open circuit voltage (Voc), short circuit current (Jsc) and fill factor (FF) of the battery have been improved. The improvement of these parameters directly leads to an improvement in the overall efficiency of the battery. After comprehensively considering the area of ​​overall loss, it can be concluded that the output power of the stacked battery in Example 1 of the present invention is significantly increased from the original 5.55W to 5.87W after the coating edge removal treatment. This result shows that the coating edge removal process not only improves the performance parameters of the battery, but also further enhances the actual application efficiency of the battery.

[0133] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art can understand that in order to achieve the effects of the present invention, different steps do not have to be performed in such an order. They can be performed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present invention.

[0134] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A tandem solar cell, characterized in that: include: substrate; A crystalline silicon battery cell formed on the substrate; as well as a perovskite cell formed on the crystalline silicon cell; The perovskite battery unit includes a perovskite light absorbing layer, and the area of ​​the orthographic projection of the perovskite light absorbing layer on the substrate is smaller than the area of ​​the orthographic projection of the crystalline silicon battery unit on the substrate.

2. The battery according to claim 1, characterized in that There is a first distance between the perovskite light absorbing layer and the first side surface of the crystalline silicon battery unit; There is a second distance between the perovskite light absorbing layer and the second side of the crystalline silicon battery unit, wherein the second side is opposite to the first side.

3. The battery according to claim 2, characterized in that The second interval is smaller than the first interval.

4. The battery according to claim 2, characterized in that There is a third distance between the perovskite light absorption layer and the third side of the crystalline silicon battery unit and there is a fourth distance between the perovskite light absorption layer and the fourth side of the crystalline silicon battery unit; The third spacing and the fourth spacing are both smaller than the second spacing; wherein the third side surface is opposite to the fourth side surface, the third side surface is adjacent to the first side surface and the second side surface respectively, and the fourth side surface is adjacent to the first side surface and the second side surface respectively.

5. The battery according to claim 1, characterized in that The crystalline silicon battery unit is a bottom battery, and the perovskite battery unit is a top battery.

6. The battery according to claim 1, characterized in that The crystalline silicon battery unit includes a first electrode layer, a first transparent conductive layer, a first type doped silicon wafer layer, a first intrinsic silicon wafer layer, a single crystal silicon wafer layer, a second intrinsic silicon wafer layer and a second type doped silicon wafer layer, which are formed in sequence from bottom to top; wherein the second type is opposite to the first type; and the single crystal silicon wafer layer is the substrate.

7. The battery according to claim 6, characterized in that The perovskite battery unit comprises a first charge transport layer, a perovskite light absorption layer, a second charge transport layer, a second transparent conductive layer and a second electrode layer formed in sequence from bottom to top.

8. The battery according to claim 7, characterized in that The battery further includes a composite layer formed between the crystalline silicon battery unit and the perovskite battery unit.

9. The battery according to claim 8, characterized in that The orthographic projection areas of the perovskite light absorbing layer, the composite layer, the first transparent conductive layer, and the second transparent conductive layer on the substrate are the same.

10. The battery according to claim 9, characterized in that The orthographic projection areas of the first charge transport layer, the perovskite light absorbing layer, the second charge transport layer, the first transparent conductive layer, the composite layer, the first transparent conductive layer and the second transparent conductive layer on the substrate are the same.

11. The battery according to claim 6, characterized in that The perovskite cell further includes a buffer layer formed between the second charge transport layer and the second transparent conductive layer.

12. A method for preparing a tandem solar cell, characterized in that: include: forming a crystalline silicon battery cell on a substrate; A perovskite cell unit is formed on the crystalline silicon cell unit; wherein the perovskite light absorption layer in the perovskite cell unit is formed by a coating method, and the area of ​​the orthographic projection of the perovskite light absorption layer on the substrate is smaller than the area of ​​the orthographic projection of the crystalline silicon cell unit on the substrate.

13. The method according to claim 12, characterized in that The step of forming a crystalline silicon battery unit on a substrate comprises: Using single crystal silicon wafer as substrate; Forming a second intrinsic silicon layer and a second type doped silicon layer on the first surface of the substrate in sequence from bottom to top; A first intrinsic silicon layer, a first type doped silicon layer, a first transparent conductive layer and a first electrode layer are sequentially formed on the second surface of the crystalline silicon layer from top to bottom.

14. The method according to claim 13, characterized in that The first type doped silicon wafer layer includes a P-type silicon wafer layer; the second type doped silicon wafer layer includes an N-type silicon wafer layer.

15. The method according to claim 12, characterized in that Forming a perovskite battery cell on the crystalline silicon battery cell comprises: On the crystalline silicon battery unit, a first charge transport layer, a perovskite light absorption layer, a second charge transport layer, a second transparent conductive layer and a second electrode layer are formed in sequence from bottom to top.

16. The method according to claim 15, characterized in that The method further comprises: A buffer layer is formed between the second charge transport layer and the second transparent conductive layer.

17. The method according to claim 15, characterized in that The method further includes forming a composite layer between the crystalline silicon battery cell and the perovskite battery cell.

18. The method according to claim 17, characterized in that The method further comprises: The composite layer, the first transparent conductive layer and the second transparent conductive layer are patterned respectively, so that the areas of the orthographic projections of the patterned composite structure, the first transparent conductive structure and the second transparent conductive structure on the substrate overlap.

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