Capacitor structure and preparation method thereof
By forming a first plate layer with a smooth surface at a lower temperature and providing a stress buffer layer between it and the second diffusion barrier layer, the problem of insufficient flatness of the metal plate layer of the existing capacitance structure is solved, and the breakdown voltage and reliability of the capacitance structure are improved.
Patent Information
- Application Number
- CN202311319232.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-12
- Publication Date
- 2025-04-15
AI Technical Summary
The flatness of the metal plate layer of the existing capacitance structure is insufficient, resulting in a reduced reliability of the capacitance structure and easy breakdown.
By forming the first plate layer at the first temperature, the surface of the plate layer is smooth by using a physical vapor deposition method, and a stress buffer layer is provided between the first plate layer and the second diffusion barrier layer to relieve stress differences and improve the flatness of the plate layer.
The breakdown voltage of the capacitance structure is improved, and the reliability and performance of the capacitance structure are enhanced.
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Figure CN119836224A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a capacitor structure and a method for preparing the same. Background Art
[0002] Capacitor structures are widely used in integrated circuits, among which Metal-Insulator-Metal is a capacitor structure commonly used in semiconductor chips.
[0003] However, the metal plate layer of the existing capacitor is not flat enough, which reduces the reliability of the capacitor structure and makes the capacitor structure easy to be broken down. Summary of the invention
[0004] Based on this, it is necessary to provide a capacitor structure and a preparation method thereof to address the problem of insufficient flatness of the metal plate layer of the capacitor structure in the prior art.
[0005] In order to achieve the above objectives, on the one hand, the present application provides a method for preparing a capacitor structure, comprising:
[0006] providing a substrate, on which a first diffusion barrier layer is formed;
[0007] Controlling the temperature of the process chamber to a first temperature;
[0008] Under the process condition of the first temperature, forming a first electrode layer on the first diffusion barrier layer;
[0009] forming a stress buffer layer and a second diffusion barrier layer in sequence on the first electrode layer;
[0010] Under a process condition of a second temperature, forming a dielectric layer on the second diffusion barrier layer, wherein the first temperature is lower than a first preset temperature, the second temperature is higher than a second preset temperature, and the second preset temperature is higher than the first preset temperature;
[0011] A second electrode layer is formed on the dielectric layer.
[0012] In one embodiment, the first temperature is preset to 50°C to 150°C;
[0013] Forming a first electrode layer on the first diffusion barrier layer includes:
[0014] A first electrode layer is formed on the first diffusion barrier layer by using a physical vapor deposition method.
[0015] In one embodiment, the second preset temperature is 300°C to 450°C.
[0016] In one embodiment, the material of the first electrode layer includes aluminum, the materials of the first diffusion barrier layer and the second diffusion barrier layer include tantalum nitride, and the material of the stress buffer layer includes tantalum.
[0017] In one embodiment, the step of sequentially forming a stress buffer layer and a second diffusion barrier layer on the first electrode layer includes:
[0018] controlling the temperature of the process chamber to be a third temperature;
[0019] Under the process condition of the third temperature, the stress buffer layer and the second diffusion barrier layer are formed on the first electrode layer.
[0020] In one embodiment, the third temperature is 20°C~100°C.
[0021] In one embodiment, the thickness of the first electrode layer ranges from 700 Å to 4000 Å, and the total thickness of the stress buffer layer and the second diffusion barrier layer ranges from 300 Å to 800 Å.
[0022] The present application also provides a capacitor structure, comprising:
[0023] substrate;
[0024] a first diffusion barrier layer, above the substrate;
[0025] A first electrode layer, located above the first diffusion barrier layer;
[0026] A stress buffer layer, located above the first electrode layer;
[0027] a second diffusion barrier layer, above the stress buffer layer;
[0028] a dielectric layer, located above the second diffusion barrier layer;
[0029] The second electrode layer is located above the dielectric layer.
[0030] In one embodiment, the material of the first electrode layer includes aluminum, the material of the first diffusion barrier layer and the second diffusion barrier layer includes tantalum nitride, and the material of the stress buffer layer includes tantalum.
[0031] In one embodiment, the thickness of the first electrode layer ranges from 700 Å to 4000 Å, and the total thickness of the stress buffer layer and the second diffusion barrier layer ranges from 300 Å to 800 Å.
[0032] The capacitor structure and preparation method thereof provided in the present application form a first electrode layer under process conditions of a first temperature (for example, a lower temperature) so that the lattice of the material forming the first electrode layer is smaller, thereby obtaining a first electrode layer surface with a relatively smooth surface.
[0033] At the same time, the present application sets a stress buffer layer between the first electrode layer and the second diffusion barrier layer. Under the process conditions of the second temperature (for example, a higher temperature), the stress buffer layer relieves the stress between the first electrode layer and the second diffusion barrier layer, reduces the possibility of defects on the surface of the first electrode layer, improves the flatness of the first electrode layer, and increases the breakdown voltage of the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0035] Figure 1 is a flow chart of a method for preparing a capacitor structure provided in an embodiment;
[0036] Figures 2 to 5 A schematic diagram of an intermediate structure obtained in a method for preparing a capacitor structure provided in an embodiment;
[0037] Figure 6 to Figure 7 This is a scan of a spherical defect in the first electrode layer in the conventional technology;
[0038] Figure 8 This is a scan image of a first electrode layer of a capacitor structure obtained after a stress buffer layer is provided in an embodiment.
[0039] Description of reference numerals: capacitor structure-100; substrate-110; first diffusion barrier layer-120; first electrode layer-130; stress buffer layer-140; second diffusion barrier layer-150; dielectric layer-160; second electrode layer-170. DETAILED DESCRIPTION
[0040] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0042] It should be understood that when an element or layer is referred to as being "on, adjacent to, or connected to other elements or layers, it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, or directly connected to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present embodiment, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.
[0043] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used herein to describe the relationship between an element or feature shown in the figures and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0044] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0045] Embodiments of the embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the embodiments, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, embodiments of the embodiments should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the embodiments.
[0046] In one embodiment, see Figure 1 , a method for preparing a capacitor structure 100 is provided, comprising the following steps:
[0047] Step S100 : providing a substrate 110 , on which a first diffusion barrier layer 120 is formed.
[0048] Step S200: controlling the temperature of the process chamber to be a first temperature.
[0049] Step S300 : forming a first electrode layer 130 on the first diffusion barrier layer 120 under a process condition of a first temperature.
[0050] Step S400 : forming a stress buffer layer 140 and a second diffusion barrier layer 150 in sequence on the first electrode layer 130 .
[0051] Step S500: forming a dielectric layer 160 on the second diffusion barrier layer 150 under a second temperature process condition, wherein the first temperature is lower than a first preset temperature, the second temperature is higher than the second preset temperature, and the second preset temperature is higher than the first preset temperature.
[0052] Step S600 : forming a second electrode layer 170 on the dielectric layer 160 .
[0053] In step S100, refer to Figure 2 The substrate 110 may be made of semiconductor material, insulating material or any combination thereof. The substrate 110 may be a single-layer structure or a multi-layer structure. For example, the substrate 110 may be a silicon substrate, a silicon germanium substrate, a silicon germanium carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium arsenide substrate, an indium phosphide substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 110 may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator or silicon germanium on insulator.
[0054] In order to prevent the material of the first electrode layer 130 from diffusing into the substrate 110 and affecting the properties of the substrate 110, a first diffusion barrier layer 120 may be formed on the substrate 110. As an example, the first diffusion barrier layer 120 may be formed by sputtering.
[0055] As an example, the thickness of the first diffusion barrier layer 120 may range from 100 Å to 400 Å.
[0056] In step S200, the substrate 110 is placed on a chuck in a process chamber. As an example, an electrostatic adsorption structure may be provided on the chuck, and the substrate 110 is adsorbed on the chuck by the electrostatic adsorption structure.
[0057] The chuck is also provided with a heating device. As an example, the inner wall of the process chamber may also be provided with a temperature sensor, and the temperature of the chuck or the process chamber is measured by the temperature sensor.
[0058] At this time, the chuck can be heated to the first temperature by a heating device, and the temperature of the chuck or the process chamber can be monitored by a temperature sensor, and the power of the heating device can be adjusted according to the monitoring result to control the temperature of the chuck or the process chamber to be stably maintained at the first temperature.
[0059] The first temperature is less than the first preset temperature. As an example, the first preset temperature may be in the range of 50° C. to 150° C. For example, the first preset temperature may be 70° C.
[0060] The above data are only examples. In actual embodiments, the first preset temperature is not limited to the above data.
[0061] In step S300 , as an example, the first electrode layer 130 may be formed on the first diffusion barrier layer 120 by using a physical vapor deposition method under a process condition of a first temperature.
[0062] The material of the first electrode layer 130 may include metal materials such as cobalt, nickel, titanium, tungsten, tantalum, tantalum titanium, tungsten nitride, copper, and aluminum.
[0063] Of course, other processes may also be used to form the first electrode layer 130. For example, chemical vapor deposition, atomic layer deposition, high-density plasma deposition, plasma enhanced deposition, and spin-coating of the dielectric layer 160 may also be used to form the first electrode layer 130.
[0064] The thickness of the first electrode layer 130 may be 700 Å to 4000 Å. The above data are only used as examples. In actual embodiments, the thickness of the first electrode layer 130 is not limited to the above data.
[0065] In step S400, refer to Figure 3 In order to prevent the material of the first electrode layer 130 from diffusing into the dielectric layer 160 and affecting the properties of the dielectric layer 160 , a second diffusion barrier layer 150 may be formed between the first electrode layer 130 and the dielectric layer 160 .
[0066] As an example, the material of the first diffusion barrier layer 120 and the second diffusion barrier layer 150 includes tantalum nitride, cobalt, platinum, titanium tungsten, or the like.
[0067] At this time, the stress buffer layer 140 may be formed on the first electrode layer 130 first, and then the second diffusion barrier layer 150 may be formed on the stress buffer layer 140 .
[0068] The stress buffer layer 140 and the second diffusion barrier layer 150 may also be formed by using a physical vapor deposition method.
[0069] As an example, when the material of the first electrode layer 130 includes aluminum, and the materials of the first diffusion barrier layer 120 and the second diffusion barrier layer 150 include tantalum nitride, the material of the stress buffer layer 140 includes tantalum.
[0070] In another example, when the material of the first electrode layer 130 includes aluminum, and the materials of the first diffusion barrier layer 120 and the second diffusion barrier layer 150 include titanium nitride, the material of the stress buffer layer 140 includes titanium.
[0071] In step S500 , the temperature of the process chamber may be maintained at the second temperature by adjusting the heating device.
[0072] The second temperature is greater than the second preset temperature, and the second preset temperature is greater than the first preset temperature. As an example, the second preset temperature may range from 300° C. to 450° C. For example, the second preset temperature may be 400° C.
[0073] The above data are only examples. In actual embodiments, the second preset temperature is not limited to the above data.
[0074] See also Figure 4 , under the process condition of the second temperature, a dielectric layer 160 is formed on the first electrode layer 130. As an example, the method of forming the dielectric layer 160 can be a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process, a plasma enhanced deposition process, and a spin coating dielectric layer 160 process.
[0075] The material of the dielectric layer 160 may be silicon oxide, silicon nitride, aluminum oxide or silicon oxynitride. The thickness of the dielectric layer 160 may range from 200 Å to 500 Å.
[0076] In step S600, refer to Figure 5 A second electrode layer 170 is formed on the dielectric layer 160. The thickness of the second electrode layer 170 may range from 300 Å to 700 Å. The second electrode layer 170, the dielectric layer 160 and the first electrode layer 130 constitute the capacitor structure 100.
[0077] When forming the second electrode layer 170 , the temperature of the process chamber may be controlled at the first preset temperature. Of course, when forming the second electrode layer 170 , the temperature of the process chamber may be controlled at other temperatures.
[0078] It is understood that the temperature for forming the second electrode layer 170 may be consistent with or inconsistent with the temperature for forming the first diffusion barrier layer 120, the stress buffer layer 140, and the second diffusion barrier layer 150. As an example, the temperatures for forming the first diffusion barrier layer 120, the stress buffer layer 140, the second diffusion barrier layer 150, and the second electrode layer 170 may all be 70°C.
[0079] In another example, the temperature for forming the first diffusion barrier layer 120 , the stress buffer layer 140 , and the second diffusion barrier layer 150 may be 70° C., and the temperature for forming the second electrode layer 170 may be 60° C.
[0080] As an example, the process of forming the second electrode layer 170 may be the same as the process of forming the first electrode layer 130 . Of course, the process of forming the second electrode layer 170 may also be different from the process of forming the first electrode layer 130 .
[0081] The material of the first electrode layer 130 may be the same as that of the second electrode layer 170. The material of the first electrode layer 130 may also be different from that of the second electrode layer 170. As an example, the material of the first electrode layer 130 is aluminum, and the material of the second electrode layer 170 is tantalum nitride or titanium nitride.
[0082] In the conventional technology, due to the large stress difference between the stress value of the second diffusion barrier layer 150 and the stress value of the first electrode layer 130, when the dielectric layer 160 is formed under the process condition of the second temperature (for example, 400°C) in step S600, the large stress difference may cause spherical defects (Hillock defects) to appear on the first electrode layer 130. Figure 6 and Figure 7 Such spherical defects will seriously affect the flatness of the first electrode layer 130 , thereby affecting the flatness of each film layer above the first electrode layer 130 , and ultimately reducing the breakdown voltage of the capacitor structure 100 .
[0083] In this embodiment, please refer to Figure 8 A stress buffer layer 140 is disposed between the first electrode layer 130 and the second diffusion barrier layer 150, and the stress of the stress buffer layer 140 can match the stress of the first electrode layer 130. In step S600, under the process condition of the second temperature, the stress buffer layer 140 can form a greater compressive stress on the first electrode layer 130 to suppress the generation of spherical defects, thereby obtaining a flat first electrode layer 130, thereby improving the breakdown voltage of the capacitor structure 100.
[0084] At the same time, in the present embodiment, during the process of forming the first electrode layer 130 on the substrate 110, due to the low first temperature, the size of the grains of the material of the first electrode layer 130 will be reduced, thereby obtaining a densely arranged first electrode layer 130, so that the surface of the first electrode layer 130 is relatively flat. When a voltage is applied to the capacitor structure 100, the voltage is evenly distributed in the first electrode layer 130, further increasing the breakdown voltage of the capacitor structure 100 and improving the performance of the capacitor structure 100.
[0085] In one embodiment, step S400 includes:
[0086] Step S410: controlling the temperature of the process chamber to be a third temperature.
[0087] Step S420 : forming a stress buffer layer 140 and a second diffusion barrier layer 150 on the first electrode layer 130 under a process condition of a third temperature.
[0088] In step S410 , the temperature of the process chamber is set to a third temperature by controlling the heating device.
[0089] As an example, the third temperature may be 20° C. to 100° C. For example, the third temperature may be 40° C. to 60° C. The above data are only examples, and in actual embodiments, the third temperature is not limited to the above data.
[0090] In step S420 , under the process condition of the third temperature, a stress buffer layer 140 and a second diffusion barrier layer 150 are sequentially formed on the first electrode layer 130 .
[0091] As an example, the stress buffer layer 140 and the second diffusion barrier layer 150 may be formed by chemical vapor deposition, atomic layer deposition, high density plasma deposition, plasma enhanced deposition, spin coating of the dielectric layer 160 and other processes.
[0092] The stress buffer layer 140 and the second diffusion barrier layer 150 are formed under the same process conditions, so there is no need to adjust related process parameters, thereby increasing the speed of forming the stress buffer layer 140 and the second diffusion barrier layer 150 .
[0093] As an example, the total thickness of the stress buffer layer 140 and the first diffusion barrier layer 120 ranges from 300 Å to 800 Å. The above data are only examples, and in actual embodiments, the total thickness of the stress buffer layer 140 and the first diffusion barrier layer 120 is not limited to the above data.
[0094] It should be understood that although Figure 1The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0095] In one embodiment, please refer to Figure 5 , a capacitor structure 100 is also provided, including: a substrate 110, a first diffusion barrier layer 120, a first electrode layer 130, a stress buffer layer 140, a second diffusion barrier layer 150, a dielectric layer 160 and a second electrode layer 170.
[0096] The substrate 110 may be made of a semiconductor material, an insulating material, or any combination thereof. The substrate 110 may be a single-layer structure or a multi-layer structure. For example, the substrate 110 may be a silicon substrate, a silicon germanium substrate, a silicon germanium carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium arsenide substrate, an indium phosphide substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 110 may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator, or silicon germanium on insulator.
[0097] The first diffusion barrier layer 120 is located above the substrate 110. The first electrode layer 130 is located between the first diffusion barrier layer 120 and the second diffusion barrier layer 150. The first diffusion barrier layer 120 and the second diffusion barrier layer 150 can prevent the material of the first electrode layer 130 from diffusing into the substrate 110 or the dielectric layer 160.
[0098] As an example, the material of the first diffusion barrier layer 120 and the second diffusion barrier layer 150 includes tantalum nitride, cobalt, platinum, titanium tungsten, or the like.
[0099] As an example, the material of the first electrode layer 130 may include metal materials such as cobalt, nickel, titanium, tungsten, tantalum, tantalum titanium, tungsten nitride, copper, and aluminum.
[0100] The thickness of the first electrode layer 130 may be 700 Å to 4000 Å. The above data are only used as examples. In actual embodiments, the thickness of the first electrode layer 130 is not limited to the above data.
[0101] The stress buffer layer 140 is located between the first electrode layer 130 and the second diffusion barrier layer 150 . The stress value of the stress buffer layer 140 is between the stress value of the first electrode layer 130 and the stress value of the second diffusion barrier layer 150 .
[0102] The total thickness of the stress buffer layer 140 and the second diffusion barrier layer 150 ranges from 300 Å to 800 Å.
[0103] As an example, when the material of the first electrode layer 130 includes aluminum, and the materials of the first diffusion barrier layer 120 and the second diffusion barrier layer 150 include tantalum nitride, the material of the stress buffer layer 140 includes tantalum.
[0104] In another example, when the material of the first electrode layer 130 includes aluminum, and the materials of the first diffusion barrier layer 120 and the second diffusion barrier layer 150 include titanium nitride, the material of the stress buffer layer 140 includes titanium.
[0105] The dielectric layer 160 is located above the second diffusion barrier layer 150. The dielectric layer 160 may be made of silicon oxide, silicon nitride, aluminum oxide or silicon oxynitride.
[0106] The second electrode layer 170 is located above the dielectric layer 160. The material of the second electrode layer 170 is tantalum nitride or titanium nitride.
[0107] In this embodiment, please refer to Figure 8 A stress buffer layer 140 is disposed between the first electrode layer 130 and the second diffusion barrier layer 150, and the stress of the stress buffer layer 140 can match the stress of the first electrode layer 130. In step S600, under the process condition of the second temperature, the stress buffer layer 140 can form a greater compressive stress on the first electrode layer 130 to suppress the generation of spherical defects, thereby obtaining a flat first electrode layer 130, thereby improving the breakdown voltage of the capacitor structure 100.
[0108] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0109] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a capacitor structure, characterized in that: include: providing a substrate, on which a first diffusion barrier layer is formed; Controlling the temperature of the process chamber to a first temperature; Under the process condition of the first temperature, forming a first electrode layer on the first diffusion barrier layer; forming a stress buffer layer and a second diffusion barrier layer in sequence on the first electrode layer; Under a process condition of a second temperature, forming a dielectric layer on the second diffusion barrier layer, wherein the first temperature is lower than a first preset temperature, the second temperature is higher than a second preset temperature, and the second preset temperature is higher than the first preset temperature; A second electrode layer is formed on the dielectric layer.
2. The method for preparing a capacitor structure according to claim 1, characterized in that: The first preset temperature is 50°C to 150°C; The step of forming a first electrode layer on the first diffusion barrier layer comprises: A first electrode layer is formed on the first diffusion barrier layer by using a physical vapor deposition method.
3. The method for preparing a capacitor structure according to claim 1, characterized in that: The second preset temperature is 300°C~450°C.
4. The method for preparing a capacitor structure according to claim 1, characterized in that: The material of the first electrode layer includes aluminum, the materials of the first diffusion barrier layer and the second diffusion barrier layer include tantalum nitride, and the material of the stress buffer layer includes tantalum.
5. The method for preparing a capacitor structure according to claim 1, characterized in that: The step of sequentially forming a stress buffer layer and a second diffusion barrier layer on the first electrode layer comprises: Under the process condition of a third temperature, the stress buffer layer and the second diffusion barrier layer are formed on the first electrode layer.
6. The method for preparing a capacitor structure according to claim 5, characterized in that: The third temperature is 20°C~100°C.
7. The method for preparing a capacitor structure according to claim 1, characterized in that: The thickness of the first electrode layer ranges from 700 Å to 4000 Å, and the total thickness of the stress buffer layer and the second diffusion barrier layer ranges from 300 Å to 800 Å.
8. A capacitor structure, characterized in that: include: substrate; a first diffusion barrier layer, above the substrate; A first electrode layer, located above the first diffusion barrier layer; A stress buffer layer, located above the first electrode layer; a second diffusion barrier layer, above the stress buffer layer; a dielectric layer, located above the second diffusion barrier layer; The second electrode layer is located above the dielectric layer.
9. The capacitor structure according to claim 8, characterized in that: The material of the first electrode layer includes aluminum, the material of the first diffusion barrier layer and the second diffusion barrier layer includes tantalum nitride, and the material of the stress buffer layer includes tantalum.
10. The capacitor structure according to claim 8, characterized in that: The thickness of the first electrode layer ranges from 700 Å to 4000 Å, and the total thickness of the stress buffer layer and the second diffusion barrier layer ranges from 300 Å to 800 Å.