Chip testing method based on deep learning optimization

Abstract

The invention discloses a chip testing method based on deep learning optimization, and relates to the technical field of chip testing, and the method comprises the steps: outputting an optimal power supply power-on sequence through a Q value updating and priority experience playback mechanism; electrical signal feature vectors of the pins are extracted through a convolutional neural network, self-supervised learning is adopted, abnormal connection between pin signals is detected by comparing a loss function, whether the pins are short-circuited or open-circuited is judged by calculating signal feature distances, and an open-short circuit detection result of the chip is obtained; a multi-layer perceptron is used for automatically adjusting and optimizing configuration parameters, and optimized chip configuration parameters are obtained; and performing system-level chip testing and verification by using the recurrent neural network to obtain a system-level testing result. In the aspects of power-on sequence optimization, open-circuit and short-circuit detection, parameter tuning and system-level testing, high efficiency, accuracy and comprehensiveness which cannot be achieved by a traditional method are achieved, the efficiency and reliability of chip testing are improved, and the method is suitable for mass production and quality control of high-complexity chips.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip testing method based on deep learning optimization. Background Art

[0002] With the rapid development of semiconductor technology, the integration and complexity of chips are increasing. Traditional chip testing methods have been unable to cope with the complex system-on-chip (SoC) and multi-chip package (SIP) testing requirements. Current chip testing methods usually rely on automatic test equipment (ATE) and preset test vectors, but the test efficiency and accuracy are greatly limited when faced with the diversity of chip functions and performance. The traditional chip testing process relies on a fixed power-on sequence, manual configuration parameters, and engineering experience to analyze and judge the test results. With the increasing complexity of chip design, the amount of chip test data has increased dramatically, manual analysis and optimization have become more difficult, and test blind spots are prone to occur, affecting the reliability and mass production process of the chip. On the other hand, deep learning technology has made significant progress in image recognition, natural language processing and other fields in recent years, and its potential in processing complex data and automated decision-making has been widely recognized. Therefore, introducing deep learning technology into the field of chip testing, especially in the optimization of automated test processes, data analysis and decision support, has become an important direction to solve the current bottleneck of chip testing. Summary of the invention

[0003] The present invention provides a chip testing method based on deep learning optimization, aiming to solve the problems of low chip testing efficiency, complex data analysis, and poor reliability of test results in the prior art.

[0004] In order to solve the above problems, the technical solution adopted by the present invention is as follows: The present invention provides a chip testing method based on deep learning optimization, comprising: (1) Based on the power profile and historical initialization data, the deep Q network is used to optimize the power-on sequence of the chip, and the optimal power-on sequence is output through the Q value update and priority experience playback mechanism; (2) According to the optimal power-on sequence and the chip pin connection diagram, the electrical signal feature vector of the pin is extracted through a convolutional neural network. Self-supervised learning is used to detect abnormal connections between pin signals through a contrast loss function. By calculating the signal feature distance, it is determined whether the pin is short-circuited or open-circuited, and the open-short circuit detection result of the chip is obtained. (3) Based on the optimal power-on sequence, open-short circuit detection results, and chip configuration files, a multi-layer perceptron is used to automatically tune the configuration parameters to obtain the optimized chip configuration parameters; (4) Based on the chip test data, the chip design standards and target parameter set, and the optimized chip configuration parameters, a recurrent neural network is used to perform system-level chip testing and verification to obtain system-level test results.

[0005] Specifically, in step (1), the power configuration file describes the power requirements and power-on sequence of each module of the chip, and the historical initialization data records the initialization success rate under different power-on sequences.

[0006] Specifically, in step (1), the superposition characteristic of quantum bits is used to construct a quantum Q value table, and the Q value is updated and adjusted through quantum gate operations. At each moment, the system queries the quantum Q value table according to the current state and selects the power-on operation. At the same time, the quantum entanglement characteristic is used to realize quantum optimization adjustment of TD error, and the convergence speed of Q value is accelerated through the superposition and entanglement of quantum states. The construction of the quantum Q value table includes initializing the quantum bit state, updating the quantum bit state according to the power-on decision, and obtaining the Q value through quantum measurement. The quantum gate operation includes Hadamard gate, CNOT gate and rotation gate, which are used to operate the quantum bit to realize the update and adjustment of the Q value. The quantum optimization adjustment also includes quantum error correction of the Q value, and the errors in the Q value update process are detected and corrected by quantum error correction code to ensure the accuracy of the Q value.

[0007] Specifically, in step (1), the Q value is used to guide the power-on decision, including the power-on decision of the current state, the Q value maximization principle, the power-on decision mechanism and the adjustment of the TD error; the power-on decision of the current state means that at each moment, the system queries the currently known Q value table or deep Q network according to the current state and selects the power-on operation; the Q value maximization principle means that in the future state, the maximum Q value among all possible power-on operations is selected; the power-on decision mechanism means that in the current state, the operation that maximizes the Q value is selected; the adjustment of the TD error means minimizing the deviation between the current Q value and the target Q value by continuously updating the Q value.

[0008] Specifically, in step (1), the priority experience replay mechanism refers to the priority learning of operations with large TD errors based on the experience replay weight.

[0009] Specifically, in step (2), the contrast loss function formula is: in, Indicates pin The electrical state characteristics, For pin and The Euclidean distance between It indicates that the loss is calculated when the two pins are connected differently; m is the threshold between normal and abnormal connection.

[0010] Specifically, in step (2), in the process of extracting the electrical signal feature vector of the pin, multimodal data is also obtained through a number of sensors, including the temperature and vibration of the chip; the multimodal data is fused with the electrical signal feature vector; the fusion process includes data preprocessing, feature extraction and feature fusion; the data preprocessing includes normalizing and denoising the multimodal data; feature extraction includes using different neural network models to extract features from the multimodal data respectively, and the extracted features include temperature feature vectors and vibration feature vectors; feature fusion includes fusing the electrical signal feature vector with feature vectors of other modes, using weighted summation or splicing to obtain an enhanced feature vector, and performing dimensionality reduction processing on the enhanced feature vector, using principal component analysis or autoencoder method to reduce the dimension of the feature vector.

[0011] Specifically, in step (3), the Adam optimizer is used to update the configuration parameter set in the multilayer perceptron. The chip configuration parameters are gradually adjusted and optimized by minimizing the comprehensive loss function, which combines the power consumption, frequency and temperature performance indicators. The learning rate hot restart strategy is used to periodically adjust the learning rate so that the comprehensive loss function avoids the local optimal solution. The learning rate adjustment formula is: in, is the current learning rate, and are the minimum and maximum learning rates, respectively, is the current iteration number, Restart period for the learning rate.

[0012] Specifically, in step (4), the hidden state of the recurrent neural network is used to store the information derived from the previous time step and is updated at each time step. The hidden layer of the recurrent neural network is used to process the timing information of the input data and learn the temporal dependencies through multi-layer recursive units.

[0013] Optionally, in step (4), if the value of the system-level test result reaches 0.9, the chip is determined to have passed all tests, otherwise it fails.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The power-on sequence of the chip is optimized through the deep Q network (DQN). Combined with the power profile and historical initialization data, the power-on sequence is dynamically adjusted through Q value update and priority experience playback mechanism to output the optimal power-on solution. Compared with the traditional fixed power-on sequence, it can be adaptively optimized according to the actual test environment to avoid test failures caused by improper power-on sequence, and improve the success rate and overall efficiency of chip startup test. Based on the convolutional neural network (CNN), the feature vector of the chip pin electrical signal is extracted. The self-supervised learning method is used to detect abnormal connections between pin signals by comparing the loss function. By calculating the signal feature distance, it can accurately determine whether the chip pin is short-circuited or open-circuited. This neural network-based open-short circuit detection method has the characteristics of high automation and high accuracy, which can effectively reduce the error of manual detection and improve the detection accuracy and speed. Use a multi-layer perceptron (MLP) to automatically tune the chip's configuration parameters based on the optimal power-on sequence, open-short circuit detection results, and the chip's configuration file to ensure that the chip is always in the optimal configuration state during the test. Compared with the traditional manual parameter adjustment method, the automated tuning process can significantly improve the parameter adjustment efficiency, reduce debugging time, and optimize the chip's power consumption, frequency, and other parameters to ensure the chip's stability and performance during the test. The chip test data is analyzed through a recurrent neural network (RNN), and system-level testing and verification is performed in combination with the chip's design standards and target parameter sets, as well as the optimized configuration parameters. RNN can capture the timing dependencies in the test data and comprehensively analyze the chip's performance in different test scenarios. The final output of the system-level test results not only covers the chip's performance in various test scenarios, but also effectively determines whether the chip meets the design standards, providing accurate system-level test evaluation to ensure that the chip's functions and performance meet expected requirements.

[0015] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the embodiments of the present invention are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 This is a flow chart of the chip testing method based on deep learning optimization described in the embodiment. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0019] The embodiment of the present invention discloses a chip testing method based on deep learning optimization. The method is performed in an ATE (automatic test equipment) test system. After the ATE PCB is completed, the chip test can be performed. Figure 1 As shown, it specifically includes the following four steps: power-on sequence optimization, open and short circuit testing, online parameter configuration optimization, and system-level testing and verification.

[0020] 1. Power-on sequence optimization According to the power profile and historical initialization data , using the deep Q network (DQN) to optimize the power-on sequence of the chip, and output the optimal power-on sequence through Q value update and priority experience playback mechanism , maximize the success rate of chip initialization.

[0021] Among them, the superposition characteristics of quantum bits are used to construct a quantum Q value table, and the Q value is updated and adjusted through quantum gate operations; at each moment, the system queries the quantum Q value table according to the current state and selects the power-on operation; at the same time, the quantum entanglement characteristics are used to realize quantum optimization adjustment of TD errors, and the convergence speed of Q values ​​is accelerated through the superposition and entanglement of quantum states, thereby improving the efficiency and accuracy of power-on sequence optimization; the construction of the quantum Q value table includes initializing the quantum bit state, updating the quantum bit state according to the power-on decision, and obtaining the Q value through quantum measurement; the quantum gate operations include Hadamard gates, CNOT gates and rotation gates, which are used to operate on quantum bits to realize the update and adjustment of Q values; the quantum optimization adjustment also includes quantum error correction of Q values, and errors in the Q value update process are detected and corrected by quantum error correction codes to ensure the accuracy of Q values.

[0022] Power Profiles Describes the power requirements and power-on timing of each module of the chip, historical initialization data What is recorded is the initialization success rate under different power-on sequences.

[0023] The Q value update formula is used to calculate the value of each power-up operation, as follows: in: Indicates the current status Next, select the current power-on operation The Q value at the time represents the state Perform the following operations The expected cumulative reward that can be obtained after The current chip status, including historical initialization data and current power configuration; is the power-on operation at the current moment, that is, the power-on sequence operation selected by the chip at time point t; is the immediate reward, indicating the improvement in the success rate of the current power-on sequence; γ is the discount factor, which weighs the impact of future rewards on the current decision, γ∈[0,1]. If γ is close to 1, it means that future rewards are more important. Conversely, if γ is close to 0, it means that the system pays more attention to the current immediate reward; α is the learning rate, which controls the step size of the Q value update and is a decimal used to balance the weights of new and old information.

[0024] Indicates that at the next moment In this state, the maximum Q value among all possible power-on operations A is selected. This value represents At this moment, the future reward that can be obtained by performing the optimal operation; A represents an operation in the set of all possible power-on operations. Usually different power-on strategies will produce different operation sequences.

[0025] The Q value is used to guide the power-on decision, including the power-on decision of the current state, the Q value maximization principle, the power-on decision mechanism and the adjustment of the TD error.

[0026] The power-on decision of the current state is: at each time t, the system To query the currently known Q value table or deep Q network, select the power-on operation .

[0027] The Q value maximization principle means that in order to obtain the best power-on sequence, the Q value in the update formula is updated. , that is, in the future state In this case, the maximum Q value among all possible power-on operations is selected. This maximum value represents the long-term cumulative benefit that the current operation can bring.

[0028] The power-on decision mechanism refers to: Next, select the operation that maximizes the Q value. This is done to ensure that in each state, the power-on operation selected by the system can bring the optimal cumulative reward, that is, to ensure that the chip is in the best state in each power-on step, thereby avoiding the adverse effects of unreasonable power-on sequence on the chip.

[0029] The adjustment of TD error means that the Q value is updated through the TD error. The TD error reflects the deviation between the current Q value and the target Q value. This error is minimized by continuously updating the Q value, thereby continuously improving the power-on sequence.

[0030] The TD error at the current moment is the core of the experience replay priority calculation and is directly related to the Q value calculation formula. The TD error calculation formula is: The TD error at the current moment indicates the gap between the currently predicted Q value and the actual reward. The larger the TD error, the less accurate the model's estimate of the current power-on operation. That is, the larger the estimation error of the current Q value, the higher the learning priority should be. Prioritizing learning these experiences helps the model quickly converge to the optimal strategy.

[0031] In this embodiment, a priority experience replay mechanism is adopted to sort the experience priority of each power-on operation, and the operation with large TD error is learned first. The experience replay weight calculation formula is: in: is the TD error of the i-th experience, which represents the prediction error of the Q value in this experience; is the TD error of the kth experience, which serves as a reference value in the experience set; β is a parameter that controls the impact of priority, which takes a value between 0 and 1 and is used to adjust the weight of experience replay.

[0032] The priority experience replay mechanism ensures that the model learns the effective power-on sequence faster.

[0033] Through repeated training and Q value update, the optimal action sequence for each power-on sequence can be determined, that is, the optimal power-on sequence can be obtained. ,This sequence is composed of the Q value maximization strategy obtained by multiple iterative optimization, that is the set of optimal power-on action sequences selected under different states, ensuring the highest initialization success rate.

[0034] 2. Open and short circuit test After the power supply power-on sequence optimization is completed, according to the optimal power supply power-on sequence Chip pin connection diagram , extract the electrical signal feature vector of the pin through convolutional neural network (CNN) , self-supervised learning is used to detect abnormal connections between pin signals through contrast loss function, and by calculating the signal feature distance, it is determined whether the pin is short-circuited or open-circuited, and the open-short circuit detection result of the chip is obtained. .

[0035] In the process of extracting the electrical signal feature vector of the pin, in addition to extracting the electrical signal feature vector, multimodal data such as temperature and vibration of the chip are obtained through other sensors, and these multimodal data are fused with the electrical signal feature vector; the multimodal data fusion includes three steps: data preprocessing, feature extraction and feature fusion; data preprocessing is to normalize and denoise the multimodal data to meet the requirements of feature extraction; feature extraction is to use different neural network models to extract features from multimodal data respectively to obtain temperature feature vectors, vibration feature vectors, etc.; feature fusion is to fuse the electrical signal feature vector with the feature vectors of other modes, and obtain an enhanced feature vector by weighted summation or splicing; the feature fusion also includes dimensionality reduction processing of the fused feature vector, using methods such as principal component analysis or autoencoder to reduce the dimension of the feature vector and improve the efficiency of subsequent self-supervised learning.

[0036] In this embodiment, the chip pin connection diagram Shows the electrical connection relationship of the chip pins.

[0037] The contrast loss function formula is: in: For pin The feature vector represents the electrical state characteristics of the pin; For pin and The Euclidean distance between them indicates the difference in electrical states between them; Indicates that the loss is calculated when the two pins are connected differently; m is the threshold between normal and abnormal connections. When the distance between the feature vectors exceeds the threshold, it is determined to be a short circuit or open circuit fault, that is, the open and short circuit detection result of the chip is obtained. , which is used to ensure the integrity of chip connections.

[0038] 3. Online configuration parameter optimization After the chip passes the open and short circuit test, the power-on sequence is optimized. , Open and short circuit detection results and chip configuration files , use multi-layer perceptron (MLP) to automatically tune the configuration parameters and obtain the optimized chip configuration parameters .

[0039] In the process of automatic tuning of configuration parameters, a reinforcement learning algorithm can be introduced to dynamically adjust test parameters, such as test frequency, test voltage, etc., according to real-time feedback during the test process to optimize the test effect; the reinforcement learning algorithm includes four parts: state representation, action space, reward function and strategy update; the state representation is to encode the state of the current test process, including test parameters, test results and other information; the action space is a set of adjustable test parameters; the reward function is to reward or punish actions according to the quality of the test results; the strategy update is to update the strategy of the reinforcement learning model according to the feedback of the reward function to select better test parameters.

[0040] Chip Configuration File Defines the chip's functions and performance parameters. The initial file includes the initial configuration parameter set. .

[0041] In this embodiment, the Adam optimizer is used to update the configuration parameter set in the multilayer perceptron. , by minimizing the loss function, the chip configuration parameters are gradually adjusted to reach the optimal state. Specifically, the Adam optimizer calculates the gradient based on the loss function of the multi-layer perceptron (i.e., the deviation between the configuration parameters and the chip performance), and then updates the configuration parameter set in each iteration. , to minimize the loss function.

[0042] Loss Function Used to measure the current configuration parameter set The impact on chip performance depends on the performance target of the chip. In this embodiment, the loss function It is a comprehensive function that integrates important performance indicators of the chip, such as power consumption, frequency, and temperature, and aims to minimize the deviation between these actual indicators and the target values ​​to ensure the optimal adjustment of chip performance. The specific form is as follows: in: is the power consumption value of the current chip; is the target power consumption value, which is the design specification of the chip; is the operating frequency of the current chip; is the target operating frequency; is the current operating temperature of the chip; The maximum operating temperature of the chip. Exceeding this temperature will cause performance degradation or even chip damage. is the weight coefficient, which is used to adjust the contribution of different performance indicators to the objective function, depending on the priority in the design goal.

[0043] During the optimization process, the loss function By periodically adjusting the learning rate, we can avoid local optimal solutions and ensure that the final configuration parameter set Able to maximize chip performance.

[0044] In this embodiment, a learning rate hot restart strategy is adopted to periodically adjust the learning rate to avoid falling into a local optimal solution. The learning rate adjustment formula is: in: is the current learning rate, which indicates the learning rate used in the optimization process and is dynamically adjusted through the learning rate hot restart strategy; and They are the minimum and maximum learning rates, respectively, defining the range of learning rate adjustment; is the current iteration step number, indicating the optimization process; It is the learning rate restart period, which determines the learning rate.

[0045] Use the Adam optimizer to configure the parameter set Perform iterative updates to minimize the loss function .

[0046] During model training, the Adam optimizer iteratively updates the parameter set in the neural network. , to minimize the loss function of the configuration parameters .

[0047] The update rules of the Adam optimizer are as follows: 1) First, Adam uses the current parameter set Calculating the loss function Gradient ; 2) Adam performs weighted average of gradients and calculates first-order momentum : in is a hyperparameter that controls the first-order momentum decay; 3) Adam calculates the square weighted average of the gradient to obtain the second-order momentum : in is a hyperparameter that controls the second-order momentum decay; 4) Adam based on first-order momentum and second-order momentum Update parameter set , the update formula is as follows: in To avoid small constants with zero denominators, is the learning rate.

[0048] Through the above update process, the Adam optimizer can effectively adjust the parameter set in the multilayer perceptron , to minimize the loss function , thereby realizing automatic tuning of configuration parameters and finally obtaining the optimal configuration parameter combination, that is, the optimized chip configuration parameters , containing the final configuration values ​​of each functional module.

[0049] In this step, the learning rate The dynamic adjustment of the parameter set ensures flexibility in the optimization process and avoids falling into the local optimal solution, thereby improving the global optimization ability of the model. The iterative update of is performed through the Adam optimizer, which ensures the full use of gradient information, thereby improving the optimization efficiency and accuracy. To finally optimize the configuration parameters, the chip configuration achieves optimal performance through deep learning models and gradient optimization algorithms.

[0050] 4. Chip system testing and verification After the configuration parameters are optimized, based on the chip test data , chip design standards and target parameter sets And optimized chip configuration parameters , using recurrent neural network (RNN) to test and verify the system-level chip and obtain system-level test results , as follows: First, test the chip data Standardize to ensure that data of different dimensions have the same magnitude; then test data from the chip Extract timing features and compare them with the optimized chip configuration parameters Combine to get the data to be input into RNN .

[0051] Where n is the number of test time points, are the voltage, power consumption and temperature at each moment respectively.

[0052] RNN is used to process the timing information in the test data and can capture the changing trend of various parameters of the chip in the time dimension. RNN includes hidden states , input layer, hidden layer and output layer. Hidden state It is used to store information derived from the previous time step and update it at each time step. The input layer takes the normalized test data sequence Input into RNN. The hidden layer is used to process the timing information of the input data and learn the temporal dependencies through multi-layer recurrent units. The output layer is used to output the output of each time step. .

[0053] The update formula of RNN is: in, is the input data at the current moment; is the weight matrix, which is used for mapping between input and hidden layers; is the bias vector; σ is the activation function, and the ReLU function is used here.

[0054] The output at each time step Indicates whether the test result of the current time step meets the design requirements of the chip, and the output value It is a binary classification result, 1 means it meets the requirements, and 0 means it does not meet the requirements.

[0055] The final test decision is obtained by synthesizing the outputs of all time steps , the output formula is: like , the chip is judged to have passed the test scenario, otherwise, the test is judged to have failed.

[0056] At each time step t, we calculate the difference between the test data and the design target. The error calculation formula is: in, is a parameter in the test data. is the target value in the design phase.

[0057] After statistics are compiled for errors in all test scenarios, an error analysis report is generated and the overall performance of the chip is output.

[0058] System Level Test Results It includes qualification determination, error analysis report and overall performance evaluation of the chip under each test scenario.

[0059] The system evaluation formula is: Where m1 is the number of test scenarios, Is the final test decision for each scenario. If the system-level test result If the value reaches 0.9, the chip is judged to have passed all tests.

[0060] For the chip testing method described in this embodiment, the following operations may also be performed: During the system-level testing and verification phase, a generative adversarial network (GAN) can also be used to generate more test data samples to cover more test scenarios and boundary conditions. The generative adversarial network consists of two parts: a generator and a discriminator. The generator is used to generate test data samples, and the discriminator is used to determine whether the generated data conforms to the distribution of real data. Through adversarial training of the generator and the discriminator, the generator can generate test data samples similar to real data. The generated test data samples include different input stimuli, environmental conditions, and chip configuration parameters to comprehensively test the performance of the chip.

[0061] For data that needs to be stored, blockchain technology can also be used to encrypt and store test data to ensure the security and integrity of the test data; blockchain technology includes the generation of data blocks, the construction of chain structures and the implementation of consensus mechanisms; the generation of data blocks is to perform hash operations on test data to generate a unique identifier for the data block; the construction of the chain structure is to link the data blocks in chronological order to form a tamper-proof chain structure; the implementation of the consensus mechanism is to verify and confirm the data blocks through nodes in the distributed network to ensure the consistency and reliability of the data.

[0062] When processing data, edge computing technology can also be used to process test data in real time, reduce data transmission delays, and improve test response speeds. Edge computing technology includes edge device deployment, data preprocessing, and edge intelligent analysis. Edge device deployment is to deploy computing nodes close to test equipment to reduce data transmission distances. Data preprocessing is to perform preliminary processing on test data, such as filtering and downsampling, to reduce the amount of data. Edge intelligent analysis uses lightweight machine learning models to perform data analysis on edge devices to quickly obtain preliminary results.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A chip testing method based on deep learning optimization, characterized in that: The following steps are involved: (1) Based on the power profile and historical initialization data, the deep Q network is used to optimize the power-on sequence of the chip, and the optimal power-on sequence is output through the Q value update and priority experience playback mechanism; (2) According to the optimal power-on sequence and the chip pin connection diagram, the electrical signal feature vector of the pin is extracted through a convolutional neural network. Self-supervised learning is used to detect abnormal connections between pin signals through a contrast loss function. By calculating the signal feature distance, it is determined whether the pin is short-circuited or open-circuited, and the open-short circuit detection result of the chip is obtained. (3) Based on the optimal power-on sequence, open-short circuit detection results, and chip configuration files, a multi-layer perceptron is used to automatically tune the configuration parameters to obtain the optimized chip configuration parameters; (4) Based on the chip test data, the chip design standards and target parameter set, and the optimized chip configuration parameters, a recurrent neural network is used to perform system-level chip testing and verification to obtain system-level test results.

2. The chip testing method according to claim 1, characterized in that: In step (1), the power configuration file describes the power requirements and power-on sequence of each module of the chip, and the historical initialization data records the initialization success rate under different power-on sequences.

3. The chip testing method according to claim 1, characterized in that: In step (1), the superposition characteristic of quantum bits is used to construct a quantum Q value table, and the Q value is updated and adjusted through quantum gate operations. At each moment, the system queries the quantum Q value table according to the current state and selects the power-on operation. At the same time, the quantum entanglement characteristic is used to realize quantum optimization adjustment of TD error, and the convergence speed of Q value is accelerated through the superposition and entanglement of quantum states. The construction of the quantum Q value table includes initializing the quantum bit state, updating the quantum bit state according to the power-on decision, and obtaining the Q value through quantum measurement. The quantum gate operation includes Hadamard gate, CNOT gate and rotation gate, which are used to operate the quantum bit to realize the update and adjustment of the Q value. The quantum optimization adjustment also includes quantum error correction of the Q value, and the errors in the Q value update process are detected and corrected by quantum error correction code to ensure the accuracy of the Q value.

4. The chip testing method according to claim 1, characterized in that: In step (1), the Q value is used to guide the power-on decision, including the power-on decision of the current state, the Q value maximization principle, the power-on decision mechanism and the adjustment of the TD error; The power-on decision of the current state means that at each moment, the system queries the currently known Q value table or deep Q network according to the current state and selects the power-on operation; the Q value maximization principle means that in the future state, the maximum Q value among all possible power-on operations is selected; The power-on decision mechanism refers to selecting the operation that maximizes the Q value in the current state; the adjustment of the TD error refers to minimizing the deviation between the current Q value and the target Q value by continuously updating the Q value.

5. The chip testing method according to claim 1, characterized in that: In step (1), the priority experience replay mechanism refers to the priority learning of operations with large TD errors based on the experience replay weight.

6. The chip testing method according to claim 1, characterized in that: In step (2), the contrast loss function formula is: in, Indicates pin The electrical state characteristics, For pin and The Euclidean distance between It indicates that the loss is calculated when the two pins are connected differently; m is the threshold between normal and abnormal connection.

7. The chip testing method according to claim 1, characterized in that: In step (2), in the process of extracting the electrical signal feature vector of the pin, multimodal data including the temperature and vibration of the chip are also acquired through a number of sensors; the multimodal data is fused with the electrical signal feature vector; the fusion process includes data preprocessing, feature extraction and feature fusion; Data preprocessing includes normalizing and denoising multimodal data; feature extraction includes using different neural network models to extract features from multimodal data respectively, and the extracted features include temperature feature vectors and vibration feature vectors; feature fusion includes fusing the electrical signal feature vector with the feature vectors of other modes, using weighted summation or splicing to obtain an enhanced feature vector, and performing dimensionality reduction processing on the enhanced feature vector, using principal component analysis or autoencoder methods to reduce the dimension of the feature vector.

8. The chip testing method according to claim 1, characterized in that: In step (3), the Adam optimizer is used to update the configuration parameter set in the multilayer perceptron. The chip configuration parameters are gradually adjusted and optimized by minimizing the comprehensive loss function, which combines the power consumption, frequency and temperature performance indicators. The learning rate hot restart strategy is used to periodically adjust the learning rate so that the comprehensive loss function avoids the local optimal solution. The learning rate adjustment formula is: in, is the current learning rate, and are the minimum and maximum learning rates, respectively, is the current iteration number, Restart period for the learning rate.

9. The chip testing method according to claim 1, characterized in that: In step (4), the hidden state of the recurrent neural network is used to store the information derived from the previous time step and is updated at each time step. The hidden layer of the recurrent neural network is used to process the timing information of the input data and learn the temporal dependencies through multi-layer recursive units.

10. The chip testing method according to claim 1, characterized in that: In step (4), if the value of the system-level test result reaches 0.9, the chip is judged to have passed all tests, otherwise it fails.

Images