A method, device and equipment for extracting capacitance information

Abstract

The present application relates to the field of integrated circuit technologies, and discloses a method, apparatus, and device for extracting capacitance information. Among them, the method includes: obtaining a conductor object for which capacitance information is to be extracted, and for a first conductor in the conductor object, determining a second conductor that belongs to a different conductor network from the first conductor and has a short-circuit relationship with the first conductor; identifying a target area where the first conductor and the second conductor are short-circuited, and based on the position information of the target area, separating the first conductor and the second conductor so that there is no short-circuit relationship between the separated first conductor and the second conductor; determining a capacitance filtering area between the separated first conductor and the second conductor, and when extracting the capacitance information of the separated first conductor, excluding the capacitance information located within the capacitance filtering area. The technical solution provided by the present application can improve the accuracy of capacitance extraction.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a method, device, and equipment for extracting capacitance information. Background Art

[0002] In the field of integrated circuit technology, to meet specific design requirements, sometimes it is necessary to ignore the capacitance extracted from some conductors. Existing solutions usually filter the capacitance between different layers through process files, or regard some conductors as cuboids in the device area, thereby ignoring the capacitance of these cuboids. However, these techniques are often only applicable to specific scenarios. Once out of these specific scenarios, the accuracy of capacitance extraction will decrease. For example, for the problem of capacitance extraction at the conductor contact part, traditional methods will produce large capacitance extraction errors when the conductors are short-circuited.

[0003] Therefore, there is an urgent need for a more accurate method for extracting capacitance information. Summary of the Invention

[0004] This application provides a method, device, and equipment for extracting capacitance information, which can improve the extraction accuracy of capacitance information.

[0005] To achieve the above object, the main technical solutions adopted in this application include:

[0006] In a first aspect, an embodiment of this application provides a method for extracting capacitance information. The method includes:

[0007] Obtain a conductor object for which capacitance information is to be extracted. For a first conductor in the conductor object, determine a second conductor that belongs to a different conductor network from the first conductor and has a short-circuit relationship with the first conductor;

[0008] Identify a target area where the first conductor and the second conductor are short-circuited, and based on the position information of the target area, separate the first conductor and the second conductor so that there is no short-circuit relationship between the separated first conductor and the second conductor;

[0009] Determine a capacitance filtering area between the separated first conductor and the second conductor, and when extracting the capacitance information of the separated first conductor, exclude the capacitance information located in the capacitance filtering area.

[0010] A method for extracting capacitance information provided by this embodiment identifies a first conductor and a second conductor with a short - circuit relationship in a conductor object, thereby determining an area that may cause capacitance calculation errors. Subsequently, by separating the first conductor and the second conductor, the short - circuit relationship between them can be eliminated, ensuring that the capacitance information extraction process can be normally executed. During the process of extracting capacitance information, by determining a capacitance filtering area and removing the capacitance information within this area, the capacitance information introduced additionally due to eliminating the short - circuit relationship is avoided, thereby improving the accuracy of capacitance extraction. The entire process can not only ensure that conductors with a short - circuit relationship can normally extract capacitance information, but also reduce the error of capacitance extraction, ensuring the accuracy of capacitance information, providing more accurate data for chip layout design, and optimizing the process of chip layout design.

[0011] In one embodiment, identifying the target area where the first conductor and the second conductor are short - circuited includes:

[0012] Obtaining the first spatial coordinates corresponding to each surface of the first conductor and obtaining the second spatial coordinates corresponding to each surface of the second conductor;

[0013] According to the first spatial coordinates and the second spatial coordinates, determining the overlapping area between the first conductor and the second conductor, and determining the target area where the first conductor and the second conductor are short - circuited based on the overlapping area.

[0014] This embodiment accurately determines the geometric positions and shapes of the conductors by obtaining the spatial coordinates of each surface of the first conductor and the second conductor, providing accurate geometric data support for subsequent capacitance calculations. Then, the overlapping area between the first conductor and the second conductor can be determined through the first spatial coordinates and the second spatial coordinates, and this overlapping area can determine the target area where the two conductors are short - circuited. By identifying the target area where the short - circuit occurs, the accuracy of subsequent capacitance extraction can be ensured, reducing the calculation error caused by the short - circuit area and improving the accuracy of capacitance calculation in chip layout design.

[0015] In one embodiment, separating the first conductor and the second conductor based on the position information of the target area includes:

[0016] If the position information of the target area indicates that the target area is on the same plane, cut off a specified thickness area in the first conductor and / or the second conductor along the normal direction of the target area to separate the first conductor and the second conductor.

[0017] In this embodiment, if the target region lies on the same plane, a region with a specified thickness is cut along the normal direction, which can accurately separate the conductors, thus ensuring that the capacitance information extraction process can be normally performed. In addition, by precisely controlling the depth and position of the cut, the error introduced due to conductor cutting can be minimized as much as possible while ensuring sufficient spacing between the conductors, improving the accuracy of subsequent capacitance calculation.

[0018] In one embodiment, the region cut on the first conductor and / or the second conductor matches the projection of the target region in the normal direction.

[0019] In this embodiment, by precisely matching the cut region, it is ensured that only the necessary part of the conductor is removed, thus avoiding capacitance errors caused by unreasonable conductor cutting. Secondly, the coincidence of the cut region and the projection of the target region can effectively improve the electrical isolation between the conductors, preventing short circuits or signal interference.

[0020] In one embodiment, separating the first conductor and the second conductor based on the position information of the target region includes:

[0021] If the position information of the target region indicates that the target region lies on the same plane, move the first conductor and / or the second conductor along the normal direction of the target region to separate the first conductor and the second conductor.

[0022] In this embodiment, the first conductor and the second conductor are separated by moving, which can not only eliminate the short - circuit relationship between the conductors, but also avoid cutting the conductors themselves, thus improving the extraction accuracy of capacitance information.

[0023] In one embodiment, separating the first conductor and the second conductor based on the position information of the target region includes:

[0024] If the position information of the target region indicates that the target region lies on different multiple planes, split the target region into sub - regions corresponding to each plane respectively;

[0025] Traverse each of the sub - regions, and for the current sub - region, cut a region with a specified thickness in the first conductor and / or the second conductor along the normal direction of the current sub - region to separate the first conductor and the second conductor.

[0026] In this embodiment, by splitting the target area into multiple sub-areas, each sub-area can be independently processed on the same plane, which can avoid conductor interference between different planes and ensure the accuracy of conductor separation. By precisely cutting a specified thickness of the conductor along the normal direction within each sub-area, not only can the cutting depth and shape of the conductor be effectively controlled, but also the situation of over-cutting or under-cutting can be avoided during the cutting process, thereby improving the accuracy and quality of conductor separation. In addition, precise cutting operations can increase the physical isolation between conductors and reduce the risk of short circuits, thus ensuring the stability and safety of the circuit. This way of splitting the sub-areas enables each sub-area to be independently optimized according to specific requirements, enhancing the accuracy of capacitance calculation.

[0027] In one embodiment, separating the first conductor and the second conductor based on the position information of the target area includes:

[0028] If the position information of the target area indicates that the target area is located on multiple different planes, determine the reference planes corresponding to the multiple different planes, and move the first conductor and / or the second conductor along the normal direction of the reference planes to separate the first conductor and the second conductor.

[0029] In this embodiment, by selecting a suitable reference plane among the multiple planes of the target area and adjusting the positions of the conductors along the normal direction of the reference plane, the short-circuit relationship between the conductors can be effectively avoided, thereby ensuring the normal operation of the circuit and avoiding faults or performance degradation caused by short circuits. This method enables precise control of the relative positions of the conductors, optimizes the circuit layout without affecting other circuit components, reduces electrical interference, and improves the accuracy of capacitance calculation. At the same time, flexibly selecting the reference plane and ensuring movement along the normal direction of the reference plane can smoothly separate the conductors. This way reduces the number of conductor adjustments and the risk of inaccuracy in subsequent capacitance calculation.

[0030] In one embodiment, determining the capacitance filtering area between the separated first conductor and second conductor includes:

[0031] If the target area is located on the same plane, along the normal direction of the target area, determine the first projection area of the target area on the first conductor and the second projection area of the target area on the second conductor;

[0032] Determine the first projection area and the second projection area as the capacitance filtering area between the separated first conductor and second conductor.

[0033] In this embodiment, by projecting along the normal direction in the target area to determine the projection areas on the first conductor and the second conductor, the capacitance contribution area between the two conductors can be accurately located, thereby improving the accuracy of capacitance calculation. In addition, by setting a capacitance filtering area, that is, restricting the capacitance calculation between the first projection area and the second projection area, the calculation result is ensured to be more reliable. This method can clearly delimit the capacitance influence area and reduce the interference of the separation operation on the capacitance calculation result.

[0034] In one implementation, the method further includes:

[0035] If the target area is located on multiple different planes, split the target area into sub-areas corresponding to each plane respectively;

[0036] Traverse each of the sub-areas, and for the current sub-area, along the normal direction of the sub-area, determine the third projection area of the sub-area on the first conductor and the fourth projection area of the sub-area on the second conductor, and determine the third projection area and the fourth projection area as the capacitance filtering area between the separated first conductor and the second conductor.

[0037] In this embodiment, by splitting the target area into multiple sub-areas and performing projection and capacitance calculation on each sub-area respectively, the accuracy and adaptability of capacitance calculation can be significantly improved. This solution can more accurately process the capacitance contribution of the target area on different planes and avoid calculation errors caused by complex geometric shapes. At the same time, the capacitance calculation of each sub-area is performed on its independent plane, thus ensuring the accuracy of the calculation result.

[0038] In a second aspect, an embodiment of the present application provides a device for extracting capacitance information, and the device includes:

[0039] A conductor object acquisition unit, configured to acquire a conductor object for which capacitance information is to be extracted, and for the first conductor in the conductor object, determine a second conductor that belongs to a different conductor network from the first conductor and has a short-circuit relationship with the first conductor;

[0040] A conductor separation unit, configured to identify the target area where the first conductor and the second conductor are short-circuited, and based on the position information of the target area, separate the first conductor and the second conductor so that there is no short-circuit relationship between the separated first conductor and the second conductor;

[0041] A capacitance filtering unit, configured to determine the capacitance filtering area between the separated first conductor and the second conductor, and when extracting the capacitance information of the separated first conductor, exclude the capacitance information located within the capacitance filtering area.

[0042] In a third aspect, an embodiment of the present application provides a computer device, which includes a memory and a processor. The memory is used to store a computer program. When the computer program is executed by the processor, the method for extracting capacitance information as described above is implemented. Description of the Drawings

[0043] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0044] Figure 1 It is a flowchart of a method for extracting capacitance information provided by an embodiment of the present application;

[0045] Figure 2 It is a schematic diagram of a resection operation provided by an embodiment of the present application;

[0046] Figure 3 It is a schematic diagram of another resection operation provided by an embodiment of the present application;

[0047] Figure 4 It is a schematic diagram of another resection operation provided by an embodiment of the present application;

[0048] Figure 5 It is a schematic diagram of a reference plane provided by an embodiment of the present application;

[0049] Figure 6 It is a block diagram of a device for extracting capacitance information provided by an embodiment of the present application;

[0050] Figure 7 It is a schematic diagram of the structure of a computer device provided by an embodiment of the present application;

[0051] Figure 8 It is a schematic diagram of the structure of a first conductor and a second conductor in an overlapping state provided by an embodiment of the present application;

[0052] Figure 9(a) is a schematic diagram of separating the overlapping state by the resection method provided by an embodiment of the present application;

[0053] Figure 9(b) is a schematic diagram of separating the overlapping state by the moving method provided by an embodiment of the present application.

[0054] Description of the Reference Numerals

[0055] 1 - First Conductor, 2 - Second Conductor, 3 - Target Area, 4 - Resected Area, 5 - Reference Plane. Detailed Embodiments

[0056] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the scope of protection of this application.

[0057] In the actual application process of capacitance calculation, it is often necessary to ignore the capacitance extracted from some conductor surfaces to achieve the extraction effect of certain specific characteristics. In the current capacitance calculation scheme, for the capacitance filtering problem between different layers, it is usually described in the process file. During the calculation, the software will determine which inter-layer capacitances need to be filtered, so as to eliminate the contributions of these irrelevant conductor capacitances from the capacitance calculation results and achieve the purpose of capacitance filtering.

[0058] Another common capacitance filtering technique is for filtering the capacitance of the device region. Since the graphic information in the software is usually represented in a Manhattan structure and the device also appears in the form of a cuboid in the data structure, users often hope to ignore the capacitance information of these device regions during the capacitance extraction process. At the same time, the capacitances of other graphics can be filtered according to specific parameters or converted into the total capacitance. This capacitance filtering technique is relatively common in actual applications and can effectively meet some common design requirements.

[0059] However, the existing capacitance filtering techniques often can only be targeted at specific scenarios and may not be suitable for all situations when directly applied. A typical application scenario is the problem of capacitance extraction for the contact part between conductors. When two conductors are shorted together, the traditional capacitance calculation method cannot accurately extract the capacitance. At this time, the software will regard these two conductors as different Nets, extract their capacitance information respectively, and handle the short-circuit capacitance in the subsequent calculation. However, this processing method may lead to a large capacitance extraction error, especially in the calculation of the capacitance of the conductor contact surface. Therefore, there is a need for a more accurate method for extracting capacitance information at present.

[0060] To solve the above technical problems, according to the embodiments of this application, an embodiment of a method for extracting capacitance information is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0061] In this embodiment, a method for extracting capacitance information is provided. Figure 1 The flowchart of a method for extracting capacitance information provided by an embodiment of this application is shown in Figure 1 As shown, this process includes the following steps.

[0062] Step S1: Obtain a conductor object for which capacitance information is to be extracted. For a first conductor in the conductor object, determine a second conductor that belongs to a different conductor network from the first conductor and has a short-circuit relationship with the first conductor.

[0063] In this embodiment, the conductor object may be a conductor for which capacitance information is expected to be extracted. During the design process, for different reasons, the conductor object may include multiple different conductors. For example, when the size of the conductor object is large, for the convenience of accurately extracting capacitance information, the conductor object will be divided into multiple conductors belonging to different conductor networks during the design process. Subsequently, by separately extracting the capacitance information of these multiple conductors, the overall capacitance information of the conductor object can be obtained by summarization. Another example is that the conductor object itself already includes multiple conductors with a short-circuit relationship, and these conductors with a short-circuit relationship may also be in different conductor networks. When extracting capacitance information, it is necessary to consider the short-circuit relationship between different conductors to extract accurate capacitance information.

[0064] In this embodiment, taking any first conductor in the conductor object as the target conductor to be processed, a second conductor having a short-circuit relationship with the first conductor can be determined. It should be noted that the number of second conductors is not limited in this embodiment. For example, there may be only one second conductor having a short-circuit relationship with the first conductor, or there may be multiple second conductors. Short-circuit means that these two conductors are directly connected electrically and are not isolated by other components or media.

[0065] Specifically, obtain the conductor object to be processed from the chip layout design data, and select one conductor in the conductor object as the processing target, and this conductor is called the first conductor. In chip layout design, different conductors may belong to different networks (Nets). The network in chip layout design may refer to the connection relationship between various devices in the chip circuit, and these connection relationships can be described by a netlist. A netlist is a file describing the connection relationship between circuit components and contains the connection information between various devices in the circuit. Next, other conductors that are electrically short-circuited with the first conductor but belong to different networks can be identified, and this other conductor can be used as the above-mentioned second conductor.

[0066] Step S3, identify the target area where the first conductor and the second conductor are short - circuited, and based on the position information of the target area, separate the first conductor and the second conductor so that there is no short - circuit relationship between the separated first conductor and the second conductor.

[0067] Among them, the target area refers to the area where the first conductor and the second conductor are short - circuited, and the position information of this area is used to guide the subsequent separation operation.

[0068] Specifically, identify the target area where the first conductor and the second conductor are short - circuited. This target area is the place where two conductors are in direct contact as determined by the chip layout design data, which will affect the extraction of capacitance information. Once the target area is determined, a separation operation needs to be performed based on the position information of this target area. The position information can include the geometric shape, size, and specific position in the circuit of the target area. The separation operation means physically or logically separating the first conductor and the second conductor to eliminate the short - circuit relationship between them. This may involve changing the layout of the conductors, such as separating the first conductor and the second conductor through operations like moving or cutting. After separation, the first conductor and the second conductor can be regarded as independent conductors during the capacitance extraction process, so that the capacitance of each can be calculated more accurately.

[0069] Step S5, determine the capacitance filtering area between the separated first conductor and the second conductor, and when extracting the capacitance information of the separated first conductor, exclude the capacitance information located within the capacitance filtering area.

[0070] Among them, the capacitance filtering area refers to the area determined after separating the first conductor and the second conductor, which is used to exclude the capacitance information within this area during the capacitance extraction process.

[0071] Specifically, after the first conductor and the second conductor are separated, the capacitance filtering area needs to be determined. This area generally refers to the newly introduced conductor parts during the separation operation. For example, originally the first conductor and the second conductor had a short - circuit relationship on a certain surface. After eliminating this short - circuit relationship through the separation operation, new surfaces will be generated at the original short - circuit position for the first conductor and the second conductor. Without restrictions, capacitance information will also be extracted for these new surfaces during the subsequent process, and this part of the capacitance information belongs to the extra - introduced capacitance information. If this part of the capacitance information is included in the overall capacitance information of the conductor object, errors will occur. Therefore, after separating the first conductor and the second conductor, the capacitance information corresponding to the newly introduced conductor surfaces should be ignored. Specifically, when extracting the capacitance information of the separated first conductor, the capacitance information located within the capacitance filtering area needs to be excluded. That is to say, when calculating the capacitance of the first conductor, the newly added conductor surfaces that are cut or moved during the separation process are not considered, thereby improving the accuracy of capacitance information extraction.

[0072] A method for extracting capacitance information provided by this embodiment identifies a first conductor and a second conductor with a short - circuit relationship in a conductor object, thereby determining an area that may cause capacitance calculation errors. Subsequently, by separating the first conductor and the second conductor, the short - circuit relationship between them can be eliminated, ensuring that the capacitance information extraction process can be performed normally. During the process of extracting capacitance information, by determining a capacitance filtering area and excluding the capacitance information within this area, the capacitance information introduced additionally due to eliminating the short - circuit relationship is avoided, thereby improving the accuracy of capacitance extraction. The entire process can not only ensure that conductors with a short - circuit relationship can extract capacitance information normally, but also reduce the error of capacitance extraction, ensuring the accuracy of capacitance information, providing more accurate data for chip design, and optimizing the chip design process.

[0073] In some embodiments, identifying the target area of the short - circuit between the first conductor and the second conductor includes:

[0074] Obtaining the first spatial coordinates corresponding to each surface of the first conductor, and obtaining the second spatial coordinates corresponding to each surface of the second conductor.

[0075] Among them, the first spatial coordinates refer to the positions of each surface of the first conductor in three - dimensional space, usually represented by three coordinate values X, Y, and Z. The second spatial coordinates refer to the positions of each surface of the second conductor in three - dimensional space, usually also represented by three coordinate values X, Y, and Z. For example, the positions of each surface of the conductor in three - dimensional space can be represented by the spatial coordinates of four vertices on the surface. In this way, each surface can correspond to its respective vertex spatial coordinates, and based on the vertex spatial coordinates, the areas where each surface of the conductor is located in three - dimensional space can be restored.

[0076] According to the first spatial coordinates and the second spatial coordinates, determine the overlapping area between the first conductor and the second conductor, and determine the target area of the short - circuit between the first conductor and the second conductor based on the overlapping area.

[0077] In some embodiments, a surface on a conductor in a chip layout can be determined through the spatial coordinates of four vertices. After obtaining the first spatial coordinate and the second spatial coordinate, the surfaces of the first conductor and the surfaces of the second conductor can be restored in a three-dimensional space based on the first spatial coordinate and the second spatial coordinate. Based on the positions of the surfaces in the three-dimensional space, the actual positions of the first conductor or the second conductor defined by the surfaces in the three-dimensional space can be further determined. By identifying the overlapping relationship between the actual positions of the first conductor and the second conductor in the three-dimensional space, the target area of the short circuit between the first conductor and the second conductor can be determined. Specifically, the first conductor and the second conductor with a short circuit relationship can have at least two states during the chip layout design process: the first is the contact state, and the second is the overlapping state. Among them, the contact state can mean that there is only surface contact between the first conductor and the second conductor, but neither the first conductor nor the second conductor is embedded in the conductor structure of the other party. For example Figures 2 to 5 the first conductor and the second conductor shown are both in the contact state. The overlapping state means that at least part of the conductor structures of the first conductor and the second conductor are mutually embedded in the spatial graph. For example, in Figure 8 , a part of the conductor structure of the second conductor is embedded inside the first conductor. In this way, the short circuit relationship between the first conductor and the second conductor is not only the contact relationship between the surfaces, but there will also be a contact relationship between the surface and the internal material of the conductor. For these two different states, different methods can be used to determine the target area of the short circuit between the first conductor and the second conductor.

[0078] Specifically, for the contact state, when there is an overlapping area between any two surfaces of the first conductor and the second conductor, this overlapping area can be used as the target area of the short circuit between the first conductor and the second conductor. For the first conductor and the second conductor in the overlapping state, the part of the conductor embedded in the first conductor can be determined on the second conductor, and then the surfaces of the part of the conductor can be identified, and the identified surfaces of the part of the conductor can be used as the target area of the short circuit between the first conductor and the second conductor. For example, in Figure 8 , the shaded part can be the part of the conductor determined on the second conductor as described above. This part of the conductor has six surfaces, so these six surfaces can be used as the target area of the short circuit between the first conductor and the second conductor. Subsequently, when calculating the surface capacitance of the first conductor and the second conductor respectively, the surface capacitance of the area where these six surfaces are located can be ignored.

[0079] In this embodiment, by obtaining the spatial coordinates of each surface of the first conductor and the second conductor, the geometric position and shape of the conductor are accurately determined, providing accurate geometric data support for subsequent capacitance calculation. Then, the overlapping region between the first conductor and the second conductor can be determined through the first spatial coordinate and the second spatial coordinate, and the target region of short circuit between the two conductors can be determined through this overlapping region. By identifying the target region of short circuit, the accuracy of subsequent capacitance extraction can be ensured, the calculation error caused by the short circuit region can be reduced, and the accuracy of capacitance calculation in chip design can be improved.

[0080] In some embodiments, separating the first conductor and the second conductor based on the position information of the target region includes:

[0081] If the position information of the target region indicates that the target region is on the same plane, a region with a specified thickness in the first conductor and / or the second conductor is cut along the normal direction of the target region.

[0082] Specifically, if the position information of the target region indicates that the target region is on the same plane, the separation operation can be performed along the normal direction of this target region. That is to say, if the target region is a region on a plane, then the cutting operation will be performed in a direction perpendicular to this plane. The purpose of the cutting operation is to remove a region with a specified thickness in the first conductor and / or the second conductor. This thickness is determined according to design requirements and manufacturing processes to ensure that there is enough space between the two conductors to eliminate the short circuit phenomenon. Specifically, please refer to Figure 2 , what is labeled as Net A can be the first conductor, and what is labeled as Net B can be the second conductor. From the perspective of the two-dimensional graph, the right surface of the first conductor is short-circuited with the left surface of the second conductor. Then, when performing region cutting, a part of the first conductor and a part of the second conductor can be cut along the direction perpendicular to this short-circuited surface (as shown by the left dashed box in Figure 2 ), and the total thickness of the first conductor and the second conductor cut can be the above-mentioned specified thickness. Of course, in practical applications, it is also possible to only cut a region with a specified thickness on the first conductor or only cut a region with a specified thickness on the second conductor to achieve the purpose of eliminating the short-circuited surface. The above-mentioned specified thickness can be flexibly determined according to the actual situation. For example, in order to reduce the impact on other surfaces of the first conductor and the second conductor, the specified thickness can be set relatively small.

[0083] In this embodiment, if the target region lies on the same plane, a region with a specified thickness is cut along the normal direction, which can precisely separate the conductors, thus ensuring that the extraction process of capacitance information can be normally performed. In addition, by precisely controlling the depth and position of the cut, it is possible to minimize the errors introduced due to conductor cutting while ensuring sufficient spacing between the conductors, thereby improving the accuracy of subsequent capacitance calculation.

[0084] In some embodiments, the region cut on the first conductor and / or the second conductor matches the projection of the target region in the normal direction.

[0085] Herein, the cut region refers to the part removed from the first conductor and / or the second conductor, and this operation aims to eliminate the short circuit between the conductors. The projection refers to the projection of the target region in the direction perpendicular to its plane.

[0086] Specifically, it is necessary to determine the projection of the target region in the normal direction. That is to say, it is necessary to find out the two-dimensional shape and position of the target region on the vertical plane. Then, the cutting operation must ensure that the region cut from the first conductor and / or the second conductor exactly matches this projection. This means that the projection of the cut region in the normal direction of the target region is consistent with the projection of the target region.

[0087] Exemplarily, please refer to Figure 3 , Figure 3 which is a schematic diagram of a cutting operation provided for an embodiment of the present application. As can be seen from (a) in Figure 3 , the position information of the target region 3 identified between the first conductor 1 and the second conductor 2 indicates that the target region 3 lies on the same plane. Since for Figure 3 the target region 3 of the type in (a) in Figure 3 , if a region with a specified thickness is directly cut from the first conductor 1 and / or the second conductor 2 along the normal direction of the target region 3, it may cut unnecessary materials, resulting in a decline in the electrical performance of the conductor or damage to the structural integrity. Therefore, cutting along the projection of the target region 3 in the normal direction can ensure that only the originally short-circuited part of the conductor is removed, without removing the non-short-circuited region, that is, this projection is a direct mapping of the actual short-circuited region. Through this operation,

[0088] In this embodiment, by precisely matching the cut region, it is ensured that only the necessary part of the conductor is removed, thereby avoiding capacitance errors caused by unreasonable conductor cutting. Secondly, the cut region is consistent with the projection of the target region, which can effectively improve the electrical isolation between the conductors and prevent short circuits or signal interference.

[0089] In some embodiments, the conductors with a short - circuit relationship can also be separated by moving the conductors. It should be noted that during the process of moving the conductors, the relative positions between the conductors in the chip layout design may be changed, resulting in differences in the layout of the conductors after movement compared to before movement. If such differences are too large, it is very likely to affect the calculation accuracy of other surface capacitances of the conductors. In view of this, when using the method of moving the conductors to separate the conductors with a short - circuit relationship, it can be applied to chip layout designs with relatively simple structures, or to chip layout designs where the conductors can be separated by moving only a small distance.

[0090] In practical applications, before it is expected to use the method of moving the conductors to separate the conductors with a short - circuit relationship, the distance that the conductors move in the chip layout design can be identified. Generally speaking, if the moving distance is small, the impact on the layout of the original chip layout design is relatively small, and at this time, using the method of moving the conductors is acceptable. Specifically, a distance threshold can be preset. When the moving distance is less than or equal to this distance threshold, it is considered that the moving distance is relatively small, and at this time, the method of moving the conductors can be used to eliminate the short - circuit relationship; if the moving distance is greater than this distance threshold, it is considered that the moving distance is too large, and at this time, it is not suitable to use the method of moving the conductors to eliminate the short - circuit relationship.

[0091] In addition, before it is expected to use the method of moving the conductors to separate the conductors with a short - circuit relationship, it can also be determined whether the conductors after movement have a significant impact on the capacitance calculation of the surfaces of other conductors. If there is a significant impact, then it is not suitable to use the method of moving the conductors to eliminate the short - circuit relationship. Specifically, the impact caused by moving the conductors can be determined by the number of other conductors that are forced to move in the chip layout design, and can also be determined by the total moving distance of other conductors that are forced to move in the chip layout design. Among them, the other conductors that are forced to move refer to the conductors in the chip layout design other than the first conductor and the second conductor with a short - circuit relationship. When separating the first conductor and the second conductor by moving, due to the limitation of the layout of the original chip layout design, some other conductors also have to move adaptively. In this case, the number of these other conductors that are forced to move, as well as the total moving distance of these other conductors that are forced to move, can be counted. If the counted number exceeds the preset number threshold, or the counted total distance exceeds the preset total distance threshold, it is considered that it is not suitable to use the method of moving the conductors to eliminate the short - circuit relationship at this time.

[0092] In a scenario where it is suitable to use the method of moving the conductors to eliminate the short - circuit relationship, the first conductor and the second conductor can be separated by the method of the following embodiments.

[0093] Specifically, separating the first conductor and the second conductor based on the position information of the target area includes:

[0094] If the position information of the target area indicates that the target area is located on the same plane, move the first conductor and / or the second conductor along the normal direction of the target area to separate the first conductor and the second conductor.

[0095] Specifically, if the position information of the target area indicates that a short circuit occurs on the same plane, it means that there are contacting parts of the first conductor and the second conductor on this plane. To solve the short - circuit problem, the first conductor and / or the second conductor can be moved along the normal direction perpendicular to the plane where the target area is located. The purpose of the moving operation is to separate the originally short - circuited conductors until there is no electrical connection between them, ensuring that the short circuit is completely eliminated.

[0096] In this embodiment, the first conductor and the second conductor are separated by moving, which can not only eliminate the short - circuit relationship between the conductors, but also avoid cutting the conductors themselves, thereby improving the extraction accuracy of capacitance information.

[0097] In some embodiments, separating the first conductor and the second conductor based on the position information of the target area includes:

[0098] If the position information of the target area indicates that the target area is located on multiple different planes, split the target area into sub - areas corresponding to each plane respectively;

[0099] Traverse each sub - area, and for the current sub - area, cut off a region with a specified thickness in the first conductor and / or the second conductor along the normal direction of the current sub - area.

[0100] Specifically, since the target area may span multiple planes, which means that the short - circuit problem is not limited to a single plane but is distributed on different spatial levels. To simplify the processing, the target area is split into multiple sub - areas, and each sub - area is located on the same plane. This can transform the complex multi - plane problem into multiple single - plane problems for easy handling. Then, these sub - areas are processed one by one to ensure that the short - circuit problem on each plane is solved. For each sub - area, a region with a specified thickness in the first conductor and / or the second conductor is cut off along the normal direction of the plane where the sub - area is located. This is to physically separate the two conductors and eliminate the short circuit.

[0101] Exemplarily, please refer to Figure 4 , Figure 4 which is a schematic diagram of another cutting operation provided by the embodiment of the present application. As can be seen from (a) in Figure 4 , the position information of the target area 3 identified between the first conductor 1 and the second conductor 2 indicates that the target area 3 is located on multiple different planes. Since forFigure 4 When the target regions 3 of type (a) are located on different multiple planes, directly adjusting along a unified direction may not be able to precisely handle the conductor separation requirements between different planes. Since the positions and directions of the conductors on different planes are different, direct processing may result in incomplete conductor separation or errors. Therefore, it is necessary to split the target region 3 into multiple sub-regions, and different sub-regions can be processed on their respective planes, avoiding interference between different planes and ensuring the accuracy of the adjustment. From Figure 4 As can be seen from (b) in, the excised region 4 is obtained by splitting the target region 3 into multiple sub-regions corresponding to the horizontal plane and the vertical plane, and cutting off a specified thickness of the region along the normal direction of each sub-region, thereby precisely controlling the thickness of the separation of each conductor, avoiding unnecessary conductor loss, and at the same time ensuring the physical isolation between the conductors to avoid short circuit.

[0102] In this embodiment, by splitting the target region into multiple sub-regions, each sub-region can be independently processed on the same plane, which can avoid the interference of conductors between different planes and ensure the accuracy of conductor separation. Precisely cutting off the specified thickness of the conductor along the normal direction within each sub-region can not only effectively control the cutting depth and shape of the conductor, but also ensure that there will be no over-cutting or under-cutting during the cutting process, thereby improving the accuracy and quality of conductor separation. In addition, precise cutting operations can increase the physical isolation between conductors, reduce the risk of short circuit, and thus ensure the stability and safety of the circuit. This way of splitting sub-regions enables each sub-region to be independently optimized according to specific requirements, enhancing the accuracy of capacitance calculation.

[0103] In some embodiments, separating the first conductor and the second conductor based on the position information of the target region includes:

[0104] If the position information of the target region indicates that the target region is located on different multiple planes, determine a reference plane among the different multiple planes, and move the first conductor and / or the second conductor along the normal direction of the reference plane to separate the first conductor and the second conductor.

[0105] Among them, the reference plane is a reference plane for determining the relative positions between conductors. When dealing with the short-circuit problem, selecting a suitable reference plane can help determine how to move the conductors to eliminate the short circuit. Of course, not all planes are suitable as the reference plane. A suitable reference plane should meet the following conditions: on the one hand, the normal direction of the reference plane should allow the movement of the first conductor and the second conductor to eliminate their short-circuit relationship. On the other hand, the selection of the reference plane should minimize the interference to other parts of the circuit. For example, for Figure 3In the target region 3, only the bottom surface can be used as the reference plane because only by moving the conductor along the normal direction of the bottom surface can the short - circuit relationship between the two conductors be effectively eliminated. The vertical surfaces on the left and right sides cannot eliminate the short - circuit through the movement in the normal direction because the directions of these surfaces are not conducive to the movement and separation of the conductors.

[0106] Therefore, the reference plane is specifically defined as: moving the first conductor and / or the second conductor along the normal direction of the reference plane can enable the first conductor and the second conductor to eliminate the short - circuit relationship.

[0107] Specifically, when the target region spans multiple planes, a reference plane is determined. By moving the conductor along the normal direction of the reference plane, it can be ensured that the short - circuit between the conductors is eliminated.

[0108] Exemplarily, please refer to Figure 5 , Figure 5 which is a schematic diagram of the reference plane provided by the embodiment of the present application. As can be seen from Figure 5 the (a) in, the position information of the target region 3 identified between the first conductor 1 and the second conductor 2 indicates that the target region 3 is located on different multiple planes. Since for Figure 5 the target region 3 of the (a) type in is located on different multiple planes, for this situation, if an inappropriate reference plane (such as a vertical plane) is selected, the moving direction of the conductor may not be able to effectively avoid the short - circuit, so the problem cannot be solved.

[0109] To effectively avoid the short - circuit, a suitable reference plane needs to be selected. As can be seen from Figure 5 the (b) in, the bottom surface is more suitable as the reference plane 5. Only by moving the conductor along the normal direction of the bottom surface can the short - circuit of each surface between the two conductors be effectively avoided. On the contrary, selecting the side surface or the vertical surface as the reference plane 5 and moving the conductor along its normal direction cannot provide an effective moving space because these directions are not conducive to the effective separation of the conductors. Therefore, selecting the bottom surface as the reference plane 5 is the most suitable solution.

[0110] In this embodiment, by selecting a suitable reference plane from the multiple planes of the target region and adjusting the position of the conductor along the normal direction of the reference plane, the short - circuit relationship between the conductors can be effectively avoided, thereby ensuring the normal operation of the circuit and avoiding faults or performance degradation caused by the short - circuit. This method enables the relative position of the conductors to be accurately controlled, optimizes the circuit layout without affecting other circuit components, reduces electrical interference, and improves the accuracy of capacitance calculation. At the same time, flexibly selecting the reference plane and ensuring the movement along the normal direction of the reference plane can smoothly separate the conductors. This way reduces the number of conductor adjustments and reduces the risk of inaccuracy in the subsequent capacitance calculation process.

[0111] In some embodiments, determining the capacitance filtering region between the separated first conductor and second conductor includes:

[0112] If the target region lies in the same plane, along the normal direction of the target region, determine the first projection region of the target region on the first conductor and the second projection region of the target region on the second conductor;

[0113] Determine the first projection region and the second projection region as the capacitance filtering region between the separated first conductor and second conductor.

[0114] Wherein, when the target region lies in a single plane, the first projection region here refers to the projection of the target region on the first conductor, and the second projection region refers to the projection of the target region on the second conductor.

[0115] Specifically, if the target region lies in a single plane, this means that the short - circuit problem and the subsequent separation operation both occur in the same plane. Along the normal direction of the target region, determine the projection regions of the target region on the first conductor and the second conductor. Determining the first projection region and the second projection region as the capacitance filtering region means that in subsequent capacitance calculations, these regions will be excluded. Avoiding short - circuit errors and error capacitance contributions, thereby improving accuracy and reliability.

[0116] In this embodiment, by projecting along the normal direction of the target region to determine the projection regions on the first conductor and the second conductor, the capacitance contribution region between the two conductors can be accurately located, thereby improving the accuracy of capacitance calculation. In addition, by setting the capacitance filtering region, that is, restricting the capacitance calculation between the first projection region and the second projection region, the calculation result is ensured to be more reliable. This method can clearly delimit the capacitance influence region and reduce the interference of the separation operation on the capacitance calculation result.

[0117] In some embodiments, the method further includes:

[0118] If the target region lies in multiple different planes, split the target region into sub - regions corresponding to each plane respectively;

[0119] Traverse each sub - region, and for the current sub - region, along the normal direction of the sub - region, determine the third projection region of the sub - region on the first conductor and the fourth projection region of the sub - region on the second conductor, and determine the third projection region and the fourth projection region as the capacitance filtering region between the separated first conductor and second conductor.

[0120] Wherein, when the target region lies in multiple planes, the third projection region here refers to the projection of the target region on the first conductor, and the fourth projection region refers to the projection of the target region on the second conductor.

[0121] Specifically, when the target area spans multiple planes, direct processing may become complex. Therefore, splitting the target area into multiple sub-areas, each located on a single plane, can simplify the problem. For each sub-area, determine the projection areas of the sub-area on the first conductor and the second conductor along its normal direction. Define the third projection area and the fourth projection area as capacitance filtering areas, which means that these areas will be excluded in subsequent capacitance calculations. This avoids short-circuit errors and the contribution of error capacitance, thereby improving accuracy and reliability.

[0122] In this embodiment, by splitting the target area into multiple sub-areas and performing projection and capacitance calculations on each sub-area separately, the accuracy and adaptability of capacitance calculation can be significantly improved. This solution can handle the capacitance contribution of the target area on different planes more precisely and avoid calculation errors caused by complex geometric shapes. At the same time, the capacitance calculation of each sub-area is performed on its independent plane, thus ensuring the accuracy of the calculation results.

[0123] In one implementation, for Figure 8 the overlapping state shown, when separating the first conductor and the second conductor, the above-mentioned excision separation and movement separation methods can also be used. Refer to FIG. 9(a). When using the excision separation method, excision separation can be performed on multiple surfaces of the part of the conductor where the second conductor is embedded in the first conductor, so as to eliminate the short-circuit state between the first conductor and the second conductor. For example, the upper and lower surfaces, front and back surfaces, and left surface of the part of the conductor can be excised by a specified thickness, while the right surface can be left untreated because the right surface is currently actually inside the second conductor, and the short-circuit relationship between the first conductor and the second conductor has been eliminated without excising the right surface. Subsequently, when calculating the surface capacitance of the first conductor and the second conductor, the projection areas of the above-mentioned five surfaces, namely the upper and lower surfaces, front and back surfaces, and left surface, on the first conductor and the second conductor can be determined, and the capacitance of these projection areas can be ignored.

[0124] Refer to FIG. 9(b). When using the movement separation method, the left surface of the above-mentioned part of the conductor can be used as a reference plane, and then the first conductor and / or the second conductor can be moved along the normal direction of the reference plane to separate the first conductor and the second conductor. When calculating the surface capacitance of the first conductor after separation, the area where the right surface of the original part of the conductor was located can be ignored; when calculating the surface capacitance of the second conductor after separation, the areas where the upper and lower surfaces, front and back surfaces, and left surface of the original part of the conductor were located can be ignored.

[0125] Correspondingly, please refer to Figure 6 the block diagram of a capacitance information extraction device provided by an embodiment of the present application. The terminal includes:

[0126] A conductor object acquisition unit 101 is configured to acquire a conductor object for which capacitance information is to be extracted, and for a first conductor in the conductor object, determine a second conductor that belongs to a different conductor network from the first conductor and has a short - circuit relationship with the first conductor;

[0127] A conductor separation unit 103 is configured to identify a target region where the first conductor and the second conductor are short - circuited, and based on the position information of the target region, separate the first conductor and the second conductor so that there is no short - circuit relationship between the separated first conductor and the second conductor;

[0128] A capacitance filtering unit 105 is configured to determine a capacitance filtering region between the separated first conductor and the second conductor, and when extracting the capacitance information of the separated first conductor, exclude the capacitance information located within the capacitance filtering region.

[0129] In some alternative embodiments, the conductor separation unit 103 is specifically configured to acquire first spatial coordinates corresponding to each surface of the first conductor and second spatial coordinates corresponding to each surface of the second conductor; determine the overlapping coordinates between the first spatial coordinates and the second spatial coordinates, and use the region represented by the overlapping coordinates as the target region where the first conductor and the second conductor are short - circuited.

[0130] In some alternative embodiments, the conductor separation unit 103 is specifically configured to, if the position information of the target region indicates that the target region is on the same plane, cut off a region with a specified thickness in the first conductor and / or the second conductor along the normal direction of the target region.

[0131] In some alternative embodiments, the region cut off on the first conductor and / or the second conductor matches the projection of the target region in the normal direction.

[0132] In some alternative embodiments, the conductor separation unit 103 is specifically configured to, if the position information of the target region indicates that the target region is on the same plane, move the first conductor and / or the second conductor along the normal direction of the target region to separate the first conductor and the second conductor.

[0133] In some alternative embodiments, the conductor separation unit 103 is specifically configured to, if the position information of the target region indicates that the target region is on multiple different planes, split the target region into multiple sub - regions, where any one of the sub - regions is on the same plane; traverse each sub - region, and for the current sub - region, cut off a region with a specified thickness in the first conductor and / or the second conductor along the normal direction of the current sub - region.

[0134] In some alternative embodiments, the conductor separation unit 103 is specifically configured to, if the position information of the target area indicates that the target area is located on multiple different planes, determine a reference plane among the multiple different planes, and move the first conductor and / or the second conductor along the normal direction of the reference plane to separate the first conductor and the second conductor.

[0135] In some alternative embodiments, the capacitance filtering unit 105 is specifically configured to, if the target area is located on the same plane, determine a first projection area of the target area on the first conductor and a second projection area of the target area on the second conductor along the normal direction of the target area; and determine the first projection area and the second projection area as the capacitance filtering area between the separated first conductor and second conductor.

[0136] In some alternative embodiments, the device further includes a region splitting and processing unit, configured to, if the target area is located on multiple different planes, split the target area into multiple sub-areas, where any one of the sub-areas is located on the same plane; traverse each sub-area, and for the current sub-area, determine a third projection area of the sub-area on the first conductor and a fourth projection area of the sub-area on the second conductor along the normal direction of the sub-area, and determine the third projection area and the fourth projection area as the capacitance filtering area between the separated first conductor and second conductor.

[0137] The further function descriptions of the above-mentioned various modules and units are the same as those in the corresponding foregoing embodiments, and will not be elaborated herein.

[0138] The capacitance information extraction device in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0139] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of a computer device provided by an embodiment of the present application, as Figure 7As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting the components, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if needed, multiple processors and / or multiple buses can be used together with multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (such as an array of servers, a set of blade servers, or a multi-processor system). Figure 7 In [the figure], one processor 10 is taken as an example.

[0140] The processor 10 can be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 can further include a hardware chip. The above hardware chip can be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above programmable logic device can be a complex programmable logic device, a field-programmable gate array, a generic array logic, or any combination thereof.

[0141] Among them, the memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiments.

[0142] The memory 20 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device, etc. In addition, the memory 20 can include a high-speed random access memory and can also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 can optionally include a memory remotely set relative to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0143] The memory 20 can include a volatile memory, such as a random access memory; the memory can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state drive; the memory 20 can also include a combination of the above types of memories.

[0144] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

[0145] Embodiments of the present application also provide a computer-readable storage medium. The methods according to the embodiments of the present application can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium. Thus, the methods described herein can be stored as such software processes on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0146] The methods, apparatuses, or units illustrated in the above embodiments can be specifically implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0147] For the convenience of description, when describing the above apparatuses, they are described as various units according to functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0148] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, an apparatus, or a device. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) that contain computer-usable program code.

[0149] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus, and devices according to embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0150] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0151] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0152] It should also be noted that the term "comprising", "including", or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, commodity, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, commodity, or device including the said element.

[0153] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the apparatus embodiments, since they are basically similar to the method embodiments, they are described relatively simply, and the relevant parts can be referred to the descriptions of the method embodiments.

[0154] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

[0155] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for extracting capacitance information, characterized in that: The method comprises: Acquire a conductor object for which capacitance information is to be extracted, and for a first conductor in the conductor object, determine a second conductor that belongs to a different conductor network than the first conductor and is in a short-circuit relationship with the first conductor; Identifying a target area where the first conductor and the second conductor are short-circuited, and separating the first conductor and the second conductor based on location information of the target area so that there is no short-circuit relationship between the separated first conductor and the second conductor; A capacitance filtering region between the separated first conductor and the second conductor is determined, and when the capacitance information of the separated first conductor is extracted, the capacitance information located in the capacitance filtering region is eliminated.

2. The method according to claim 1, characterized in that Identifying a target area of ​​a short between the first conductor and the second conductor includes: Acquire first space coordinates corresponding to each surface of the first conductor, and acquire second space coordinates corresponding to each surface of the second conductor; An overlapping area between the first conductor and the second conductor is determined according to the first space coordinate and the second space coordinate, and a target area for short circuit between the first conductor and the second conductor is determined based on the overlapping area.

3. The method according to claim 1 or 2, characterized in that: Based on the position information of the target area, separating the first conductor and the second conductor includes: If the position information of the target area indicates that the target area is located on the same plane, a region of a specified thickness in the first conductor and / or the second conductor is cut off along a normal direction of the target area to separate the first conductor and the second conductor.

4. The method according to claim 3, characterized in that The area cut off from the first conductor and / or the second conductor matches the projection of the target area in the normal direction.

5. The method according to claim 1 or 2, characterized in that: Based on the position information of the target area, separating the first conductor and the second conductor includes: If the position information of the target area indicates that the target area is located on the same plane, the first conductor and / or the second conductor is moved along the normal direction of the target area to separate the first conductor and the second conductor.

6. The method according to claim 1 or 2, characterized in that: Based on the position information of the target area, separating the first conductor and the second conductor includes: If the location information of the target area indicates that the target area is located on multiple different planes, split the target area into sub-areas corresponding to each plane; Each of the sub-regions is traversed, and for a current sub-region, a region of a specified thickness in the first conductor and / or the second conductor is cut off along a normal direction of the current sub-region to separate the first conductor and the second conductor.

7. The method according to claim 1 or 2, characterized in that: Based on the position information of the target area, separating the first conductor and the second conductor includes: If the position information of the target area indicates that the target area is located on multiple different planes, a reference plane corresponding to the multiple different planes is determined, and the first conductor and / or the second conductor is moved along the normal direction of the reference plane to separate the first conductor and the second conductor.

8. The method according to claim 1, characterized in that Determining a capacitive filtering area between the separated first conductor and the second conductor includes: If the target areas are located on the same plane, determining a first projection area of ​​the target area on the first conductor and a second projection area of ​​the target area on the second conductor along a normal direction of the target area; The first projection area and the second projection area are determined as capacitive filtering areas between the separated first conductor and the second conductor.

9. The method according to claim 8, characterized in that The method further comprises: If the target area is located on multiple different planes, split the target area into sub-areas corresponding to each plane; Traverse each of the sub-areas, and for the current sub-area, determine a third projection area of ​​the sub-area on the first conductor and a fourth projection area of ​​the sub-area on the second conductor along the normal direction of the sub-area, and determine the third projection area and the fourth projection area as a capacitive filtering area between the separated first conductor and the second conductor.

10. A device for extracting capacitance information, characterized in that: The device comprises: A conductor object acquisition unit, configured to acquire a conductor object for which capacitance information is to be extracted, and for a first conductor in the conductor object, determine a second conductor that belongs to a different conductor network than the first conductor and is in a short-circuit relationship with the first conductor; a conductor separation unit, configured to identify a target area where the first conductor and the second conductor are short-circuited, and to separate the first conductor and the second conductor based on position information of the target area, so that there is no short-circuit relationship between the separated first conductor and the second conductor; The capacitance filtering unit is used to determine a capacitance filtering area between the separated first conductor and the second conductor, and to remove capacitance information located in the capacitance filtering area when extracting capacitance information of the separated first conductor.

11. A computer device, characterized in that: The computer device includes a memory and a processor, the memory is used to store a computer program, and when the computer program is executed by the processor, the method for extracting capacitance information as claimed in any one of claims 1 to 9 is implemented.

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