Voltage stabilizing circuit and memory

Abstract

The invention provides a voltage stabilizing circuit and a memory, the voltage stabilizing circuit comprises a control circuit, a first adjusting circuit and a second adjusting circuit, the control circuit is used for comparing an output voltage with a preset voltage to generate a control signal; the first adjusting circuit is used for performing discharging processing or charging processing on the adjusting node according to the control signal, and performing pull-down processing or pull-up processing on the output voltage according to the voltage at the adjusting node; the second adjusting circuit is used for coupling the output node to the feedback node and adjusting the output voltage according to the voltage at the feedback node.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a voltage stabilizing circuit and a memory. Background Art

[0002] In memory chips such as dynamic random access memory (DRAM), digital low dropout voltage regulators (DLDO) are usually used for voltage stabilization. By sharing a control module, the charge pump and power tubes can be distributed to various modules in the DRAM to reduce the area. However, in charge pump-based DLDO, when the output suddenly changes, the transient response performance of DLDO is poor. Summary of the invention

[0003] Embodiments of the present disclosure provide a voltage stabilization circuit and a memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a voltage stabilizing circuit, the voltage stabilizing circuit comprising a control circuit, a first adjustment circuit, and a second adjustment circuit, the control circuit and the first adjustment circuit are connected, the first adjustment circuit and the second adjustment circuit are connected to a feedback node, the first adjustment circuit is coupled to an output node, the second adjustment circuit is coupled to the output node, and the voltage at the output node is an output voltage, wherein:

[0005] The control circuit is used to receive the output voltage and a preset voltage, compare the output voltage with the preset voltage, and generate a control signal;

[0006] The first adjustment circuit is used to receive the control signal; and to discharge or charge the adjustment node inside the first adjustment circuit according to the control signal; and to pull down or pull up the output voltage according to the voltage at the adjustment node;

[0007] The second adjustment circuit is used to couple the output node to the feedback node and adjust the output voltage according to the voltage at the feedback node;

[0008] The first adjustment circuit and the second adjustment circuit jointly make the voltage value of the output voltage within a preset range.

[0009] In a second aspect, an embodiment of the present disclosure provides a memory, wherein the memory includes a voltage stabilizing circuit as described in any one of the first aspects.

[0010] The disclosed embodiment provides a voltage stabilizing circuit and a memory, the voltage stabilizing circuit includes a control circuit, a first adjustment circuit and a second adjustment circuit, the control circuit is connected to the first adjustment circuit, the first adjustment circuit and the second adjustment circuit are connected to a feedback node, the first adjustment circuit is coupled to an output node, the second adjustment circuit is coupled to the output node, and the voltage at the output node is an output voltage, wherein: the control circuit is used to receive the output voltage and a preset voltage, compare the output voltage with the preset voltage, and generate a control signal; the first adjustment circuit is used to receive the control signal; and according to the control signal, the adjustment node inside the first adjustment circuit is discharged or charged; and according to the voltage at the adjustment node, the output voltage is pulled down or pulled up; the second adjustment circuit is used to couple the output node to the feedback node, and adjust the output voltage according to the voltage at the feedback node. In this way, according to the control signal, the output voltage is pulled down or pulled up by the first adjustment circuit; and according to the voltage at the feedback node, the output voltage is adjusted by the second adjustment circuit, so that when the output of the voltage stabilizing circuit suddenly changes, the voltage value of the output voltage is within a preset range through the first adjustment circuit and the second adjustment circuit, thereby improving the transient response performance of the voltage stabilizing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the composition structure of a voltage stabilizing circuit;

[0012] Figure 2 A schematic diagram of the structure of a voltage stabilizing circuit provided in an embodiment of the present disclosure Figure 1 ;

[0013] Figure 3 A schematic diagram of the structure of a second adjustment circuit provided in an embodiment of the present disclosure;

[0014] Figure 4 A schematic diagram of the structure of a voltage stabilizing circuit provided in an embodiment of the present disclosure Figure 2 ;

[0015] Figure 5 A schematic diagram of the structure of a voltage stabilizing circuit provided in an embodiment of the present disclosure Figure 3 ;

[0016] Figure 6 A schematic diagram of the structure of a voltage stabilizing circuit provided in an embodiment of the present disclosure Figure 4 ;

[0017] Figure 7 A schematic diagram of a voltage and current variation curve provided in an embodiment of the present disclosure;

[0018] Figure 8 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant applications, rather than to limit the present disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant applications are shown in the drawings.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0021] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0022] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0023] DLDO uses a dynamic voltage comparator and a shift register to replace the error amplifier in the analog low dropout voltage regulator (ALDO), and uses a metal oxide semiconductor field effect transistor (MOS) array to replace the large-sized power tube in ALDO. In DLDO, the shift register controls the number of MOS tubes (also called power tubes) turned on in the MOS array according to the output of the dynamic voltage comparator, and controls the output voltage to be near the reference voltage through the control unit. Although this reduces the requirements for the power supply voltage and is insensitive to changes in process, voltage and temperature, it also has some disadvantages, such as poor transient response performance of DLDO, that is, when the load of DLDO changes suddenly, its output voltage will jump, and the speed of the output voltage jump changes with the load current. ALDO can quickly adjust the output voltage to the rated level through the error amplifier and power tube, but DLDO uses a shift register as the control core and can only adjust the number of power tubes through the sampling results of the sampling clock. Its recovery speed is limited by the frequency of the sampling clock and the number of unit clock changes of the power tube, resulting in a slow transient response speed.

[0024] In DRAM, in order to solve the problem that the same power supply needs to power multiple modules distributed in different positions in the DRAM, but the distance between the modules is relatively far, and ALDO is sensitive to signal interference, the traditional circuit solves this problem by placing a complete ALDO at multiple positions and adding shielding to the routing, but this will increase the occupied area. Since the digital signal output by the comparator is not sensitive to signal interference, DLDO is used, which reduces the area by sharing a control module and distributing the control unit and power tube composed of the charge pump to each module. Since the area of ​​the comparator in DLDO is smaller than that of the error amplifier in ALDO, the area can be further reduced.

[0025] See also Figure 1 , which shows a schematic diagram of the composition structure of a voltage stabilizing circuit. Figure 1 As shown, the voltage stabilizing circuit 10 includes a control circuit 11, a first regulating circuit 12, a second regulating circuit 13, a fine-tuning circuit 14 and a tail current source circuit 15. The first regulating circuit 12 and the second regulating circuit 13 are connected to a feedback node P GATE The second adjustment circuit 13 is coupled to the output node, and the voltage at the output node is the output voltage V OUTThe control circuit 11 includes a first comparator 111, a first NOT gate 112, a second comparator 113 and a second NOT gate 114, the first adjustment circuit 12 includes a transistor 121 and a transistor 122, the second adjustment circuit 13 includes a feedback capacitor 131 and a power tube 132, and the fine tuning circuit 14 includes a third comparator 141 and a fine tuning module (Fine Tuning Module) 142. The specific connection relationship is detailed in Figure 1 .

[0026] like Figure 1 As shown, the positive input terminal of the first comparator 111 is used to receive the output voltage V OUT The inverting input terminal of the first comparator 111 is used to receive the first preset voltage V REFL The non-inverting input terminal of the second comparator 113 is used to receive the output voltage V OUT The inverting input terminal of the second comparator 113 is used to receive the second preset voltage V REFH The non-inverting input terminal of the third comparator 141 is used to receive the output voltage V OUT The inverting input terminal of the third comparator 141 is used to receive the reference voltage V REF , the clock terminal of the third comparator 141 is used to receive the clock signal CLK. REFL is less than the second preset voltage V REFH , and the first preset voltage V REFL and the second preset voltage V REFH The interval formed is the output voltage V of the voltage stabilizing circuit 10 OUT The preset range of the voltage value obtained after adjustment; the reference voltage V REF The voltage value is within the preset range, and the reference voltage V REF The output voltage V of the voltage regulator circuit 10 is OUT The target voltage obtained after adjustment.

[0027] Here, the transistor 121 is an N-type metal oxide semiconductor field effect transistor (NMOS transistor), and the transistor 122 and the power transistor 132 are P-type metal oxide semiconductor field effect transistors (PMOS transistors).

[0028] The first adjustment circuit 12 can also be called a charge pump, that is, a switch composed of a PMOS tube and an NMOS tube controlled by logic "0" (low level state) and logic "1" (high level state), and its output node is the feedback node P GATE Wherein, transistor 121 is fed back to node P GATE The transistor 122 discharges the feedback node P GATE During charging, both transistor 121 and transistor 122 are not turned on at the same time.

[0029] When the first regulating circuit 12 and the second regulating circuit 13 jointly make the output voltage V OUT After stabilizing within the preset range, the fine-tuning module 142 in the fine-tuning circuit 14 is used to accurately adjust the output voltage V OUT , making it equal to or close to the reference voltage V REF .

[0030] It should be noted that the first comparator 111 and the second comparator 113 are static comparators and are always in an on state, so that the output voltage V OUT The response to transient changes is faster, and the adjustment time is about tens of nanoseconds (ns). The third comparator 141 is a dynamic comparator controlled by the clock signal CLK, and the frequency of the clock signal CLK is relatively low, for example, about 1 Mega Hertz (MHz).

[0031] The transient response performance of traditional DLDO is poor, and the transient response performance can be enhanced by introducing analog auxiliary circuits. In the voltage stabilization circuit 10, the charge pump-based DLDO changes the control unit from the traditional shift register to a charge pump, and the dynamic high-resistance node (i.e., the feedback node P GATE ) can enhance loop stability and transient response performance through the coupling of feedback capacitor 131. However, in a charge pump-based DLDO, when the output suddenly changes, due to the delay of each comparator (first comparator 111, second comparator 113 and third comparator 141), and when transistor 121 and transistor 122 are not turned on, the feedback node P GATE The gate of the power tube 132 is a high-impedance node, and the feedback capacitor 131 is a unit gain feedback. OUT The coupling is used to reduce the gate voltage of the power tube 132, resulting in the output voltage V OUT The current of the power tube 132 refers to the drain-source current of the power tube 132 (the current flowing from the drain Drain to the source Source, I ds), the load current refers to the current obtained by the external load from the voltage stabilizing circuit 10, that is, the current required by the load. The voltage stabilizing circuit 10 adjusts the power tube current to meet the load current requirement.

[0032] Based on this, an embodiment of the present disclosure provides a voltage stabilizing circuit, which includes a control circuit, a first adjustment circuit and a second adjustment circuit, wherein the control circuit is connected to the first adjustment circuit, the first adjustment circuit and the second adjustment circuit are connected to a feedback node, the first adjustment circuit is coupled to an output node, the second adjustment circuit is coupled to an output node, and the voltage at the output node is an output voltage, wherein: the control circuit is used to receive the output voltage and a preset voltage, compare the output voltage with the preset voltage, and generate a control signal; the first adjustment circuit is used to receive the control signal; and according to the control signal, discharge or charge the adjustment node inside the first adjustment circuit; and according to the voltage at the adjustment node, pull down or pull up the output voltage; the second adjustment circuit is used to couple the output node to the feedback node, and adjust the output voltage according to the voltage at the feedback node. In this way, according to the control signal, the output voltage is pulled down or pulled up by the first adjustment circuit; and according to the voltage at the feedback node, the output voltage is adjusted by the second adjustment circuit, so that when the output of the voltage stabilizing circuit suddenly changes, the voltage value of the output voltage is made within a preset range by the first adjustment circuit and the second adjustment circuit, thereby improving the transient response performance of the voltage stabilizing circuit.

[0033] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0034] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a voltage stabilizing circuit provided by an embodiment of the present disclosure Figure 1 .like Figure 2 As shown, the voltage stabilizing circuit 20 may include a control circuit 21, a first adjustment circuit 22, and a second adjustment circuit 23, the control circuit 21 is connected to the first adjustment circuit 22, the first adjustment circuit 22 and the second adjustment circuit 23 are connected to a feedback node, the first adjustment circuit 22 is coupled to an output node, the second adjustment circuit 23 is coupled to the output node, and the voltage at the output node is the output voltage, wherein:

[0035] The control circuit 21 is used to receive the output voltage and the preset voltage, compare the output voltage with the preset voltage, and generate a control signal;

[0036] The first adjustment circuit 22 is used to receive a control signal; discharge or charge an adjustment node inside the first adjustment circuit 22 according to the control signal; and pull down or pull up an output voltage according to a voltage at the adjustment node;

[0037] A second adjustment circuit 23, used for coupling the output node to the feedback node and adjusting the output voltage according to the voltage at the feedback node;

[0038] The first adjustment circuit 22 and the second adjustment circuit 23 work together to make the voltage value of the output voltage within a preset range.

[0039] This embodiment specifically relates to a circuit related to a power supply in an integrated circuit design, and more particularly to a circuit related to a transient enhancement technology applied to DLDO, but is not specifically limited thereto.

[0040] It should be noted that the feedback node is P GATE Indicates that the output node is V OUT Indicates that the voltage value at the output node (i.e., the output voltage) is represented by the voltage V OUT In addition, pulling down or pulling up the output voltage is equivalent to discharging or charging the output node.

[0041] It should also be noted that the adjustment node is located inside the first adjustment circuit 22. Figure 2 Not shown in FIG.

[0042] Here, the preset range is the target range of the voltage value obtained after the voltage stabilizing circuit 20 adjusts the output voltage. When the preset voltage is not equal to the output voltage, the control circuit 21 obtains a control signal according to the comparison result between the output voltage and the preset voltage, and the first adjustment circuit 22 and the second adjustment circuit 23 jointly make the voltage value of the output voltage within the preset range according to the control signal; when the preset voltage is equal to the output voltage, the voltage stabilizing circuit 20 does not need to adjust the output voltage. It can be understood that the equality involved here includes errors within the allowable range.

[0043] In some embodiments, see Figure 3 , which shows a schematic diagram of the composition structure of a second adjustment circuit provided by an embodiment of the present disclosure. Figure 3 As shown, the second adjustment circuit 23 may include a feedback circuit 231 and a power tube circuit 232, and the feedback circuit 231 and the power tube circuit 232 are respectively coupled to the feedback node and the output node, wherein:

[0044] A feedback circuit 231, used for adjusting the voltage at the feedback node according to the output voltage;

[0045] The power tube circuit 232 is used to adjust the output voltage according to the voltage at the feedback node.

[0046] It should be noted that the feedback circuit 231 is used to couple the change of the output node to the feedback node, and the power tube circuit 232 is used to adjust the output voltage according to the voltage at the feedback node.

[0047] In some embodiments, Figure 3 As shown, the feedback circuit 231 includes a feedback capacitor a1, and the power tube circuit 232 includes a power tube a2, wherein:

[0048] The first plate of the feedback capacitor a1 and the control end of the power tube a2 are both connected to the feedback node, the second plate of the feedback capacitor a1 and the second end of the power tube a2 are both connected to the output node; the first end of the power tube a2 is connected to the power supply voltage.

[0049] It should be noted that the power tube a2 may be a PMOS tube. If the power tube a2 is a PMOS tube, the first end of the power tube a2 may be a source connected to the power supply voltage; the second end of the power tube a2 may be a drain connected to the output node; and the control end of the power tube a2 is a gate connected to the feedback node.

[0050] Here, the power supply voltage is represented by VDD and the ground voltage is represented by VSS. VDD is used to provide a high-level signal (logic "1"), and VSS is used to provide a low-level signal (logic "0").

[0051] The effect of feedback capacitor a1 on the output voltage is shown in formula (1):

[0052] I=C*(dV / dt) (1)

[0053] Where I represents current, C represents capacitance, V represents voltage, t represents time, and dV / dt represents the rate of change of the voltage difference across the capacitor. From formula (1), it can be seen that the rate of change of the voltage difference across the feedback capacitor a1 is positively correlated with I.

[0054] Based on formula (1), dV can be obtained by formula (2), where dV is the difference between the output voltage and the voltage at the feedback node:

[0055] dV=I*dt / C (2)

[0056] When the output voltage changes transiently, based on the coupling effect of the feedback capacitor a1, the feedback capacitor a1 feeds back the sudden output voltage to the feedback node. The voltage at the feedback node is the gate voltage of the power tube a2, which in turn affects the switching degree of the power tube a2. For example, when the output voltage drops by V1, if I = 0, the voltage difference dV across the feedback capacitor a1 is 0, and the voltage at the feedback node also drops by V1. In other words, the change in the output voltage is fed back to the voltage at the feedback node at a ratio close to 1. Here, I = 0 means that there is no current at the feedback node, which means that the resistance is infinite, or it is a high-resistance state.

[0057] It can be understood that when the feedback node is in a high impedance state, that is, the feedback node is floating, the feedback efficiency of the feedback capacitor a1 is relatively large, and the change of the output node is fed back to the feedback node at a ratio of approximately 1:1. If the output voltage drops, the voltage at the feedback node drops, the gate voltage of the power tube a2 drops, the power tube a2 is turned on more, and the I ds The current is larger, pulling up the output voltage, thereby preventing the output voltage from falling; similarly, if the output voltage rises, the voltage at the feedback node rises, the gate voltage of power tube a2 rises, power tube a2 is turned on less, and the I ds The current is smaller, pulling the output voltage down, thus preventing the output voltage from rising.

[0058] It should be noted that the size of the power transistor a2 is much larger than the sizes of other transistors in the voltage stabilizing circuit 20. In addition, the capacitance value of the feedback capacitor a1 is related to the parasitic capacitance at the feedback node.

[0059] In some embodiments, see Figure 4 , which shows a schematic diagram of the composition structure of a voltage stabilizing circuit provided by an embodiment of the present disclosure Figure 2 .like Figure 4 As shown, the first adjustment circuit 22 may include a first adjustment subcircuit 221 and a second adjustment subcircuit 222, the adjustment node includes a first adjustment node and a second adjustment node, the preset voltage includes a first preset voltage and a second preset voltage, the control signal includes a first control signal and a second control signal, the control circuit 21 and the first adjustment subcircuit 221 are connected to the first adjustment node, and the control circuit 21 and the second adjustment subcircuit 222 are connected to the second adjustment node, wherein:

[0060] The control circuit 21 is used to receive the output voltage, the first preset voltage and the second preset voltage, compare the output voltage with the first preset voltage and the second preset voltage respectively, and generate a first control signal and a second control signal; when the first control signal is in an enabled state, the first adjustment node is charged, or when the second control signal is in an enabled state, the second adjustment node is discharged;

[0061] The first adjustment subcircuit 221 is used for charging the output node and discharging the feedback node according to the voltage at the first adjustment node;

[0062] The second adjustment subcircuit 222 is used for discharging the output node and charging the feedback node according to the voltage at the second adjustment node;

[0063] The first preset voltage is smaller than the second preset voltage, and an interval formed by the first preset voltage and the second preset voltage is a preset range.

[0064] It should be noted that the first adjustment node is represented by A, the second adjustment node is represented by B; the first preset voltage is represented by V REFL Indicates that the second preset voltage is V REFH Indicated by V REFL ~V REFH express.

[0065] like Figure 4 As shown, the first adjustment subcircuit 221 is connected to the ground voltage VSS, and the second adjustment subcircuit 222 is connected to the power supply voltage VDD. When the first control signal is in the enabled state, the path of the first adjustment subcircuit 221 is opened, forming a path from the feedback node to the ground, and the feedback node is discharged; similarly, when the second control signal is in the enabled state, the path of the second adjustment subcircuit 222 is opened, forming a path from the feedback node to the power supply, and the feedback node is charged.

[0066] Furthermore, in some embodiments, Figure 4 As shown, the first adjustment subcircuit 221 may include a first transistor U1, a second transistor U2 and a first capacitor U3, and the second adjustment subcircuit 222 may include a third transistor U4, a fourth transistor U5 and a second capacitor U6, wherein:

[0067] A first terminal of the first transistor U1 is connected to the ground voltage VSS, a second terminal of the first transistor U1 and a first plate of the first capacitor U3 are both connected to the first adjustment node, a control terminal of the first transistor U1 is connected to the power supply voltage VDD, and a second plate of the first capacitor U3 is connected to the output node;

[0068] The first end of the second transistor U2 is connected to the first adjustment node, and the control end of the second transistor U2 is used to receive the first control signal; the first end of the third transistor U4 is connected to the second adjustment node, and the control end of the third transistor U4 is used to receive the second control signal; the second end of the second transistor U2 and the second end of the third transistor U4 are both connected to the feedback node;

[0069] The first end of the fourth transistor U5 is connected to the power supply voltage VDD, the second end of the fourth transistor U5 and the first plate of the second capacitor U6 are both connected to the second adjustment node, the control end of the fourth transistor U5 is connected to the ground voltage VSS, and the second plate of the second capacitor U6 is connected to the output node.

[0070] As mentioned above, the size of the power transistor a2 is much larger than the sizes of the first transistor U1 , the second transistor U2 , the third transistor U4 and the fourth transistor U5 .

[0071] It should be noted that the first transistor U1 and the second transistor U2 may be NMOS transistors, and the third transistor U4 and the fourth transistor U5 may be PMOS transistors. Thus, if the first transistor U1 is an NMOS transistor, the first end of the first transistor U1 may be a source connected to the ground voltage VSS; the second end of the first transistor U1 may be a drain connected to the first adjustment node; the control end of the first transistor U1 is a gate connected to the power supply voltage VDD. If the second transistor U2 is an NMOS transistor, the first end of the second transistor U2 may be a source connected to the first adjustment node; the second end of the second transistor U2 may be a drain connected to the feedback node; the control end of the second transistor U2 is a gate that receives the first control signal. If the third transistor U4 is a PMOS transistor, the first end of the third transistor U4 may be a source connected to the second adjustment node; the second end of the third transistor U4 may be a drain connected to the feedback node; the control end of the third transistor U4 is a gate that receives the second control signal. If the fourth transistor U5 is a PMOS tube, then the first end of the fourth transistor U5 can be a source connected to the power supply voltage VDD; the second end of the fourth transistor U5 can be a drain connected to the second adjustment node; the control end of the fourth transistor U5 is a gate connected to the ground voltage VSS.

[0072] It can be understood that the second transistor U2 is an NMOS tube, so it is in an enabled state when the first control signal is in a high level state (logic "1"); the third transistor U4 is a PMOS tube, so it is in an enabled state when the second control signal is in a low level state (logic "0").

[0073] It should also be noted that the power supply voltage connected to the control terminal of the first transistor U1 can be VDD or other positive voltages, as long as the first transistor U1 is always turned on, and no specific limitation is made to this. Similarly, the ground voltage connected to the control terminal of the fourth transistor U5 can be 0 volts (volt, V) or other negative voltages, as long as the fourth transistor U5 is always turned on, and no specific limitation is made to this. In addition, the power supply voltages VDD connected to each transistor (power transistor a2, first transistor U1, fourth transistor U5) can be the same or different, and the specific voltage values ​​of each power supply voltage VDD can be the same or different, and no specific limitation is made to this.

[0074] Here, the first control signal and the second control signal are not both in the enabled state at the same time, and the second transistor U2 and the third transistor U4 are not both turned on at the same time. When both the first control signal and the second control signal are in the disabled state, neither the second transistor U2 nor the third transistor U4 is turned on, that is, the feedback node is in a high impedance state. When any one of the second transistor U2 and the third transistor U4 is turned on, the current I at the feedback node is not equal to 0. Then, according to formula (2), the change in the output voltage is fed back to the change in the voltage at the feedback node, which will be weakened with time and the magnitude of the current.

[0075] When the second transistor U2 is turned on, the first adjustment node is charged, and the first adjustment node is charged until the current at the second transistor U2 is equal to the current at the first transistor U1; specifically, the current of the second transistor U2 is increased due to the gate-source voltage V GS The change of the drain-source voltage V DS The change in increases gradually until the currents of the two are equal.

[0076] Similarly, when the third transistor U4 is turned on, the second adjustment node will be discharged, and the second adjustment node will be discharged until the current at the third transistor U4 is equal to the current at the fourth transistor U5; specifically, the current of the third transistor U4 is equal to the current at the fourth transistor U5 due to the gate-source voltage V GS The change of the drain-source voltage V DS The change in increases gradually until the currents of the two are equal.

[0077] In addition, the capacitance value of feedback capacitor a1 can be calculated by C c Indicates that the capacitance value of the first capacitor U3 can be expressed as C n Indicates that the capacitance value of the second capacitor U6 can be expressed as C p In one possibility, the capacitance values ​​of the feedback capacitor a1, the first capacitor U3 and the second capacitor U6 are equal and equal to 20 pF, as shown in formula (3), but this is not specifically limited:

[0078] C c =C p =C n =20pF (3)

[0079] It should be noted that C n and C p The value of V will affect the output voltage rise. If its value is too large, the output voltage will rise from V REFL rises above V REFH In addition, C n and C p The size of the output capacitor CL (also called load capacitance) to set, if C n and C p The size of C L Small, can not achieve the effect of voltage stabilization; if C n and C p The size of C L If the voltage is too large, the voltage stabilization effect cannot be achieved, and the circuit area is larger. Therefore, for example, C n and C p The size can be C L 1 / 2 of the size, but this is not specifically limited.

[0080] It should also be noted that C L is connected to a voltage V OUT and the capacitance between the ground voltage VSS (not shown in the figure), and C L It needs to be as small as possible and varies with the load current.

[0081] In some embodiments, the width-to-length ratio of the second transistor U2 is greater than the width-to-length ratio of the first transistor U1 , and the width-to-length ratio of the third transistor U4 is greater than the width-to-length ratio of the fourth transistor U5 .

[0082] It should be noted that the aspect ratio refers to the ratio of the width to the length of the conductive channel of the transistor. From formula (4), it can be seen that when the voltage V GS The larger the width-to-length ratio, the smaller the transistor current I ds The larger the transistor is, the stronger the driving capability is. In other words, the aspect ratio of the transistor is related to the current I ds in direct proportion; in addition, the driving capabilities of the first transistor U1 and the second transistor U2 are different, and the driving capabilities of the third transistor U4 and the fourth transistor U5 are different.

[0083]

[0084] Where I represents the current I ds ; K'=u×C ox , represents the product of electron mobility and gate oxide capacitance per unit area; W represents the width of the conductive channel, L represents the length of the conductive channel, V GS Represents the gate-source voltage, V TH Represents the threshold voltage.

[0085] In addition, the width-to-length ratio of the second transistor U2 is N times (N is greater than 0) that of the first transistor U1, and the width-to-length ratio of the third transistor U4 is N times that of the fourth transistor U5. Exemplarily, N is about several hundred, but this is not specifically limited.

[0086] When the second transistor U2 is turned on, because the width-to-length ratio of the second transistor U2 is greater than the width-to-length ratio of the first transistor U1, the first adjustment node is charged under the joint action of the first transistor U1 and the second transistor U2. Similarly, when the third transistor U4 is turned on, because the width-to-length ratio of the third transistor U4 is greater than the width-to-length ratio of the fourth transistor U5, the second adjustment node is discharged under the joint action of the third transistor U4 and the fourth transistor U5.

[0087] exist Figure 4 Based on Figure 5 , which shows a schematic diagram of the composition structure of a voltage stabilizing circuit provided by an embodiment of the present disclosure Figure 3 .like Figure 5 As shown, in some embodiments, the control circuit 21 may include a first comparison circuit 211 and a second comparison circuit 212, wherein:

[0088] A first comparison circuit 211 is used to receive the output voltage and a first preset voltage, compare the output voltage with the first preset voltage, and output a first control signal in an enabled state when the first preset voltage is greater than the output voltage, or output a first control signal in a disabled state when the first preset voltage is less than or equal to the output voltage;

[0089] The second comparison circuit 212 is used to receive the output voltage and the second preset voltage, compare the output voltage with the second preset voltage, and output the second control signal in an enabled state when the second preset voltage is less than the output voltage, or output the second control signal in a disabled state when the second preset voltage is greater than or equal to the output voltage.

[0090] When the voltage V OUT <V REFL , the first control signal is in the enabled state, at which time the second transistor U2 is turned on, and under the joint action of the first transistor U1 and the second transistor U2, the first adjustment node is charged, so that the voltage V OUT When the voltage V OUT >V REFH , the second control signal is in the enabled state, and the third transistor U4 is turned on. Under the joint action of the third transistor U4 and the fourth transistor U5, the second adjustment node is discharged, so that the voltage V OUT decline.

[0091] It can be understood that when the voltage V OUT <V REFL Or the voltage V OUT >V REFH, that is, when the output voltage is not within the preset range, the second transistor U2 or the third transistor U4 will be additionally turned on to enhance the regulation capability of the voltage at the feedback node.

[0092] Furthermore, in some embodiments, Figure 5 As shown, the first comparison circuit 211 may include a first comparator b1 and a first NOT gate b2, and the second comparison circuit 212 may include a second comparator b3 and a second NOT gate b4, wherein:

[0093] The non-inverting input terminal of the first comparator b1 is used to receive the output voltage, the inverting input terminal of the first comparator b1 is used to receive the first preset voltage, the output terminal of the first comparator b1 is connected to the input terminal of the first NOT gate b2, and the output terminal of the first NOT gate b2 is used to output the first control signal;

[0094] The non-inverting input terminal of the second comparator b3 is used to receive the output voltage, the inverting input terminal of the second comparator b3 is used to receive the second preset voltage, the output terminal of the second comparator b3 is connected to the input terminal of the second NOT gate b4, and the output terminal of the second NOT gate b4 is used to output the second control signal.

[0095] It should be noted that the positive input terminal of the comparator can be represented by "+", and the negative input terminal of the comparator can be represented by "-". When the voltage of the positive input terminal is higher than the voltage of the negative input terminal, the comparator outputs a high-level signal; when the voltage of the positive input terminal is lower than the voltage of the negative input terminal, the comparator outputs a low-level signal; and when the voltages of the positive and negative input terminals of the comparator reach absolute equality, its output is the original state before the voltages of the positive and negative input terminals reach absolute equality, that is, the state formed when the voltages of the positive and negative input terminals are unequal is maintained unchanged.

[0096] It should also be noted that the first comparator b1 and the second comparator b3 are static comparators, but there is also a certain delay, which is related to the speed of the static comparator adjustment. For example, if the delay of the comparator is 1ns, then at the voltage V OUT Lower than V REFL Or the voltage V OUT Greater than V REFH After 1ns, the comparator will output a valid signal, that is, a control signal in an enabled state. In addition, during this 1ns period, the feedback node is in a high-impedance state.

[0097] Taking the sudden increase of load current as an example, before the comparator outputs a valid signal (i.e. the second transistor U2 and the third transistor U4 are not turned on), the feedback capacitor a1 of the high-resistance feedback is still used to adjust the voltage V OUTAfter the comparator outputs a valid signal (the second transistor U2 is turned on), since the width-to-length ratio of the second transistor U2 is greater than that of the first transistor U1, the first adjustment node is charged, the voltage at the first adjustment node is raised, and is coupled to the output node through the first capacitor U3 to raise the voltage V OUT The increase in the voltage at the first adjustment node simultaneously increases the current of the first transistor U1 to reduce the gate voltage of the power transistor a2.

[0098] It can be understood that when the voltage V OUT <V REFL When the first comparator b1 outputs a low-level signal, and then the first NOT gate b2 inverts the low-level signal and outputs a high-level first control signal, thereby turning on the second transistor U2. At this time, the first adjustment node is charged, thereby pulling up the voltage V OUT In addition, the feedback node will be discharged, causing the voltage at the feedback node to drop, and the power tube a2 will be turned on more, pulling up the voltage V OUT In this way, the first adjustment circuit and the second adjustment circuit jointly prevent the output voltage from decreasing, so that the voltage value of the output voltage is within a preset range.

[0099] When the voltage V OUT >V REFH When the second comparator b3 outputs a high-level signal, and then after the second NOT gate b4 inverts the high-level signal, it outputs a low-level second control signal, thereby turning on the third transistor U4. At this time, the second adjustment node is discharged, thereby pulling down the voltage V OUT In addition, the feedback node will be charged, causing the voltage at the feedback node to rise, and the power tube a2 will be turned on less, pulling down the voltage V OUT In this way, the first adjustment circuit and the second adjustment circuit jointly prevent the output voltage from rising, so that the voltage value of the output voltage is within a preset range.

[0100] exist Figure 5 Based on Figure 6 , which shows a schematic diagram of the composition structure of a voltage stabilizing circuit provided by an embodiment of the present disclosure Figure 4 .like Figure 6 As shown, in some embodiments, the voltage stabilizing circuit 20 may further include a fine-tuning circuit 24, and the fine-tuning circuit 24 includes a logic circuit 241, a third comparison circuit 242 and a third adjustment circuit 243, wherein:

[0101] a logic circuit 241, configured to receive a first control signal and a second control signal, perform logic processing according to the first control signal and the second control signal, and output an enable signal in an enabled state when the level states of the first control signal and the second control signal are different, or output an enable signal in a disabled state when the level states of the first control signal and the second control signal are the same;

[0102] The third comparison circuit 242 is used to receive the output voltage, the reference voltage and the clock signal, and compare the reference voltage with the output voltage when the clock signal is in a valid state, and output a third control signal;

[0103] The third adjustment circuit 243 is used to receive the enable signal and the third control signal, and when the enable signal is in the enabled state, adjust the voltage value of the output voltage to be equal to the voltage value of the reference voltage according to the third control signal;

[0104] The voltage value of the reference voltage is within a preset range, and the reference voltage is a target voltage obtained after adjustment by the voltage stabilizing circuit 20 .

[0105] Here, the reference voltage is V REF express.

[0106] It should be noted that the clock signal may be a system clock signal, a local clock signal, or other clock signals, which are not specifically limited. In addition, at the rising edge of the clock signal, the clock signal is in a valid state.

[0107] Here, when the level states of the first control signal and the second control signal are different, exemplarily, when the first control signal is "0" and the second control signal is "1", or, when the first control signal is "1" and the second control signal is "0", the enable signal is in an enabled state. When the level states of the first control signal and the second control signal are the same, exemplarily, if both the first control signal and the second control signal are "0", or, if both the first control signal and the second control signal are "1", the enable signal is in a disabled state.

[0108] When the voltage V OUT <V REF Or the voltage V OUT >V REF , the third comparison circuit 242 will output the third control signal, and the third adjustment circuit 243 will adjust the voltage V according to the third control signal when the enable signal is in the enabled state. OUT =V REF .

[0109] Furthermore, in some embodiments, Figure 6As shown, the logic circuit 241 may include an XOR gate c1, the third comparison circuit 242 may include a third comparator c2, and the third adjustment circuit 243 may include a fine-tuning module c3, wherein:

[0110] The first input terminal of the XOR gate c1 is used to receive the first control signal, the second input terminal of the XOR gate c1 is used to receive the second control signal, and the output terminal of the XOR gate c1 is connected to the enable terminal of the fine-tuning module c3 to output an enable signal;

[0111] The non-inverting input terminal of the third comparator c2 is used to receive the output voltage, the inverting input terminal of the third comparator c2 is used to receive the reference voltage, the clock terminal of the third comparator c2 is used to receive the clock signal, the output terminal of the third comparator c2 is connected to the input terminal of the fine-tuning module c3, and is used to output the third control signal; the output terminal of the fine-tuning module c3 is connected to the feedback node.

[0112] It should be noted that the output voltage regulation capability of the first adjustment circuit is much greater than that of the fine-tuning circuit. When the first adjustment circuit and the fine-tuning circuit work together, the output voltage regulation capability of the fine-tuning circuit can be ignored.

[0113] It should also be noted that when the voltage V OUT At V REFL ~V REFH When the third comparator c2 is in operation, the control signals output by the first comparator b1 and the second comparator b3 make the second transistor U2 and the third transistor U4 not turned on, and the first adjustment circuit does not operate.

[0114] It can be understood that when the level states of the first control signal and the second control signal are different, the XOR gate c1 outputs a high level signal, that is, when the enable signal is in a high level state (logic "1"), it is an enable state.

[0115] In addition, XOR gate c1 controls the switch of fine-tuning module c3. OUT <V REFL Or the voltage V OUT >V REFH When the level states of the first control signal and the second control signal are the same, the enable signal is in a non-enabled state, and the fine-tuning module c3 can be turned off, thereby saving power.

[0116] The third comparator c2 is a dynamic comparator, also known as a clocked comparator, which has a certain delay, which is related to the frequency of the clock signal. Before the clock signal arrives, the feedback capacitor a1 can be used to adjust the voltage V OUT .

[0117] The first adjustment circuit and the second adjustment circuit can jointly adjust the voltage V OUTIn the preset range V REFL ~V REFH But the voltage V OUT Not necessarily equal to V REF At this time, after the fine-tuning module c3 adjusts the voltage V OUT =V REF Specifically, when the voltage V OUT <V REF When the third comparator c2 outputs a low level signal; and because V REF At V REFL ~V REFH Therefore, the first comparator b1 outputs a high-level signal, the first control signal is a low-level signal, and the second comparator b3 outputs a low-level signal, the second control signal is a high-level signal. At this time, the level states of the first control signal and the second control signal are different, and the XOR gate c1 outputs a high-level enable signal. In this way, when the enable signal is in the enable state, the low-level signal output by the third comparator c2 passes through the fine-tuning module c3, so that the voltage at the feedback node is low voltage, and the power tube a2 will be turned on more, and the pull-up voltage V OUT , which makes the voltage V OUT =V REF .

[0118] In addition, when the voltage V OUT >V REF , the third comparator c2 outputs a high-level signal; the first comparator b1 outputs a high-level signal, the first control signal is a low-level signal, and the second comparator b3 outputs a low-level signal, the second control signal is a high-level signal, at this time, the level states of the first control signal and the second control signal are different, and the XOR gate c1 outputs a high-level enable signal. In this way, when the enable signal is in the enable state, the high-level signal output by the third comparator c2 passes through the fine-tuning module c3, so that the voltage at the feedback node is a high voltage, the power tube a2 will be turned on less, and the pull-down voltage V OUT , which makes the voltage V OUT =V REF .

[0119] In some embodiments, Figure 6 As shown, the voltage stabilizing circuit 20 further includes a tail current source circuit 25 .

[0120] exist Figure 6 For the first adjustment node A, when the voltage V OUT In steady state, the voltage at point A is 0, and no current flows through the second transistor U2 and the third transistor U4. When the load current suddenly changes, the voltage V OUTWhen the voltage drops by ΔV, due to the delay of the first comparator b1, the second transistor U2 is not turned on, so there is still no current flowing through point A. From formula (1), it can be seen that the voltage difference across the first capacitor U3 does not change, so the voltage at point A also drops by ΔV. This ΔV temporarily increases the voltage V when the second transistor U2 is turned on. GS When the first comparator b1 outputs a valid signal (i.e., the enabled first control signal) and turns on the second transistor U2, due to the existence of ΔV, V GS =V DD +ΔV, greater than the V of the first transistor U1 GS =V DD On the other hand, the width-to-length ratio of the second transistor U2 is much greater than that of the first transistor U1. As can be seen from formula (4), the current of the second transistor U2 is much greater than the current of the first transistor U1. At this time, the feedback node is discharged rapidly at the same time, and the drop in the voltage at the feedback node increases the current of the power tube a2, which helps to raise the voltage V OUT At the same time, the voltage at point A is rapidly raised within a time of ns, that is, dt is in the nanosecond level, which is small enough. From formula (2), we can see that dV is the voltage V across the first capacitor U3. OUT The change in the difference between the voltage at point A and the voltage at point A is also small enough, so the change in the voltage at point A will be coupled to the voltage V in a certain proportion. OUT , that is, the voltage at point A rises rapidly, making the voltage V OUT also rises rapidly, thus reducing the voltage V OUT The maximum voltage drop in transient response, even if the current of power tube a2 is less than the load current. As the voltage at point A is raised, the voltage V GS Rapidly decreases, that is, the current of the second transistor U2 rapidly decreases, and finally the current of the second transistor U2 is equal to the current of the first transistor U1, at which time the voltage at point A stops rising.

[0121] Here, the current of power tube a2 refers to the I ds Current, load current refers to the current obtained by the external load from the voltage stabilizing circuit 20, that is, the current required by the load.

[0122] based on Figure 6 The voltage stabilizing circuit 20 shown in FIG. Figure 7 , which shows a schematic diagram of a voltage and current change curve provided by an embodiment of the present disclosure. Figure 7 As shown, based on the voltage stabilizing circuit 20 disclosed in the present invention, at time t0, a load current I load Transient change, the change is ΔI load; During the t0~t1 stage, the gate voltage of the power tube a2 decreases through the coupling of the feedback capacitor a1, and the current of the power tube a2 (expressed by I MOS indicates) starts to rise; at time t1, the voltage V OUT <V REFL , the first comparator b1 starts to work; at time t2, the first comparator b1 outputs a valid signal, based on the voltage stabilizing circuit 20, so that at time t2, even if the current of the power tube a2 is less than the load current, the voltage V OUT There is also a certain degree of recovery, and the current of power tube a2 is still increasing; at time t3, the voltage V OUT Returns the dead zone range (i.e. preset range) V REFL ~V REFH However, the first comparator b1 has a delay, the charge pump is still enabled, and the stability of the circuit is guaranteed by the feedback capacitor a1; at time t4, the voltage V OUT Maintain a stable value, and then adjust the voltage V OUT Maintain at V REF In addition, at time t4, the current of the second transistor U2 is equal to the current of the first transistor U1, the current flowing through the first adjustment sub-circuit 221 reaches a steady state, the voltage at point A no longer rises, and at this time the voltage V OUT Enter V REFL ~V REFH The charge pump is turned off by the first comparator b1 and the second comparator b3, and the voltage at point A will not continue to rise. At time t5, the voltage V OUT Enter V REFL ~V REFH The charge pump is no longer enabled through the first comparator b1 and the second comparator b3, the feedback node is in a high impedance state, and the voltage V OUT However, based on the voltage stabilizing circuit 10 of the related art, the voltage V OUT Finally, it did not stabilize at V REFL ~V REFH between.

[0123] In summary, compared with the first adjustment circuit 12 in the voltage stabilizing circuit 10, the voltage stabilizing circuit 20 additionally adds a second transistor U2, a third transistor U4, a first capacitor U3 and a second capacitor U6 in the first adjustment circuit 22, and the width-to-length ratio of the second transistor U2 is N times the width-to-length ratio of the first transistor U1, and the width-to-length ratio of the third transistor U4 is N times the width-to-length ratio of the fourth transistor U5; at the same time, the output capacitance is very small. Therefore, the output voltage in the present disclosure is not raised through the power tube current, but through the form of capacitors (first capacitors and second capacitors). In this process, the power tube gate is still charged and discharged normally, thereby reducing the drop in output voltage during transient changes; that is, the transient response performance of the voltage stabilizing circuit 20 is enhanced when the output suddenly changes, that is, when the power tube current is less than the load current, and at the same time, the power tube gate voltage is guaranteed to continue to drop, the output voltage is raised, thereby achieving enhanced transient response performance.

[0124] The present disclosure utilizes MOS tubes with different driving capabilities to charge and discharge capacitors, and then through the coupling of the capacitors, when the power tube current is less than the load current, the output voltage can still be increased, or when the power tube current is greater than the load current, the output voltage can still be reduced, thereby improving the transient response performance of the voltage stabilizing circuit 20.

[0125] In another embodiment of the present disclosure, see Figure 8 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Figure 8 As shown, the memory 30 includes the voltage stabilizing circuit 20 described in any one of the aforementioned embodiments.

[0126] Among them, the memory 30 can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., without specific limitation.

[0127] In some embodiments, the memory 30 may include a DRAM chip. The DRAM chip may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, which are not specifically limited here.

[0128] In the embodiment of the present disclosure, for the memory 30, when the output of the voltage stabilizing circuit changes suddenly, the transient response performance of the voltage stabilizing circuit can be improved.

[0129] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0130] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0131] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0132] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0133] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0134] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0135] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A voltage stabilizing circuit, characterized in that: The voltage stabilizing circuit includes a control circuit, a first adjustment circuit, and a second adjustment circuit. The control circuit is connected to the first adjustment circuit. The first adjustment circuit and the second adjustment circuit are connected to a feedback node. The first adjustment circuit is coupled to an output node. The second adjustment circuit is coupled to the output node. The voltage at the output node is the output voltage. The control circuit is used to receive the output voltage and a preset voltage, compare the output voltage with the preset voltage, and generate a control signal; The first adjustment circuit is used to receive the control signal; and to discharge or charge the adjustment node inside the first adjustment circuit according to the control signal; and to pull down or pull up the output voltage according to the voltage at the adjustment node; The second adjustment circuit is used to couple the output node to the feedback node and adjust the output voltage according to the voltage at the feedback node; The first adjustment circuit and the second adjustment circuit jointly make the voltage value of the output voltage within a preset range.

2. The voltage stabilizing circuit according to claim 1, characterized in that: The second adjustment circuit includes a feedback circuit and a power tube circuit, and the feedback circuit and the power tube circuit are coupled to the feedback node and the output node respectively, wherein: The feedback circuit is used to adjust the voltage at the feedback node according to the output voltage; The power tube circuit is used to adjust the output voltage according to the voltage at the feedback node.

3. The voltage stabilizing circuit according to claim 1, characterized in that: The first adjustment circuit includes a first adjustment subcircuit and a second adjustment subcircuit, the adjustment node includes a first adjustment node and a second adjustment node, the preset voltage includes a first preset voltage and a second preset voltage, the control signal includes a first control signal and a second control signal, the control circuit and the first adjustment subcircuit are connected to the first adjustment node, and the control circuit and the second adjustment subcircuit are connected to the second adjustment node, wherein: The control circuit is configured to receive the output voltage, the first preset voltage, and the second preset voltage, compare the output voltage with the first preset voltage and the second preset voltage respectively, and generate the first control signal and the second control signal; when the first control signal is in an enabled state, charge the first adjustment node, or when the second control signal is in an enabled state, discharge the second adjustment node; The first adjustment subcircuit is used to charge the output node and discharge the feedback node according to the voltage at the first adjustment node; The second adjustment subcircuit is used to discharge the output node and charge the feedback node according to the voltage at the second adjustment node; The first preset voltage is smaller than the second preset voltage, and an interval formed by the first preset voltage and the second preset voltage is the preset range.

4. The voltage stabilizing circuit according to claim 3, characterized in that: The first adjustment subcircuit includes a first transistor, a second transistor and a first capacitor, and the second adjustment subcircuit includes a third transistor, a fourth transistor and a second capacitor, wherein: The first terminal of the first transistor is connected to the ground voltage, the second terminal of the first transistor and the first plate of the first capacitor are both connected to the first adjustment node, the control terminal of the first transistor is connected to the power supply voltage, and the second plate of the first capacitor is connected to the output node; The first end of the second transistor is connected to the first adjustment node, and the control end of the second transistor is used to receive the first control signal; the first end of the third transistor is connected to the second adjustment node, and the control end of the third transistor is used to receive the second control signal; the second end of the second transistor and the second end of the third transistor are both connected to the feedback node; The first end of the fourth transistor is connected to the power supply voltage, the second end of the fourth transistor and the first plate of the second capacitor are both connected to the second adjustment node, the control end of the fourth transistor is connected to the ground voltage, and the second plate of the second capacitor is connected to the output node.

5. The voltage stabilizing circuit according to claim 4, characterized in that: The width-to-length ratio of the second transistor is greater than that of the first transistor, and the width-to-length ratio of the third transistor is greater than that of the fourth transistor.

6. The voltage stabilizing circuit according to claim 3, characterized in that: The control circuit comprises a first comparison circuit and a second comparison circuit, wherein: The first comparison circuit is used to receive the output voltage and the first preset voltage, compare the output voltage with the first preset voltage, and output the first control signal in an enabled state when the first preset voltage is greater than the output voltage, or output the first control signal in a disabled state when the first preset voltage is less than or equal to the output voltage; The second comparison circuit is used to receive the output voltage and the second preset voltage, compare the output voltage with the second preset voltage, and output the second control signal in an enabled state when the second preset voltage is less than the output voltage, or output the second control signal in a disabled state when the second preset voltage is greater than or equal to the output voltage.

7. The voltage stabilizing circuit according to claim 6, characterized in that: The first comparison circuit includes a first comparator and a first NOT gate, and the second comparison circuit includes a second comparator and a second NOT gate, wherein: The non-inverting input terminal of the first comparator is used to receive the output voltage, the inverting input terminal of the first comparator is used to receive the first preset voltage, the output terminal of the first comparator is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is used to output the first control signal; The non-inverting input terminal of the second comparator is used to receive the output voltage, the inverting input terminal of the second comparator is used to receive the second preset voltage, the output terminal of the second comparator is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is used to output the second control signal.

8. The voltage stabilizing circuit according to claim 3, characterized in that: The voltage stabilizing circuit further includes a fine-tuning circuit, and the fine-tuning circuit includes a logic circuit, a third comparison circuit and a third adjustment circuit, wherein: The logic circuit is used to receive the first control signal and the second control signal, perform logic processing according to the first control signal and the second control signal, and output an enable signal in an enabled state when the level states of the first control signal and the second control signal are different, or output the enable signal in a disabled state when the level states of the first control signal and the second control signal are the same; The third comparison circuit is used to receive the output voltage, the reference voltage and the clock signal, and when the clock signal is in a valid state, compare the reference voltage with the output voltage and output a third control signal; The third adjustment circuit is used to receive the enable signal and the third control signal, and when the enable signal is in an enabled state, adjust the voltage value of the output voltage to be equal to the voltage value of the reference voltage according to the third control signal; The voltage value of the reference voltage is within the preset range, and the reference voltage is a target voltage obtained after adjustment by the voltage stabilizing circuit.

9. The voltage stabilizing circuit according to claim 8, characterized in that: The logic circuit includes an XOR gate, the third comparison circuit includes a third comparator, and the third adjustment circuit includes a fine-tuning module, wherein: The first input end of the XOR gate is used to receive the first control signal, the second input end of the XOR gate is used to receive the second control signal, and the output end of the XOR gate is connected to the enable end of the fine-tuning module to output the enable signal; The non-inverting input terminal of the third comparator is used to receive the output voltage, the inverting input terminal of the third comparator is used to receive the reference voltage, the clock terminal of the third comparator is used to receive the clock signal, the output terminal of the third comparator is connected to the input terminal of the fine-tuning module for outputting the third control signal; the output terminal of the fine-tuning module is connected to the feedback node.

10. A memory, characterized in that: The memory includes the voltage stabilizing circuit according to any one of claims 1 to 9.

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