Bias current generation circuit, filter circuit, power supply system and electronic equipment

Abstract

The invention discloses a bias current generation circuit, a filter circuit, a power supply system and electronic equipment, the bias current generation circuit comprises a bias current generation module, a power supply voltage end of the bias current generation module is connected with a voltage stabilizing circuit of the power supply system, the voltage stabilizing circuit is used for outputting a first power supply voltage, and the first power supply voltage is used for outputting a second power supply voltage; and the bias current generation module is used for outputting bias current under the power supply of the first power supply voltage. By adopting the circuit, the correlation of the current source to the voltage of the analog power supply can be reduced, the bias current generation circuit is prevented from being interfered by fluctuation of the analog power supply, and the PSR of the bias current source is improved.

Description

Technical Field

[0001] The present invention relates to the field of vehicle technology, and in particular to a bias current generating circuit, a filtering circuit, a power supply system and an electronic device. Background Art

[0002] In the related art, the analog power supply supplies power to the bias current generation module. However, since the analog power supply voltage is coupled by the on-chip digital signal, the bias current generation module is easily interfered by the analog power supply voltage, and the PSR (Power Supply Rejection, low-frequency power supply ripple rejection ratio) is relatively low within the bandwidth range. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a bias current generating circuit, which can reduce the correlation of the current source to the analog power supply voltage, avoid the bias current generating circuit being disturbed by the fluctuation of the analog power supply, and improve the PSR of the bias current source.

[0004] A second objective of the present invention is to provide a filter circuit.

[0005] A third objective of the present invention is to provide a power supply system.

[0006] A fourth objective of the present invention is to provide an electronic device.

[0007] A fifth object of the present invention is to provide a vehicle.

[0008] In order to solve the above problems, an embodiment of a first aspect of the present invention provides a bias current generating circuit for a power supply system, the circuit comprising: a bias current generating module, the power supply voltage end of the bias current generating module is connected to a voltage stabilizing circuit of the power supply system, the voltage stabilizing circuit is used to output a first power supply voltage, and the bias current generating module is used to output a bias current under the power supply of the first power supply voltage.

[0009] According to the bias current generating circuit of the embodiment of the present invention, compared with the prior art in which the bias current generating module is directly powered by an analog power supply, in the present application, the first power supply voltage output after being stabilized by the voltage stabilizing circuit is used as the power supply for the bias current generating module, thereby reducing the correlation of the current source with the analog power supply voltage, avoiding the bias current generating circuit from being disturbed by the fluctuation of the analog power supply, and improving the PSR of the bias current source.

[0010] A second aspect of the present invention provides a filtering circuit, comprising: a first switch module, wherein a first end of the first switch module is connected to a voltage stabilizing circuit of a power supply system in which the first switch module is located to receive a first power supply voltage output by the voltage stabilizing circuit, and a control end of the first switch module is used to receive a first enable signal, and the first enable signal has the same logic as a power switch signal of the power supply system; a second switch module, wherein a first end of the second switch module is connected to an analog power supply, and a control end of the second switch module is used to receive a second enable signal, and the second enable signal has an opposite logic to the power switch signal of the power supply system; a filtering structure, wherein a first end of the filtering structure is connected to a second end of the first switch module and a power supply voltage end of the bias current generating circuit described in the above embodiment, and a second end of the filtering structure is connected to a second end of the second switch module, and the filtering structure is used to filter the first power supply voltage or the power supply voltage provided by the analog power supply so that the filtered second power supply voltage powers the bias current generating circuit.

[0011] According to the filtering circuit of the embodiment of the present invention, the filtering structure selectively filters the first power supply voltage output by the voltage stabilization circuit or the power supply voltage provided by the analog power supply under the action of the first enable signal and the second enable signal, so as to power the bias current generating circuit with the second power supply voltage obtained after filtering, thereby reducing the interference of the noise signal on the power supply voltage and the bias current.

[0012] A third aspect of the present invention provides a power supply system, comprising: a voltage stabilizing circuit, the voltage stabilizing circuit being used to convert the voltage of an analog power supply into a first power supply voltage in a power supply state; the bias current generating circuit described in the above embodiment and the filtering circuit described in the above embodiment, the power supply voltage end of the bias current generating circuit being connected to the output end of the filtering circuit, and the first input end of the filtering circuit being connected to the output end of the voltage stabilizing circuit; wherein the filtering circuit is used to filter the first power supply voltage in a power supply state to obtain a second power supply voltage, so that the second power supply voltage powers the bias current generating circuit.

[0013] According to the power supply system of the embodiment of the present invention, when the power supply system is in the power supply state, the voltage stabilizing circuit converts the voltage of the analog power supply into a first power supply voltage, and the filtering structure filters the first power supply voltage and then supplies power to the bias current generating circuit, thereby reducing the correlation of the current source with the analog power supply voltage, improving the power supply ripple suppression capability, avoiding the bias current generating circuit from being disturbed by the fluctuation of the analog power supply, and improving the PSR of the bias current source. At the same time, the first power supply voltage is bidirectionally filtered to couple the noise through the filtering structure, thereby reducing the influence of the noise on the generated bias current.

[0014] A fourth aspect of the present invention provides an electronic device, including the power supply system described in the above embodiment.

[0015] According to the electronic device of the embodiment of the present invention, through the power supply system of the above embodiment, the correlation of the current source and the voltage stabilizing circuit to the analog power supply voltage can be reduced, the bias current generating circuit and the voltage stabilizing circuit can be prevented from being disturbed by the fluctuation of the analog power supply, and the PSR of the bias current source and the voltage stabilizing circuit can be improved.

[0016] A fifth aspect of the present invention provides a vehicle, comprising the electronic device described in the above embodiment.

[0017] According to the vehicle of the embodiment of the present invention, through the electronic device of the above embodiment, the correlation of the current source to the analog power supply voltage can be reduced, the bias current generating circuit can be prevented from being disturbed by the fluctuation of the analog power supply, and the PSR can be improved.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0020] Figure 1 is a structural block diagram of a bias current generating circuit according to an embodiment of the present invention;

[0021] Figure 2 is a schematic diagram of a power supply system according to an embodiment of the present invention;

[0022] Figure 3 is a schematic diagram of a filter circuit according to an embodiment of the present invention;

[0023] Figure 4 is a schematic diagram of an enable signal and a power switch signal according to an embodiment of the present invention;

[0024] Figure 5 is a schematic diagram of a power supply system according to another embodiment of the present invention;

[0025] Figure 6 is a structural block diagram of an electronic device according to an embodiment of the present invention;

[0026] Figure 7 is a structural block diagram of a vehicle according to an embodiment of the present invention.

[0027] Reference numerals:

[0028] Vehicle 3000; electronic device 2000; power supply system 1000; filter circuit 900; bias current generating circuit 800; voltage stabilizing circuit 700;

[0029] Bias current generating module 1; first filtering unit 11; bias current generating unit 12; low voltage common source common gate current mirror 13; bias voltage providing unit 14; bias current output unit 15; second filtering unit 16; pre-charging module 17; first resistance unit 161; first capacitance unit 162; switch unit 2; start control module 3; first stage operational amplifier structure 4; second stage operational amplifier structure 5; compensation module 6; power supply unit 41; operational amplifier unit 42; current mirror unit 411; current source subunit 412; output conversion unit 51; output unit 52; start circuit 7; first power supply module 71; second power supply module 72; current mirror module 73; series inverse ratio tube structure 711; first current mirror unit 731; second current mirror unit 732; first switch module 91; second switch module 92; bias current demand module 93; filter structure 8; first filter module 81; second filter module 82; second resistor unit 821; second capacitor unit 822; first MOS tube MN14; second MOS tube MP15; third MOS tube MP16; fourth MOS tube MP17; fifth MOS tube MP18; sixth MOS tube MN15; seventh MOS tube MN16; eighth MOS tube MN18; ninth MOS tube MN21; tenth MOS tube MP19; eleventh MOS tube MP20; twelfth MOS tube MN25; thirteenth MOS tube MP21; fourteenth MOS tube MP22; fifteenth MOS tube MN20 ; the sixteenth MOS tube MN2; the seventeenth MOS tube MN6; the eighteenth MOS tube MP10; the nineteenth MOS tube MP11; the twentieth MOS tube MP6; the twenty-first MOS tube MP7; the twenty-second MOS tube MP8; the twenty-third MOS tube MP9; the twenty-fourth MOS tube MN8; the twenty-fifth MOS tube MN9; the twenty-sixth MOS tube MN7; the twenty-seventh MOS tube MN10; the twenty-eighth MOS tube MN11; the twenty-ninth MOS tube MN12; the thirtieth MOS tube MP12; the thirty-first MOS tube MP13; the thirty-second MOS tube MP14; the thirty-third MOS tube MP3; the thirty-fourth MOS tube MN3; the thirty-fifth MOS tube MN22; the thirty-sixth MOS tube MN7; the twenty-seventh MOS tube MN10; the twenty-eighth MOS tube MN11; the twenty-ninth MOS tube MN12; the thirtieth MOS tube MP12; the thirty-first MOS tube MP13; the thirty-second MOS tube MP14; the thirty-third MOS tube MP3; the thirty-fourth MOS tube MN3; the thirty-fifth MOS tube MN22; The sixth MOS tube MN23; the thirty-seventh MOS tube MN0; the thirty-eighth MOS tube MN4; the thirty-ninth MOS tube MN5; the fortieth MOS tube MN1; the forty-first MOS tube MP4; the forty-second MOS tube MP5; the forty-third MOS tube MP0; the forty-fourth MOS tube MP1; the forty-fifth MOS tube MP2; the forty-sixth MOS tube MP23; the forty-seventh MOS tube MN24; the first resistor R4; the second resistor R5; the third resistor R6; the fourth resistor R7; the fifth resistor R8; the sixth resistor R9; the seventh resistor R1; the eighth resistor R2; the ninth resistor R0; the first capacitor C3; the second capacitor CL; the third capacitor C4; the fourth capacitor C5; the fifth capacitor C2; the sixth capacitor C0. DETAILED DESCRIPTION

[0030] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0031] In order to solve the above problems, an embodiment of the first aspect of the present invention provides a bias current generating circuit, which can reduce the correlation of the current source to the analog power supply voltage, avoid the bias current generating circuit being disturbed by the fluctuation of the analog power supply, and improve the PSR of the bias current source.

[0032] In an embodiment, the bias current generating circuit is used in a power supply system, wherein the power supply system may be an on-chip power supply system.

[0033] Reference below Figure 1 The bias current generating circuit 800 according to an embodiment of the present invention is described as follows. Figure 1 As shown, the bias current generating circuit 800 includes: a bias current generating module 1.

[0034] Among them, the power supply voltage end of the bias current generating module 1 is connected to the voltage stabilizing circuit 700 of the power supply system 1000, the voltage stabilizing circuit 700 is used to output a first power supply voltage, and the bias current generating module 1 is used to output a bias current under the power supply of the first power supply voltage, that is, the bias current generating module 1 works to output a bias current under the power supply of the first power supply voltage.

[0035] Specifically, in order to solve this problem, in the present application, the bias current generating module 1 is powered by the first power supply voltage output by the voltage stabilizing circuit, that is, the bias current generating module 1 operates under the first power supply voltage output by the voltage stabilizing circuit, and the bias current generating module 1 is no longer powered directly by the analog power supply, but operates under the output voltage of the voltage stabilizing circuit, thereby reducing the correlation of the current source to the analog power supply voltage, avoiding the bias current generating circuit from being disturbed by the fluctuation of the analog power supply, and improving the PSR of the bias current source.

[0036] In addition, the current source structure in the present application uses a voltage-controlled reference current source, rather than a current source based on a threshold voltage or a Widlar current source, and has higher current accuracy.

[0037] According to the bias current generating circuit of the embodiment of the present invention, compared with the prior art in which the bias current generating module 1 is powered by an analog power supply, the first power supply voltage output by the voltage stabilizing circuit in the present application is used to power the bias current generating module 1, and the bias current generating module 1 and the voltage stabilizing circuit form a self-bias loop, thereby reducing the correlation of the current source to the analog power supply voltage, avoiding the bias current generating circuit from being disturbed by the fluctuation of the analog power supply, and improving the PSR of the bias current source.

[0038] In some embodiments, Figure 2 As shown, the bias current generating module 1 includes: a first filtering unit 11 , a bias current generating unit 12 , a low voltage cascode current mirror 13 and a bias voltage providing unit 14 .

[0039] Among them, the first end of the first filtering unit 11 is connected to the reference power supply, and the first filtering unit 11 is used to filter the reference voltage provided by the reference power supply; the first end of the bias current generating unit 12 is connected to the second end of the first filtering unit 11, and the bias current generating unit 12 is used to generate a bias current according to the filtered reference voltage; the first end of the low-voltage cascode current mirror 13 is the power supply voltage end, and the second end of the low-voltage cascode current mirror 13 is connected to the second end of the bias current generating unit 12 for mirroring the bias current; the first end of the bias voltage providing unit 14 is connected to the third end of the low-voltage cascode current mirror 13, and the second end of the bias voltage providing unit 14 is the bias voltage end for providing a bias voltage.

[0040] Specifically, after the first filtering unit 11 filters the reference voltage, the bias current generating unit 12 generates a bias current according to the filtered reference voltage, and the low-voltage cascode current mirror 13 copies the bias current generated by the bias current generating unit 12 to the bias voltage providing unit 14, and the bias voltage is provided by the bias voltage providing unit 14. Therefore, the low-voltage cascode current mirror 13 is adopted in the present application, so as to further improve the accuracy of PSR and bias current replication, and at the same time, the substrate of the low-voltage cascode current mirror 13 uses the filtered power supply voltage, so as to further reduce the influence of power supply noise on the signal.

[0041] In some embodiments, Figure 2 As shown, the bias current generating unit 12 includes: a first MOS transistor MN14, a first resistor R4 and a second resistor R5.

[0042] Among them, the gate of the first MOS tube MN14 is connected to the second end of the first filtering unit 11, and the drain of the first MOS tube MN14 is connected to the second end of the low-voltage cascode current mirror 13, wherein the first MOS tube MN14 is a source follower, and the first MOS tube MN14 can be an NMOS tube; the first end of the first resistor R4 is connected to the source of the first MOS tube MN14, and the second end of the first resistor R4 is connected to the fourth end of the low-voltage cascode current mirror 13; the first end of the second resistor R5 is connected to the second end of the first resistor R4, and the second end of the second resistor R5 is connected to the negative voltage source.

[0043] Specifically, after the first filtering unit 11 filters the reference voltage, the first MOS tube MN14 provides current driving capability to generate a bias current on the first resistor R4 and the second resistor R5. Thus, the bias current generating unit 12 generates a bias current under the action of the filtered reference voltage, thereby reducing the interference of the noise signal on the bias current.

[0044] In some embodiments, Figure 2 As shown, the low voltage cascode current mirror 13 includes: a second MOS transistor MP15, a third MOS transistor MP16, a fourth MOS transistor MP17 and a fifth MOS transistor MP18.

[0045] The drain of the second MOS transistor MP15 is connected to the voltage stabilizing circuit 700, and the gate of the second MOS transistor MP15 is connected to the drain of the first MOS transistor MN14; the gate of the third MOS transistor MP16 is connected to the gate of the second MOS transistor MP15, and the drain of the third MOS transistor MP16 is connected to the drain of the second MOS transistor MP15; the drain of the fourth MOS transistor MP17 is connected to the source of the second MOS transistor MP15, the source of the fourth MOS transistor MP17 is connected to the drain of the first MOS transistor MN14, and the gate of the fourth MOS transistor MP17 is connected to the second end of the first resistor R4; the gate of the fifth MOS transistor MP18 is connected to the gate of the fourth MOS transistor MP17, the drain of the fifth MOS transistor MP18 is connected to the source of the third MOS transistor MP16, and the source of the fifth MOS transistor MP18 is connected to the first end of the bias voltage providing unit 14. The second MOS transistor MP15, the third MOS transistor MP16, the fourth MOS transistor MP17 and the fifth MOS transistor MP18 are PMOS transistors, and the second MOS transistor MP15, the third MOS transistor MP16, the fourth MOS transistor MP17 and the fifth MOS transistor MP18 form a low-voltage common-source common-gate current mirror 13 through a common-source and common-gate connection mode.

[0046] Specifically, after the bias current generating unit 12 generates the bias current, the low-voltage cascode current mirror 13 composed of the second MOS transistor MP15, the third MOS transistor MP16, the fourth MOS transistor MP17 and the fifth MOS transistor MP18 mirrors the bias current, that is, the bias current generated by the bias current generating unit 12 is copied, thereby, the low-voltage cascode current mirror 13 realizes the mirror copy of the bias current, improves the accuracy of PSR and bias current copy, and the mirror copy of the bias current is more accurate. At the same time, the substrate of the low-voltage cascode current mirror 13 uses the filtered power supply voltage VDDL1C, which further reduces the influence of power supply noise on the signal.

[0047] In some embodiments, Figure 2 As shown, the bias voltage providing unit 14 includes: a sixth MOS transistor MN15.

[0048] The drain of the sixth MOS transistor MN15 is connected to the source of the fifth MOS transistor MP18, the source of the sixth MOS transistor MN15 is connected to the negative voltage source, and the gate of the sixth MOS transistor MN15 is used to provide a bias voltage, wherein the sixth MOS transistor MN15 may be an NMOS transistor. That is, the low-voltage cascode current mirror 13 copies the bias current generated by the bias current generating unit 12 to the bias voltage providing unit 14, and the bias voltage is provided by the sixth MOS transistor MN15 of the bias voltage providing unit 14.

[0049] In some embodiments, Figure 2 As shown, the bias current generating module 1 further includes: a second filtering unit 16 and a bias current output unit 15 .

[0050] Among them, the first end of the second filtering unit 16 is connected to the second end of the bias voltage providing unit 14, the second end of the second filtering unit 16 is connected to the voltage stabilizing circuit 700, and the second filtering unit 16 is used to filter the bias voltage; the first end of the bias current output unit 15 is connected to the third end of the second filtering module 82, and the bias current output unit 15 is used to output the bias current according to the filtered bias voltage.

[0051] Specifically, the second filtering unit 16 filters the bias voltage provided by the bias voltage providing unit 14 to eliminate interference signals, and the bias current output unit 15 outputs the bias current according to the filtered bias voltage, thereby greatly reducing interference of noise signals on the bias current.

[0052] In some embodiments, the bias current output unit 15 is multiple, such as Figure 2 As shown, each bias current output unit 15 includes: a power tube MN19.

[0053] The gate of the power tube MN19 is connected to the third end of the second filter module 82, the drain of the power tube MN19 is used to provide a bias current to the corresponding bias current demand module 93, and the source of the power tube MN19 is connected to a negative voltage source. The power tube is an NMOS tube current mirror. The power tube can also be an MNN.

[0054] In some embodiments, Figure 2 As shown, the second filtering unit 16 includes: a first resistance unit 161 and a first capacitance unit 162 .

[0055] Among them, the first end of the first resistor unit 161 is connected to the second end of the bias voltage providing unit 14, the second end of the first resistor unit 161 is connected to the first end of the first capacitor unit 162 and the first end of the bias current output unit 15, the third end of the first resistor unit 161 is connected to the voltage stabilizing circuit 700, and the second end of the first capacitor unit 162 is connected to the negative voltage source. Therefore, the bias voltage provided by the bias voltage providing unit 14 is filtered through the RC filtering structure composed of the first resistor unit 161 and the first capacitor unit 162, and the second filtering unit 16 basically filters the noise of the concerned frequency band, greatly reducing the interference of the noise signal on the bias voltage and bias current.

[0056] In some embodiments, Figure 2 As shown, the bias current generating circuit 800 also includes: a pre-charging module 17.

[0057] The first end of the pre-charging module 17 is connected to the analog power supply, the second end of the pre-charging module 17 is connected to the first end of the first capacitor unit 162, and the pre-charging module 17 is used to perform pre-charging control on the first capacitor unit 162. Thus, by pre-charging the first capacitor unit 162, the startup speed of the bias current generating circuit is further accelerated.

[0058] Specifically, the first capacitor unit 162 is used as a power source to supply power to the circuit, and the pre-charging module 17 performs pre-charging control on the first capacitor unit 162 , that is, controls the pre-charging module 17 to charge the first capacitor unit 162 in advance, thereby accelerating the power supply of the entire system of the first capacitor unit 162 .

[0059] In some embodiments, Figure 2 As shown, the bias current generating circuit 800 further includes: a switch unit 2 and a start control module 3 .

[0060] Among them, the first end of the switch unit 2 is connected to the first end of the first resistance unit 161 and the first end of the bias voltage providing unit 14, and the second end of the switch unit 2 is connected to the second end of the first resistance unit 161; the first end of the start-up control module 3 is connected to the voltage stabilizing circuit 700 to receive the first power supply voltage, and the second end of the start-up control module 3 is connected to the control end of the switch unit 2. The start-up control module 3 is used to be turned on when the quick start function is turned on to short-circuit the first resistance unit 161.

[0061] In addition, an RC filter structure may be used in the start control module 3 to filter noise.

[0062] Specifically, the switch unit 2 is turned on or off by starting the control module 3, wherein, Figure 2As shown, the switch unit 2 includes a MOS tube MN17, that is, the on or off of the MOS tube MN17 is controlled by the startup control module 3. When the quick startup function is turned on, the startup control module 3 turns on the MOS tube MN17, short-circuits the first resistance unit 161, and pre-charges the first capacitance unit 162 to reduce the time constant and realize the accelerated startup of the bias current generating circuit.

[0063] In some embodiments, Figure 2 As shown, the first resistance unit 161 includes: a seventh MOS transistor MN16 and a third resistor R6.

[0064] Among them, the gate of the seventh MOS tube MN16 is connected to the voltage stabilizing circuit 700, and the drain of the seventh MOS tube MN16 is connected to the second end of the bias voltage providing unit 14 and the first end of the switch unit 2; the first end of the third resistor R6 is connected to the source of the seventh MOS tube MN16, and the second end of the third resistor R6 is connected to the first end of the first capacitor unit 162, the first end of the bias current output unit 15, and the second end of the switch unit 2, wherein the seventh MOS tube MN16 is an NMOS tube, and the seventh MOS tube MN16 is a MOS resistor.

[0065] Specifically, by controlling the conduction state of the seventh MOS transistor MN16, the passing and blocking of the signal of a specific frequency are controlled, and the signal of the specific frequency is filtered out by the third resistor R6 after passing through. Therefore, the MOS transistor resistor is used in the first resistor unit 161, thereby greatly saving chip area and reducing costs, and the gate of the seventh MOS transistor MN16 uses the bias voltage VDDL1C after filtering, further reducing the influence of power supply noise on the signal.

[0066] In some embodiments, Figure 2 As shown, the first capacitor unit 162 includes: a first capacitor C3 and an eighth MOS transistor MN18.

[0067] Among them, the first end of the first capacitor C3 is connected to the second end of the third resistor R6, the second end of the switch unit 2, and the second end of the pre-charge module 17, and the second end of the first capacitor C3 is connected to the negative voltage source; the gate of the eighth MOS tube MN18 is connected to the second end of the third resistor R6, the second end of the switch unit 2, and the second end of the pre-charge module 17, and the source of the eighth MOS tube MN18 and the drain of the eighth MOS tube MN18 are both connected to the negative voltage source, wherein the eighth MOS tube MN18 is an NMOS tube, and the eighth MOS tube MN18 is a MOS capacitor, that is, the MOS capacitor used utilizes the structural characteristics of the MOS tube, and uses the gate of the eighth MOS tube MN18 as the upper plate, and connects the three ends of the source, drain and substrate of the eighth MOS tube MN18 as the lower plate, and the gate oxide between the gate and the channel is used as an insulating medium to form a MOS capacitor. Therefore, the first capacitor unit 162 adopts a MOS capacitor, which can save chip area to a great extent and reduce costs.

[0068] Specifically, by controlling the conduction state of the eighth MOS transistor MN18, the passing and blocking of the signal of a specific frequency is controlled, and the signal of the specific frequency is filtered out by the first capacitor C3 after passing through. Therefore, the MOS transistor capacitor is used in the first capacitor unit 162, thereby greatly saving chip area and reducing costs.

[0069] In some embodiments, Figure 2 As shown, the pre-charging module 17 includes: a ninth MOS transistor MN21 and a fourth resistor R7.

[0070] Among them, the gate of the ninth MOS tube MN21 is used to receive the switch enable signal, and the drain of the ninth MOS tube MN21 is connected to the analog power supply; the first end of the fourth resistor R7 is connected to the source of the ninth MOS tube MN21, and the second end of the fourth resistor R7 is connected to the first end of the first capacitor C3. Specifically, the pre-charge module 17 controls the on and off of the ninth MOS tube MN21 to control the on and off of the pre-charge function. Therefore, the pre-charge function is started by the on-state of the ninth MOS tube MN21, further accelerating the startup speed of the bias current generating circuit.

[0071] In some embodiments, Figure 2 As shown, the bias current generating circuit 800 further includes: a second capacitor CL.

[0072] The first end of the second capacitor CL is connected to the voltage stabilizing circuit 700, and the second end of the second capacitor CL is connected to the negative voltage source. The second capacitor CL is used to filter the first supply voltage output by the voltage stabilizing circuit 700, thereby reducing the interference of the noise signal on the output voltage and bias current of the voltage stabilizing circuit.

[0073] A second aspect of the present invention provides a filter circuit 900, such as Figure 3 As shown, it includes: a first switch module 91, a second switch module 92 and a filtering structure 8.

[0074] The first end of the first switch module 91 is connected to the voltage stabilizing circuit 700 of the power supply system 1000 to receive the first supply voltage output by the voltage stabilizing circuit, and the control end of the first switch module 91 is used to receive the first enable signal, such as Figure 4 As shown, the first enable signal PDA has the same logic as the power switch signal PowerDown of the power supply system, wherein the power switch signal is a signal for controlling the power supply of the power supply system; the first end of the second switch module 92 is connected to the analog power supply, and the control end of the second switch module 92 is used to receive the second enable signal, such as Figure 4 As shown, the second enable signal PDB is logically opposite to the power switch signal PowerDown of the power supply system; the first end of the filter structure 8 is connected to the second end of the first switch module 91 and the power supply voltage end of the bias current generating circuit 800 of the above embodiment, and the second end of the filter structure 8 is connected to the second end of the second switch module 92. The filter structure 8 is used to filter the first power supply voltage or the power supply voltage provided by the analog power supply, so that the filtered second power supply voltage is used to power the bias current generating circuit. The analog power supply can be a digital low-voltage power supply.

[0075] Specifically, the switching states of the first switch module 91 and the second switch module 92 are controlled by the power supply switch signal to selectively input the first power supply voltage output by the voltage stabilizing circuit or the power supply voltage provided by the analog power supply into the filter structure 8, and the filter structure 8 filters the first power supply voltage or the power supply voltage provided by the analog power supply so that the filtered second power supply voltage is used to power the bias current generating circuit. That is to say, the first enable signal has the same logic as the power supply switch signal. When the first switch module 91 is turned on by the first enable signal, the second enable signal is opposite in logic to the power supply switch signal. At this time, the second switch module 92 is turned off, and the first power supply voltage is input into the filter structure 8 through the first switch module 91, and the filter structure 8 filters the first power supply voltage so that the filtered second power supply voltage is used to power the bias current generating circuit. When the first switch module 91 is turned off by the first enable signal, the second switch module 92 is turned on, and the power supply voltage provided by the analog power supply is input into the filter structure 8 through the second switch module 92, and the filter structure 8 filters the power supply voltage provided by the analog power supply so that the filtered second power supply voltage is used to power the bias current generating circuit. Therefore, in the present application, the power supply voltage provided by the voltage stabilization circuit or the analog power supply is filtered by the filtering structure 8, thereby reducing the interference of the noise signal on the power supply voltage and the bias current.

[0076] Exemplarily, the first switch module 91 is turned on when the first enable signal received at the control end is at a low potential. When the first switch module 91 is turned on, the first power supply voltage output by the voltage stabilizing circuit is input to the filtering structure 8 through the first switch module 91. The filtering structure 8 filters the first power supply voltage to obtain a second power supply voltage, so that the filtered second power supply voltage is used to power the bias current generating circuit. Since the control end of the second switch module 92 is controlled by the second enable signal, wherein the second enable signal is logically opposite to the power supply switch signal of the power supply system, when the second enable signal received by the second switch module 92 is at a high potential, the second switch module 92 is cut off, and the power supply voltage provided by the analog power supply cannot pass through the second switch module 92; similarly, when the first enable signal received by the control end of the first switch module 91 is at a high potential, it is cut off, and the second enable signal received by the second switch module 92 is at a low potential and is turned on. Under the action of the second switch module 92 being turned on, the power supply voltage provided by the analog power supply is input to the filter structure 8 through the second switch module 92, and the filter structure 8 filters the power supply voltage provided by the analog power supply to obtain the second power supply voltage, so that the filtered second power supply voltage is used to power the bias current generating circuit.

[0077] According to the filtering circuit of the embodiment of the present invention, the filtering structure 8 selectively filters the first power supply voltage output by the voltage stabilizing circuit or the power supply voltage provided by the analog power supply under the action of the first enable signal and the second enable signal, so as to power the bias current generating circuit with the second power supply voltage obtained after filtering, thereby reducing the interference of the noise signal on the power supply voltage and the bias current.

[0078] In some embodiments, Figure 3 As shown, the filtering structure 8 includes: a first filtering module 81 and a second filtering module 82 .

[0079] The first end of the first filter module 81 is connected to the second end of the first switch module 91 and the power supply voltage end, and the second end of the first filter module 81 is connected to the negative voltage source; the first end of the second filter module 82 is connected to the second end of the second switch module 92, the second end of the second filter module 82 is connected to the first end of the first filter module 81, and the third end of the second filter module 82 is connected to the negative voltage source. The first filter module 81 and the second filter module 82 filter the first power supply voltage so that the filtered second power supply voltage is used to power the bias current generation circuit; the first filter module 81 and the second filter module 82 filter the power supply voltage provided by the analog power supply so that the filtered second power supply voltage is used to power the bias current generation circuit.

[0080] Specifically, the first switch module 91 is turned on when the first enable signal received at the control end is at a low potential. When the first switch module 91 is turned on, the first power supply voltage output by the voltage stabilizing circuit is input to the filter structure 8 through the first switch module 91. The first filter module 81 and the second filter module 82 filter the first power supply voltage to obtain the second power supply voltage, so that the filtered second power supply voltage is used to power the bias current generating circuit. Since the control end of the second switch module 92 is controlled by the second enable signal, wherein the second enable signal is logically opposite to the power supply switch signal of the power supply system, when the second enable signal received by the second switch module 92 is high potential, the second switch module 92 is cut off, and the power supply voltage provided by the analog power supply cannot pass through the second switch module 92; similarly, when the first enable signal received by the control end of the first switch module 91 is high potential, it is cut off, and the second enable signal received by the second switch module 92 is low potential and turned on, under the action of the second switch module 92 being turned on, the power supply voltage provided by the analog power supply is input to the filter structure 8 through the second switch module 92, and the first filter module 81 and the second filter module 82 filter the power supply voltage provided by the analog power supply to obtain the second power supply voltage, so that the filtered second power supply voltage is used to power the bias current generating circuit. Therefore, in the present application, the power supply voltage provided by the voltage stabilizing circuit or the analog power supply is filtered by the filter structure 8, that is, the power supply voltage output by the voltage stabilizing circuit is subjected to bidirectional filtering and coupling noise processing, so as to further reduce the interference of the noise signal on the power supply voltage and the bias current.

[0081] In some embodiments, Figure 3 As shown, the bias current generating circuit 800 includes a low-voltage cascode current mirror 13 for mirroring the bias current, and the substrate terminals of all MOS tubes in the low-voltage cascode current mirror 13 are connected to the first terminal and the power supply voltage terminal of the first filtering module 81. In other words, the filtered second power supply voltage is used to power the low-voltage cascode current mirror 13, and the low-voltage cascode current mirror 13 outputs the mirror bias current under the power supply of the second power supply voltage.

[0082] In some embodiments, Figure 2 As shown, the bias current generating circuit 800 includes a bias voltage providing unit 14 for providing a bias voltage and a second filtering unit 16 for filtering the bias voltage. The second end of the second filtering unit 16 is connected to the first end of the first filtering module 81 and the power supply voltage end, so that the second power supply voltage is used as the bias voltage of the second filtering unit 16. In other words, the filtered second power supply voltage is used as the bias voltage of the second filtering unit 16. For example, the gate of the seventh MOS transistor MN16 uses the bias voltage VDDL1C after filtering, which further reduces the influence of power supply noise on the signal.

[0083] In some embodiments, Figure 3 As shown, the first switch module 91 includes: a tenth MOS transistor MP19.

[0084] The drain of the tenth MOS transistor MP19 is connected to the voltage stabilizing circuit 700, the gate of the tenth MOS transistor MP19 is used to receive the first enable signal, and the source of the tenth MOS transistor MP19 is connected to the first end of the filter structure 8 and the power supply voltage end, wherein the tenth MOS transistor MP19 is a PMOS transistor. That is to say, the gate of the tenth MOS transistor MP19 is turned on when the received first enable signal PDA is at a low potential, and the first power supply voltage output by the voltage stabilizing circuit is input to the first filter module 81 through the tenth MOS transistor MP19, and the first filter module 81 filters the first power supply voltage ADDL to obtain the second power supply voltage, so that the filtered second power supply voltage is used to power the bias current generating circuit.

[0085] In some embodiments, Figure 3 As shown, the second switch module 92 includes: an eleventh MOS transistor MP20.

[0086] Among them, the drain of the eleventh MOS transistor MP20 is connected to the analog power supply, the gate of the eleventh MOS transistor MP20 is used to receive the second enable signal, and the source of the eleventh MOS transistor MP20 is connected to the second end of the filter structure 8. In other words, the gate of the eleventh MOS transistor MP20 is turned on when the received second enable signal is at a low potential, and the power supply voltage provided by the analog power supply is input to the second filter module 82 through the eleventh MOS transistor MP20. The second filter module 82 filters the power supply voltage to obtain the second power supply voltage, so that the filtered second power supply voltage is used to power the bias current generating circuit.

[0087] In some embodiments, Figure 3 As shown, the first filtering module 81 includes: a third capacitor C4 and a twelfth MOS transistor MN25.

[0088] The first end of the third capacitor C4 is connected to the second end of the first switch module 91 and the power supply voltage end, and the second end of the third capacitor C4 is connected to the negative voltage source; the gate of the twelfth MOS tube MN25 is connected to the first end of the third capacitor C4, and the drain of the twelfth MOS tube MN25 and the source of the twelfth MOS tube MN25 are both connected to the negative voltage source, wherein the twelfth MOS tube MN25 is an NMOS tube, and the twelfth MOS tube MN25 is a MOS capacitor, that is, the MOS capacitor used utilizes the structural characteristics of the MOS tube, uses the gate of the twelfth MOS tube MN25 as the upper plate, and connects the source, drain and substrate of the twelfth MOS tube MN25 as the lower plate, and the gate oxide between the gate and the channel is used as an insulating medium to form a MOS capacitor. Therefore, the MOS capacitor is used in the first filter module 81, which can provide a larger capacitance value under the same area, can save chip area to a great extent, and reduce costs.

[0089] In some embodiments, Figure 3 As shown, the second filtering module 82 includes: a second resistance unit 821 and a second capacitance unit 822 .

[0090] Among them, the first end of the second resistor unit 821 is connected to the second end of the second switch module 92, the second end of the second resistor unit 821 is connected to the first end of the second capacitor unit 822, the third end of the second resistor unit 821 is connected to the negative voltage source, the second end of the second capacitor unit 822 is connected to the power supply voltage end and the first end of the third capacitor C4, and the third end of the second capacitor unit 822 is connected to the negative voltage source. Therefore, the second filter module 82 basically filters the noise of the concerned frequency band through the RC filter structure composed of the second resistor unit 821 and the second capacitor unit 822, and greatly reduces the interference of the noise signal on the output voltage and bias current of the voltage stabilization circuit.

[0091] In some embodiments, Figure 3 As shown, the second resistance unit 821 includes: a thirteenth MOS transistor MP21, a fifth resistor R8 and a fourteenth MOS transistor MP22.

[0092] Among them, the drain of the thirteenth MOS tube MP21 is connected to the second end of the second switch module 92; the first end of the fifth resistor R8 is connected to the gate of the thirteenth MOS tube MP21, and the second end of the fifth resistor R8 is connected to the negative voltage source; the drain of the fourteenth MOS tube MP22 is connected to the source of the thirteenth MOS tube MP21, the gate of the fourteenth MOS tube MP22 is connected to the first end of the fifth resistor R8, and the source of the fourteenth MOS tube MP22 is connected to the first end of the second capacitor unit 822.

[0093] In some embodiments, as shown in FIG23 , the second capacitor unit 822 includes: a sixth resistor R9 , a fourth capacitor C5 , and a fifteenth MOS transistor MN20 .

[0094] Among them, the first end of the sixth resistor R9 is connected to the source of the fourteenth MOS transistor MP22, and the second end of the sixth resistor R9 is connected to the power supply voltage end and the first end of the third capacitor C4; the first end of the fourth capacitor C5 is connected to the first end of the sixth resistor R9, and the second end of the fourth capacitor C5 is connected to the negative voltage source; the gate of the fifteenth MOS transistor MN20 is connected to the first end of the fourth capacitor C5, and the source of the fifteenth MOS transistor MN20 and the drain of the fifteenth MOS transistor MN20 are both connected to the negative voltage source, wherein the fifteenth MOS transistor MN20 is an NMOS transistor, and the fifteenth MOS transistor MN20 is a MOS capacitor, that is, the MOS capacitor used utilizes the structural characteristics of the MOS transistor, uses the gate of the fifteenth MOS transistor MN20 as an upper plate, and connects the source, drain and substrate of the fifteenth MOS transistor MN20 as a lower plate, and the gate oxide between the gate and the channel is used as an insulating medium to form a MOS capacitor. Therefore, the use of the MOS capacitor in the second filtering module 82 can save chip area to a great extent and reduce costs.

[0095] Exemplarily, when the first enable signal PDA is at a high potential, the analog power supply VDD1SYS is required to provide VDDL1C, that is, when the first enable signal PDA is at a high potential, the second enable signal PDB is at a low potential. At this time, the filter structure 8 filters the analog power supply VDD1SYS to obtain VDDL1C. Figure 4As shown, PDA has the same logic as the power switch signal PowerDown of the power supply system, and PDB has the opposite logic to the power switch signal PowerDown of the power supply system. Therefore, the coupling noise of the digital power supply VDD1SYS is filtered through the thirteenth MOS tube MP21, the fourteenth MOS tube MP22, the fourth capacitor C5, the fifteenth MOS tube MN20, the sixth resistor R9, the third capacitor C4 and the twelfth MOS tube MN25. When the first enable signal PDA is flipped from a high potential to a low potential, VDDL1C is provided by VDDL, that is, when the first enable signal PDA is at a low potential, the filter structure 8 filters the first power supply voltage VDDL to obtain VDDL1C. At this time, the thirteenth MOS tube MP21, the fourteenth MOS tube MP22, the fourth capacitor C5, the fifteenth MOS tube MN20, the sixth resistor R9, the third capacitor C4 and the twelfth MOS tube MN25 filter the coupling noise of the digital power supply VDD1SYS. The fourteenth MOS tube MP22, the fifteenth MOS tube MN20, the twelfth MOS tube MN25, the sixth resistor R9, the fourth capacitor C5, and the third capacitor C4 filter the thermal noise generated by the eleventh MOS tube MP20 from being turned on to being turned off. The third capacitor C4 and the twelfth MOS tube MN25 are used to filter the high-frequency noise of the voltage VDDL1C, thereby realizing bidirectional noise filtering. Thus, when the analog power supply is powered, the analog power supply noise is filtered. When the first power supply voltage is powered, not only the first power supply voltage itself noise is filtered, but also the thermal noise of the analog power supply end switch is filtered. The filter structure 8 uses a MOS resistor, and uses the characteristic that the MOS tube can be equivalent to a resistor when working in the linear region, so that a larger resistance value can be provided under the same area, reducing the chip area and saving costs. Similarly, the filter structure 8 uses a MOS capacitor, so that a larger capacitance value can be provided under the same area. At the same time, the use of the MOS capacitor also achieves the purpose of reducing the chip area and saving costs.

[0096] A third aspect of the present invention provides a power supply system 1000, such as Figure 2 and Figure 5 As shown, the power supply system 1000 includes: a voltage stabilizing circuit 700, a bias current generating circuit 800 of the above embodiment, and a filtering circuit 900 of the above embodiment.

[0097] Among them, the voltage stabilizing circuit is used to convert the voltage of the analog power supply into a first power supply voltage in the power supply state; the bias current generating circuit 800 of the above embodiment and the filter circuit 900 of the above embodiment, the power supply voltage terminal of the bias current generating circuit 800 is connected to the output terminal of the filter circuit 900, and the first input terminal of the filter circuit 900 is connected to the output terminal of the voltage stabilizing circuit 700; wherein the filter circuit is used to filter the first power supply voltage in the power supply state to obtain a second power supply voltage, so that the second power supply voltage powers the bias current generating circuit.

[0098] In an embodiment, the voltage stabilizing circuit may be an LDO (Low Dropout Regulator). LDO is a core module of an on-chip power supply system, and is characterized by converting a high-voltage domain power supply voltage into a low-voltage domain power supply voltage, and has many advantages such as low cost, low power consumption, low noise, and strong power ripple suppression capability. Therefore, LDO is often used as an ideal choice for some high-performance, noise-sensitive analog or mixed analog and digital applications, and is widely used in the fields of the Internet of Things, biomedicine, portable devices, etc.

[0099] Specifically, the voltage stabilizing circuit converts the voltage VDDA of the analog power supply into the first power supply voltage VDDL under the power supply state, that is, when the power supply switch signal PowerDown of the power supply system is at a low potential, the voltage stabilizing circuit supplies power, and the voltage stabilizing circuit converts the high voltage provided by the analog power supply into a low voltage with a certain load capacity and a temperature coefficient approximately zero, and when the power supply switch signal PowerDown is at a low potential, the first power supply voltage VDDL output by the voltage stabilizing circuit is input to the filter structure 8 through the first switch module 91, and the filter structure 8 filters the first power supply voltage to obtain the second power supply voltage, so that the filtered second power supply voltage is used to power the bias current generating circuit. Therefore, in the present application, the bias current generating module 1 uses the filtered first power supply voltage as the power supply voltage to form a self-biased structure, and the voltage stabilizing circuit uses a current source for biasing, reduces the correlation of the current source with the analog power supply voltage, improves the power supply ripple suppression capability, avoids the bias current generating circuit from being disturbed by the fluctuation of the analog power supply, and improves the PSR. At the same time, the first power supply voltage is bidirectionally filtered and coupled noise is filtered through the filter structure 8, thereby reducing the influence of noise on the generated bias current.

[0100] According to the power supply system of the embodiment of the present invention, when the power supply system is in the power supply state, the voltage stabilizing circuit converts the voltage of the analog power supply into a first power supply voltage, and the filtering structure 8 filters the first power supply voltage and then supplies power to the bias current generating circuit, thereby reducing the correlation of the current source with the analog power supply voltage, improving the power supply ripple suppression capability, avoiding the bias current generating circuit from being disturbed by the fluctuation of the analog power supply, and improving the PSR of the bias current source. At the same time, the first power supply voltage is bidirectionally filtered to couple the noise through the filtering structure 8, thereby reducing the influence of the noise on the generated bias current.

[0101] In some embodiments, the second input terminal of the filter circuit 900 is connected to the analog power supply, and the filter circuit is also used to filter the voltage of the analog power supply in the non-powered state to obtain the second power supply voltage. That is to say, when the power supply switch signal PowerDown of the power supply system is at a high potential, the power supply voltage provided by the analog power supply is input to the filter structure 8 through the second switch module 92, and the filter structure 8 filters the voltage of the analog power supply to obtain the second power supply voltage, so that the filtered second power supply voltage is used to power the bias current generating circuit, thereby realizing the analog power supply to power the bias current generating circuit.

[0102] In some embodiments, Figure 1 and Figure 2 As shown, the voltage stabilizing circuit 700 includes: a first-stage operational amplifier structure 4 and a second-stage operational amplifier structure 5 .

[0103] Among them, the power supply terminal of the first-stage operational amplifier structure 4 is suitable for inputting the bias current provided by the bias current generating circuit, and the input terminal of the first-stage operational amplifier structure 4 is suitable for inputting the bandgap reference voltage, and is used to generate an operational amplifier signal according to the bandgap reference voltage; the first input terminal of the second-stage operational amplifier structure 5 is connected to a circuit suitable for connecting an analog power supply, the second input terminal of the second-stage operational amplifier structure 5 is connected to the output terminal of the first-stage operational amplifier structure 4, and the output terminal of the second-stage operational amplifier structure 5 is connected to the first input terminal of the filter circuit 900, and is used to generate a first power supply voltage according to the operational amplifier signal.

[0104] Specifically, the first-stage operational amplifier structure 4 generates an operational amplifier signal according to the bandgap reference voltage, and the second-stage operational amplifier structure 5 converts the voltage VDDA of the analog power supply into the first power supply voltage VDDL through the operational amplifier signal, that is, the voltage stabilizing circuit converts the high voltage provided by the analog power supply into a low voltage with a certain load capacity and a temperature coefficient of approximately zero, so as to be used by the bias current generating circuit. Therefore, the voltage stabilizing circuit in the present application adopts a two-stage operational amplifier structure, and the first stage is a symmetrical voltage stabilizing circuit, which has better symmetry and matching than other voltage stabilizing circuits, and provides better offset and CMRR (common mode rejection) ratio, common mode rejection ratio) characteristics, even in the case of low gain of the operational amplifier structure, it can provide good PSR, reduce the correlation of the current source to the analog power supply voltage, improve the power supply ripple suppression capability, and avoid the bias current generating circuit being disturbed by the fluctuation of the analog power supply. At the same time, based on the above design, the bias current generating circuit and the voltage stabilizing circuit form a self-bias loop, and the bias current of the voltage stabilizing circuit is derived from the bias current of the bias current generating circuit mirror, thereby reducing the correlation of the voltage stabilizing circuit to the analog power supply voltage, avoiding the voltage stabilizing circuit being disturbed by the fluctuation of the analog power supply, and improving the PSR of the voltage stabilizing circuit.

[0105] In some embodiments, Figure 2As shown, the first-stage operational amplifier structure 4 includes: a power supply unit 41 and an operational amplifier unit 42 .

[0106] The first input terminal of the power supply unit 41 is suitable for connecting an analog power supply, and the second input terminal of the power supply unit 41 is suitable for inputting a bias current, which is used to generate an operational amplifier power supply current according to the bias current; the power supply terminal of the operational amplifier unit 42 is connected to the output terminal of the power supply unit 41, and the input terminal of the operational amplifier unit 42 is suitable for inputting a bandgap reference voltage, which is used to generate an operational amplifier signal according to the bandgap reference voltage. The bandgap reference voltage is a reference voltage with a temperature coefficient approximately equal to zero.

[0107] Specifically, the power supply unit 41 generates an op amp power supply current according to the bias current provided by the bias current generating circuit, and provides the op amp power supply current to the op amp unit 42, so that the op amp unit 42 can work normally according to the op amp power supply current. The op amp unit 42 generates an op amp signal according to the bandgap reference voltage, so as to convert the voltage VDDA of the analog power supply into the first power supply voltage VDDL through the op amp signal, that is, the voltage stabilizing circuit converts the high voltage voltage provided by the analog power supply into a low voltage voltage with a certain load capacity and a temperature coefficient of approximately zero, for use by the bias current generating circuit. Therefore, the first-stage op amp structure 4 in the present application is a symmetrical voltage stabilizing circuit, which has better symmetry and matching than other voltage stabilizing circuits, provides better offset and CMRR characteristics, and can provide good PSR even in the case of low gain of the op amp structure. At the same time, the bias current of the voltage stabilizing circuit is derived from the bias current of the bias current generating circuit mirror, which reduces the correlation of the current source to the analog power supply voltage.

[0108] In some embodiments, Figure 2 As shown, the power supply unit 41 includes: a current mirror unit 411 and a current source subunit 412 .

[0109] Among them, the input end of the current mirror unit 411 is suitable for inputting a bias current for mirroring the bias current; the first end of the current source subunit 412 is connected to the output end of the current mirror unit 411, the second end of the current source subunit 412 is connected to the power supply end of the operational amplifier unit 42, and the third end of the current source subunit 412 is suitable for connecting an analog power supply.

[0110] Specifically, the current mirror unit 411 of the power supply mirrors the bias current provided by the bias current generating circuit to provide a bias current for the current source subunit 412, so that the current source subunit 412 generates an operational amplifier power supply current according to the bias current. In addition, the bias current of the voltage stabilizing circuit is derived from the bias current mirrored by the bias current generating circuit, thereby reducing the correlation of the current source with the analog power supply voltage.

[0111] In some embodiments, Figure 2As shown, the current mirror unit 411 includes a sixteenth MOS transistor MN2 and a seventeenth MOS transistor MN6.

[0112] Among them, the gate of the sixteenth MOS transistor MN2 is suitable for inputting bias current, and the source of the sixteenth MOS transistor MN2 is connected to the negative voltage source; the gate of the seventeenth MOS transistor MN6 is suitable for inputting bias current, the source of the seventeenth MOS transistor MN6 is connected to the drain of the sixteenth MOS transistor MN2, and the drain of the seventeenth MOS transistor MN6 is connected to the first end of the current source subunit 412, wherein the sixteenth MOS transistor MN2 and the seventeenth MOS transistor MN6 are NMOS transistors. Specifically, the sixteenth MOS transistor MN2 and the seventeenth MOS transistor MN6 form a current mirror to copy the input bias current to the current source subunit 412, so that the current source subunit 412 generates an op amp power supply current according to the bias current. At the same time, the bias current of the voltage stabilizing circuit is derived from the bias current of the bias current generation circuit mirror, reducing the correlation of the current source to the analog power supply voltage.

[0113] In some embodiments, Figure 2 As shown, the current source sub-unit 412 includes an eighteenth MOS transistor MP10, a nineteenth MOS transistor MP11, a twentieth MOS transistor MP6 and a twenty-first MOS transistor MP7.

[0114] The source of the eighteenth MOS tube MP10 is connected to the drain of the seventeenth MOS tube MN6 and the gate of the eighteenth MOS tube MP10, the gate of the eighteenth MOS tube MP10 is connected to the gate of the nineteenth MOS tube MP11 to provide a bias for the nineteenth MOS tube MP11, and the source of the nineteenth MOS tube MP11 is connected to the power supply terminal of the operational amplifier unit 42; the source of the twentieth MOS tube MP6 is connected to the drain of the eighteenth MOS tube MP10 and the gate of the twentieth MOS tube MP6, the drain of the twentieth MOS tube MP6 is suitable for connecting to the analog power supply, and the gate of the twentieth MOS tube MP6 is connected to the twentieth MOS tube MP6. The gate of the first MOS tube MP7 is connected to provide bias for the twenty-first MOS tube MP7, the source of the twenty-first MOS tube MP7 is connected to the drain of the nineteenth MOS tube MP11, and the drain of the twenty-first MOS tube MP7 is suitable for connecting an analog power supply, wherein the eighteenth MOS tube MP10, the nineteenth MOS tube MP11, the twentieth MOS tube MP6, and the twenty-first MOS tube MP7 are PMOS tubes, and the eighteenth MOS tube MP10, the nineteenth MOS tube MP11, the twentieth MOS tube MP6, and the twenty-first MOS tube MP7 are connected in a common source and common gate manner to form a common source and common gate current mirror. Based on this, the common source and common gate current mirror is used to provide the current required for normal operation of the operational amplifier unit 42, that is, to provide the operational amplifier unit 42 with an operational amplifier power supply current, thereby further improving the accuracy of PSR and bias current replication.

[0115] In some embodiments, Figure 2 As shown, the operational amplifier unit 42 includes a twenty-second MOS transistor MP8, a twenty-third MOS transistor MP9, a twenty-fourth MOS transistor MN8 and a twenty-fifth MOS transistor MN9.

[0116] The gate of the twenty-second MOS tube MP8 is suitable for inputting a bandgap reference voltage, the drain of the twenty-second MOS tube MP8 is connected to the drain of the twenty-third MOS tube MP9, the drain of the twenty-third MOS tube MP9 is connected to the drain of the twenty-second MOS tube MP8 to serve as the power supply terminal of the operational amplifier unit 42, and the power supply terminal is connected to the source of the nineteenth MOS tube MP11, the twenty-second MOS tube MP8 and the twenty-third MOS tube MP9 are used to generate a differential signal, wherein the twenty-second MOS tube MP8 and the twenty-third MOS tube MP9 are PMOS tubes, and the twenty-second MOS tube MP8 The twenty-third MOS tube MP9 forms an input differential pair; the drain of the twenty-fourth MOS tube MN8 is connected to the gate of the twenty-fourth MOS tube MN8 and the source of the twenty-second MOS tube MP8, the source of the twenty-fourth MOS tube MN8 is connected to a negative voltage source, the drain of the twenty-fifth MOS tube MN9 is connected to the source of the twenty-third MOS tube MP9 and the gate of the twenty-fifth MOS tube MN9, the source of the twenty-fifth MOS tube MN9 is connected to the negative voltage source, and is used to convert the differential signal into an output current. The twenty-fourth MOS tube MN8 and the twenty-fifth MOS tube MN9 are NMOS tubes.

[0117] Specifically, the twenty-second MOS transistor MP8 and the twenty-third MOS transistor MP9 serve as a pair of input differential pairs to generate an operational amplifier signal according to the bandgap reference voltage, that is, the bandgap reference voltage is provided to the gate of the twenty-second MOS transistor MP8, so as to provide a voltage reference point for the operational amplifier unit 42 that does not significantly change with temperature, power supply voltage and process changes, thereby improving the stability and reliability of the operational amplifier unit 42. On this basis, the current source subunit 412 outputs the operational amplifier power supply current to the drain of the twenty-third MOS transistor MP9 and the drain of the twenty-second MOS transistor MP8, that is, the nineteenth MOS transistor MP11 outputs the operational amplifier power supply current to the twenty-third MOS transistor MP9 and the twenty-second MOS transistor MP8, the twenty-second MOS transistor MP8 and the twenty-third MOS transistor MP9 perform operational amplifier processing on the operational amplifier power supply current to obtain a differential signal, and the twenty-fourth MOS transistor MN8 and the twenty-fifth MOS transistor MN9 convert the differential signal into an output current, that is, the twenty-fourth MOS transistor MN8 and the twenty-fifth MOS transistor MN9 gain the differential signal by providing a current factor and convert it into an output current.

[0118] Therefore, the power supply system in the present application no longer requires an operational amplifier type voltage-to-current structure to improve the low-frequency PSR, but only needs to use a simple N-tube source follower to achieve voltage-to-current conversion, using MOS resistors and MOS capacitors, saving chip area, and reducing costs and power consumption.

[0119] In some embodiments, Figure 2 As shown, the operational amplifier unit 42 further includes: a seventh resistor R1 and an eighth resistor R2.

[0120] Among them, the first end of the seventh resistor R1 is connected to the output end of the second-stage operational amplifier structure 5, the second end of the seventh resistor R1 is connected to the first end of the eighth resistor R2, the second end of the eighth resistor R2 is connected to the negative voltage source, a first node is provided between the second end of the seventh resistor R1 and the first end of the eighth resistor R2, and the first node is connected to the gate of the twenty-third MOS tube MP9 to form a negative feedback loop, that is, the gate of the twenty-third MOS tube MP9 is connected to the negative feedback network to form a negative feedback loop, the first end of the seventh resistor R1 is connected to the output end of the second-stage operational amplifier structure 5, and the seventh resistor R1 and the eighth resistor R2 are used to divide the first power supply voltage VDDL and input it into the gate of the twenty-third MOS tube MP9 as a gate voltage.

[0121] In some embodiments, Figure 2 As shown, the operational amplifier unit 42 further includes a twenty-sixth MOS transistor MN7 and a twenty-seventh MOS transistor MN10.

[0122] Among them, the gate of the twenty-sixth MOS transistor MN7 is connected to the gate of the twenty-fourth MOS transistor MN8 and the drain of the twenty-fourth MOS transistor MN8, and the source of the twenty-sixth MOS transistor MN7 is connected to the negative voltage source, so as to improve the output impedance; the gate of the twenty-seventh MOS transistor MN10 is connected to the gate of the twenty-fifth MOS transistor MN9 and the drain of the twenty-fifth MOS transistor MN9, and the source of the twenty-seventh MOS transistor MN10 is connected to the negative voltage source, and the drain of the twenty-seventh MOS transistor MN10 is connected to the output end of the second-stage operational amplifier structure 5 through the fifth capacitor C2, so as to improve the output impedance, and the fifth capacitor C2 is used as a compensation capacitor, and the fifth capacitor C2 is a common-source and common-gate compensation capacitor connected to the common-source and common-gate transistor composed of the twenty-third MOS transistor MP9 and the twenty-seventh MOS transistor MN10, so as to ensure that the negative feedback loop has a certain phase margin and is in a stable state. The twenty-sixth MOS transistor MN7 and the twenty-seventh MOS transistor MN10 are NMOS transistors, and the twenty-fourth MOS transistor MN8 and the twenty-fifth MOS transistor MN9, the twenty-sixth MOS transistor MN7 and the twenty-seventh MOS transistor MN10 are completely symmetrical current mirror structures, providing a current factor to gain the differential signal.

[0123] In some embodiments, Figure 2As shown, the operational amplifier unit 42 further includes: a twenty-eighth MOS transistor MN11 and a twenty-ninth MOS transistor MN12.

[0124] The gate of the twenty-eighth MOS tube MN11 is connected to the gate of the twenty-ninth MOS tube MN12, the source of the twenty-eighth MOS tube MN11 is connected to the drain of the twenty-sixth MOS tube MN7, the gate of the twenty-eighth MOS tube MN11 and the gate of the twenty-ninth MOS tube MN12 are suitable for accessing a bias voltage, the source of the twenty-ninth MOS tube MN12 is connected to the drain of the twenty-seventh MOS tube MN10, so as to improve the output gain to obtain an operational amplifier signal, wherein the twenty-eighth MOS tube MN11 and the twenty-ninth MOS tube MN12 are NMOS tubes, the twenty-eighth MOS tube MN11 and the twenty-ninth MOS tube MN12 are common-source and common-gate tubes, and the output gain of the differential signal generated by the twenty-second MOS tube MP8 and the twenty-third MOS tube MP9 is improved to obtain an operational amplifier signal, thereby further improving the gain.

[0125] In some embodiments, Figure 2 As shown, the second-stage operational amplifier structure 5 includes: an output conversion unit 51 and an output unit 52 .

[0126] The output conversion unit 51 is connected to the drain of the twenty-eighth MOS transistor MN11 and the drain of the twenty-ninth MOS transistor MN12, and is used to convert the output signal of the twenty-eighth MOS transistor MN11 and the output signal of the twenty-ninth MOS transistor MN12 into an operational amplifier signal output; the input end of the output unit 52 is connected to the output end of the output conversion unit 51, and the output end of the output unit 52 is connected to the first input end of the filter circuit 900 to output the first power supply voltage VDDL. The twenty-eighth MOS transistor MN11 and the twenty-ninth MOS transistor MN12 increase the output gain of the differential signal to obtain an output signal, and convert the output signal of the twenty-eighth MOS transistor MN11 and the output signal of the twenty-ninth MOS transistor MN12 into an operational amplifier signal output, so as to convert the voltage VDDA of the analog power supply into the first power supply voltage VDDL through the operational amplifier signal, and then output the first power supply voltage VDDL through the output unit 52, thereby, the voltage stabilizing circuit converts the high voltage provided by the analog power supply into a low voltage with a certain load capacity and a temperature coefficient of approximately zero, so as to be used by the bias current generating circuit.

[0127] In some embodiments, Figure 2 As shown, the output conversion unit 51 includes a 30th MOS transistor MP12 and a 31st MOS transistor MP13.

[0128] Among them, the source of the 30th MOS transistor MP12 is connected to the drain of the 28th MOS transistor MN11 and the gate of the 30th MOS transistor MP12, the gate of the 30th MOS transistor MP12 is connected to the gate of the 31st MOS transistor MP13, the drain of the 30th MOS transistor MP12 is suitable for connecting to the analog power supply, the drain of the 31st MOS transistor MP13 is suitable for connecting to the analog power supply, and the source of the 31st MOS transistor MP13 is connected to the drain of the 29th MOS transistor MN12 and the input end of the output unit 52. The 30th MOS transistor MP12 and the 31st MOS transistor MP13 are current mirrors to realize single-ended output.

[0129] In some embodiments, Figure 2 As shown, the output unit 52 includes: a thirty-second MOS transistor MP14.

[0130] The gate of the thirty-second MOS transistor MP14 is connected to the source of the thirty-first MOS transistor MP13 and the drain of the twenty-ninth MOS transistor MN12, the drain of the thirty-second MOS transistor MP14 is suitable for connecting to the analog power supply, and the source of the thirty-second MOS transistor MP14 is connected to the first end of the seventh resistor R1 and outputs the first power supply voltage VDDL. The thirty-second MOS transistor MP14 can be a PMOS transistor, and the thirty-second MOS transistor MP14 provides current load capacity as a power transistor.

[0131] In some embodiments, Figure 2 As shown, the voltage stabilizing circuit 700 further includes: a compensation module 6 .

[0132] The first end of the compensation module 6 is suitable for connecting to the analog power supply, and the second end of the compensation module 6 is connected to the gate of the 32nd MOS transistor MP14, the source of the 31st MOS transistor MP13, and the drain of the 29th MOS transistor MN12 for zero point compensation. That is, in the voltage stabilizing circuit 700, a zero point is added between the 32nd MOS transistor MP14, the 31st MOS transistor MP13, and the 29th MOS transistor MN12 to ensure that the loop has a certain phase margin and is in a stable state.

[0133] In some embodiments, Figure 2 As shown, the compensation module 6 includes: a ninth resistor R0 and a sixth capacitor C0.

[0134] The first end of the ninth resistor R0 is suitable for connecting to the analog power supply, the second end of the ninth resistor R0 is connected to the first end of the sixth capacitor C0, and the second end of the sixth capacitor C0 is connected to the gate of the thirty-second MOS transistor MP14, the source of the thirty-first MOS transistor MP13, and the drain of the twenty-ninth MOS transistor MN12. Therefore, by setting the ninth resistor R0 and the sixth capacitor C0 between the thirty-second MOS transistor MP14, the thirty-first MOS transistor MP13, and the twenty-ninth MOS transistor MN12 as zero point compensation, it is ensured that the loop has a certain phase margin and is in a stable state.

[0135] In some embodiments, Figure 2 As shown, the power supply system 1000 further includes: a starting circuit 7 .

[0136] Among them, the start-up circuit 7 is connected to the voltage stabilizing circuit 700 and the bias current generating circuit 800. The start-up circuit 7 is used to provide the required bias current to the voltage stabilizing circuit to start the voltage stabilizing circuit, and the voltage stabilizing circuit can generate the operational amplifier power supply current. Therefore, the start-up circuit 7 required for the self-biasing structure is constructed in the present application, thereby avoiding the influence of the degenerate point in the self-biasing structure on the circuit establishment state, so that the entire circuit is established in a normal working state.

[0137] In some embodiments, Figure 2 As shown, the startup circuit 7 includes: a first power supply module 71 , a second power supply module 72 and a current mirror module 73 .

[0138] Among them, the first power supply module 71 is used to provide a first bias current in response to the second enable signal flipping from a low potential to a high potential, and the second enable signal is logically opposite to the power supply switch signal of the power supply system; the input end of the second power supply module 72 is connected to the bias voltage end of the bias current generating circuit 800 and the output end of the voltage stabilizing circuit 700, and is used to control the first power supply module 71 to shut down and provide a second bias current when the bias voltage at the bias voltage end reaches the voltage threshold and the voltage stabilizing signal output by the voltage stabilizing circuit reaches the voltage stabilizing threshold; the current mirror module 73 is respectively connected to the first power supply module 71 and the second power supply module 72, and is used to mirror the first bias current or the second bias current to the output end of the voltage stabilizing circuit.

[0139] Specifically, when the second enable signal flips from a low potential to a high potential, the first power supply voltage VDDL output by the voltage stabilizing circuit powers the bias current generating circuit 800, and the first power supply module 71 provides a first bias current in response to the second enable signal flipping from a low potential to a high potential, and outputs the first bias current to the current mirror module 73. The second power supply module 72 controls the first power supply module 71 to shut down and provide a second bias current when the bias voltage at the bias voltage end reaches the voltage threshold and the voltage stabilizing signal output by the voltage stabilizing circuit reaches the voltage stabilization threshold, and outputs the second bias current to the current mirror module 73. The current mirror module 73 mirrors the first bias current or the second bias current to the output end of the voltage stabilizing circuit, thereby ensuring that the voltage stabilizing circuit can start normally.

[0140] In some embodiments, Figure 2 As shown, the first power supply module 71 includes: a thirty-third MOS tube MP3 and a series inverse ratio tube structure 711.

[0141] Among them, the drain of the thirty-third MOS tube MP3 is suitable for connecting to the analog power supply, and the source of the thirty-third MOS tube MP3 is connected to the current mirror module 73; the first end of the series inverse ratio tube structure 711 is connected to the gate of the thirty-third MOS tube MP3, the second end of the series inverse ratio tube structure 711 is connected to the negative voltage source, and the control end of the series inverse ratio tube structure 711 is suitable for inputting the second enable signal; when the second enable signal is flipped from a low potential to a high potential, the series inverse ratio tube structure 711 is turned on and the thirty-third MOS tube MP3 is turned on to provide a first bias current.

[0142] Specifically, when the second enable signal PDB is flipped from a low potential to a high potential, the series inverted ratio structure 711 is turned on to pull down the gate voltage VSPB of the thirty-third MOS tube MP3, so that the thirty-third MOS tube MP3 is turned on. At this time, the thirty-third MOS tube MP3 provides a first bias current, and the first bias current is output to the current mirror module 73 through the IB4LDO pin. The current mirror module 73 mirrors the first bias current to the output end of the voltage stabilizing circuit, thereby ensuring that the voltage stabilizing circuit can start normally.

[0143] In some embodiments, Figure 2 As shown, the series inverse ratio transistor structure 711 includes a thirty-fourth MOS transistor MN3, a thirty-fifth MOS transistor MN22 and a thirty-sixth MOS transistor MN23.

[0144] The drain of the thirty-fourth MOS transistor MN3 is connected to the gate of the thirty-third MOS transistor MP3, and the gate of the thirty-fourth MOS transistor MN3 is suitable for receiving the second enable signal; the drain of the thirty-fifth MOS transistor MN22 is connected to the source of the thirty-fourth MOS transistor MN3, and the gate of the thirty-fifth MOS transistor MN22 is suitable for receiving the second enable signal; the drain of the thirty-sixth MOS transistor MN23 is connected to the source of the thirty-fifth MOS transistor MN22, and the gate of the thirty-sixth MOS transistor MN23 is suitable for receiving the second enable signal, and the source of the thirty-sixth MOS transistor MN23 is connected to the negative voltage source. The thirty-fourth MOS transistor MN3, the thirty-fifth MOS transistor MN22, and the thirty-sixth MOS transistor MN23 are NMOS transistors. That is to say, when the second enable signal PDB is flipped from a low potential to a high potential, the thirty-fourth MOS tube MN3, the thirty-fifth MOS tube MN22 and the thirty-sixth MOS tube MN23 are turned on to pull down the gate voltage VSPB of the thirty-third MOS tube MP3, so that the thirty-third MOS tube MP3 is turned on. At this time, the first bias current is temporarily provided by the thirty-third MOS tube MP3, and the first bias current is output to the current mirror module 73 through the IB4LDO pin. The current mirror module 73 mirrors the first bias current to the output end of the voltage stabilizing circuit, thereby ensuring that the voltage stabilizing circuit can be started normally.

[0145] In some embodiments, Figure 2 As shown, the second power supply module 72 includes: a thirty-seventh MOS transistor MN0 and a thirty-eighth MOS transistor MN4.

[0146] Among them, the gate of the thirty-seventh MOS transistor MN0 is connected to the bias voltage terminal, the source of the thirty-seventh MOS transistor MN0 is connected to the negative voltage source, and is used to be turned on when the bias voltage reaches the voltage threshold; the gate of the thirty-eighth MOS transistor MN4 is connected to the output end of the voltage stabilization circuit, the source of the thirty-eighth MOS transistor MN4 is connected to the drain of the thirty-seventh MOS transistor MN0, and the drain of the thirty-eighth MOS transistor MN4 is connected to the current mirror module 73, and is used to be turned on when the voltage stabilization signal output by the voltage stabilization circuit reaches the voltage stabilization threshold. Among them, the voltage threshold can be understood as

[0147] Specifically, when the thirty-third MOS tube MP3 temporarily provides the first bias current, the voltage stabilization signal VDDL and the bias voltage VBN1 output by the voltage stabilization circuit begin to be established, when the bias voltage VBN1 reaches the voltage threshold, the thirty-seventh MOS tube MN0 is turned on, and when the voltage stabilization signal VDDL reaches the voltage stabilization threshold, the thirty-eighth MOS tube MN4 is turned on, the thirty-seventh MOS tube MN0 provides the second bias current, and outputs the second bias current to the current mirror module 73, and the current mirror module 73 mirrors the second bias current to the output end of the voltage stabilization circuit, thereby ensuring that the voltage stabilization circuit can start normally.

[0148] In some embodiments, Figure 2 As shown, the current mirror module 73 includes: a first current mirror unit 731 .

[0149] Among them, the first end of the first current mirror unit 731 is connected to the source of the thirty-third MOS tube MP3, the second end of the first current mirror unit 731 is connected to the negative voltage source, and the third end of the first current mirror unit 731 is connected to the input end of the voltage stabilizing circuit 700 to mirror the first bias current to the voltage stabilizing circuit 700, that is, the first current mirror unit 731 copies the first bias current mirror to the current mirror unit 411 of the voltage stabilizing circuit, thereby ensuring that the voltage stabilizing circuit can start normally.

[0150] In some embodiments, Figure 2 As shown, the current mirror module 73 further includes: a second current mirror unit 732 .

[0151] Among them, the first end of the second current mirror unit 732 is connected to the drain of the thirty-eighth MOS transistor MN4, the second end of the second current mirror unit 732 is connected to the gate of the thirty-third MOS transistor MP3 and the first end of the series inverse ratio transistor structure 711, so as to control the thirty-third MOS transistor MP3 to be turned off when the thirty-eighth MOS transistor MN4 is turned on, and the third end of the second current mirror unit 732 is connected to the first end of the first current mirror unit 731, so as to mirror the second bias current to the voltage stabilizing circuit. That is to say, when the bias voltage VBN1 reaches the voltage threshold, the thirty-seventh MOS transistor MN0 is turned on, and when the voltage stabilizing signal VDDL reaches the voltage stabilizing threshold, the thirty-eighth MOS transistor MN4 is turned on, and when the thirty-eighth MOS transistor MN4 is turned on, the thirty-third MOS transistor MP3 is turned off to turn off the first bias current, at which time the second bias current is provided by the thirty-seventh MOS transistor MN0, and the second bias current is output to the second current mirror unit 732, and the second current mirror unit 732 mirrors the second bias current to the voltage stabilizing circuit, thereby ensuring that the voltage stabilizing circuit can be started normally.

[0152] In some embodiments, the first current mirror unit 731 includes a thirty-ninth MOS transistor MN5 and a fortieth MOS transistor MN1.

[0153] Among them, the drain of the 39th MOS transistor MN5 is connected to the third end of the second current mirror unit 732, the gate of the 39th MOS transistor MN5, the gate of the 28th MOS transistor MN11 in the voltage stabilizing circuit 700, and the gate of the 29th MOS transistor MN12 in the voltage stabilizing circuit 700 to provide a bias voltage, and the gate of the 39th MOS transistor MN5 is connected to the gate of the 17th MOS transistor MN6 in the voltage stabilizing circuit 700 to provide a bias current; the drain of the 40th MOS transistor MN1 is connected to the source of the 39th MOS transistor MN5 and the gate of the 40th MOS transistor MN1, the gate of the 40th MOS transistor MN1 is connected to the gate of the 16th MOS transistor MN2 in the voltage stabilizing circuit 700, and the source of the 40th MOS transistor MN1 is connected to the negative voltage source. Therefore, the 39th MOS transistor MN5 and the 40th MOS transistor MN1 mirror the first bias current to the current mirror unit 411 of the voltage stabilizing circuit, thereby ensuring that the voltage stabilizing circuit can be started normally.

[0154] In some embodiments, Figure 2 As shown, the second current mirror unit 732 includes: a forty-first MOS tube MP4, a forty-second MOS tube MP5, a forty-third MOS tube MP0 and a forty-fourth MOS tube MP1.

[0155] Among them, the source of the forty-first MOS tube MP4 is connected to the gate of the forty-first MOS tube MP4 and the drain of the thirty-seventh MOS tube MN0; the gate of the forty-second MOS tube MP5 is connected to the gate of the forty-first MOS tube MP4 and the source of the forty-first MOS tube MP4, and the source of the forty-second MOS tube MP5 is connected to the drain of the thirty-ninth MOS tube MN5; the source of the forty-third MOS tube MP0 is connected to the gate of the forty-third MOS tube MP0 and the drain of the forty-first MOS tube MP4, and the drain of the forty-third MOS tube MP0 is suitable for connecting to an analog power supply; the gate of the forty-fourth MOS tube MP1 is connected to the gate of the forty-third MOS tube MP0 and the source of the forty-third MOS tube MP0, the source of the forty-fourth MOS tube MP1 is connected to the drain of the forty-second MOS tube MP5, and the drain of the forty-fourth MOS tube MP1 is suitable for connecting to an analog power supply. Among them, the forty-first MOS tube MP4, the forty-second MOS tube MP5, the forty-third MOS tube MP0 and the forty-fourth MOS tube MP1 are PMOS tubes, and the forty-first MOS tube MP4, the forty-second MOS tube MP5, the forty-third MOS tube MP0 and the forty-fourth MOS tube MP1 form a common source and common gate current mirror through a common source and common gate connection mode, so as to copy the second bias current mirror image to the thirty-ninth MOS tube MN5 and the fortieth MOS tube MN1 through the common source and common gate current mirror, and the thirty-ninth MOS tube MN5 and the fortieth MOS tube MN1 provide the second bias current for the current mirror unit 411 of the voltage stabilizing circuit, thereby ensuring that the voltage stabilizing circuit can be started normally.

[0156] In some embodiments, Figure 2 As shown, the second current mirror unit 732 further includes: a forty-fifth MOS tube MP2.

[0157] Among them, the gate of the forty-fifth MOS tube MP2 is connected to the gate of the forty-third MOS tube MP0, the source of the forty-third MOS tube MP0, and the drain of the forty-first MOS tube MP4, and the source of the forty-fifth MOS tube MP2 is connected to the gate of the thirty-third MOS tube MP3 and the drain of the thirty-fourth MOS tube MN3, so as to control the thirty-third MOS tube MP3 to be turned off to turn off the first bias current when it is turned on.

[0158] Specifically, when the thirty-third MOS tube MP3 temporarily provides the first bias current, the voltage stabilization signal VDDL and the bias voltage VBN1 output by the voltage stabilization circuit begin to be established, when the bias voltage VBN1 reaches the voltage threshold, the thirty-seventh MOS tube MN0 is turned on, and when the voltage stabilization signal VDDL reaches the voltage stabilization threshold, the thirty-eighth MOS tube MN4 is turned on, the thirty-seventh MOS tube MN0 and the thirty-eighth MOS tube MN4 are turned on to pull down the gate potential of the forty-fifth MOS tube MP2 to make it turned on, because the drain of the forty-fifth MOS tube MP2 has a voltage-high pull-up capability much greater than the pull-down capability of the series inverse ratio tubes, the thirty-fourth MOS tube MN3, the thirty-fifth MOS tube MN22, and the thirty-sixth MOS tube MN23, the gate voltage VSPB of the thirty-third MOS tube MP3 is pulled to a high potential, and the thirty-third MOS tube MP3 is turned off to turn off the first bias current, and at this time the thirty-seventh MOS tube MN0 starts to provide the second bias current.

[0159] In some embodiments, Figure 2 As shown, the start-up circuit 7 further includes: two forty-sixth MOS transistors MP23.

[0160] Among them, the drain of each forty-sixth MOS tube MP23 is suitable for connecting to the analog power supply, the gate of each forty-sixth MOS tube MP23 is used to receive the second enable signal, and the sources of the two forty-sixth MOS tubes MP23 are respectively connected to the gate of the thirty-third MOS tube MP3 and the gate of the forty-fifth MOS tube MP2, and are used to pull up the gate of the thirty-third MOS tube MP3 and the gate of the forty-fifth MOS tube MP2 when the power supply switch signal of the power supply system is a closing signal.

[0161] Specifically, when the power supply switch signal of the power supply system is a shutdown signal, wherein the shutdown signal is a high potential, the second enable signal received by the gate of each forty-sixth MOS tube MP23 is a low potential, and the gate voltage VSPB of the thirty-third MOS tube MP3 and the gate voltage VBP of the forty-fifth MOS tube MP2 are pulled up. At this time, the thirty-third MOS tube MP3 and the forty-fifth MOS tube MP2 are turned off to turn off the first bias current.

[0162] In some embodiments, Figure 2 As shown, the start-up circuit 7 further includes: four forty-seventh MOS transistors MN24.

[0163] Among them, the source of each forty-seventh MOS tube MN24 is connected to the negative voltage source, the gate of each forty-seventh MOS tube MN24 is used to receive the first enable signal, and the drains of the four forty-seventh MOS tubes MN24 are respectively connected to the bias voltage terminal, the gate of the fourteenth MOS tube MP22 in the bias current generating circuit 800, the gate of the twenty-second MOS tube MP8 in the voltage stabilizing circuit 700, and the output end of the voltage stabilizing circuit 700, so as to pull down the bias voltage terminal, the gate of the fourteenth MOS tube MP22, the gate of the twenty-second MOS tube MP8, and the output end of the voltage stabilizing circuit when the power supply switch signal is a closing signal.

[0164] Specifically, when the power switch signal is a shutdown signal, the first enable signal received by the gate of each forty-seventh MOS tube MN24 is a high potential, so as to pull down the bias voltage terminal, the gate of the fourteenth MOS tube MP22, the gate of the twenty-second MOS tube MP8 and the output terminal of the voltage stabilizing circuit 700, that is, to pull down VDDL, VREF1, VREF2 and VBN1.

[0165] In some embodiments, Figure 2 As shown, the power supply system 1000 further includes: an RC filter circuit 94 .

[0166] Among them, the first end of the RC filter circuit is suitable for connecting to the reference voltage source, the second end of the RC filter circuit is connected to the input end of the first-stage operational amplifier structure 4, and the RC filter circuit is used to output the filtered bandgap reference voltage VREF1 according to the reference voltage VREF of the reference voltage source. The RC filter circuit is used at the input end of the bandgap reference voltage, which basically filters the noise of the frequency band of concern and greatly reduces the interference of the noise signal on the power supply voltage and bias current output by the voltage stabilization circuit.

[0167] A fourth aspect of the present invention provides an electronic device, such as Figure 6 As shown, the electronic device 2000 includes the power supply system 1000 of the above embodiment.

[0168] According to the electronic device of the embodiment of the present invention, the power supply system of the above embodiment can reduce the correlation of the current source to the analog power supply voltage, avoid the bias current generating circuit being disturbed by the fluctuation of the analog power supply, and improve the PSR.

[0169] A fifth aspect of the present invention provides a vehicle 3000, such as Figure 7 As shown, the vehicle 3000 includes the electronic device 2000 of the above embodiment.

[0170] According to the vehicle of the embodiment of the present invention, through the electronic device of the above embodiment, the correlation of the current source to the analog power supply voltage can be reduced, the bias current generating circuit can be prevented from being disturbed by the fluctuation of the analog power supply, and the PSR can be improved.

[0171] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0172] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A bias current generating circuit, characterized in that: For a power supply system, the circuit comprises: A bias current generating module, wherein the power supply voltage terminal of the bias current generating module is connected to the voltage stabilizing circuit of the power supply system, the voltage stabilizing circuit is used to output a first power supply voltage, and the bias current generating module is used to output a bias current under the power supply of the first power supply voltage.

2. The bias current generating circuit according to claim 1, wherein: The bias current generating module comprises: a first filtering unit, wherein a first end of the first filtering unit is connected to a reference power supply, and the first filtering unit is used to filter a reference voltage provided by the reference power supply; a bias current generating unit, wherein a first end of the bias current generating unit is connected to a second end of the first filtering unit, and the bias current generating unit is used to generate a bias current according to a filtered reference voltage; A low-voltage cascode current mirror, wherein a first end of the low-voltage cascode current mirror is the power supply voltage end, and a second end of the low-voltage cascode current mirror is connected to a second end of the bias current generating unit for mirroring the bias current; A bias voltage providing unit, a first end of the bias voltage providing unit and a third end of the low voltage cascode current mirror, and a second end of the bias voltage providing unit is a bias voltage end for providing a bias voltage.

3. The bias current generating circuit according to claim 2, wherein: The bias current generating unit comprises: A first MOS transistor, wherein a gate of the first MOS transistor is connected to a second end of the first filtering unit, and a drain of the first MOS transistor is connected to a second end of the low-voltage common-source common-gate current mirror; a first resistor, wherein a first end of the first resistor is connected to the source of the first MOS tube, and a second end of the first resistor is connected to a fourth end of the low-voltage cascode current mirror; A second resistor, wherein a first end of the second resistor is connected to a second end of the first resistor, and a second end of the second resistor is connected to a negative voltage source.

4. The bias current generating circuit according to claim 3, characterized in that: The low voltage cascode current mirror comprises: a second MOS tube, wherein the drain of the second MOS tube is connected to the voltage stabilizing circuit, and the gate of the second MOS tube is connected to the drain of the first MOS tube; a third MOS tube, wherein a gate of the third MOS tube is connected to the gate of the second MOS tube, and a drain of the third MOS tube is connected to the drain of the second MOS tube; a fourth MOS tube, wherein the drain of the fourth MOS tube is connected to the source of the second MOS tube, the source of the fourth MOS tube is connected to the drain of the first MOS tube, and the gate of the fourth MOS tube is connected to the second end of the first resistor; A fifth MOS tube, wherein the gate of the fifth MOS tube is connected to the gate of the fourth MOS tube, the drain of the fifth MOS tube is connected to the source of the third MOS tube, and the source of the fifth MOS tube is connected to the first end of the bias voltage providing unit.

5. The bias current generating circuit according to claim 4, characterized in that: The bias voltage providing unit comprises: A sixth MOS tube, wherein the drain of the sixth MOS tube is connected to the source of the fifth MOS tube, the source of the sixth MOS tube is connected to a negative voltage source, and the gate of the sixth MOS tube is used to provide a bias voltage.

6. The bias current generating circuit according to claim 2, characterized in that: The bias current generating module also includes: a second filtering unit, wherein a first end of the second filtering unit is connected to a second end of the bias voltage providing unit, a second end of the second filtering unit is connected to the voltage stabilizing circuit, and the second filtering unit is used to filter the bias voltage; A bias current output unit, wherein a first end of the bias current output unit is connected to a third end of the second filtering module, and the bias current output unit is used to output the bias current according to the filtered bias voltage.

7. The bias current generating circuit according to claim 6, characterized in that: There are multiple bias current output units, and each bias current output unit includes: A power tube, wherein the gate of the power tube is connected to the third end of the second filtering module, the drain of the power tube is used to provide the bias current to the corresponding bias current demand module, and the source of the power tube is connected to the negative voltage source.

8. The bias current generating circuit according to claim 6 or 7, characterized in that: The second filtering unit comprises: A first resistance unit and a first capacitance unit, wherein the first end of the first resistance unit is connected to the second end of the bias voltage providing unit, the second end of the first resistance unit is connected to the first end of the first capacitance unit and the first end of the bias current output unit, the third end of the first resistance unit is connected to the voltage stabilizing circuit, and the second end of the first capacitance unit is connected to a negative voltage source.

9. The bias current generating circuit according to claim 8, characterized in that: The bias current generating circuit further includes: A pre-charging module, wherein a first end of the pre-charging module is connected to an analog power supply, a second end of the pre-charging module is connected to a first end of the first capacitor unit, and the pre-charging module is used to perform pre-charging control on the first capacitor unit.

10. The bias current generating circuit according to claim 9, characterized in that: The bias current generating circuit further includes: a switch unit, wherein a first end of the switch unit is connected to a first end of the first resistor unit and a first end of the bias voltage providing unit, and a second end of the switch unit is connected to a second end of the first resistor unit; A startup control module, wherein a first end of the startup control module is connected to the voltage stabilizing circuit to receive the first supply voltage, a second end of the startup control module is connected to a control end of the switch unit, and the startup control module is used to be turned on when the quick startup function is turned on to short-circuit the first resistance unit.

11. The bias current generating circuit according to claim 10, characterized in that: The first resistance unit comprises: a seventh MOS tube, wherein a gate of the seventh MOS tube is connected to the voltage stabilizing circuit, and a drain of the seventh MOS tube is connected to the second end of the bias voltage providing unit and the first end of the switch unit; A third resistor, wherein a first end of the third resistor is connected to the source of the seventh MOS tube, and a second end of the third resistor is connected to the first end of the first capacitor unit, the first end of the bias current output unit, and the second end of the switch unit.

12. The bias current generating circuit according to claim 11, characterized in that: The first capacitor unit includes: a first capacitor, wherein a first end of the first capacitor is connected to a second end of the third resistor, a second end of the switch unit, and a second end of the pre-charge module, and a second end of the first capacitor is connected to a negative voltage source; An eighth MOS tube, wherein the gate of the eighth MOS tube is connected to the second end of the third resistor, the second end of the switch unit, and the second end of the pre-charge module, and the source of the eighth MOS tube and the drain of the eighth MOS tube are both connected to a negative voltage source.

13. The bias current generating circuit according to claim 12, characterized in that: The pre-charging module comprises: a ninth MOS tube, wherein a gate of the ninth MOS tube is used to receive a switch enable signal, and a drain of the ninth MOS tube is connected to the analog power supply; A fourth resistor, wherein a first end of the fourth resistor is connected to the source of the ninth MOS transistor, and a second end of the fourth resistor is connected to the first end of the first capacitor.

14. The bias current generating circuit according to claim 1, wherein: The bias current generating circuit further includes: A second capacitor, wherein a first end of the second capacitor is connected to the voltage stabilizing circuit, and a second end of the second capacitor is connected to a negative voltage source.

15. A filter circuit, characterized in that: include: A first switch module, wherein a first end of the first switch module is connected to a voltage stabilizing circuit of a power supply system in which the first switch module is located to receive a first supply voltage output by the voltage stabilizing circuit, and a control end of the first switch module is used to receive a first enable signal, wherein the first enable signal has the same logic as a power switch signal of the power supply system; a second switch module, wherein a first end of the second switch module is connected to an analog power supply, and a control end of the second switch module is used to receive a second enable signal, wherein the second enable signal is logically opposite to a power switch signal of the power supply system; A filtering structure, wherein a first end of the filtering structure is connected to a second end of the first switch module and a power supply voltage end of the bias current generating circuit according to any one of claims 1 to 9, and a second end of the filtering structure is connected to a second end of the second switch module, and the filtering structure is used to filter the first power supply voltage or the power supply voltage provided by the analog power supply so that the filtered second power supply voltage powers the bias current generating circuit.

16. The filter circuit according to claim 15, characterized in that: The filtering structure comprises: A first filtering module, wherein a first end of the first filtering module is connected to a second end of the first switch module and the power supply voltage end, and a second end of the first filtering module is connected to a negative voltage source; A second filtering module, wherein a first end of the second filtering module is connected to a second end of the second switch module, a second end of the second filtering module is connected to a first end of the first filtering module, and a third end of the second filtering module is connected to a negative voltage source.

17. The filter circuit according to claim 16, characterized in that: The bias current generating circuit comprises a low voltage cascode current mirror for mirroring the bias current, and the substrate ends of all MOS tubes in the low voltage cascode current mirror are connected to the first end of the first filtering module and the power supply voltage end.

18. The filter circuit according to claim 16, characterized in that: The bias current generating circuit includes a bias voltage providing unit for providing a bias voltage and a second filtering unit for filtering the bias voltage, and the second end of the second filtering unit is connected to the first end of the first filtering module and the power supply voltage end so that the second power supply voltage serves as the bias voltage of the second filtering unit.

19. The filter circuit according to claim 15 or 16, characterized in that: The first switch module comprises: A tenth MOS tube, wherein the drain of the tenth MOS tube is connected to the voltage stabilizing circuit, the gate of the tenth MOS tube is used to receive a first enable signal, and the source of the tenth MOS tube is connected to the first end of the filter structure and the power supply voltage end.

20. The filter circuit according to claim 15 or 16, characterized in that: The second switch module comprises: An eleventh MOS tube, wherein the drain of the eleventh MOS tube is connected to the analog power supply, the gate of the eleventh MOS tube is used to receive a second enable signal, and the source of the eleventh MOS tube is connected to the second end of the filter structure.

21. The filter circuit according to claim 16, characterized in that: The first filtering module comprises: A third capacitor, wherein a first end of the third capacitor is connected to the second end of the first switch module and the power supply voltage end, and a second end of the third capacitor is connected to a negative voltage source; A twelfth MOS tube, wherein the gate of the twelfth MOS tube is connected to the first end of the third capacitor, and the drain of the twelfth MOS tube and the source of the twelfth MOS tube are both connected to a negative voltage source.

22. The filter circuit according to claim 21, characterized in that: The second filtering module comprises: A second resistance unit and a second capacitance unit, wherein the first end of the second resistance unit is connected to the second end of the second switch module, the second end of the second resistance unit is connected to the first end of the second capacitance unit, the third end of the second resistance unit is connected to a negative voltage source, the second end of the second capacitance unit is connected to the power supply voltage end and the first end of the third capacitor, and the third end of the second capacitance unit is connected to the negative voltage source.

23. The filter circuit according to claim 22, characterized in that: The second resistance unit includes: a thirteenth MOS tube, wherein a drain of the thirteenth MOS tube is connected to the second end of the second switch module; a fifth resistor, wherein a first end of the fifth resistor is connected to the gate of the thirteenth MOS transistor, and a second end of the fifth resistor is connected to a negative voltage source; A fourteenth MOS tube, wherein the drain of the fourteenth MOS tube is connected to the source of the thirteenth MOS tube, the gate of the fourteenth MOS tube is connected to the first end of the fifth resistor, and the source of the fourteenth MOS tube is connected to the first end of the second capacitor unit.

24. The filter circuit according to claim 23, characterized in that: The second capacitor unit includes: a sixth resistor, wherein a first end of the sixth resistor is connected to the source of the fourteenth MOS tube, and a second end of the sixth resistor is connected to the power supply voltage terminal and the first end of the third capacitor; a fourth capacitor, wherein a first end of the fourth capacitor is connected to the first end of the sixth resistor, and a second end of the fourth capacitor is connected to a negative voltage source; A fifteenth MOS tube, wherein the gate of the fifteenth MOS tube is connected to the first end of the fourth capacitor, and the source of the fifteenth MOS tube and the drain of the fifteenth MOS tube are both connected to a negative voltage source.

25. A power supply system, characterized in that: include: A voltage stabilizing circuit, the voltage stabilizing circuit is used to convert the voltage of the analog power supply into a first power supply voltage in a power supply state ； The bias current generating circuit according to any one of claims 1 to 14 and the filter circuit according to any one of claims 15 to 24, wherein the power supply voltage terminal of the bias current generating circuit is connected to the output terminal of the filter circuit, and the first input terminal of the filter circuit is connected to the output terminal of the voltage stabilizing circuit; The filtering circuit is used to filter the first supply voltage in a power supply state to obtain a second supply voltage, so that the second supply voltage supplies power to the bias current generating circuit.

26. The power supply system according to claim 25, characterized in that: The second input terminal of the filter circuit is connected to the analog power supply, and the filter circuit is further used to filter the voltage of the analog power supply in a non-powered state to obtain the second power supply voltage.

27. The power supply system according to claim 25, characterized in that: The voltage stabilizing circuit comprises: A first-stage operational amplifier structure, wherein a power supply terminal of the first-stage operational amplifier structure is suitable for inputting a bias current provided by the bias current generating circuit, and an input terminal of the first-stage operational amplifier structure is suitable for inputting a bandgap reference voltage, for generating an operational amplifier signal according to the bandgap reference voltage; A second-stage operational amplifier structure, wherein the first input terminal of the second-stage operational amplifier structure is connected to a device suitable for connecting an analog power supply, the second input terminal of the second-stage operational amplifier structure is connected to the output terminal of the first-stage operational amplifier structure, and the output terminal of the second-stage operational amplifier structure is connected to the first input terminal of the filter circuit, for generating a first power supply voltage according to the operational amplifier signal.

28. The power supply system according to claim 27, characterized in that: The first-stage operational amplifier structure includes: A power supply unit, wherein a first input terminal of the power supply unit is suitable for connecting an analog power supply, and a second input terminal of the power supply unit is suitable for inputting a bias current, and is used to generate an operational amplifier power supply current according to the bias current; An operational amplifier unit, wherein a power supply terminal of the operational amplifier unit is connected to an output terminal of the power supply unit, and an input terminal of the operational amplifier unit is suitable for inputting a bandgap reference voltage and is used to generate an operational amplifier signal according to the bandgap reference voltage.

29. The power supply system according to claim 28, characterized in that: The power supply unit comprises: A current mirror unit, wherein the input end of the current mirror unit is suitable for inputting a bias current, and is used for mirroring the bias current; A current source subunit, wherein a first end of the current source subunit is connected to an output end of the current mirror unit, a second end of the current source subunit is connected to a power supply end of the operational amplifier unit, and a third end of the current source subunit is suitable for connecting to an analog power supply.

30. The power supply system according to claim 29, characterized in that: The current mirror unit comprises: a sixteenth MOS transistor, wherein the gate of the sixteenth MOS transistor is suitable for inputting the bias current, and the source of the sixteenth MOS transistor is connected to a negative voltage source; A seventeenth MOS tube, the gate of the seventeenth MOS tube is suitable for inputting the bias current, the source of the seventeenth MOS tube is connected to the drain of the sixteenth MOS tube, and the drain of the seventeenth MOS tube is connected to the first end of the current source subunit.

31. The power supply system according to claim 30, characterized in that: The current source subunit comprises: an eighteenth MOS tube and a nineteenth MOS tube, wherein the source of the eighteenth MOS tube is connected to the drain of the seventeenth MOS tube and the gate of the eighteenth MOS tube, the gate of the eighteenth MOS tube is connected to the gate of the nineteenth MOS tube to provide a bias for the nineteenth MOS tube, and the source of the nineteenth MOS tube is connected to the power supply terminal of the operational amplifier unit; a twentieth MOS tube and a twenty-first MOS tube, wherein the source of the twentieth MOS tube is connected to the drain of the eighteenth MOS tube and the gate of the twentieth MOS tube, the drain of the twentieth MOS tube is suitable for connecting to an analog power supply, the gate of the twentieth MOS tube is connected to the gate of the twenty-first MOS tube to provide a bias for the twenty-first MOS tube, the source of the twenty-first MOS tube is connected to the drain of the nineteenth MOS tube, and the drain of the twenty-first MOS tube is suitable for connecting to an analog power supply.

32. The power supply system according to claim 31, characterized in that: The operational amplifier unit comprises: a twenty-second MOS tube and a twenty-third MOS tube, wherein the gate of the twenty-second MOS tube is suitable for inputting a bandgap reference voltage, the drain of the twenty-second MOS tube is connected to the drain of the twenty-third MOS tube, the drain of the twenty-third MOS tube is connected to the drain of the twenty-second MOS tube to serve as a power supply terminal of the operational amplifier unit, the power supply terminal is connected to the source of the nineteenth MOS tube, and the twenty-second MOS tube and the twenty-third MOS tube are used to generate a differential signal; A twenty-fourth MOS tube and a twenty-fifth MOS tube, wherein the drain of the twenty-fourth MOS tube is connected to the gate of the twenty-fourth MOS tube and the source of the twenty-second MOS tube, the source of the twenty-fourth MOS tube is connected to a negative voltage source, the drain of the twenty-fifth MOS tube is connected to the source of the twenty-third MOS tube and the gate of the twenty-fifth MOS tube, and the source of the twenty-fifth MOS tube is connected to the negative voltage source, and are used to convert the differential signal into an output current.

33. The power supply system according to claim 32, characterized in that: The operational amplifier unit also includes: A seventh resistor and an eighth resistor, wherein the first end of the seventh resistor is connected to the output end of the second-stage operational amplifier structure, the second end of the seventh resistor is connected to the first end of the eighth resistor, the second end of the eighth resistor is connected to a negative voltage source, and a first node is provided between the second end of the seventh resistor and the first end of the eighth resistor, and the first node is connected to the gate of the twenty-third MOS tube to form a negative feedback loop.

34. The power supply system according to claim 33, characterized in that: The operational amplifier unit also includes: a twenty-sixth MOS tube, wherein the gate of the twenty-sixth MOS tube is connected to the gate of the twenty-fourth MOS tube and the drain of the twenty-fourth MOS tube, and the source of the twenty-sixth MOS tube is connected to the negative voltage source, so as to increase the output impedance; A twenty-seventh MOS tube, a gate of the twenty-seventh MOS tube is connected to the gate of the twenty-fifth MOS tube and the drain of the twenty-fifth MOS tube, a source of the twenty-seventh MOS tube is connected to the negative voltage source, and a drain of the twenty-seventh MOS tube is connected to the output end of the second-stage operational amplifier structure through a fifth capacitor for improving the output impedance, and the fifth capacitor is used as a compensation capacitor.

35. The power supply system according to claim 34, characterized in that: The operational amplifier unit also includes: a twenty-eighth MOS tube and a twenty-ninth MOS tube, the gate of the twenty-eighth MOS tube is connected to the gate of the twenty-ninth MOS tube, the source of the twenty-eighth MOS tube is connected to the drain of the twenty-sixth MOS tube, the gate of the twenty-eighth MOS tube and the gate of the twenty-ninth MOS tube are suitable for connecting to a bias voltage, and the source of the twenty-ninth MOS tube is connected to the drain of the twenty-seventh MOS tube to increase the output gain to obtain the operational amplifier signal.

36. The power supply system according to claim 35, characterized in that: The second-stage operational amplifier structure includes: an output conversion unit, the output conversion unit being connected to the drain of the twenty-eighth MOS tube and the drain of the twenty-ninth MOS tube, and being used for converting the output signal of the twenty-eighth MOS tube and the output signal of the twenty-ninth MOS tube into an operational amplifier signal output; An output unit, wherein an input end of the output unit is connected to an output end of the output conversion unit, and an output end of the output unit is connected to a first input end of the filter circuit to output the first supply voltage.

37. The power supply system according to claim 36, characterized in that: The output conversion unit comprises: a 30th MOS tube and a 31st MOS tube, wherein the source of the 30th MOS tube is connected to the drain of the 28th MOS tube and the gate of the 30th MOS tube, the gate of the 30th MOS tube is connected to the gate of the 31st MOS tube, the drain of the 30th MOS tube is suitable for connecting to an analog power supply, the drain of the 31st MOS tube is suitable for connecting to an analog power supply, and the source of the 31st MOS tube is connected to the drain of the 29th MOS tube and the input end of the output unit.

38. The power supply system according to claim 37, characterized in that: The output unit comprises: a thirty-second MOS tube, wherein the gate of the thirty-second MOS tube is connected to the source of the thirty-first MOS tube and the drain of the twenty-ninth MOS tube, the drain of the thirty-second MOS tube is suitable for connecting to an analog power supply, and the source of the thirty-second MOS tube is connected to the first end of the seventh resistor and outputs the first supply voltage.

39. The power supply system according to claim 38, characterized in that: The voltage stabilizing circuit further includes: A compensation module, wherein the first end of the compensation module is suitable for connecting to an analog power supply, and the second end of the compensation module is connected to the gate of the thirty-second MOS tube, the source of the thirty-first MOS tube, and the drain of the twenty-ninth MOS tube for performing zero-point compensation.

40. The power supply system according to claim 39, characterized in that: The compensation module comprises: A ninth resistor and a sixth capacitor, wherein the first end of the ninth resistor is suitable for connecting to an analog power supply, the second end of the ninth resistor is connected to the first end of the sixth capacitor, and the second end of the sixth capacitor is connected to the gate of the thirty-second MOS tube, the source of the thirty-first MOS tube, and the drain of the twenty-ninth MOS tube.

41. The power supply system according to any one of claims 25 to 40, characterized in that: The power supply system further comprises: A start-up circuit is connected to the voltage stabilizing circuit and the bias current generating circuit, and is used for providing the voltage stabilizing circuit with the bias current it needs.

42. The power supply system according to any one of claims 25 to 40, characterized in that: The startup circuit comprises: A first power supply module, the first power supply module is used to provide a first bias current in response to a second enable signal flipping from a low potential to a high potential, and the second enable signal is logically opposite to a power switch signal of the power supply system; a second power supply module, wherein the input end of the second power supply module is connected to the bias voltage end of the bias current generating circuit and the output end of the voltage stabilizing circuit, and is used for controlling the first power supply module to shut down and provide a second bias current when the bias voltage of the bias voltage end reaches a voltage threshold and the voltage stabilizing signal output by the voltage stabilizing circuit reaches the voltage stabilizing threshold; A current mirror module, wherein the current mirror module is connected to the first power supply module and the second power supply module respectively, and is used to mirror the first bias current or the second bias current to the output end of the voltage stabilization circuit.

43. The power supply system according to claim 42, characterized in that: The first power supply module comprises: a thirty-third MOS tube, wherein the drain of the thirty-third MOS tube is suitable for connecting to an analog power supply, and the source of the thirty-third MOS tube is connected to the current mirror module; A series inverted ratio tube structure, wherein a first end of the series inverted ratio tube structure is connected to the gate of the thirty-third MOS tube, a second end of the series inverted ratio tube structure is connected to a negative voltage source, and a control end of the series inverted ratio tube structure is suitable for inputting a second enable signal; When the second enable signal is flipped from a low potential to a high potential, the series inverse ratio transistor structure is turned on and the thirty-third MOS transistor is turned on to provide the first bias current.

44. The power supply system according to claim 43, characterized in that: The series inverse ratio tube structure comprises: a thirty-fourth MOS tube, the drain of which is connected to the gate of the thirty-third MOS tube, and the gate of which is suitable for receiving the second enable signal; a thirty-fifth MOS transistor, wherein the drain of the thirty-fifth MOS transistor is connected to the source of the thirty-fourth MOS transistor, and the gate of the thirty-fifth MOS transistor is suitable for receiving the second enable signal; A thirty-sixth MOS tube, the drain of the thirty-sixth MOS tube is connected to the source of the thirty-fifth MOS tube, the gate of the thirty-sixth MOS tube is suitable for receiving the second enable signal, and the source of the thirty-sixth MOS tube is connected to a negative voltage source.

45. The power supply system according to claim 44, characterized in that: The second power supply module includes: a thirty-seventh MOS transistor, the gate of which is connected to the bias voltage terminal, the source of which is connected to a negative voltage source, and is configured to be turned on when the bias voltage reaches a voltage threshold; A thirty-eighth MOS tube, the gate of the thirty-eighth MOS tube is connected to the output end of the voltage stabilizing circuit, the source of the thirty-eighth MOS tube is connected to the drain of the thirty-seventh MOS tube, and the drain of the thirty-eighth MOS tube is connected to the current mirror module, and is used for being turned on when the voltage stabilizing signal output by the voltage stabilizing circuit reaches a voltage stabilizing threshold.

46. ​​The power supply system according to claim 45, characterized in that: The current mirror module comprises: A first current mirror unit, wherein the first end of the first current mirror unit is connected to the source of the thirty-third MOS tube, the second end of the first current mirror unit is connected to a negative voltage source, and the third end of the first current mirror unit is connected to the input end of the voltage stabilizing circuit to mirror the first bias current to the voltage stabilizing circuit.

47. The power supply system according to claim 46, characterized in that: The current mirror module also includes: A second current mirror unit, wherein the first end of the second current mirror unit is connected to the drain of the thirty-eighth MOS tube, the second end of the second current mirror unit is connected to the gate of the thirty-third MOS tube and the first end of the series inverse ratio tube structure to control the thirty-third MOS tube to be cut off when the thirty-eighth MOS tube is turned on, and the third end of the second current mirror unit is connected to the first end of the first current mirror unit to mirror the second bias current to the voltage stabilizing circuit.

48. The power supply system according to claim 47, characterized in that: The first current mirror unit comprises: a thirty-ninth MOS tube, wherein the drain of the thirty-ninth MOS tube is connected to the third end of the second current mirror unit, the gate of the thirty-ninth MOS tube, the gate of the twenty-eighth MOS tube in the voltage stabilizing circuit, and the gate of the twenty-ninth MOS tube in the voltage stabilizing circuit to provide a bias voltage, and the gate of the thirty-ninth MOS tube is connected to the gate of the seventeenth MOS tube in the voltage stabilizing circuit to provide a bias current; The 40th MOS tube, the drain of the 40th MOS tube is connected to the source of the 39th MOS tube and the gate of the 40th MOS tube, the gate of the 40th MOS tube is connected to the gate of the 16th MOS tube in the voltage stabilizing circuit, and the source of the 40th MOS tube is connected to a negative voltage source.

49. The power supply system according to claim 48, characterized in that: The second current mirror unit comprises: a forty-first MOS tube, wherein the source of the forty-first MOS tube is connected to the gate of the forty-first MOS tube and the drain of the thirty-seventh MOS tube; a 42nd MOS tube, wherein the gate of the 42nd MOS tube is connected to the gate of the 41st MOS tube and the source of the 41st MOS tube, and the source of the 42nd MOS tube is connected to the drain of the 39th MOS tube; a forty-third MOS tube, wherein the source of the forty-third MOS tube is connected to the gate of the forty-third MOS tube and the drain of the forty-first MOS tube, and the drain of the forty-third MOS tube is suitable for connecting to an analog power supply; A forty-fourth MOS tube, the gate of the forty-fourth MOS tube is connected to the gate of the forty-third MOS tube and the source of the forty-third MOS tube, the source of the forty-fourth MOS tube is connected to the drain of the forty-second MOS tube, and the drain of the forty-fourth MOS tube is suitable for connecting an analog power supply.

50. The power supply system according to claim 49, characterized in that: The second current mirror unit further includes: a forty-fifth MOS tube, wherein the gate of the forty-fifth MOS tube is connected to the gate of the forty-third MOS tube, the source of the forty-third MOS tube, and the drain of the forty-first MOS tube, and the source of the forty-fifth MOS tube is connected to the gate of the thirty-third MOS tube and the drain of the thirty-fourth MOS tube, and is used for controlling the thirty-third MOS tube to be cut off to turn off the first bias current when being turned on.

51. The power supply system according to claim 50, characterized in that: The startup circuit also includes: Two forty-sixth MOS tubes, the drain of each of the forty-sixth MOS tubes is suitable for connecting to an analog power supply, the gate of each of the forty-sixth MOS tubes is used to receive a second enable signal, and the sources of the two forty-sixth MOS tubes are respectively connected to the gate of the thirty-third MOS tube and the gate of the forty-fifth MOS tube, and are used to pull up the gate of the thirty-third MOS tube and the gate of the forty-fifth MOS tube when the power supply switch signal of the power supply system is a shutdown signal.

52. The power supply system according to claim 53, characterized in that: The startup circuit also includes: Four forty-seventh MOS tubes, each of which has a source connected to a negative voltage source, each of which has a gate used to receive a first enable signal, and the drains of the four forty-seventh MOS tubes are respectively connected to the bias voltage terminal, the gate of the fourteenth MOS tube in the bias current generating circuit, the gate of the twenty-second MOS tube in the voltage stabilizing circuit, and the output end of the voltage stabilizing circuit, and are used to pull down the bias voltage terminal, the gate of the fourteenth MOS tube, the gate of the twenty-second MOS tube, and the output end of the voltage stabilizing circuit when the power supply switch signal is a shutdown signal.

53. The power supply system according to any one of claims 27 to 52, characterized in that: The power supply system further comprises: An RC filter circuit, wherein the first end of the RC filter circuit is suitable for being connected to a reference voltage source, the second end of the RC filter circuit is connected to the input end of the first-stage operational amplifier structure, and the RC filter circuit is used to output a filtered bandgap reference voltage according to the reference voltage of the reference voltage source.

54. An electronic device, characterized in that: A power supply system comprising any one of claims 25-53.

55. A vehicle, characterized in that: An electronic device comprising the electronic device described in claim 54.

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