Low dropout regulator

Abstract

The invention provides a low dropout regulator. The low dropout regulator comprises a standby power supply circuit, an amplifier, a first transistor, a first input power supply circuit, a first bypass power supply circuit, a first capacitor and a resistance voltage divider, the first input power supply circuit and the first bypass power supply circuit are connected in parallel between a first end of the first transistor and an output end of an output voltage of a low dropout regulator LDO; the second end of the first transistor is grounded; under the condition that the first bypass power supply circuit is controlled to be switched on, the first input power supply circuit is switched off, and power is supplied to the LDO output voltage through the first bypass power supply circuit; under the condition that the first input power supply circuit is controlled to be switched on, the first bypass power supply circuit is switched off, and the LDO outputs voltage to supply power through the first input power supply circuit. By the adoption of the scheme, under the condition that bypass voltage is allowed to be adjusted, only one large-capacitance capacitor is needed to stabilize the LDO loop, and the LDO circuit is suitable for more scenes.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and in particular to a low voltage dropout linear regulator. Background Art

[0002] Low Dropout Regulator (LDO) can convert unstable input voltage into DC output voltage so that it can be used as power supply for other systems. LDO has the advantages of simple circuit structure, small chip area and low noise, and has become an important component of power management chip.

[0003] In the related art, there are two ways to use LDO with dual-end input and single-end output. One way is the bypass power supply solution, and the other way is the dual low-dropout linear regulator solution. The bypass power supply solution introduces a bypass power supply with a fixed voltage from the outside. When the voltage of the bypass power supply is appropriate, it is connected to the internal voltage rail through a switch and supplies power to the load. However, this solution cannot adjust the voltage of the bypass power supply. When a bypass power supply with a suitable voltage value cannot be provided, this solution is not applicable. Another dual low-dropout linear regulator solution, this solution adds an additional low-dropout linear regulator on the basis of the bypass power supply architecture to adjust the voltage of the bypass power supply and finally output a suitable chip power supply voltage. However, this solution uses two low-dropout linear regulators, which not only consumes more chip area, but also requires two capacitors with larger capacitance to stabilize the two low-dropout linear regulator loops respectively. Due to process limitations, the capacitors of low-dropout linear regulators usually need to be connected to the off-chip capacitors through chip pins. Therefore, this solution requires the chip to provide two pins, which greatly limits the applicable scenarios of this solution. Summary of the invention

[0004] The disclosed embodiment provides a low voltage dropout linear regulator, which can avoid adding additional chip pins when adjusting the bypass voltage, and is applicable to more scenarios.

[0005] The present disclosure provides a low voltage dropout linear regulator, comprising:

[0006] A standby power supply circuit, an amplifier, a first transistor, a first input power supply circuit, a first bypass power supply circuit, a first capacitor, and a resistor divider;

[0007] The output end of the standby power supply circuit is connected to the positive power supply end of the amplifier, and the negative power supply end of the amplifier is grounded;

[0008] A first input terminal of the amplifier is connected to a reference voltage, a second input terminal of the amplifier is connected to a feedback node of a resistor divider, and an output terminal of the amplifier is connected to a control terminal of the first transistor;

[0009] The first input power supply circuit and the first bypass power supply circuit are connected in parallel between the first end of the first transistor and the output end of the output voltage of the low-dropout linear regulator LDO, and the second end of the first transistor is grounded;

[0010] The first capacitor and the resistor divider are respectively connected between the output terminal of the LDO output voltage and the ground;

[0011] The first input power supply circuit and the first bypass power supply circuit are respectively configured as follows: the amplifier controls the on-current size of the first transistor by comparing the feedback voltage of the LDO output voltage and the reference voltage; when the first bypass power supply circuit is controlled to be turned on, the first input power supply circuit is turned off, and the LDO output voltage is powered by the first bypass power supply circuit; when the first input power supply circuit is controlled to be turned on, the first bypass power supply circuit is turned off, and the LDO output voltage is powered by the first input power supply circuit.

[0012] Optionally, the first bypass power supply circuit includes: a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor;

[0013] The first end of the second transistor is connected to the second end of the third transistor, the second end of the second transistor is connected to the first end of the first transistor, and the control end of the second transistor inputs a first control signal;

[0014] The control end of the fourth transistor, the first end of the fourth transistor and the control end of the fifth transistor are respectively connected to the first end of the third transistor; the control end of the third transistor inputs a second control signal;

[0015] The second end of the fourth transistor and the second end of the fifth transistor are respectively connected to a bypass voltage;

[0016] The first end of the sixth transistor is connected to the first end of the fifth transistor, the second end of the sixth transistor is connected to the output end of the LDO output voltage, and the control end of the sixth transistor inputs a third control signal.

[0017] Optionally, the first input power circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor;

[0018] The first end of the seventh transistor is connected to the second end of the eighth transistor; the second end of the seventh transistor is connected to the first end of the first transistor; the control end of the seventh transistor inputs a second control signal;

[0019] The control terminal and the first terminal of the ninth transistor and the control terminal of the tenth transistor are respectively connected to the first terminal of the eighth transistor; the control terminal of the eighth transistor inputs a first control signal;

[0020] The second end of the ninth transistor and the second end of the tenth transistor are respectively connected to an input voltage;

[0021] The first end of the eleventh transistor is connected to the first end of the tenth transistor, the second end of the eleventh transistor is connected to the output end of the LDO output voltage, and the control end of the eleventh transistor inputs a fourth control signal.

[0022] Optionally, the standby power supply circuit includes a second input power supply circuit, a second bypass power supply circuit and a second capacitor;

[0023] The second input power circuit is connected in parallel with the second bypass power circuit; the output end of the second input power circuit and the output end of the second bypass power circuit are respectively connected to the positive power end of the amplifier;

[0024] The second capacitor is connected between the output terminal of the second bypass power supply circuit and ground;

[0025] The second input power supply circuit and the second bypass power supply circuit are configured to use a higher output voltage of the second input power supply circuit and the second bypass power supply circuit as an output voltage of the standby power supply circuit.

[0026] Optionally, the second input power circuit includes a first resistor, a first source follower, a first voltage regulator diode and a third capacitor; the first source follower includes a twelfth transistor and a thirteenth transistor;

[0027] The first end of the first resistor and the first end of the twelfth transistor are connected to an input power supply;

[0028] The second end of the first resistor, the negative terminal of the first voltage stabilizing diode, and the first end of the third capacitor are respectively connected to the control end of the twelfth transistor, and are respectively connected to the control end of the thirteenth transistor;

[0029] The second end of the twelfth transistor is connected to the second end of the thirteenth transistor, and the first end of the thirteenth transistor serves as the output end of the second input power circuit;

[0030] The positive terminal of the first voltage stabilizing diode and the second terminal of the third capacitor are grounded respectively.

[0031] Optionally, the second bypass power supply circuit includes: a second resistor, a second source follower, a second voltage regulator diode and a fourth capacitor; the source follower includes a fourteenth transistor and a fifteenth transistor;

[0032] The first end of the second resistor and the first end of the fourteenth transistor are connected to a bypass power supply;

[0033] The second end of the second resistor, the negative terminal of the second voltage stabilizing diode, and the first end of the fourth capacitor are respectively connected to the control end of the fourteenth transistor, and are respectively connected to the control end of the fifteenth transistor;

[0034] The second end of the fourteenth transistor is connected to the second end of the fifteenth transistor, and the first end of the fifteenth transistor serves as the output end of the second bypass power supply circuit;

[0035] The positive terminal of the second voltage stabilizing diode and the second terminal of the fourth capacitor are grounded respectively.

[0036] Optionally, it further includes a first comparator, a second comparator, a NOR gate and a first inverter;

[0037] The positive power supply terminal of the first comparator and the positive power supply terminal of the second comparator are respectively connected to the output terminal of the second input power supply circuit, and are respectively connected to the output terminal of the second bypass power supply circuit;

[0038] The negative power supply terminal of the first comparator and the negative power supply terminal of the second comparator are grounded respectively;

[0039] The first comparator has a first input terminal connected to the bypass power supply, a second input terminal inputting the input power supply, and an output terminal connected to the first input terminal of the NOR gate, and is used to compare the bypass voltage output by the bypass power supply with the input voltage provided by the input power supply, and output a signal;

[0040] The second comparator has a first input terminal connected to the bypass power supply, a second input terminal connected to the reference voltage, and an output terminal connected to the second input terminal of the NOR gate, and is used to compare the bypass voltage provided by the bypass power supply with the reference voltage and output a signal;

[0041] The NOR gate is used to select the output signals of the first comparator and the second comparator, and output a first control signal;

[0042] The first inverter is used to convert the first control signal into a second control signal.

[0043] Optionally, it also includes a level converter and a second inverter;

[0044] The level converter is connected between the LDO output voltage and ground;

[0045] The level converter is used to convert the first control signal into a third control signal, or convert the second control signal into a fourth control signal;

[0046] The second inverter is used to convert the third control signal into a fourth control signal, or convert the fourth control signal into a third control signal.

[0047] Optionally, the second transistor, the fourth transistor, the fifth transistor and the sixth transistor are P-type MOS transistors; the first transistor and the third transistor are N-type MOS transistors.

[0048] Optionally, the seventh transistor, the ninth transistor, the tenth transistor and the eleventh transistor are P-type MOS transistors, and the eighth transistor is an N-type MOS transistor.

[0049] In the technical solution provided by the embodiment of the present disclosure, the linear regulator includes a standby power supply circuit, an amplifier, a first transistor, a first input power supply circuit, a first bypass power supply circuit, a first capacitor and a resistor divider, wherein the first input power supply circuit and the first bypass power supply circuit are connected in parallel between the first end of the first transistor and the output end of the output voltage of the low-dropout linear regulator LDO, and the amplifier controls the conduction current of the first transistor by comparing the feedback voltage of the LDO output voltage and the reference voltage. When the first bypass power supply circuit is controlled to be turned on, the first input power supply circuit is turned off, and the LDO output voltage is powered by the first bypass power supply circuit; when the first input power supply circuit is controlled to be turned on, the first bypass power supply circuit is turned off, and the LDO output voltage is powered by the first input power supply circuit. Output voltage power supply; that is, the above-mentioned LDO includes an amplifier and a first transistor, and the first input power supply circuit and the first bypass power supply circuit are connected in parallel between the first end of the first transistor and the output end of the output voltage of the low-voltage difference linear regulator LDO, and the first input power supply circuit and the first bypass power supply circuit are controlled to be turned on or off to realize the power supply of the LDO output voltage. Compared with the bypass power supply scheme in the related art, the bypass power supply voltage can be adjusted by adjusting the current of the first transistor. Compared with the dual low-voltage difference linear regulator scheme in the related art, there is only one first capacitor with a larger capacitance. In the case where LDO generally requires additional pins to be connected to off-chip capacitors, additional chip pins can be avoided, which is suitable for more application scenarios and can also reduce the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 It is a schematic diagram of a bypass power supply circuit in the related art;

[0052] Figure 2 It is a circuit diagram of a dual low voltage difference linear regulator solution in the related art;

[0053] Figure 3 A schematic diagram of a linear voltage regulator circuit provided by an embodiment of the present disclosure;

[0054] Figure 4 A schematic diagram of a linear voltage regulator circuit provided by an embodiment of the present disclosure;

[0055] Figure 5 A signal timing diagram is provided for the embodiments of the present disclosure. DETAILED DESCRIPTION

[0056] In order to enable those skilled in the art to better understand the scheme of the present disclosure, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present disclosure.

[0057] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0058] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0059] It should be noted that, in the present disclosure, the first end, the second end and the control end of the transistor may be a drain, a source and a gate, respectively.

[0060] In the related art, the circuit diagram of the bypass power supply solution can be referred to Figure 1 ,like Figure 1As shown, the bypass power supply solution includes an LDO, a bypass switch and a judgment circuit thereof. Among them, the LDO is composed of an amplifier A1, a transistor MN1, a transistor MP1, a transistor MP2, a resistor R1, a resistor R2 and a capacitor C1. Resistors R1 and R2 form a resistor divider to divide the output voltage VCC of the LDO to a suitable potential VFB. Amplifier A1 receives the reference voltage VREF and VFB signals, and outputs the control terminal signal of transistor MN1 to adjust the on-current of transistor MN1. The on-current of transistor MN1 is transmitted to transistor MP1, and the on-current of transistor MP1 is proportionally mirrored and amplified by transistor MP2, and the output voltage VCC of the LDO is supplied.

[0061] The bypass switch is composed of a transistor MP3 and a transistor MP4, and the judgment circuit of the bypass switch is composed of a comparator A2, which receives a reference voltage VREF and a voltage provided by a bypass power supply BYP, and judges whether the voltage of the bypass power supply BYP is properly connected. If the judgment is passed, the control signal SEL1 is set low, the transistor MP3 and the transistor MP4 are turned on, the voltage of BYP is connected, and the output voltage VCC is powered by the bypass power supply BYP.

[0062] The voltage of the bypass power supply BYP is usually slightly higher than the output voltage VCC, but significantly lower than the voltage of the input power supply VIN. When the bypass switch, i.e., transistor MP3 and transistor MP4, is turned on, the load circuit on the output voltage VCC will be powered by the voltage of BYP instead of the voltage of VIN, and the power consumption difference is ΔP = (VIN-BYP) × ILOAD, where ILOAD is the load current on the output voltage VCC.

[0063] In the above technical solution, the bypass power supply supplies power to the internal circuit of the chip through the bypass switch (supplying power to the internal circuit of the chip through VCC), but its voltage is a fixed value of external input. If its voltage value does not match the power supply voltage required by the internal circuit of the chip, then this solution is not applicable.

[0064] In the related art, a dual low-dropout linear regulator may include two low-dropout linear regulators (LDOs) and a bypass switch and a judgment circuit thereof. The circuit diagram of the dual low-dropout linear regulator solution can be referred to Figure 2 ,like Figure 2As shown, the first low-voltage dropout linear regulator consists of an amplifier A1, a transistor MN1, a transistor MP1, a transistor MP2, a resistor R1, a resistor R2 and a capacitor C1. Its working principle is the same as the bypass power supply scheme mentioned above. The bypass switch and its judgment circuit are composed of a comparator A2, a transistor MP3, and a transistor MP4, and its working principle is the same as the bypass power supply scheme mentioned above. The second low-voltage dropout linear regulator consists of an amplifier A3, a transistor MN2, a transistor MP5, a transistor MP6, a resistor R3, a resistor R4 and a capacitor C2. Its working principle is similar to that of the first low-voltage dropout linear regulator, but its input is LDO and its output is VCC.

[0065] The above solution uses a second low-dropout linear regulator to adjust the fixed voltage value of the external input bypass power supply and convert it into an output voltage VCC with a suitable voltage value, and power the internal circuit of the chip. Although the above solution solves the disadvantage that the bypass power supply solution cannot adjust the chip power supply voltage value, it uses an additional low-dropout linear regulator, which consumes more chip area. At the same time, since low-dropout linear regulators usually require large-capacitance off-chip capacitors C1 and C2 to stabilize the loop, the above solution requires the chip to provide additional pins, which limits its application scenarios.

[0066] To solve the above problems, Figure 3 is a schematic circuit diagram of a low voltage dropout linear regulator provided by an embodiment of the present disclosure, such as Figure 3 As shown, it includes: a standby power supply circuit 100, an amplifier A0, a first transistor M1, a first input power supply circuit 200, a first bypass power supply circuit 300, a first capacitor C1 and a resistor divider 400;

[0067] Among them, the output end of the standby power supply circuit 100 is connected to the positive power supply end of the amplifier A0, and the negative power supply end of the amplifier A0 is grounded; the first input end of the amplifier A0 is connected to the reference voltage; the second input end of the amplifier A0 is connected to the feedback node of the resistor divider 400; the output end of the amplifier A0 is connected to the control end of the first transistor M1; the first input power supply circuit 200 and the first bypass power supply circuit 300 are connected in parallel between the first end of the first transistor M1 and the output end of the low voltage difference linear regulator LDO output voltage; the second end of the first transistor M1 is grounded; the first capacitor C1 and the resistor divider 400 are respectively connected between the output end of the LDO output voltage and the ground; wherein, the feedback voltage VFB is output from the feedback node.

[0068] The first input power supply circuit 200 and the first bypass power supply circuit 300 are respectively configured as follows: the amplifier A0 controls the conduction current of the first transistor M1 by comparing the feedback voltage VFB of the LDO output voltage and the reference voltage VREF. When the first bypass power supply circuit 300 is controlled to be turned on, the first input power supply circuit 200 is turned off, and the LDO output voltage is powered by the first bypass power supply circuit 300; when the first input power supply circuit 200 is controlled to be turned on, the first bypass power supply circuit 300 is turned off, and the LDO output voltage is powered by the first input power supply circuit 200. The standby power supply circuit 100 provides the amplifier A0 with normal operation.

[0069] In the technical solution provided by the embodiment of the present disclosure, the linear regulator includes a standby power supply circuit 100, an amplifier A0, a first transistor M1, a first input power supply circuit 200, a first bypass power supply circuit 300, a first capacitor C1 and a resistor divider 400, wherein the first input power supply circuit 200 and the first bypass power supply circuit 300 are connected in parallel between the first end of the first transistor M1 and the output end of the output voltage VCC of the low voltage difference linear regulator LDO, and the amplifier A0 controls the conduction current of the first transistor M1 by comparing the feedback voltage VFB of the LDO output voltage and the reference voltage VREF. When the first bypass power supply circuit 300 is controlled to be turned on, the first input power supply circuit 200 is turned off, and the LDO output voltage VCC is powered by the first bypass power supply circuit 300; when the first input power supply circuit 200 is controlled to be turned on, the first bypass power supply circuit 300 is turned off, and the LDO output voltage VCC is powered by the first input power supply circuit 200. The LDO includes an amplifier A0 and a first transistor M1, and connects a first input power supply circuit 200 and a first bypass power supply circuit 300 in parallel between a first end of the first transistor M1 and an output end of an output voltage VCC of the low voltage difference linear regulator LDO. The first input power supply circuit 200 and the first bypass power supply circuit 300 are controlled to be turned on or off, so as to realize the power supply to the LDO output voltage. Compared with the bypass power supply scheme in the related art, the amplifier A0 can adjust the current of the first transistor M1 by comparing the feedback voltage VFB of the LDO output voltage and the reference voltage VREF, so as to realize the adjustment of the bypass power supply voltage. Moreover, there is only one first capacitor C1 with a large capacitance. Compared with the dual low voltage difference linear regulator scheme in the related art, in the case where the LDO generally requires an additional pin to be connected to an off-chip capacitor, the additional chip pin can be avoided, so as to adapt to more application scenarios and also reduce the chip area.

[0070] In the embodiments of the present disclosure, Figure 4As shown, optionally, the standby power supply circuit includes a second input power supply circuit 101, a second bypass power supply circuit 102 and a second capacitor C2; wherein the second input power supply circuit 101 is connected in parallel with the second bypass power supply circuit 102; the output end of the second input power supply circuit 101 and the output end of the second bypass power supply circuit 102 are respectively connected to the positive power supply end of the amplifier A0; the second capacitor C2 is connected between the output end of the second bypass power supply circuit 102 and the ground; the second input power supply circuit 101 and the second bypass power supply circuit 102 are configured to: use the higher of the output voltages of the second input power supply circuit 101 and the second bypass power supply circuit 102 as the output voltage of the standby power supply circuit.

[0071] The second capacitor C2 has a function of voltage stabilization and a small capacitance value. Since the second input power circuit 101 and the second bypass power circuit 102 are connected in parallel, and their output terminals are both connected to the positive power terminal of the amplifier A0, it can be configured to use the higher output voltage of the second input power circuit 101 and the second bypass power circuit 102 as the output voltage VSTBY of the standby power circuit.

[0072] Specific, optional, such as Figure 4 As shown, the second input power circuit 101 includes a first resistor R1, a first source follower, a first voltage regulator diode D1 and a third capacitor C3, and the first source follower includes a twelfth transistor M12 and a thirteenth transistor M13.

[0073] Wherein, the first end of the first resistor R1 and the first end of the twelfth transistor M12 are connected to the input power source VIN;

[0074] The second end of the first resistor R1, the negative end of the first voltage zener diode D1, and the first end of the third capacitor C3 are respectively connected to the control end of the twelfth transistor M12, and are respectively connected to the control end of the thirteenth transistor M13; the second end of the twelfth transistor M12 is connected to the second end of the thirteenth transistor M13, and the first end of the thirteenth transistor M13 serves as the output end of the second input power supply circuit; the positive end of the first voltage zener diode D1 and the second end of the third capacitor C3 are respectively grounded.

[0075] Among them, the twelfth transistor M12 can be an N-type metal-oxide-semiconductor (MOS) tube, and the thirteenth transistor M13 can be an N-type MOS tube. The second input power circuit can receive the voltage of the input power supply VIN; the control signal VSTBY_GATE1 is generated through the first voltage zener diode D1, and the voltage of the control end of the twelfth transistor M12 and the thirteenth transistor M13 is controlled by the control signal VSTBY_GATE1 so that it will not be higher than the voltage of the input power supply VIN. Specifically, when the voltage across the first voltage zener diode D1 is small, the first voltage zener diode D1 is turned off. When the voltage across the first voltage zener diode D1 is greater than a voltage value, the first voltage zener diode D1 is turned on, and the voltage at the negative end of the first voltage zener diode D1 can be maintained at a fixed value. Therefore, when the voltage of VIN is small, the voltage of the control signal VSTBY_GATE1 is the same as the voltage of VIN. When the voltage of VIN is greater than a voltage value, the first voltage zener diode D1 is turned on, and the voltage of the control signal VSTBY_GATE1 remains unchanged.

[0076] Specific, optional, such as Figure 4 As shown, the second bypass power supply circuit 102 includes: a second resistor R2, a second source follower, a second voltage regulator diode D2 and a fourth capacitor C4, wherein the second source follower includes a fourteenth transistor M14 and a fifteenth transistor M15.

[0077] Among them, the first end of the second resistor R2 and the first end of the fourteenth transistor M14 are connected to the second bypass voltage end; the second end of the second resistor R2, the negative end of the second voltage stabilizing diode D2, and the first end of the fourth capacitor C4 are respectively connected to the control end of the fourteenth transistor M14, and are respectively connected to the control end of the fifteenth transistor M15; the second end of the fourteenth transistor M14 is connected to the second end of the fifteenth transistor M15, and the first end of the fifteenth transistor M15 serves as the output end of the second bypass power supply circuit; the positive end of the second voltage stabilizing diode D2 and the second end of the fourth capacitor C4 are respectively grounded.

[0078] The architecture of the second bypass power supply circuit 102 is similar to that of the second input power supply circuit 101, and the circuit principle is also similar. The fourteenth transistor M14 and the fifteenth transistor M15 can be N-type MOS tubes. The second bypass power supply circuit 102 can receive the voltage of the bypass power supply BYP; generate a control signal VSTBY_GATE2 through the second voltage stabilizing diode D2, and control the voltage of the control end of the fourteenth transistor M14 and the fifteenth transistor M15 through the control signal VSTBY_GATE2 so that it will not be higher than the voltage of the bypass power supply BYP.

[0079] In the standby power supply circuit, the body diodes of the first source follower and the second source follower are reversely connected, that is, the back-to-back connection is not conductive. For example, the body diodes of the fourteenth transistor M14 and the fifteenth transistor M15 are reversely connected, that is, the back-to-back connection is not conductive, which can prevent backflow.

[0080] In the embodiment of the present disclosure, optionally, Figure 4 As shown, it may further include a first comparator A1, a second comparator A2, a NOR gate F1 and a first inverter In1.

[0081] The positive power supply terminal of the first comparator A1 and the positive power supply terminal of the second comparator A2 are respectively connected to the output terminal of the second input power supply circuit 101 and the output terminal of the second bypass power supply circuit 102; the negative power supply terminal of the first comparator A1 and the negative power supply terminal of the second comparator A2 are respectively grounded;

[0082] A first comparator A1, a first input terminal connected to the bypass power supply BYP, a second input terminal connected to the input power supply VIN, an output terminal connected to the first input terminal of the NOR gate, for comparing the bypass voltage provided by the bypass power supply BYP with the input voltage provided by the input power supply VIN, and outputting a signal;

[0083] The second comparator A2 has a first input terminal connected to the bypass power supply BYP and a second input terminal connected to the reference voltage VREF; an output terminal connected to the second input terminal of the NOR gate, and is used to compare the voltage provided by the bypass power supply BYP and the reference voltage VREF, and output a signal; the NOR gate F1 is used to select the output signals of the first comparator A1 and the second comparator A2, and output a first control signal SEL1; the first inverter In1 is used to convert the first control signal SEL1 into the second control signal SEL2.

[0084] In the embodiment of the present disclosure, optionally, Figure 4 As shown, it also includes a level converter Level-shifter and a second inverter In2; wherein the level converter Level-shifter is connected between the LDO output voltage and the ground; the level converter Level-shifter is used to convert the first control signal SEL1 into the third control signal SEL3, or convert the second control signal SEL2 into the fourth control signal SEL4; the second inverter In2 is used to convert the third control signal SEL3 into the fourth control signal SEL4, or convert the fourth control signal SEL4 into the third control signal SEL3.

[0085] Wherein, if the voltage of the bypass power supply BYP is greater than the reference voltage VREF, or the voltage of the bypass power supply BYP is greater than the voltage of the input power supply VIN, the first control signal SEL1=L, the second control signal SEL2=H, that is, the first control signal SEL1 is a low level signal, and the second control signal SEL2 is a high level signal, at this time, the second bypass power supply circuit 102 is selected as the power supply branch of the output voltage VSTBY of the standby power supply circuit. If both conditions are not met, SEL1=H, SEL2=L, and the second input power supply circuit 101 can be selected as the power supply branch of the output voltage VSTBY of the standby power supply circuit. Wherein, the first control signal SEL1 and the second control signal SEL2 are transmitted to the level converter (Level-shifter) of the LDO output voltage (VCC) voltage domain, and the third control signal SEL3 and the fourth control signal SEL4 of the VCC voltage domain are output, and the third control signal SEL3 or the fourth control signal SEL4 can be converted into the corresponding fourth control signal SEL4 and the third control signal SEL3 through the second inverter In2.

[0086] It should be noted that the first control signal, the second control signal, the third control signal and the fourth control signal may be obtained by other external means, for example, by external signal simulation technology.

[0087] In the embodiment of the present disclosure, optionally, Figure 4 As shown, the first bypass power supply circuit includes: a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6;

[0088] The first end of the second transistor M2 is connected to the second end of the third transistor M3; the second end of the second transistor M2 is connected to the first end of the first transistor M1; the control end of the second transistor M2 inputs the first control signal SEL1;

[0089] The control end of the fourth transistor M4, the first end of the fourth transistor M4 and the control end of the fifth transistor M5 are respectively connected to the first end of the third transistor M3; the control end of the third transistor M3 inputs the second control signal SEL2; the second end of the fourth transistor M4 and the second end of the fifth transistor M5 are respectively connected to the bypass power supply BYP;

[0090] The sixth transistor M6 has a first end connected to the first end of the fifth transistor M5 , a second end connected to the output end of the LDO output voltage, and a control end inputting the third control signal SEL3 .

[0091] The second transistor M2 , the fourth transistor M4 , the fifth transistor M5 and the sixth transistor M6 may be P-type MOS transistors, and the third transistor M3 may be an N-type MOS transistor.

[0092] In the embodiments of the present disclosure, Figure 4 As shown, the first input power circuit includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11;

[0093] The seventh transistor M7 has a first end connected to the second end of the eighth transistor M8; a second end connected to the first end of the first transistor M1; and a control end inputting a second control signal SEL2;

[0094] The control end and the first end of the ninth transistor M9 and the control end of the tenth transistor M10 are respectively connected to the first end of the eighth transistor M8; the control end of the eighth transistor M8 inputs the first control signal SEL1; the second end of the ninth transistor M9 and the second end of the tenth transistor M10 are respectively connected to the input power supply VIN;

[0095] The eleventh transistor M11 has a first end connected to the first end of the tenth transistor M10 , a second end connected to the output end of the LDO output voltage VCC, and a control end inputting the fourth control signal SEL4 .

[0096] The seventh transistor M7 , the ninth transistor M9 , the tenth transistor M10 and the eleventh transistor M11 may be P-type MOS transistors, and the eighth transistor M8 may be an N-type MOS transistor.

[0097] In the embodiment of the present disclosure, optionally, the resistor divider includes a third resistor R3 and a fourth resistor R4; the third resistor R3 and the fourth resistor R4 are connected in series; and the feedback node is set between the third resistor R3 and the fourth resistor R4.

[0098] In the embodiment of the present disclosure, the control implementation of the LDO can be: the amplifier A0 receives the reference voltage VREF and the feedback voltage VFB fed back by the feedback node of the resistor divider, compares the reference voltage VREF and the feedback voltage VFB, and generates a drive control signal according to the error signal between the two to adjust the conduction degree of the first transistor M1, thereby adjusting the conduction current of the first transistor M1. When the first input power supply circuit is turned on, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are turned on, the second transistor M2, the third transistor M3 and the fourth transistor M4 are turned off, and the current of the first transistor M1 flows through the ninth transistor M9, wherein the tenth transistor M10 and the ninth transistor M9 are in a current mirror structure, the tenth transistor M10 and the ninth transistor M9 have different sizes, the size of the tenth transistor M10 is larger than the ninth transistor M9, and the tenth transistor M10 can proportionally mirror-amplify the on-current of the ninth transistor M9 and supply power to the output voltage VCC of the LDO; when the first bypass power supply circuit is turned on, the second transistor M2, the third transistor M3 and the fourth transistor M4 are turned on, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are turned off, and the current of the first transistor M1 flows through the fourth transistor M4, and the fifth transistor M5 proportionally mirror-amplifies the on-current of the fourth transistor M4 and supplies power to the output voltage VCC of the LDO. The fourth transistor M4 and the fifth transistor M5 form a current mirror structure.

[0099] In this embodiment, the conduction of the eleventh transistor M11 is controlled by the fourth control signal SEL4, and the conduction of the sixth transistor M6 is controlled by the third control signal SEL3. When the output voltage VCC of the LDO is greater than the voltage of the bypass power supply BYP, the potential of the third control signal SEL3 needs to be not less than the potential of VCC to effectively control the sixth transistor M6 to be turned off, so the first control signal SEL1 needs to be converted into a control signal below the VCC voltage threshold. Similarly, the second control signal SEL2 needs to be converted into a control signal below the VCC voltage threshold.

[0100] In this embodiment, the body diodes of the seventh transistor M7 and the eighth transistor M8 are reversely connected, that is, the back-to-back connection is not conductive, and when the first control signal SEL1 and the second control signal SEL2 turn off their channels, the seventh transistor M7 and the eighth transistor M8 form a branch on both sides, that is, whether the potential on the first transistor M1 side is high or the potential on the ninth transistor M9 side is high, current backflow can be prevented, so this branch can prevent bidirectional backflow. The second transistor M2 and the third transistor M3 branches are similar.

[0101] In this embodiment, the body diodes of the tenth transistor M10 and the eleventh transistor M11 are connected back to back and are not conducting. When the bypass power supply BYP is selected, the fourth control signal SEL4 is pulled up to the VCC potential. When the LDO output voltage VCC is higher than the voltage of the input power supply VIN, the channel of the eleventh transistor M11 is turned off, which can prevent the current from the LDO output voltage to the voltage of VIN from being reversed. Since the first control signal SEL1 and the second control signal SEL2 turn off the branch where the seventh transistor M7 and the eighth transistor M8 are located, the channels of the ninth transistor M9 and the tenth transistor M10 are also turned off, which can prevent the current from the voltage of the input power supply VIN to the LDO output voltage from being reversed. At this time, the branch where the tenth transistor M10 and the eleventh transistor M11 are located can prevent bidirectional reverse injection. The situation of the fifth transistor M5 and the sixth transistor M6 branch is similar.

[0102] In this embodiment, Figure 5 : is a timing diagram of each signal in the embodiment of the present disclosure. Among them, each signal includes the voltage of the input power supply VIN, the voltage of the bypass power supply BYP, the output voltage VSTBY of the standby power supply circuit, the LDO output voltage VCC, the first control signal SEL1, the second control signal SEL2, the third control signal SEL3 and the fourth control signal SEL4. When the voltage bias of the input power supply VIN is high and the voltage bias of the bypass power supply BYP is low, the output voltage VSTBY of the standby power supply circuit and the LDO output voltage VCC are charged by the input power supply VIN, and will not be fed back to the bypass power supply BYP.

[0103] When the voltage bias of the bypass power supply BYP is high and the voltage bias of the input power supply VIN is low, the output voltage VSTBY of the standby power supply circuit and the LDO output voltage VCC are charged by the bypass power supply BYP and will not be fed back to the input power supply VIN.

[0104] When the voltage of the input power supply VIN is biased high first and the voltage of the bypass power supply BYP is biased high later, the output voltage VSTBY of the standby power supply circuit and the LDO output voltage VCC are first charged by the input power supply VIN and will not be fed back to the bypass power supply BYP. After the voltage of the bypass power supply BYP is biased high, since the voltage of the input power supply VIN is higher than the voltage of the bypass power supply BYP, the output voltage VSTBY of the standby power supply circuit is still powered by the input power supply VIN, and its load is relatively small. The LDO output voltage VCC is no longer charged by the high voltage input power supply VIN, but is instead powered by the lower voltage bypass power supply BYP to reduce power loss.

[0105] When the voltage of the bypass power supply BYP is biased high first and the voltage of the input power supply VIN is biased high later, the output voltage VSTBY of the standby power supply circuit and the LDO output voltage VCC are first charged by the bypass power supply BYP and will not be fed back to the input power supply VIN. After the voltage of the input power supply VIN is biased high, since the voltage of the input power supply VIN is higher than the voltage of the bypass power supply BYP, the output voltage VSTBY of the standby power supply circuit becomes powered by the input power supply VIN, and its load is smaller. The LDO output voltage VCC is still powered by the bypass power supply BYP with a lower voltage to maintain low power loss.

[0106] Compared with the bypass power supply solution in the related art, the technical solution provided by the embodiment of the present disclosure can adjust the bypass power supply voltage by adjusting the current of the first transistor, and is suitable for the situation where the bypass power supply voltage does not match the voltage required by the internal circuit of the chip.

[0107] Compared with the dual low-dropout linear regulator solution in the prior art, the embodiment of the present disclosure has only one LDO loop, that is, a loop composed of an amplifier, a first transistor, a first input power circuit or a first bypass power circuit, a first capacitor, and a resistor divider, etc. Only a large-capacitance off-chip capacitor is required to stabilize the loop, and no additional chip pins are required, which can be applied to more application scenarios. In the embodiment of the present disclosure, the amplifier and the first transistor can work for the first bypass power circuit and the first input power circuit at the same time, reducing the chip area.

[0108] Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A low voltage dropout linear regulator, characterized in that: include: A standby power supply circuit, an amplifier, a first transistor, a first input power supply circuit, a first bypass power supply circuit, a first capacitor, and a resistor divider; The output end of the standby power supply circuit is connected to the positive power supply end of the amplifier, and the negative power supply end of the amplifier is grounded; The first input terminal of the amplifier is connected to a reference voltage, the second input terminal of the amplifier is connected to a feedback node of a resistor divider, and the output terminal of the amplifier is connected to a control terminal of the first transistor; The first input power supply circuit and the first bypass power supply circuit are connected in parallel between the first end of the first transistor and the output end of the output voltage of the low-dropout linear regulator LDO, and the second end of the first transistor is grounded; The first capacitor and the resistor divider are respectively connected between the output terminal of the LDO output voltage and the ground; The first input power supply circuit and the first bypass power supply circuit are respectively configured as follows: the amplifier controls the on-current size of the first transistor by comparing the feedback voltage of the LDO output voltage and the reference voltage; when the first bypass power supply circuit is controlled to be turned on, the first input power supply circuit is turned off, and the LDO output voltage is powered by the first bypass power supply circuit; when the first input power supply circuit is controlled to be turned on, the first bypass power supply circuit is turned off, and the LDO output voltage is powered by the first input power supply circuit.

2. The voltage stabilizer according to claim 1, characterized in that: The first bypass power supply circuit includes: a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; The first end of the second transistor is connected to the second end of the third transistor, the second end of the second transistor is connected to the first end of the first transistor, and the control end of the second transistor inputs a first control signal; The control end of the fourth transistor, the first end of the fourth transistor and the control end of the fifth transistor are respectively connected to the first end of the third transistor; the control end of the third transistor inputs a second control signal; The second end of the fourth transistor and the second end of the fifth transistor are respectively connected to a bypass power supply; The first end of the sixth transistor is connected to the first end of the fifth transistor, the second end of the sixth transistor is connected to the output end of the LDO output voltage, and the control end of the sixth transistor inputs a third control signal.

3. The voltage stabilizer according to claim 1, characterized in that: The first input power circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor; The first end of the seventh transistor is connected to the second end of the eighth transistor; the second end of the seventh transistor is connected to the first end of the first transistor; the control end of the seventh transistor inputs a second control signal; The control terminal and the first terminal of the ninth transistor and the control terminal of the tenth transistor are respectively connected to the first terminal of the eighth transistor; the control terminal of the eighth transistor inputs a first control signal; The second end of the ninth transistor and the second end of the tenth transistor are respectively connected to an input power supply; The first end of the eleventh transistor is connected to the first end of the tenth transistor, the second end of the eleventh transistor is connected to the output end of the LDO output voltage, and the control end of the eleventh transistor inputs a fourth control signal.

4. The voltage stabilizer according to claim 1, characterized in that: The standby power supply circuit includes a second input power supply circuit, a second bypass power supply circuit and a second capacitor; The second input power circuit is connected in parallel with the second bypass power circuit; the output end of the second input power circuit and the output end of the second bypass power circuit are respectively connected to the positive power end of the amplifier; The second capacitor is connected between the output terminal of the second bypass power supply circuit and ground; The second input power supply circuit and the second bypass power supply circuit are configured to use a higher output voltage of the second input power supply circuit and the second bypass power supply circuit as an output voltage of the standby power supply circuit.

5. The voltage stabilizer according to claim 4, characterized in that: The second input power circuit includes a first resistor, a first source follower, a first voltage regulator diode and a third capacitor; the first source follower includes a twelfth transistor and a thirteenth transistor; The first end of the first resistor and the first end of the twelfth transistor are connected to an input power supply; The second end of the first resistor, the negative terminal of the first voltage stabilizing diode, and the first end of the third capacitor are respectively connected to the control end of the twelfth transistor, and are respectively connected to the control end of the thirteenth transistor; The second end of the twelfth transistor is connected to the second end of the thirteenth transistor, and the first end of the thirteenth transistor serves as the output end of the second input power circuit; The positive terminal of the first voltage stabilizing diode and the second terminal of the third capacitor are grounded respectively.

6. The voltage stabilizer according to claim 5, characterized in that: The second bypass power supply circuit includes: a second resistor, a second source follower, a second voltage regulator diode and a fourth capacitor; the source follower includes a fourteenth transistor and a fifteenth transistor; The first end of the second resistor and the first end of the fourteenth transistor are connected to a bypass power supply; The second end of the second resistor, the negative terminal of the second voltage stabilizing diode, and the first end of the fourth capacitor are respectively connected to the control end of the fourteenth transistor, and are respectively connected to the control end of the fifteenth transistor; The second end of the fourteenth transistor is connected to the second end of the fifteenth transistor, and the first end of the fifteenth transistor serves as the output end of the second bypass power supply circuit; The positive terminal of the second voltage stabilizing diode and the second terminal of the fourth capacitor are grounded respectively.

7. The voltage stabilizer according to claim 6, characterized in that: Also includes a first comparator, a second comparator, a NOR gate and a first inverter; The positive power supply terminal of the first comparator and the positive power supply terminal of the second comparator are respectively connected to the output terminal of the second input power supply circuit, and are respectively connected to the output terminal of the second bypass power supply circuit; The negative power supply terminal of the first comparator and the negative power supply terminal of the second comparator are grounded respectively; The first comparator has a first input terminal connected to the bypass power supply, a second input terminal inputting the input power supply, and an output terminal connected to the first input terminal of the NOR gate, and is used to compare the bypass voltage output by the bypass power supply with the input voltage provided by the input power supply, and output a signal; The second comparator has a first input terminal connected to a bypass power supply and a second input terminal connected to a reference voltage; The output end is connected to the second input end of the NOR gate, and is used to compare the bypass voltage provided by the bypass power supply with the reference voltage and output a signal; The NOR gate is used to select the output signals of the first comparator and the second comparator, and output a first control signal; The first inverter is used to convert the first control signal into a second control signal.

8. The voltage stabilizer according to claim 7, characterized in that: Also included is a level shifter and a second inverter; The level converter is connected between the LDO output voltage and ground; The level converter is used to convert the first control signal into a third control signal, or convert the second control signal into a fourth control signal; The second inverter is used to convert the third control signal into a fourth control signal, or convert the fourth control signal into a third control signal.

9. The voltage stabilizer according to claim 2, characterized in that: The second transistor, the fourth transistor, the fifth transistor and the sixth transistor are P-type MOS transistors; the first transistor and the third transistor are N-type MOS transistors.

10. The voltage stabilizer according to claim 3, characterized in that: The seventh transistor, the ninth transistor, the tenth transistor and the eleventh transistor are P-type MOS transistors, and the eighth transistor is an N-type MOS transistor.

Images