Voltage source circuit and Micro-LED drive circuit

Abstract

The invention discloses a voltage source circuit and a Micro-LED drive circuit, and the voltage source circuit is characterized in that the source end of a power tube is the input end of the voltage source circuit, and is connected with a power supply; the drain end of the power tube is the output end of the voltage source circuit and outputs an output voltage; the grid end of the power tube is connected with the output end of the amplifier, the resistance feedback network is connected between the drain end of the power tube and the input end of the amplifier, the amplifier, the power tube and the resistance feedback network are connected to form a negative feedback loop, and the amplifier is also connected with the power supply. And the full-blocking feed-forward frequency compensation module is connected between the drain end of the power tube and the amplifier. According to the voltage source circuit, the effect of traditional Miller compensation is achieved, a full-blocking feed-forward path can be achieved, and the voltage source circuit has better stability. When the LED driving circuit is applied to the Micro-LED driving circuit, the anti-interference capability of the Micro-LED driving circuit can be improved, the work is more stable, and the color uniformity is better.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a voltage source circuit and a Micro-LED driving circuit. Background Art

[0002] LDO (Low-dropout regulator) is one of the important components of SOC (System on Chip). Its main function is to provide a voltage source for the ideal power supply voltage for digital-to-analog converters, voltage-controlled oscillators, etc. Since the load of LDO changes dynamically, the output current of LDO also changes dynamically. LDO forms negative feedback through operational amplifiers, power tubes, feedback circuits, etc., so frequency compensation is very important for LDO. Among the existing technologies, the most common compensation method is Miller compensation, but the disadvantage of this compensation method is that the stability is still average. Summary of the invention

[0003] The purpose of this application is to provide a voltage source circuit and a Micro-LED driving circuit with good stability.

[0004] To achieve the above-mentioned purpose, the present application provides a voltage source circuit, which includes: an amplifier, a power tube, a resistor feedback network, and a fully blocked feedforward frequency compensation module; the source end of the power tube is the input end of the voltage source circuit, which is connected to a power supply; the drain end of the power tube is the output end of the voltage source circuit, which outputs an output voltage; the gate end of the power tube is connected to the output end of the amplifier, the resistor feedback network is connected between the drain end of the power tube and the input end of the amplifier, the amplifier, the power tube, and the resistor feedback network are connected to form a negative feedback loop, the amplifier is also connected to the power supply and powered by the power supply, and the fully blocked feedforward frequency compensation module is connected between the drain end of the power tube and the amplifier.

[0005] In one embodiment, the fully blocked feedforward frequency compensation module includes a ninth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, a resistance unit, and a second capacitor. The source end of the ninth PMOS tube is connected to a power supply, the gate end of the ninth PMOS tube is connected to a second P-type bias voltage, the drain end of the ninth PMOS tube is connected to the drain end of the sixth NMOS tube, the gate end of the sixth NMOS tube is connected to the drain end of the power tube, the source end of the sixth NMOS tube is connected to the drain end of the seventh NMOS tube, the gate end of the seventh NMOS tube is connected to the second N-type bias voltage, the source end of the seventh NMOS tube is connected to the ground, the source end of the sixth NMOS tube is also connected to one end of the resistance unit, the other end of the resistance unit is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the amplifier.

[0006] In one embodiment, the resistance unit includes a second hundred resistor and a fifteenth PMOS tube, one end of the second hundred resistor is one end of the resistance unit, the other end of the second hundred resistor is connected to the source end of the fifteenth PMOS tube, the drain end of the fifteenth PMOS tube is the other end of the resistance unit, the gate end of the fifteenth PMOS tube is connected to the ground, and the fifteenth PMOS tube is biased in the deep linear region.

[0007] In one embodiment, the fully blocked feedforward frequency compensation module further includes an eighth resistor, and the gate end of the ninth PMOS tube is not connected to the second P-type bias voltage, but is connected to the drain end of the ninth PMOS tube via the eighth resistor.

[0008] In one embodiment, the amplifier includes a two-stage amplification structure, wherein the first-stage amplification structure includes a third PMOS tube, a fourth PMOS tube, a second NMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a second resistor, and a third resistor. The source end of the third PMOS tube and the source end of the fourth PMOS tube together constitute a bias current input end of the amplifier to receive a bias current. The gate end of the third PMOS tube is the first input end of the amplifier and is connected to the resistor feedback network. The gate end of the fourth PMOS tube is the second input end of the amplifier and receives a reference voltage. The drain end of the fourth PMOS tube is connected to the drain end of the second NMOS tube and the drain end of the second NMOS tube. The gate end of the S tube, the gate end of the first NMOS tube, the gate end of the second NMOS tube, and the gate end of the third NMOS tube are all connected and receive the same bias voltage, the source end of the second NMOS tube is connected to the drain end of the second NMOS tube, the source end of the second NMOS tube is connected to the ground via the second resistor, the source end of the third NMOS tube is connected to the ground via the third resistor, the drain end of the third NMOS tube is connected to the source end of the first NMOS tube, the drain end of the first NMOS tube is connected to the drain end of the fourth PMOS tube, the drain end of the fourth PMOS tube is the first-stage output node of the amplifier, and the source end of the first NMOS tube is connected to the other end of the second capacitor.

[0009] In one embodiment, the second-stage amplification structure includes a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a fourth resistor, and a fifth resistor. The source end of the fifth PMOS tube and the source end of the sixth PMOS tube are both connected to a power supply. The gate end of the fifth PMOS tube is connected to the gate end of the sixth PMOS tube and the drain end of the fifth PMOS tube. The drain end of the fifth PMOS tube is connected to the drain end of the fourth NMOS tube. The gate end of the fourth NMOS tube is connected to the drain end of the fourth PMOS tube. The source end of the fourth NMOS tube is connected to the ground via the fourth resistor. The source end of the fifth NMOS tube is connected to the ground via the fifth resistor. The gate end of the fifth NMOS tube also receives the bias voltage. The drain end of the fifth NMOS tube is connected to the drain end of the sixth PMOS tube. The drain end of the sixth PMOS tube is the second-stage output node of the amplifier and also serves as the output end of the amplifier, and is connected to the gate end of the power tube.

[0010] In one embodiment, the amplifier further includes a filter capacitor and a filter resistor, the gate terminal of the fourth PMOS tube is connected to the ground via the filter capacitor, and the gate terminal of the fourth PMOS tube receives the reference voltage via the filter resistor.

[0011] In one embodiment, the voltage source circuit further includes a dynamic feedback current and zero point compensation module, and the dynamic feedback current and zero point compensation module is connected between the bias current input terminal of the amplifier and the output terminal of the amplifier.

[0012] In one embodiment, the dynamic feedback current and zero point compensation module includes a second PMOS tube, a twentieth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a first resistor, and a first capacitor. The source end of the twentieth PMOS tube is connected to a power supply, the drain end of the twentieth PMOS tube is connected to the source end of the second PMOS tube, the drain end of the twentieth PMOS tube is connected to the bias current input end of the amplifier, the gate end of the second PMOS tube and the gate end of the twentieth PMOS tube are both connected to the output end of the amplifier, the source end of the seventh PMOS tube is connected to the power supply via the first resistor, the gate end of the seventh PMOS tube is connected to the gate end of the eighth PMOS tube and the drain end of the seventh PMOS tube, the drain end of the seventh PMOS tube is connected to the output end of the amplifier, the source end of the eighth PMOS tube is connected to the power supply, and the drain end of the eighth PMOS tube is connected to the output end of the amplifier via the first capacitor.

[0013] In one implementation, the dynamic feedback current and zero-point compensation module further includes a seventh resistor, and the source end of the eighth PMOS tube is connected to the power supply via the seventh resistor.

[0014] In one embodiment, the voltage source circuit further includes a capacitor discharge module, and the capacitor discharge module is connected between the amplifier and an output terminal of the voltage source circuit.

[0015] In one embodiment, the capacitor discharge module includes a tenth PMOS tube, an eighth NMOS tube, and a ninth NMOS tube, the source end of the tenth PMOS tube is connected to a power supply, the gate end of the tenth PMOS tube receives a second P-type bias voltage, the drain end of the tenth PMOS tube is connected to the drain end of the eighth NMOS tube, the gate end of the eighth NMOS tube is connected to the drain end of the fifth PMOS tube, the source end of the eighth NMOS tube is connected to the ground, the source end of the ninth NMOS tube is connected to the ground, the gate end of the ninth NMOS tube is connected to the drain end of the tenth PMOS tube, and the drain end of the ninth NMOS tube is connected to the drain end of the power tube.

[0016] In one embodiment, the capacitor discharge module further includes a one hundredth PMOS tube, an eighty-first NMOS tube, and an eighty-second NMOS tube, the drain end of the tenth PMOS tube is connected to the drain end of the eighth NMOS tube via the one hundredth PMOS tube, the source end of the one hundredth PMOS tube is connected to the drain end of the tenth PMOS tube, the drain end of the one hundredth PMOS tube is connected to the drain end of the eighth NMOS tube, the gate end of the one hundredth PMOS tube receives a first P-type bias voltage, the source end of the eighth NMOS tube is connected to ground via the eighty-first NMOS tube and the eighty-second NMOS tube, the drain end of the eighty-first NMOS tube is connected to the source end of the eighth NMOS tube, the source end of the eighty-first NMOS tube is connected to the drain end of the eighty-second NMOS tube, the source end of the eighty-second NMOS tube is connected to ground, and the gate end of the eighty-first NMOS tube and the gate end of the eighty-second NMOS tube are both connected to the gate end of the eighth NMOS tube.

[0017] In one embodiment, the resistor feedback network includes a first feedback resistor and a second feedback resistor, the first feedback resistor and the second feedback resistor are connected in series, one end of the first feedback resistor is connected to the drain end of the power tube, one end of the second feedback resistor is connected to the ground, and the connection point of the first feedback resistor and the second feedback resistor is connected to the gate end of the third PMOS tube.

[0018] In one implementation, the resistor feedback network further includes a second capacitor, and the second capacitor is connected between the drain end of the power tube and a connection point between the first feedback resistor and the second feedback resistor.

[0019] In one embodiment, the voltage source circuit further includes a current and voltage bias module, which includes a second hundredth PMOS tube, a first PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a current source, and a sixth resistor. The source end of the second hundredth PMOS tube and the source end of the twelfth PMOS tube are both connected to a power supply. The gate end of the second hundredth PMOS tube is connected to the gate end of the twelfth PMOS tube, the drain end of the thirteenth PMOS tube, and one end of the sixth resistor, and receives the same second hundredth P-type bias voltage. The drain end of the second hundredth PMOS tube is connected to the source end of the first PMOS tube. The drain end of the first PMOS tube serves as a bias current output end of the current and voltage bias module to output a bias current. The gate end of the first PMOS tube is connected to the gate end of the thirteenth PMOS tube, the other end of the sixth resistor, and the gate end of the thirteenth PMOS tube. The drain ends of the thirteenth NMOS tubes are all connected and receive the same first P-type bias voltage, the source end of the thirteenth PMOS tube is connected to the drain end of the twelfth PMOS tube; the gate end of the thirteenth NMOS tube is all connected to the gate end of the twelfth NMOS tube, the drain end of the twelfth NMOS tube, and the drain end of the fourteenth PMOS tube, and serves as the bias voltage output end of the current and voltage bias module to output the bias voltage, the source end of the thirteenth NMOS tube is connected to the drain end of the eleventh NMOS tube, the gate end of the eleventh NMOS tube is all connected to the gate end of the tenth NMOS tube, the drain end of the tenth NMOS tube, and the source end of the twelfth NMOS tube, and receive the same second hundredth N-type bias voltage, the source end of the eleventh NMOS tube and the source end of the tenth NMOS tube are all connected to the ground, the gate end of the fourteenth PMOS tube receives an enable signal, the source end of the fourteenth PMOS tube is connected to the output end of the current source, and the input end of the current source is connected to the power supply.

[0020] The present application also provides a system-level chip Micro-LED driving circuit, which includes a voltage source module. The voltage source module is the voltage source circuit as described above, which provides power supply voltage for other modules in the Micro-LED driving circuit.

[0021] In summary, the beneficial effects of the present application are as follows: the voltage source circuit of the present application, by setting a fully blocked feedforward frequency compensation module between the output end of the circuit and the amplifier, not only achieves the effect of traditional Miller compensation, but also can achieve a fully blocked feedforward path, completely blocking the noise path from the power supply to the output end of the circuit, avoiding the interference of power supply noise, so it has better stability. The voltage source circuit of the present application is applied to the Micro-LED driving circuit to provide power supply voltage for other modules in the Micro-LED driving circuit, which can improve the anti-interference ability of the Micro-LED driving circuit, make the operation more stable, and improve the color uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A functional structure diagram of a voltage source circuit provided in this application;

[0024] Figure 2 A schematic diagram of a specific circuit structure of a voltage source circuit provided in the first embodiment of the present application;

[0025] Figure 3 A schematic diagram of a specific circuit structure of a voltage source circuit provided in the second embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application.

[0027] See also Figure 1As shown, the present application provides a voltage source circuit, which includes: an amplifier 10, a power tube 20, a resistor feedback network 30, and a fully blocked feedforward frequency compensation module 40; the source end of the power tube 20 is the input end of the voltage source circuit, connected to the power supply Vdd; the drain end of the power tube 20 is the output end of the voltage source circuit, and outputs an output voltage Vout; the gate end of the power tube is connected to the output end of the amplifier 10, the resistor feedback network 30 is connected between the drain end of the power tube 20 and the input end of the amplifier 10, the amplifier 10, the power tube 20, and the resistor feedback network 30 are connected to form a negative feedback loop, the amplifier 10 is also connected to the power supply Vdd, and is powered by the power supply Vdd, and the fully blocked feedforward frequency compensation module 40 is connected between the drain end of the power tube 20 and the amplifier 10.

[0028] The voltage source circuit of the present application, through the fully blocked feedforward frequency compensation module 40, not only achieves the effect of traditional Miller compensation, but also can realize a fully blocked feedforward path, completely blocking the noise path from the power supply to the output end of the circuit, avoiding the interference of power supply noise, so it has better stability.

[0029] For details, please refer to Figure 2 As shown, in the first embodiment, the fully blocked feedforward frequency compensation module 40 (the dotted line frame C portion in the figure) includes a ninth PMOS tube P9, a sixth NMOS tube N6, a seventh NMOS tube N7, a resistor unit, and a second capacitor C200. The source end of the ninth PMOS tube P9 is connected to the power supply Vdd, and the gate end of the ninth PMOS tube P9 is connected to the second P-type bias voltage vbp200 (Note: the P-type bias voltage here does not mean that the bias voltage is P-type, but is for the convenience of distinguishing that the bias voltage is used for the P-type MOS tube, and the N-type bias voltage in the following text is used for the N-type MOS tube, which is specially explained). The ninth PM The drain end of the OS transistor P9 is connected to the drain end of the sixth NMOS transistor N6, the gate end of the sixth NMOS transistor N6 is connected to the drain end of the power transistor 20, the source end of the sixth NMOS transistor N6 is connected to the drain end of the seventh NMOS transistor N7, the gate end of the seventh NMOS transistor N7 is connected to the second N-type bias voltage vbn200, the source end of the seventh NMOS transistor N7 is connected to the ground Gnd, the source end of the sixth NMOS transistor N6 is also connected to one end of the resistance unit, the other end of the resistance unit is connected to one end of the second capacitor C200, and the other end of the second capacitor C200 is connected to the amplifier 10.

[0030] The amplifier 10 (the part except all the dotted line parts and the power tube 20 in the figure) includes a two-stage amplification structure, wherein the first-stage amplification structure includes a third PMOS tube P3, a fourth PMOS tube P4, a second NMOS tube N200, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a second resistor R2, and a third resistor R3. The source end of the third PMOS tube P3 and the source end of the fourth PMOS tube P4 together constitute the bias current input end of the amplifier 10, receiving the bias current (the bias current will be connected to the power supply Vdd, provided by the current and voltage bias module to be described later). The gate end of the third PMOS tube P3 is the first input end of the amplifier 10, connected to the resistor feedback network 30. The gate end of the fourth PMOS tube P4 is the second input end of the amplifier 10, receiving a reference voltage Vref. The drain end of the fourth PMOS tube P4 is connected to the drain end of the second NMOS tube N200, The gate end of the second NMOS transistor N200, the gate end of the first NMOS transistor N1, the gate end of the second NMOS transistor N2, and the gate end of the third NMOS transistor N3 are all connected and receive the same bias voltage (the bias voltage will be connected to the power supply Vdd, provided by the current and voltage bias module to be described later), the source end of the second NMOS transistor N200 is connected to the drain end of the second NMOS transistor N2, the source end of the second NMOS transistor N2 is connected to the ground Gnd via the second resistor R2, the source end of the third NMOS transistor N3 is connected to the ground Gnd via the third resistor R3, the drain end of the third NMOS transistor N3 is connected to the source end of the first NMOS transistor N1, the drain end of the first NMOS transistor N1 is connected to the drain end of the fourth PMOS transistor P4, the drain end of the fourth PMOS transistor P4 is the first-stage output node of the amplifier 10, and the source end of the first NMOS transistor N1 is connected to the other end of the second capacitor C200.

[0031] The fully blocked feedforward frequency compensation module 40 of the present application constructs a zero point of the left half plane, which is used to compensate the first-stage output node of the amplifier 10. Moreover, there is no feedforward path between the output end of the circuit and the amplifier 10, because when there is high-frequency noise in the power supply Vdd, the noise will be transmitted to the first-stage output node of the amplifier 10, the drain end of the fourth PMOS tube P4, which is also the drain end of the first NMOS tube N1, and then transmitted to the source end of the first NMOS tube N1, and the second capacitor C200 is approximately short-circuited, and the noise is transmitted to the resistor unit and is blocked and weakened by the resistor unit. Even if some high-frequency noise reaches the source end of the sixth NMOS tube N6, it cannot be further transmitted to the gate end of the sixth NMOS tube N6, so the noise path from the power supply Vdd to the output end of the circuit is completely blocked. Therefore, the zero point of the right half plane is eliminated, and the phase margin of the circuit is avoided to be reduced by the zero point of the right half plane, and a better power supply rejection ratio is obtained.

[0032] Please refer to Figure 2 and Figure 3 ,exist Figure 2 In the first embodiment shown, the resistor unit only includes the second hundredth resistor R200; Figure 3 In the second embodiment shown, the resistance unit includes a second hundred resistor R200 and a fifteenth PMOS tube P15, one end of the second hundred resistor R200 is one end of the resistance unit, the other end of the second hundred resistor R200 is connected to the source end of the fifteenth PMOS tube P15, the drain end of the fifteenth PMOS tube P15 is the other end of the resistance unit, the gate end of the fifteenth PMOS tube P15 is connected to the ground Gnd, and the fifteenth PMOS tube P15 is biased in the deep linear region. Because the resistance value required by the resistance unit of the present application is relatively high, if only one resistor is selected to serve as it, the resistor needs to occupy a larger chip area; and the MOS tube biased in the deep linear region itself can be regarded as a high resistance resistor, and combined with a smaller resistance resistor to serve as the resistance unit, the chip area can be reduced and the chip cost can be reduced.

[0033] Please refer to the comparison Figure 2 and Figure 3 ,exist Figure 3 In the second embodiment shown, the fully blocked feedforward frequency compensation module 40 further includes an eighth resistor R8, and the gate end of the ninth PMOS tube P9 is not connected to the second P-type bias voltage vbp200, but is connected to the drain end of the ninth PMOS tube P9 via the eighth resistor R8.

[0034] Next, see Figure 2As shown, other structures of the amplifier 10 are further introduced. The second-stage amplification structure includes a fifth PMOS tube P5, a sixth PMOS tube P6, a fourth NMOS tube N4, a fifth NMOS tube N5, a fourth resistor R4, and a fifth resistor R5. The source end of the fifth PMOS tube P5 and the source end of the sixth PMOS tube P6 are both connected to the power supply Vdd, the gate end of the fifth PMOS tube P5 is connected to the gate end of the sixth PMOS tube P6 and the drain end of the fifth PMOS tube P5, the drain end of the fifth PMOS tube P5 is connected to the drain end of the fourth NMOS tube N4, and the gate end of the fourth NMOS tube N4 is connected to the drain end of the fifth PMOS tube P5. The gate terminal of the fifth NMOS tube N5 also receives the bias voltage, and the drain terminal of the fifth NMOS tube N5 is connected to the drain terminal of the sixth PMOS tube P6. The drain terminal of the sixth PMOS tube P6 is the second-stage output node of the amplifier 10, and also serves as the output terminal of the amplifier 10, and is connected to the gate terminal of the power tube 20. The amplifier 10 used in the voltage source circuit of the present application is a push-pull amplifier 10 with a two-stage amplification structure.

[0035] In one embodiment, the amplifier 10 further includes a filter capacitor Clpf and a filter resistor Rlpf, the gate end of the fourth PMOS transistor P4 is connected to the ground Gnd via the filter capacitor Clpf, and the gate end of the fourth PMOS transistor P4 receives the reference voltage Vref via the filter resistor Rlpf. The filter capacitor Clpf and the filter resistor Rlpf form a low-pass filter, which performs filtering processing on the reference voltage Vref received by the second input terminal of the amplifier 10 to ensure the purity of the reference voltage Vref and improve the accuracy of the comparative amplification of the amplifier 10.

[0036] Please refer to Figure 1 As shown, in one embodiment, the voltage source circuit further includes a dynamic feedback current and zero point compensation module 50, and the dynamic feedback current and zero point compensation module 50 is connected between the bias current input terminal of the amplifier 10 and the output terminal of the amplifier 10. The dynamic feedback current and zero point compensation module 50 of the present application not only constructs a zero point that changes with the load current change, but also has a dynamic zero point and feedback mechanism, which can dynamically track the changes of the primary and secondary poles in the loop, has better applicability of frequency compensation, and further improves the stability of the voltage source circuit.

[0037] See also Figure 2As shown, in the first embodiment, the dynamic feedback current and zero compensation module 50 includes a second PMOS tube P2, a twentieth PMOS tube P20, an eighth PMOS tube P8, a first resistor R1, a seventh resistor R7 and a first capacitor C1, the source end of the twentieth PMOS tube P20 is connected to the power supply Vdd, the drain end of the twentieth PMOS tube P20 is connected to the source end of the second PMOS tube P2, the drain end of the twentieth PMOS tube P20 is connected to the bias current input end of the amplifier 10, the gate end of the second PMOS tube P2, the twentieth PMOS tube P8 and the eighth PMOS tube P8 are connected to the bias current input end of the amplifier 10, and the gate end of the second PMOS tube P2, the twentieth PMOS tube P8 and the eighth PMOS tube P8 are connected to the bias current input end of the amplifier 10. The gate ends of the PMOS tube P20 are connected to the output end of the amplifier 10, the source end of the seventh PMOS tube P7 is connected to the power supply Vdd via the first resistor R1, the gate end of the seventh PMOS tube P7 is connected to the gate end of the eighth PMOS tube P8 and the drain end of the seventh PMOS tube P7, the drain end of the seventh PMOS tube P7 is connected to the output end of the amplifier 10, the source end of the eighth PMOS tube P8 is connected to the power supply Vdd, and the drain end of the eighth PMOS tube P8 is connected to the output end of the amplifier 10 via the first capacitor C1.

[0038] The eighth PMOS tube P8 is biased in the linear region, and its resistance changes with the second-stage output node of the amplifier 10. When the load current increases, the pole of this point moves toward the high frequency. At this time, the resistance of the eighth PMOS tube P8 decreases, so the zero point of the structure also moves toward the high frequency. In addition, when the load current increases, the second PMOS tube P2, the twentieth PMOS tube P20, the seventh PMOS tube P7, and the first resistor R1 detect that the load current increases, and then feedback is fed back to the bias current input end of the amplifier 10, and then fed back to the first-stage output node and the second-stage output node of the amplifier 10, and the two poles are pushed to the unit gain bandwidth product, which is conducive to the LDO loop becoming more and more stable as the load current increases. Therefore, compared with the fixed zero pole voltage source circuit of the traditional Miller compensation, the dynamic feedback current and zero point compensation module 50 of the present application has a dynamic zero point and feedback mechanism, which can dynamically track the changes of the primary and secondary poles in the loop and has better applicability of frequency compensation.

[0039] Please refer to the comparison Figure 2 and Figure 3 ,exist Figure 3 In the second embodiment shown, the dynamic feedback current and zero point compensation module 50 further includes a seventh resistor R7, and the source end of the eighth PMOS tube P8 is not directly connected to the power supply Vdd, but is connected to the power supply Vdd via the seventh resistor R7. In this way, it is possible to avoid the situation where the equivalent resistance generated by the eighth PMOS tube P8 is too small, resulting in the dynamic compensation zero point failure.

[0040] Please refer to Figure 1As shown, in one embodiment, the voltage source circuit further includes a capacitor discharge module, which is connected between the amplifier 10 and the output end of the voltage source circuit. The capacitor discharge module detects that the voltage source circuit has an excessive overshoot peak voltage, and opens the output capacitor (also called an off-chip capacitor) discharge path to reduce the overshoot peak voltage and overshoot recovery time.

[0041] See also Figure 2 As shown, in the first embodiment, the capacitor discharge module includes a tenth PMOS tube P10, an eighth NMOS tube N8, and a ninth NMOS tube N9, the source end of the tenth PMOS tube P10 is connected to the power supply Vdd, the gate end of the tenth PMOS tube P10 receives the second P-type bias voltage vbp200, the drain end of the tenth PMOS tube P10 is connected to the drain end of the eighth NMOS tube N8, the gate end of the eighth NMOS tube N8 is connected to the drain end of the fifth PMOS tube P5, the source end of the eighth NMOS tube N8 is connected to the ground Gnd, the source end of the ninth NMOS tube N9 is connected to the ground Gnd, the gate end of the ninth NMOS tube N9 is connected to the drain end of the tenth PMOS tube P10, and the drain end of the ninth NMOS tube N9 is connected to the drain end of the power tube 20.

[0042] The working principle of the capacitor discharge module is that it is triggered when there is a large overshoot voltage in the output voltage, and an additional charge discharge path is provided to the output end (off-chip capacitor), thereby reducing the overshoot voltage. Specifically, when there is a large overshoot in the output voltage Vout, the gate voltage of the eighth NMOS tube N8 drops, so the current generated by the eighth NMOS tube N8 is less than the current generated by the tenth PMOS tube P10, so the gate voltage of the ninth NMOS tube N9 rises, and finally the ninth NMOS tube N9 is turned on to generate a current path to the ground Gnd, discharging the output end (off-chip capacitor) of the LDO, thereby reducing the overshoot voltage. Please refer to compare again. Figure 2 and Figure 3 ,exist Figure 3In the second embodiment shown in the figure, the capacitor discharge module further includes a 100th PMOS tube P100, an 81st NMOS tube N81, and an 82nd NMOS tube N82. The drain end of the tenth PMOS tube P10 is connected to the drain end of the eighth NMOS tube N8 via the 100th PMOS tube P100. The source end of the 100th PMOS tube P100 is connected to the drain end of the tenth PMOS tube P10. The drain end of the 100th PMOS tube P100 is connected to the drain end of the eighth NMOS tube N8. The gate end of the 100th PMOS tube P100 receives a first P-type bias voltage v bp1, the source end of the eighth NMOS tube N8 is connected to the ground Gnd via the eighty-first NMOS tube N81 and the eighty-second NMOS tube N82, the drain end of the eighty-first NMOS tube N81 is connected to the source end of the eighth NMOS tube N8, the source end of the eighty-first NMOS tube N81 is connected to the drain end of the eighty-second NMOS tube N82, the source end of the eighty-second NMOS tube N82 is connected to the ground Gnd, and the gate end of the eighty-first NMOS tube N81 and the gate end of the eighty-second NMOS tube N82 are both connected to the gate end of the eighth NMOS tube N8.

[0043] The 100th PMOS tube P100 and the 10th PMOS tube P10 form a common source and common gate current mirror, and the current is more accurate. The 81st NMOS tube N81, the 82nd NMOS tube N82 and the 8th NMOS tube N8 together increase the gate length and reduce the current of this branch, ensuring that when there is a large overshoot in the output voltage Vout, the current of this branch is less than the current of the branch where the 10th PMOS tube P10 is located, so that the 9th NMOS tube N9 is normally turned on.

[0044] See also Figure 2 and Figure 3 ,exist Figure 2 The first embodiment shown and Figure 3 In the second embodiment shown, the resistor feedback network 30 includes a first feedback resistor Rfb1 and a second feedback resistor Rfb2, the first feedback resistor Rfb1 and the second feedback resistor Rfb2 are connected in series, one end of the first feedback resistor Rfb1 is connected to the drain end of the power tube 20, one end of the second feedback resistor Rfb2 is connected to the ground Gnd, and the connection point of the first feedback resistor Rfb1 and the second feedback resistor Rfb2 is connected to the gate end of the third PMOS tube P3. The resistor feedback network 30 feeds back the load current to the amplifier 10, so that the amplifier 10 dynamically adjusts the gate voltage of the power tube 20 and then dynamically adjusts the input (equivalent on-resistance) of the voltage source circuit to stabilize the output voltage Vout.

[0045] See also Figure 2 and Figure 3,exist Figure 2 The first embodiment shown and Figure 3 In the second embodiment shown, the resistor feedback network 30 further includes a second capacitor C2, and the second capacitor C2 is connected between the drain end of the power tube 20 and the connection point between the first feedback resistor Rfb1 and the second feedback resistor Rfb2. In this way, a zero-pole pair can be constructed here, and the frequency of the pole is higher than the zero point. Setting the zero point near the unity gain bandwidth product can further assist in improving the phase margin.

[0046] Finally, as mentioned earlier, see Figure 2 and Figure 3 ,exist Figure 2 The first embodiment shown and Figure 3In the second embodiment shown, the voltage source circuit also includes a current and voltage bias module to provide bias current and bias voltage for each module in the circuit. The current and voltage bias module includes a second PMOS tube P200, a first PMOS tube P1, a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a thirteenth NMOS tube N13, a current source idc, and a sixth resistor R6. The source end of the second PMOS tube P200 and the source end of the twelfth PMOS tube P12 are both connected to the power supply Vdd, and the gate end of the second PMOS tube P200 is connected to the gate end of the twelfth PMOS tube P14. The gate end of the OS transistor P12, the drain end of the thirteenth PMOS transistor P13, and one end of the sixth resistor R6 are all connected and receive the same second-hundredth P-type bias voltage vbp200. The drain end of the second-hundredth PMOS transistor P200 is connected to the source end of the first PMOS transistor P1. The drain end of the first PMOS transistor P1 serves as the bias current output end of the current and voltage bias module to output the bias current. The gate end of the first PMOS transistor P1 is connected to the gate end of the thirteenth PMOS transistor P13, the other end of the sixth resistor R6, and the drain end of the thirteenth NMOS transistor N13. The thirteenth PMOS tube P13 and the twelfth PMOS tube P12 are connected to each other and receive the same first P-type bias voltage vbp1. The source end of the thirteenth PMOS tube P13 is connected to the drain end of the twelfth PMOS tube P12. The gate end of the thirteenth NMOS tube N13 is connected to the gate end of the twelfth NMOS tube N12, the drain end of the twelfth NMOS tube N12, and the drain end of the fourteenth PMOS tube P14, and serves as the bias voltage output end of the current and voltage bias module to output the bias voltage. The source end of the thirteenth NMOS tube N13 is connected to the drain end of the eleventh NMOS tube N11, and the eleventh NM The gate terminal of the OS transistor N11 is connected to the gate terminal of the tenth NMOS transistor N10, the drain terminal of the tenth NMOS transistor N10, and the source terminal of the twelfth NMOS transistor N12, and receives the same second hundredth N-type bias voltage vbn200, the source terminal of the eleventh NMOS transistor N11 and the source terminal of the tenth NMOS transistor N10 are both connected to the ground Gnd, the gate terminal of the fourteenth PMOS transistor P14 receives an enable signal en, the source terminal of the fourteenth PMOS transistor P14 is connected to the output terminal of the current source idc, and the input terminal of the current source idc is connected to the power supply Vdd.

[0047] The present application also provides a system-on-chip Micro-LED driving circuit, which includes a voltage source module. The voltage source module is the voltage source circuit as described above, which provides power supply voltage for other modules in the Micro-LED driving circuit (such as a digital-to-analog converter or a voltage-controlled oscillator).

[0048] In summary, the beneficial effects of this application are:

[0049] The voltage source circuit of the present application, by setting a fully blocked feedforward frequency compensation module between the output end of the circuit and the amplifier, not only achieves the effect of traditional Miller compensation, but also can realize a fully blocked feedforward path, completely blocking the noise path from the power supply to the output end of the circuit, avoiding the interference of power supply noise, so it has better stability. The voltage source circuit of the present application is applied to the Micro-LED driving circuit to provide power supply voltage for other modules in the Micro-LED driving circuit, which can improve the anti-interference ability of the Micro-LED driving circuit, make the operation more stable, and improve the color uniformity.

[0050] The fully blocked feedforward frequency compensation module of the present application constructs a zero point of the left half plane, which is used to compensate the first-stage output node of the amplifier. Moreover, there is no feedforward path between the output of the LDO and the output of the amplifier, because when there is high-frequency noise in the power supply, the noise will be transmitted to the first-stage output node of the amplifier, the drain end of the fourth PMOS tube, which is also the drain end of the first NMOS tube, and then transmitted to the source end of the first NMOS tube, and the second hundred capacitor is approximately short-circuited, and the noise is transmitted to the resistance unit and is blocked and weakened by the resistance unit. Even if some high-frequency noise reaches the source end of the sixth NMOS tube, it cannot be further transmitted to the gate end of the sixth NMOS tube, so the noise path from the power supply to the output end of the LDO is completely blocked. Therefore, the zero point of the right half plane is eliminated, and the right half plane zero point is avoided from reducing the phase margin of the LDO, which has a better power supply rejection ratio.

[0051] The voltage source circuit of the present application, through the dynamic feedback current and zero point compensation module, not only constructs a zero point that changes with the load current, but also has a dynamic zero point and feedback mechanism, which can dynamically track the changes of the primary and secondary poles in the loop, has better applicability of frequency compensation, and further improves the stability of the voltage source circuit.

[0052] In the dynamic feedback current and zero point compensation module of the present application, the eighth PMOS tube is biased in the linear region, and its resistance changes with the second-stage output node of the amplifier. When the load current increases, the pole of this point moves toward the high frequency. At this time, the resistance of the eighth PMOS tube decreases, so the zero point of the structure also moves toward the high frequency. In addition, when the load current increases, the second PMOS tube, the twentieth PMOS tube, the seventh PMOS tube, and the first resistor detect that the load current increases, and then feedback is fed back to the bias current input terminal of the amplifier, and then fed back to the first-stage output node and the second-stage output node of the amplifier, and the two poles are pushed to the unit gain bandwidth product, which is conducive to the LDO loop becoming more and more stable as the load current increases. Therefore, compared with the fixed zero pole voltage source circuit of the traditional Miller compensation, the dynamic feedback current and zero point compensation module of the present application has a dynamic zero point and feedback mechanism, which can dynamically track the changes of the primary and secondary poles in the loop, and has better applicability of frequency compensation.

[0053] The voltage source circuit of the present application detects excessive overshoot peak voltage in the voltage source circuit through a capacitor discharge module, and opens an output capacitor (also called an off-chip capacitor) discharge path to reduce the overshoot recovery time.

[0054] The resistor feedback network of the present application also includes a second capacitor, which is connected between the drain end of the power tube and the connection point between the first feedback resistor and the second feedback resistor. In this way, a zero-pole pair can be constructed, and the frequency of the pole is higher than the zero point. Setting the zero point near the unity gain bandwidth product can further help improve the phase margin.

[0055] The technical solutions provided by the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A voltage source circuit, characterized in that: The voltage source circuit includes: an amplifier, a power tube, a resistor feedback network, and a fully blocked feedforward frequency compensation module; the source end of the power tube is the input end of the voltage source circuit and is connected to a power supply; the drain end of the power tube is the output end of the voltage source circuit and outputs an output voltage; the gate end of the power tube is connected to the output end of the amplifier, the resistor feedback network is connected between the drain end of the power tube and the input end of the amplifier, the amplifier, the power tube, and the resistor feedback network are connected to form a negative feedback loop, the amplifier is also connected to the power supply and is powered by the power supply, and the fully blocked feedforward frequency compensation module is connected between the drain end of the power tube and the amplifier.

2. The voltage source circuit according to claim 1, characterized in that: The fully blocked feedforward frequency compensation module includes a ninth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, a resistance unit, and a second capacitor. The source end of the ninth PMOS tube is connected to a power supply, the gate end of the ninth PMOS tube is connected to a second P-type bias voltage, the drain end of the ninth PMOS tube is connected to the drain end of the sixth NMOS tube, the gate end of the sixth NMOS tube is connected to the drain end of the power tube, the source end of the sixth NMOS tube is connected to the drain end of the seventh NMOS tube, the gate end of the seventh NMOS tube is connected to the second N-type bias voltage, the source end of the seventh NMOS tube is connected to the ground, the source end of the sixth NMOS tube is also connected to one end of the resistance unit, the other end of the resistance unit is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the amplifier.

3. The voltage source circuit according to claim 2, characterized in that: The resistance unit includes a second hundred resistor and a fifteenth PMOS tube, one end of the second hundred resistor is one end of the resistance unit, the other end of the second hundred resistor is connected to the source end of the fifteenth PMOS tube, the drain end of the fifteenth PMOS tube is the other end of the resistance unit, the gate end of the fifteenth PMOS tube is connected to the ground, and the fifteenth PMOS tube is biased in the deep linear region.

4. The voltage source circuit according to claim 2, characterized in that: The fully blocked feedforward frequency compensation module further includes an eighth resistor, and the gate end of the ninth PMOS tube is not connected to the second P-type bias voltage, but is connected to the drain end of the ninth PMOS tube via the eighth resistor.

5. The voltage source circuit according to claim 2, characterized in that: The amplifier includes a two-stage amplification structure, wherein the first-stage amplification structure includes a third PMOS tube, a fourth PMOS tube, a second NMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a second resistor, and a third resistor. The source end of the third PMOS tube and the source end of the fourth PMOS tube together constitute a bias current input end of the amplifier to receive a bias current. The gate end of the third PMOS tube is the first input end of the amplifier and is connected to the resistor feedback network. The gate end of the fourth PMOS tube is the second input end of the amplifier to receive a reference voltage. The drain end of the fourth PMOS tube is connected to the drain end of the second NMOS tube and the gate end of the second NMOS tube. The gate end of the first NMOS tube, the gate end of the second NMOS tube, and the gate end of the third NMOS tube are all connected and receive the same bias voltage, the source end of the second NMOS tube is connected to the drain end of the second NMOS tube, the source end of the second NMOS tube is connected to the ground via the second resistor, the source end of the third NMOS tube is connected to the ground via the third resistor, the drain end of the third NMOS tube is connected to the source end of the first NMOS tube, the drain end of the first NMOS tube is connected to the drain end of the fourth PMOS tube, the drain end of the fourth PMOS tube is the first-stage output node of the amplifier, and the source end of the first NMOS tube is connected to the other end of the second capacitor.

6. The voltage source circuit according to claim 5, characterized in that: The second-stage amplification structure includes a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a fourth resistor, and a fifth resistor. The source end of the fifth PMOS tube and the source end of the sixth PMOS tube are both connected to a power supply. The gate end of the fifth PMOS tube is connected to the gate end of the sixth PMOS tube and the drain end of the fifth PMOS tube. The drain end of the fifth PMOS tube is connected to the drain end of the fourth NMOS tube. The gate end of the fourth NMOS tube is connected to the drain end of the fourth PMOS tube. The source end of the fourth NMOS tube is connected to the ground via the fourth resistor. The source end of the fifth NMOS tube is connected to the ground via the fifth resistor. The gate end of the fifth NMOS tube also receives the bias voltage. The drain end of the fifth NMOS tube is connected to the drain end of the sixth PMOS tube. The drain end of the sixth PMOS tube is the second-stage output node of the amplifier and also serves as the output end of the amplifier and is connected to the gate end of the power tube.

7. The voltage source circuit according to claim 5, characterized in that: The amplifier further includes a filter capacitor and a filter resistor. The gate end of the fourth PMOS tube is connected to the ground via the filter capacitor. The gate end of the fourth PMOS tube receives the reference voltage via the filter resistor.

8. The voltage source circuit according to claim 6, characterized in that: The voltage source circuit further includes a dynamic feedback current and zero-point compensation module, which is connected between the bias current input terminal of the amplifier and the output terminal of the amplifier.

9. The voltage source circuit according to claim 8, characterized in that: The dynamic feedback current and zero-point compensation module includes a second PMOS tube, a twentieth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a first resistor, and a first capacitor. The source end of the twentieth PMOS tube is connected to a power supply, the drain end of the twentieth PMOS tube is connected to the source end of the second PMOS tube, the drain end of the twentieth PMOS tube is connected to the bias current input end of the amplifier, the gate end of the second PMOS tube and the gate end of the twentieth PMOS tube are both connected to the output end of the amplifier, the source end of the seventh PMOS tube is connected to the power supply via the first resistor, the gate end of the seventh PMOS tube is connected to the gate end of the eighth PMOS tube and the drain end of the seventh PMOS tube, the drain end of the seventh PMOS tube is connected to the output end of the amplifier, the source end of the eighth PMOS tube is connected to the power supply, and the drain end of the eighth PMOS tube is connected to the output end of the amplifier via the first capacitor.

10. The voltage source circuit according to claim 9, characterized in that: The dynamic feedback current and zero-point compensation module further includes a seventh resistor, and the source end of the eighth PMOS tube is connected to the power supply via the seventh resistor.

11. The voltage source circuit according to claim 6, characterized in that: The voltage source circuit further includes a capacitor discharge module, and the capacitor discharge module is connected between the amplifier and an output end of the voltage source circuit.

12. The voltage source circuit according to claim 11, characterized in that: The capacitor discharge module includes a tenth PMOS tube, an eighth NMOS tube, and a ninth NMOS tube. The source end of the tenth PMOS tube is connected to a power supply, the gate end of the tenth PMOS tube receives a second P-type bias voltage, the drain end of the tenth PMOS tube is connected to the drain end of the eighth NMOS tube, the gate end of the eighth NMOS tube is connected to the drain end of the fifth PMOS tube, the source end of the eighth NMOS tube is connected to the ground, the source end of the ninth NMOS tube is connected to the ground, the gate end of the ninth NMOS tube is connected to the drain end of the tenth PMOS tube, and the drain end of the ninth NMOS tube is connected to the drain end of the power tube.

13. The voltage source circuit according to claim 12, characterized in that: The capacitor discharge module also includes a 100th PMOS tube, an 81st NMOS tube, and an 82nd NMOS tube. The drain end of the 100th PMOS tube is connected to the drain end of the 8th NMOS tube via the 100th PMOS tube, the source end of the 100th PMOS tube is connected to the drain end of the 100th PMOS tube, the drain end of the 100th PMOS tube is connected to the drain end of the 8th NMOS tube, the gate end of the 100th PMOS tube receives a first P-type bias voltage, the source end of the 8th NMOS tube is connected to the ground via the 81st NMOS tube and the 82nd NMOS tube, the drain end of the 81st NMOS tube is connected to the source end of the 8th NMOS tube, the source end of the 81st NMOS tube is connected to the drain end of the 82nd NMOS tube, the source end of the 82nd NMOS tube is connected to the ground, and the gate end of the 81st NMOS tube and the gate end of the 82nd NMOS tube are both connected to the gate end of the 80th NMOS tube.

14. The voltage source circuit according to claim 5, characterized in that: The resistor feedback network includes a first feedback resistor and a second feedback resistor, the first feedback resistor and the second feedback resistor are connected in series, one end of the first feedback resistor is connected to the drain end of the power tube, one end of the second feedback resistor is connected to the ground, and the connection point of the first feedback resistor and the second feedback resistor is connected to the gate end of the third PMOS tube.

15. The voltage source circuit according to claim 14, characterized in that: The resistor feedback network also includes a second capacitor connected between the drain end of the power tube and a connection point between the first feedback resistor and the second feedback resistor.

16. The voltage source circuit according to claim 5, characterized in that: The voltage source circuit also includes a current and voltage bias module, which includes a second hundredth PMOS tube, a first PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a current source, and a sixth resistor. The source end of the second hundredth PMOS tube and the source end of the twelfth PMOS tube are both connected to a power supply. The gate end of the second hundredth PMOS tube is connected to the gate end of the twelfth PMOS tube, the drain end of the thirteenth PMOS tube, and one end of the sixth resistor, and receives the same second hundredth P-type bias voltage. The drain end of the second hundredth PMOS tube is connected to the source end of the first PMOS tube. The drain end of the first PMOS tube serves as a bias current output end of the current and voltage bias module to output a bias current. The gate end of the first PMOS tube is connected to the gate end of the thirteenth PMOS tube, the other end of the sixth resistor, and the thirteenth NMOS tube. The drain ends of the OS tubes are all connected and receive the same first P-type bias voltage, the source end of the thirteenth PMOS tube is connected to the drain end of the twelfth PMOS tube; the gate end of the thirteenth NMOS tube is connected to the gate end of the twelfth NMOS tube, the drain end of the twelfth NMOS tube, and the drain end of the fourteenth PMOS tube, and serves as the bias voltage output end of the current and voltage bias module to output the bias voltage, the source end of the thirteenth NMOS tube is connected to the drain end of the eleventh NMOS tube, the gate end of the eleventh NMOS tube is connected to the gate end of the tenth NMOS tube, the drain end of the tenth NMOS tube, and the source end of the twelfth NMOS tube, and receive the same second hundredth N-type bias voltage, the source end of the eleventh NMOS tube and the source end of the tenth NMOS tube are both connected to the ground, the gate end of the fourteenth PMOS tube receives an enable signal, the source end of the fourteenth PMOS tube is connected to the output end of the current source, and the input end of the current source is connected to the power supply.

17. A Micro-LED driving circuit, characterized in that: The Micro-LED driving circuit includes a voltage source module, which is a voltage source circuit as described in any one of claims 1 to 16, and provides power supply voltage for other modules in the Micro-LED driving circuit.

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