Voltage stabilizing circuit, chip and electronic equipment

Abstract

The invention discloses a voltage stabilizing circuit, a chip and electronic equipment. A second low voltage-withstanding module in the voltage stabilizing circuit is respectively connected with the first low voltage-withstanding module and the voltage stabilizing module; the first low-voltage-withstanding module is used for generating a first signal based on a power signal greater than an amplitude threshold and transmitting the first signal to the second low-voltage-withstanding module; the voltage stabilizing module is used for generating a second signal based on the input signal and transmitting the second signal to the second low voltage resistant module; the second low-voltage-withstanding module is used for generating a signal of a low-potential end of the first low-voltage-withstanding module and a signal of a low-potential end of the second low-voltage-withstanding module based on the first signal and the second signal, and the potential difference between a power signal of a high-potential end of the first low-voltage-withstanding module and the signal of the low-potential end of the first low-voltage-withstanding module is smaller than a first reference potential difference; the potential difference between the signal of the high potential end and the signal of the low potential end of the second low voltage resistant module is smaller than the second reference potential difference. According to the invention, the possibility of breakdown of low-voltage-resistant devices in the first low-voltage-resistant module and the second low-voltage-resistant module can be reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic information technology, and in particular to a voltage stabilizing circuit, a chip and an electronic device. Background Art

[0002] In circuit design, in order to reduce the cost of the circuit, low-voltage devices may be used in circuits with a higher amplitude of the power signal. However, since the potential difference between the high potential end and the low potential end that the low-voltage device can withstand is relatively low, if the low-voltage device is used in a circuit with a higher amplitude of the power signal, the potential difference applied to both ends of the low-voltage device may be relatively high, and the low-voltage device may be damaged by the breakdown of the power signal with a higher amplitude. Therefore, there is an urgent need for a voltage stabilizing circuit to protect the low-voltage device from being broken down and damaged in a circuit with a higher amplitude of the power signal. Summary of the invention

[0003] The present application provides a voltage stabilizing circuit, a chip and an electronic device, which can be used to reduce the possibility of breakdown of low-voltage devices in the circuit. The technical solution is as follows:

[0004] On the one hand, the present application provides a voltage stabilizing circuit, characterized in that the voltage stabilizing circuit includes a first low-voltage withstand module, a second low-voltage withstand module and a voltage stabilizing module, the second low-voltage withstand module is connected to the first low-voltage withstand module and the voltage stabilizing module respectively; the first low-voltage withstand module is used to generate a first signal based on an acquired power supply signal, and transmit the first signal to the second low-voltage withstand module, the power supply signal is a signal at a high potential end of the first low-voltage withstand module, and the amplitude of the power supply signal is greater than an amplitude threshold; the voltage stabilizing module is used to generate a second signal based on an acquired input signal, and transmit the second signal to the second low-voltage withstand module; the second low-voltage withstand module is used A signal of a low potential end of a first low voltage withstand module is generated based on a first signal and a second signal, a signal of a low potential end of a second low voltage withstand module is generated based on the first signal and the second signal, a potential difference between a power supply signal and a signal of the low potential end of the first low voltage withstand module is smaller than a first reference potential difference between a high potential end and a low potential end of the first low voltage withstand module, a potential difference between a signal of a high potential end and a signal of a low potential end of the second low voltage withstand module is smaller than a second reference potential difference between a high potential end and a low potential end of the second low voltage withstand module, and the low potential end of the first low voltage withstand module is a high potential end of the second low voltage withstand module.

[0005] In a possible implementation, the voltage stabilization module includes a signal source unit, a feedback unit and an output unit, the feedback unit is connected to the signal source unit and the output unit respectively, the input signal includes a first input signal and a second input signal; the signal source unit is used to generate a first reference signal based on the first input signal and the second input signal, and transmit the first reference signal to the feedback unit; the feedback unit is used to obtain a third input signal, generate a first output signal and a second output signal based on the first reference signal and the third input signal, and transmit the first output signal and the second output signal to the output unit; the output unit is used to generate a second signal based on the first output signal and the second output signal.

[0006] In one possible implementation, the output unit is also used to transmit a second signal to the feedback unit; the feedback unit is also used to adjust the first output signal and the second output signal based on the comparison result of the second signal and the first reference signal to obtain an adjusted first output signal and an adjusted second output signal; the output unit is also used to adjust the second signal based on the adjusted first output signal and the adjusted second output signal.

[0007] In a possible implementation, the voltage stabilization module also includes a current mirror unit, which is connected to the signal source unit and the feedback unit respectively; the signal source unit is also used to transmit a first input signal to the current mirror unit; the current mirror unit is used to generate a third input signal based on the first input signal and transmit the third input signal to the feedback unit; the feedback unit is used to receive the third input signal.

[0008] In a possible implementation, the voltage stabilization circuit also includes a supplementary module, the voltage stabilization module includes a feedback unit and an output unit, the supplementary module is connected to the voltage stabilization module, and the input signal also includes a second reference signal; the supplementary module is used to transmit the second reference signal to the feedback unit; the feedback unit is used to generate a third output signal and a fourth output signal based on the second reference signal, and transmit the third output signal and the fourth output signal to the output unit; the output unit is used to generate a second signal based on the third output signal and the fourth output signal.

[0009] In a possible implementation, the amplitude of the second signal is positively correlated with the amplitude of the first reference signal, the amplitude of the first reference signal is positively correlated with the amplitude of the second input signal, and the amplitude of the second input signal is determined based on the first reference potential difference and the second reference potential difference.

[0010] In one possible implementation, the voltage stabilizing circuit also includes a control module, which is connected to the first low-voltage withstand module; the control module is used to transmit a control signal to the first low-voltage withstand module; and the first low-voltage withstand module is used to transmit a first signal to the second low-voltage withstand module when the control signal is turned on.

[0011] In one possible implementation, the voltage stabilizing circuit also includes a load module, which is connected to the second low-voltage-withstand module; the amplitude of the signal at the low-potential end of the second low-voltage-withstand module is inversely proportional to the resistance value corresponding to the load module, and the signal at the low-potential end of the first low-voltage-withstand module is determined based on the resistance value corresponding to the load module.

[0012] On the other hand, a chip is provided, the chip comprising any possible voltage stabilization circuit described above.

[0013] On the other hand, an electronic device is provided, wherein a chip in the electronic device includes any possible voltage stabilizing circuit described above.

[0014] The technical solution provided by this application brings at least the following beneficial effects:

[0015] In the present application, a signal is generated at the low potential end of the first low voltage withstand module to control the potential difference between the high potential end and the low potential end of the first low voltage withstand module, and the potential difference between the high potential end and the low potential end of the second low voltage withstand module is also controlled, thereby achieving flexible control of the potential difference and reducing the possibility of low voltage withstand devices in the first low voltage withstand module and the second low voltage withstand module being broken down and damaged. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a structural schematic diagram of a voltage stabilizing circuit provided in an embodiment of the present application;

[0018] Figure 2 is a structural schematic diagram of a voltage stabilizing module provided in an embodiment of the present application;

[0019] Figure 3 It is a partial structural schematic diagram of a voltage stabilizing circuit provided in an embodiment of the present application;

[0020] Figure 4 is a structural schematic diagram of another voltage stabilizing circuit provided in an embodiment of the present application;

[0021] Figure 5 is a structural schematic diagram of another voltage stabilizing circuit provided in an embodiment of the present application;

[0022] Figure 6 It is a structural schematic diagram of another voltage stabilizing circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0024] Different circuit components have different withstand voltage ratings. The withstand voltage rating is the maximum voltage that the component can withstand. According to the withstand voltage rating, the components can be divided into high withstand voltage components and low withstand voltage components. High withstand voltage components can withstand a larger voltage, while low withstand voltage components can withstand a lower voltage.

[0025] If a high-voltage device is used in a low-voltage environment, the voltage applied to both ends of the high-voltage device is small. However, since the internal resistance of the high-voltage device may be relatively large, the high-voltage device may still generate large power consumption and heat in a low-voltage environment, resulting in power waste and may affect the overall performance of the circuit. If a low-voltage device is used in a high-voltage environment, the voltage applied to both ends of the low-voltage device is large, which may exceed the maximum tolerable voltage corresponding to the process parameters of the low-voltage device, causing the low-voltage device to be broken down and damaged. Therefore, when designing an integrated circuit (IC), high-voltage devices are usually used in a high-voltage environment and low-voltage devices are used in a low-voltage environment.

[0026] In the process of chip manufacturing, with the improvement of production technology, the process node has reached several nanometers. The process node is usually measured in nanometers, which mainly refers to the minimum feature size of semiconductor devices in the chip manufacturing process. In addition, the number of devices in the chip has increased, and the process design kit (PDK) will include various metal-oxide-semiconductor field-effect transistors (MOSFET) suitable for different power domains, or it will include a variety of MOSFETs with different withstand voltage ratings.

[0027] However, the working power supply of the chip has not decreased in proportion, and the working power supply of the chip is even maintained at the original high-amplitude interface power supply. If the low-voltage MOSFET devices inside the chip are connected to these high-amplitude interface power supplies, the gate-source voltage (Vgs) and drain-source voltage (Vds) of the MOSFET devices will exceed the applicable range of the MOSFET devices, that is, exceed the voltage rating of the MOSFET devices. In severe cases, the MOSFET devices will be broken down and the chip will be damaged. Although high-voltage devices can work normally when connected to high-amplitude interface power supplies, high-voltage devices are usually more complicated in manufacturing processes and may require special photolithography masks to accurately control the size of their physical structures. There are also special requirements in doping processes, etc., which increase costs and production cycles. Therefore, if high-voltage MOSFET devices are used to connect higher interface power supplies, the chip cost will be too expensive.

[0028] The embodiment of the present application provides a voltage stabilizing circuit, which can protect low-voltage devices from being broken down and damaged in a circuit with a high amplitude of a power signal, reduce the number of high-voltage devices in the circuit, and thus reduce the production cost of the circuit and the production cost of the chip. The low-voltage devices in the embodiment of the present application include but are not limited to low-voltage MOSFET devices.

[0029] See also Figure 1 , shows a schematic diagram of the structure of a voltage stabilizing circuit provided in an embodiment of the present application. The voltage stabilizing circuit includes a first low withstand voltage module 11, a second low withstand voltage module 12 and a voltage stabilizing module 13, and the second low withstand voltage module 12 is connected to the first low withstand voltage module 11 and the voltage stabilizing module 13 respectively.

[0030] The first low-voltage-withstand module 11 is used to generate a first signal based on the acquired power supply signal, and transmit the first signal to the second low-voltage-withstand module 12; the voltage stabilizing module 13 is used to generate a second signal based on the acquired input signal, and transmit the second signal to the second low-voltage-withstand module 12; the second low-voltage-withstand module 12 is used to generate a signal of the low potential end of the first low-voltage-withstand module 11 based on the first signal and the second signal, and generate a signal of the low potential end of the second low-voltage-withstand module 12 based on the first signal and the second signal.

[0031] Among them, the first low-voltage module 11 and the second low-voltage module 12 each include one or more low-voltage devices, so it is necessary to control the potential difference (i.e., voltage) applied across the first low-voltage module 11 and the second low-voltage module 12 to protect the low-voltage devices in the first low-voltage module 11 and the second low-voltage module 12 from being damaged.

[0032] The power signal is a signal at the high potential end of the first low withstand voltage module 11, and the amplitude of the power signal is greater than the amplitude threshold, that is, the amplitude of the power signal exceeds the rated voltage (or withstand voltage rating) of the low withstand voltage devices in the first low withstand voltage module 11 and the second low withstand voltage module 12.

[0033] In the embodiment of the present application, the first low withstand voltage module 11 and the second low withstand voltage module 12 are connected in series, and the potential of the first low withstand voltage module 11 is higher than that of the second low withstand voltage module 12. Therefore, the low potential end of the first low withstand voltage module 11 is the high potential end of the second low withstand voltage module 12, and the signal of the low potential end of the first low withstand voltage module 11 is the signal of the high potential end of the second low withstand voltage module 12.

[0034] In the voltage stabilizing circuit provided in the embodiment of the present application, the potential difference between the power supply signal and the signal of the low potential end of the first low withstand voltage module 11 is less than the first reference potential difference between the high potential end and the low potential end of the first low withstand voltage module 11, and the potential difference between the signal of the low potential end of the first low withstand voltage module 11 (that is, the signal of the high potential end of the second low withstand voltage module 12) and the signal of the low potential end of the second low withstand voltage module 12 is less than the second reference potential difference between the high potential end and the low potential end of the second low withstand voltage module 12, thereby realizing protection of the low withstand voltage devices in the first low withstand voltage module 11 and the second low withstand voltage module 12. The first reference potential difference is the withstand voltage rating of the device with the smallest withstand voltage rating in the first low withstand voltage module 11, and the second reference potential difference is the withstand voltage rating of the device with the smallest withstand voltage rating in the second low withstand voltage module 12.

[0035] See also Figure 2 , shows a schematic diagram of the structure of a voltage stabilizing module 13 provided in an embodiment of the present application. The voltage stabilizing module 13 includes a signal source unit 131, a feedback unit 132 and an output unit 133, and the feedback unit 132 is connected to the signal source unit 131 and the output unit 133 respectively. The input signal includes a first input signal and a second input signal; the signal source unit 131 is used to generate a first reference signal based on the first input signal and the second input signal, and transmit the first reference signal to the feedback unit 132. The first input signal and the second input signal are different signals of the input signal source unit 131, and the amplitudes of the first input signal and the second input signal are different.

[0036] The feedback unit 132 is used to obtain the third input signal, generate the first output signal and the second output signal based on the first reference signal and the third input signal, and transmit the first output signal and the second output signal to the output unit 133. The embodiment of the present application does not limit the manner in which the feedback unit 132 obtains the third input signal. For example, see Figure 2The voltage stabilizing module 13 also includes a current mirror unit 134, which is connected to the signal source unit 131 and the feedback unit 132 respectively. The signal source unit 131 is also used to transmit a first input signal to the current mirror unit 134; the current mirror unit 134 is used to generate a third input signal according to the first input signal, and transmit the third input signal to the feedback unit 132; the feedback unit 132 is used to receive the third input signal. Among them, the first input signal is a voltage signal, and the current mirror unit 134 can convert the first input signal into a stable current signal, that is, into a third input signal. After the third input signal is transmitted to the feedback unit 132, the feedback unit 132 can generate a first output signal and a second output signal based on the first reference signal and the third input signal. Then the output unit 133 is used to generate a second signal based on the first output signal and the second output signal.

[0037] In a possible implementation, the amplitude of the second signal may fluctuate. For example, a change in the temperature of the environment in which the voltage stabilizing circuit is located may cause changes in the parameters of certain devices, resulting in changes in the amplitude of the second signal. The amplitude of the second signal affects the amplitude of the signal at the low potential end of the first low withstand voltage module 11. The amplitude of the signal at the low potential end of the first low withstand voltage module 11 affects the potential difference across the first low withstand voltage module 11 and the potential difference across the second low withstand voltage module 12. Therefore, the embodiment of the present application can control the amplitude of the second signal through negative feedback, so that the amplitude of the second signal is stable, thereby ensuring the stability of the potential difference across the first low withstand voltage module 11 and the second low withstand voltage module 12.

[0038] Exemplarily, the output unit 133 is also used to transmit a second signal to the feedback unit 132; the feedback unit 132 is also used to adjust the first output signal and the second output signal based on the comparison result of the second signal and the first reference signal to obtain an adjusted first output signal and an adjusted second output signal; the output unit 133 is also used to adjust the second signal based on the adjusted first output signal and the adjusted second output signal.

[0039] In the embodiment of the present application, the amplitude of the second signal and the first reference signal are the same in an ideal state, so when the comparison result of the second signal and the first reference signal indicates that the amplitude of the second signal is greater than the amplitude of the first reference signal, the feedback unit 132 can generate a feedback signal to adjust the first output signal and the second output signal, thereby reducing the amplitude of the second signal and achieving the adjustment of the second signal. When the comparison result of the second signal and the first reference signal indicates that the amplitude of the second signal is less than the amplitude of the first reference signal, the feedback unit 132 can generate a feedback signal to adjust the first output signal and the second output signal, thereby increasing the amplitude of the second signal and achieving the adjustment of the second signal.

[0040] See also Figure 3, which shows a partial structural diagram of a voltage stabilization circuit provided in an embodiment of the present application. Among them, the signal source unit 131 includes Figure 3 The bias voltage source (BIAS), MN5, MN4, R0 and C0 in the current mirror unit 134 include Figure 3 The feedback unit 132 includes Figure 3 MN1, MP1 and error amplifier (EA); the output unit 133 includes Figure 3 MN0, MP0, capacitor C1 and output end.

[0041] The first input signal acquired by the signal source unit 131 is the electrical signal output by BIAS, the second input signal is VDD, and the first reference signal generated by the signal source unit 131 based on the first input signal and the second input signal is VR. Exemplarily, the signal source unit 131 can generate the first reference signal VR based on the following formula (1).

[0042] VR=VDD-I ref *R0 (1)

[0043] In formula (1), VR is the first reference signal, VDD is the second input signal, and I ref A current mirror composed of MN3, MN4 and MN5 generates a current signal based on the first input signal and flows through MN4, and the current signal flows through a filter connected to MN4 to generate VR. The filter connected to MN4 includes a resistor R0 and a capacitor C0.

[0044] Because I ref is a current that is independent of the second input signal VDD and is inversely proportional to the resistance R0. ref The value of I will not change with the change of the second input signal VDD, and the resistance value of the resistor R0 will not change with the change of the second input signal VDD. ref The value of *R0 can be considered as a constant value, that is, the difference between the second input signal VDD and the first reference signal VR is fixed and will not change with changes in temperature or process. Therefore, the amplitude of the first reference signal VR generated by the signal source unit 131 changes with the second input signal VDD. If the amplitude of the second input signal VDD increases, the amplitude of the first reference signal VR also increases.

[0045] Next, MP3, MN3, MP2 and MN2 in the current mirror unit 134 generate a current signal according to the first input signal (ie, the electrical signal output by BIAS), the generated current signal being also the third input signal, and transmits the third input signal to MN1 and MP1 in the feedback unit 132 .

[0046] The EA in the feedback unit 132 generates a current signal according to the first reference signal. The current signal generated by the EA and the third input signal act together on MN1 and MP1, so that MN1 generates a first output signal VA at a high potential end and MP1 generates a second output signal VB at a low potential end.

[0047] The first output signal VA is transmitted to MN0 in the output unit 133, and the second output signal VB is transmitted to MP0 in the output unit 133. The inputs of the gates of MN0 and MP0 are the first output signal VA and the second output signal VB, respectively, so that MN0 and MP0 are in a saturated state, or in a conductive state. MN0 and MP0 in the conductive state are equivalent to two MOS buffers, which transmit the first output signal VS and the second output signal VB to the output end respectively, and the output end outputs the second signal VOUT based on the first output signal VA and the second output signal VB. As shown in the following formula (2), the amplitude of the second signal is the voltage between the gate-source of the first output signal VA and MN1 Or, the amplitude of the second signal is the second output signal VB and the gate-source voltage of MP0 The amplitude between and.

[0048]

[0049] By transforming formula (2), we can get the following formula (3).

[0050]

[0051] From formula (3), it can be seen that the amplitude difference between the first output signal VA and the second output signal VB is: the amplitude difference between the gate voltage and the source voltage of MN1 and the magnitude difference between the gate voltage and the source voltage of MP1 The amplitude difference between the first output signal VA and the second output signal VB is also equal to the amplitude difference between the gate voltage and the source voltage of MN0. and the magnitude difference between the gate voltage and the source voltage of MP0 The amplitude difference between the first output signal VA and the second output signal VB is fixed and is not affected by the first input signal and the second input signal.

[0052] In the embodiment of the present application, the amplitude of the second signal VOUT is determined by the feedback loop formed by the amplifier EA and the subsequent devices, so that in an ideal state, the amplitude of the second signal VOUT is the same as the amplitude of the first reference signal VR input to the EA. The EA in the feedback unit 132 can compare and amplify the amplitude difference between the second signal VOUT and the first reference signal VR. If the second signal VOUT is greater than the first reference signal VR, the EA outputs a lower feedback signal, which acts on MN1 and MP1, so that the amplitudes of the first output signal VA and the second output signal VB are reduced, thereby reducing the amplitude of the second signal VOUT. If the second signal VOUT is less than the first reference signal VR, the EA outputs a higher feedback signal, which acts on MN1 and MP1, so that the amplitudes of the first output signal VA and the second output signal VB are increased, thereby increasing the amplitude of the second signal VOUT, so that the second signal is dynamically equal to the first reference signal.

[0053] Based on the above description, it can be known that the amplitude of the second signal is positively correlated with the amplitude of the first reference signal, and the amplitude of the first reference signal is positively correlated with the amplitude of the second input signal. Therefore, in an embodiment of the present application, the amplitude of the second input signal can be determined based on the first reference potential difference and the second reference potential difference, so that the signal at the low potential end of the first low withstand voltage module 11 and the signal at the low potential end of the second low withstand voltage module 12 generated based on the second signal can ensure that the potential difference applied across the first low withstand voltage module 11 and the second low withstand voltage module 12 will not cause damage to the low withstand voltage devices in the first low withstand voltage module 11 or the second low withstand voltage module 12.

[0054] In a possible implementation, the chip to which the voltage stabilizing circuit belongs may enter a low power consumption mode. When the chip enters the low power consumption mode, the chip can no longer provide the first input signal and the second input signal to the voltage stabilizing module 13, and the signal source unit 131 is disconnected, so that the voltage stabilizing module 13 can no longer generate the second signal based on the first input signal and the second input signal. If the voltage stabilizing module 13 cannot generate the second signal, the second low withstand voltage module 12 can no longer generate the signal of the low potential end of the first low withstand voltage module 11 and the signal of the low potential end of the second low withstand voltage module 12 based on the second signal, and the potential difference between the first low withstand voltage module 11 and the second low withstand voltage module 12 cannot be controlled.

[0055] To avoid this from happening, Figure 4As shown, the voltage stabilizing circuit provided in the embodiment of the present application further includes a supplementary module 14, and the supplementary module 14 is connected to the feedback unit 132 in the voltage stabilizing module 13, and the supplementary module 14 can provide the voltage stabilizing module 13 with an input signal required to generate a second signal. Exemplarily, the input signal includes a second reference signal. The supplementary module 14 is used to transmit the second reference signal to the feedback unit 132 when the signal source unit 131 is disconnected; the feedback unit 132 is used to generate a third output signal and a fourth output signal based on the second reference signal, and transmit the third output signal and the fourth output signal to the output unit 133; the output unit 133 is used to generate a second signal based on the third output signal and the fourth output signal.

[0056] exist Figure 3 In the circuit shown, the supplementary module 14 includes Figure 3 The signal source, switches SW0 and SW1 in the chip are in a disconnected state when the chip is in a non-low power mode, that is, when the chip is working normally. When the chip is in a low power mode, the signal source outputs a second reference signal VR_LP, and switches SW0 and SW1 are closed and turned on to transmit the second reference signal to the feedback unit 132. MN1 and MP1 in the feedback unit 132 generate a third output signal VA and a fourth output signal VB based on the second reference signal, and transmit them to MN0 and MP0 in the output unit 133. MN0 and MP0 generate and output a second signal VOUT based on the third output signal VA and the fourth output signal VB.

[0057] In this case, the second signal generated by the voltage stabilizing module 13 is approximately equal to the second reference signal, and thus the amplitude of the second reference signal can also be determined based on the first reference potential difference and the second reference potential difference.

[0058] After the voltage stabilizing module 13 generates the second signal, it transmits the second signal to the second low withstand voltage module 12, so that the second low withstand voltage module 12 can generate a signal of the low potential end of the first low withstand voltage module 11 (that is, a signal of the high potential end of the second low withstand voltage module 12) based on the first signal and the second signal, and generate a signal of the low potential end of the second low withstand voltage module 12 based on the first signal and the second signal. The second low withstand voltage module 12 generates a signal of the high potential end of the second low withstand voltage module 12 based on the first signal and the second signal, which means: after the first signal and the second signal are input into the second low withstand voltage module 12, the signal formed at the high potential end of the second low withstand voltage module 12; correspondingly, the second low withstand voltage module 12 generates a signal of the low potential end of the second low withstand voltage module 12 based on the first signal and the second signal, which means: after the first signal and the second signal are input into the second low withstand voltage module 12, the signal formed at the low potential end of the second low withstand voltage module 12.

[0059] In one possible implementation, see Figure 4, the voltage stabilizing circuit also includes a load module 16, which is connected to the second low withstand voltage module 12; since the load module 16 is connected in series with the second low withstand voltage module 12, the load module 16 and the second low withstand voltage module 12 are voltage-divided, and the low potential end of the second low withstand voltage module 12 is the high potential end of the load module 16, so the amplitude of the signal at the low potential end of the second low withstand voltage module 12 is inversely proportional to the resistance value corresponding to the load module 16. In addition, because the amplitude of the signal at the low potential end of the second low withstand voltage module 12 affects the magnitude of the current flowing through the second low withstand voltage module 12, and the larger the amplitude of the signal at the low potential end of the second low withstand voltage module 12, the smaller the current flowing through the second low withstand voltage module 12, it can be considered that the signal at the low potential end of the first low withstand voltage module 11 (that is, the signal at the high potential end of the second low withstand voltage module 12) is determined based on the resistance value corresponding to the load module 16.

[0060] Optionally, the voltage stabilizing circuit further includes Figure 4 The control module 15 is connected to the first low withstand voltage module 11; the control module 15 is used to transmit a control signal to the first low withstand voltage module 11; the first low withstand voltage module 11 is used to transmit a first signal to the second low withstand voltage module 12 when the control signal is turned on.

[0061] See also Figure 5 The schematic diagram of the structure of a voltage stabilizing circuit provided by an embodiment of the present application is shown, the first low withstand voltage module 11 and the second low withstand voltage module 12 both include a PMOS tube, MP7 and MP8 respectively, and MP7 and MP8 are both low withstand voltage devices. The clamp regulator circuit corresponds to the voltage stabilizing module 13, the low power chopper circuit corresponds to the supplementary module 14, the NMOS load circuit corresponds to the load module 16, and the MP7 control circuit corresponds to the control module 15.

[0062] Figure 5 MP7 and MP8 in the figure are two PMOS devices working in series, and the substrate potential of MP7 and MP8 is short-circuited with the source potential. The high voltage source is the power signal of the chip or module, and the amplitude of the power signal exceeds the parameters such as Vgs and Vds of MP7 and MP8 inside the voltage regulator circuit. The NMOS load circuit is a circuit structure composed of NMOS devices that can achieve various functional performances. The power signal is injected into the NMOS load circuit through MP7 and MP8, and finally flows into the ground.

[0063] The gate potential of MP7 is connected to the MP7 control circuit, and the MP7 control circuit controls the gate voltage of MP7 through amplification, buffering or switch driving structures, so that MP7 can be turned on or off accordingly. The gate potential of MP8 is connected to the clamping regulator circuit, and the second signal output by the clamping regulator circuit can be combined with MP8 to realize stable control of the signal Vmd at the low potential end of the first low withstand voltage module 11.

[0064] When the chip where the voltage stabilization circuit is located is in a non-low power mode, the clamping regulator circuit autonomously generates a second signal and provides the second signal to MP8. When the chip is in a low power mode, the low power chopper circuit (i.e., the supplementary module 14) provides an input signal to the clamping regulator circuit, so that the clamping regulator circuit generates a second signal and transmits it to MP8. After receiving the power supply signal output by the high voltage source, MP7 generates a first signal and transmits it to MP8. The first signal can be a current signal transmitted to MP8.

[0065] MP8 is turned on based on the second signal input by the clamp regulator circuit, and generates a signal of the low potential end of the first low withstand voltage module 11 and a signal of the low potential end of the second low withstand voltage module 12 based on the first signal and the second signal. The signal of the low potential end of the first low withstand voltage module 11 is Figure 4 The signal Vmd of the low potential end of the first low withstand voltage module 11 can be generated based on the following formula (4).

[0066]

[0067] In formula (4) is the voltage difference between the gate and source of MP8, and VOUT is the second signal output by the clamping regulator circuit. It can be generated based on the following formula (5) and the first signal.

[0068]

[0069] In formula (5), β is a constant coefficient, I is the current flowing from the low potential end of MP7 to the high potential end of MP8, that is, the first signal, and Vth is the threshold voltage of MP8. The influence of Vth is small, and Vth is a fixed value, so As a fixed value. Then, according to the amplitude of the power signal and the withstand voltage rating of MP7 and MP8, the required Vmd can be determined, and according to Vmd and Since the size of VOUT is approximately equal to the size of the first reference signal, and the size of the first reference signal is determined based on the first input signal and the second input signal, the embodiment of the present application can control the size of the first reference signal by adjusting the sizes of the first input signal and the second input signal, and further realize the control of the second signal and the signal of the low potential end of the first low withstand voltage module 11.

[0070] In addition, by controlling the magnitude of the second signal and the signal of the low potential end of the first low withstand voltage module 11, the potential difference between the two ends of the first low withstand voltage module 11 can also be controlled. Figure 5 For example, the potential difference across the first low withstand voltage module 11 can be determined based on the following formula (6).

[0071]

[0072] In formula (6), is the potential difference between the source and drain of MP7, that is, the potential difference between the high potential end and the low potential end of the first low withstand voltage module 11; VDD is the power supply signal output by the high voltage voltage source, which is the signal of the high potential end of the first low withstand voltage module 11; Vmd is the signal of the low potential end of the first low withstand voltage module 11, which is the signal of the low potential end of the first low withstand voltage module 11; VR is the first reference signal; is the potential difference between the gate and drain of MP8; I ref is the third input signal, I ref *R0 is the amplitude difference between VDD and VR, and is a value that is not affected by VDD. By adjusting R0, which can be calibrated, I ref * The value of R0 is used to adjust the amplitude difference between the first reference signal VR and VDD and VR, so that the potential difference between the high potential end and the low potential end of the first low withstand voltage module 11 is in the safe operating area of ​​the first low withstand voltage module 11.

[0073] By properly controlling the signal Vmd at the low potential end of the first low withstand voltage module 11, the source-drain voltage Vds of MP7 and MP8 can be kept within their normal operating ranges, thus preventing one of them from being directly exposed to the voltage difference between the power supply and the ground and being damaged by overvoltage.

[0074] The embodiment of the present application generates a signal at the low potential end of the first low voltage withstand module 11, controls the potential difference between the high potential end and the low potential end of the first low voltage withstand module 11, and also controls the potential difference between the high potential end and the low potential end of the second low voltage withstand module 12, thereby achieving flexible control of the potential difference and reducing the possibility of low voltage withstand devices in the first low voltage withstand module 11 and the second low voltage withstand module 12 being broken down and damaged.

[0075] In addition, the voltage stabilizing circuit provided in the embodiment of the present application may include not only the above-mentioned modules and devices, but also other modules or devices. Exemplarily, the voltage stabilizing circuit may include other low-voltage modules other than the second low-voltage module 12, such as other low-voltage modules 1, other low-voltage modules 2..., other low-voltage modules n, and the structures of other low-voltage modules and the second low-voltage module 12 may be the same. In addition, the voltage stabilizing circuit may also include other voltage stabilizing modules corresponding to each other low-voltage module.

[0076] See also Figure 6 , shows a schematic diagram of the structure of another voltage stabilizing circuit provided by an embodiment of the present application. The voltage stabilizing circuit includes a first low withstand voltage module 11, a second low withstand voltage module 12, a voltage stabilizing module 13, n other low withstand voltage modules and n other voltage stabilizing modules n, where n is a positive integer greater than or equal to 1. One other voltage stabilizing module is connected to another low withstand voltage module, and multiple other low withstand voltage modules form a multi-layer series structure.

[0077] The working principle between any other voltage stabilizing module and the corresponding other low withstand voltage module can refer to the working principle between the voltage stabilizing module 13 and the second low withstand voltage module 12, which will not be repeated here. It should be noted that any other voltage stabilizing module can be connected not only to other low withstand voltage modules, but also to another supplementary module, the structure of the other supplementary module is the same as the structure of the above-mentioned supplementary module 14, and the working principle and process between the other supplementary module and the connected other voltage stabilizing module can refer to the working principle and process between the above-mentioned supplementary module 14 and the voltage stabilizing module 13, which will not be repeated here.

[0078] Through multiple other voltage stabilizing modules and other supplementary modules, the potential difference between the high potential end and the low potential end of multiple other voltage-resistant modules can be controlled to avoid damage to low-voltage-resistant devices in other low-voltage-resistant modules.

[0079] In the voltage stabilizing circuit provided in the embodiment of the present application, low voltage MOSFET devices can be used, and the voltage stabilizing circuit can be applied to a high amplitude interface voltage environment, which can ensure that low withstand voltage devices are in a safe working area and will not be damaged by overvoltage. Additional photolithography procedures for high withstand voltage devices are avoided, reducing chip costs and production cycles.

[0080] In an exemplary embodiment, a chip is further provided. The chip includes any possible voltage stabilization circuit described above.

[0081] In an exemplary embodiment, an electronic device is further provided, wherein a chip in the electronic device includes any possible voltage stabilizing circuit described above.

[0082] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the signals involved in this application are all obtained with full authorization.

[0083] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0084] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A voltage stabilizing circuit, characterized in that: The voltage stabilizing circuit comprises a first low-voltage withstand module, a second low-voltage withstand module and a voltage stabilizing module, wherein the second low-voltage withstand module is connected to the first low-voltage withstand module and the voltage stabilizing module respectively; The first low withstand voltage module is used to generate a first signal based on the acquired power supply signal, and transmit the first signal to the second low withstand voltage module, wherein the power supply signal is a signal of a high potential end of the first low withstand voltage module, and the amplitude of the power supply signal is greater than an amplitude threshold; The voltage stabilizing module is used to generate a second signal based on the acquired input signal, and transmit the second signal to the second low withstand voltage module; The second low-voltage-withstand module is used to generate a signal of a low potential end of the first low-voltage-withstand module based on the first signal and the second signal, and to generate a signal of a low potential end of the second low-voltage-withstand module based on the first signal and the second signal. The potential difference between the power supply signal and the signal of the low potential end of the first low-voltage-withstand module is smaller than a first reference potential difference between a high potential end and a low potential end of the first low-voltage-withstand module, the potential difference between the signal of the high potential end and the signal of the low potential end of the second low-voltage-withstand module is smaller than a second reference potential difference between a high potential end and a low potential end of the second low-voltage-withstand module, and the low potential end of the first low-voltage-withstand module is a high potential end of the second low-voltage-withstand module.

2. The voltage stabilizing circuit according to claim 1, characterized in that: The voltage stabilization module comprises a signal source unit, a feedback unit and an output unit, the feedback unit is connected to the signal source unit and the output unit respectively, and the input signal comprises a first input signal and a second input signal; The signal source unit is configured to generate a first reference signal based on the first input signal and the second input signal, and transmit the first reference signal to the feedback unit; The feedback unit is configured to obtain a third input signal, generate a first output signal and a second output signal based on the first reference signal and the third input signal, and transmit the first output signal and the second output signal to the output unit; The output unit is used to generate the second signal based on the first output signal and the second output signal.

3. The voltage stabilizing circuit according to claim 2, characterized in that: The output unit is further used to transmit the second signal to the feedback unit; The feedback unit is further used to adjust the first output signal and the second output signal based on the comparison result of the second signal and the first reference signal to obtain an adjusted first output signal and an adjusted second output signal; The output unit is further used to adjust the second signal based on the adjusted first output signal and the adjusted second output signal.

4. The voltage stabilizing circuit according to claim 2 or 3, characterized in that: The voltage stabilization module further includes a current mirror unit, and the current mirror unit is connected to the signal source unit and the feedback unit respectively; The signal source unit is further used to transmit the first input signal to the current mirror unit; The current mirror unit is used to generate the third input signal according to the first input signal, and transmit the third input signal to the feedback unit; The feedback unit is used to receive the third input signal.

5. The voltage stabilizing circuit according to claim 1, characterized in that: The voltage stabilizing circuit further comprises a supplementary module, the voltage stabilizing module comprises a feedback unit and an output unit, the supplementary module is connected to the voltage stabilizing module, and the input signal comprises a second reference signal; The supplementing module is used to transmit the second reference signal to the feedback unit; The feedback unit is configured to generate a third output signal and a fourth output signal based on the second reference signal, and transmit the third output signal and the fourth output signal to the output unit; The output unit is used to generate the second signal based on the third output signal and the fourth output signal.

6. The voltage stabilizing circuit according to any one of claims 2 to 5, characterized in that: The amplitude of the second signal is positively correlated with the amplitude of the first reference signal, the amplitude of the first reference signal is positively correlated with the amplitude of the second input signal, and the amplitude of the second input signal is determined based on the first reference potential difference and the second reference potential difference.

7. The voltage stabilizing circuit according to any one of claims 1 to 6, characterized in that: The voltage stabilizing circuit further includes a control module, and the control module is connected to the first low withstand voltage module; The control module is used to transmit a control signal to the first low withstand voltage module; The first low withstand voltage module is configured to transmit the first signal to the second low withstand voltage module when the control signal is turned on.

8. The voltage stabilizing circuit according to any one of claims 1 to 7, characterized in that: The voltage stabilizing circuit also includes a load module, which is connected to the second low-voltage-withstand module; the amplitude of the signal at the low-potential end of the second low-voltage-withstand module is inversely proportional to the resistance value corresponding to the load module, and the signal at the low-potential end of the first low-voltage-withstand module is determined based on the resistance value corresponding to the load module.

9. A chip, characterized in that: The chip includes the voltage stabilizing circuit described in any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the chip according to claim 9.

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