Multi-clock domain burr-free switching method supporting clock dynamic switching

Abstract

The invention discloses a multi-clock domain burr-free switching method supporting clock dynamic switching, comprising the following steps: S1, an MUX multiplexer outputs a normally open clk clock signal according to the switching condition of each clock source, and sends the clk clock signal to a corresponding clock switching sub-module; s2, in the clock switching sub-module, an sel clock selection signal corresponding to the clk clock signal passes through an and gate, a three-stage register and a first-stage register to output a gating signal of the clk clock signal, and a non-signal of the sel clock selection signal passes through the and gate and the three-stage register to output a gating signal of a clock to be switched; and S3, after the clk clock signal is closed through the gating signal in a falling edge triggering mode, a feedback signal is generated, after the clock to be switched receives the feedback signal, the clock to be switched is opened through the gating signal, and switching is completed. The method provided by the invention can be applied to a clock switching system of a low-power-consumption MCU, and multi-clock switching can be realized.

Description

Technical Field

[0001] The invention relates to the field of chip technology, and in particular to a multi-clock domain glitch-free switching method supporting dynamic clock switching. Background Art

[0002] MCU chip, or microcontroller unit, is a highly integrated semiconductor chip widely used in modern electronic devices. The system clock source of MCU chip usually includes internal oscillator, external crystal oscillator and phase-locked loop, and the number of clock sources can reach 3-5. In order to meet the low power consumption requirements of MCU, the high-speed clock is switched to the low-speed clock before entering the low-power mode and the non-running clock source is turned off to reduce power consumption. Before exiting the low-power mode, the low-speed clock can be switched to the high-speed clock to meet the clock frequency requirements for normal operation of the system. MCU needs to realize the function of switching between multiple clocks. The implementation method using combinational logic mux may generate clock signal glitches, which seriously affects the stability of the system.

[0003] At present, the traditional clock glitch-free switching scheme includes: a clock selection signal generating circuit, a synchronization circuit and a multiplexer. The clock selection signal generating circuit is used to generate multiple clock selection signals, and the synchronization circuit is used to synchronize the multiple clock selection signals. After processing, among any two adjacent clock selection signals, the falling edge of the previous clock selection signal is aligned with the rising edge of the next clock selection signal, the rising edge of each clock selection signal is aligned with the rising edge of its corresponding clock signal, and the falling edge of each clock selection signal is aligned with the next falling edge of its corresponding clock signal, and then a multiplexer is used to select one output from the multiple input clock signals.

[0004] However, the current clock glitch-free switching solution contains at least the following three problems: 1) High power consumption: When this clock glitch-free switching scheme performs clock switching, a clock selection signal generating circuit is required to generate multiple clock selection signals and a set of corresponding clock signals, so that the system will generate higher power consumption; 2) Low stability: This clock glitch-free switching solution requires the falling edge of the previous clock selection signal to be aligned with the rising edge of the next clock selection signal during clock switching. If there is a time delay in the middle, the falling edge of the previous clock selection signal cannot be aligned with the rising edge of the next clock selection signal. 3) Poor adaptability: This clock glitch-free switching scheme can only switch the clock signals corresponding to two adjacent clock selection signals, and cannot switch any two clock signals. Summary of the invention

[0005] In response to the above three problems, the purpose of the present invention is to propose a multi-clock domain glitch-free switching method that supports dynamic clock switching. Multi-clock switching can be achieved by cascading multiple clock switching sub-modules, which not only solves the need for MCU to switch more than two clocks, but also solves the problem of needing to shut down the clock source in low power consumption mode. At the same time, by generating a clock switching completion flag, the problem of shutting down the clock source before the clock switching is completed can be avoided.

[0006] This is achieved through the following technical solutions: A multi-clock domain glitch-free switching method supporting dynamic clock switching, the method comprising the following steps: S1, generating multiple different clock signals through multiple clock sources, and inputting the multiple clock signals into a MUX multiplexer, the MUX multiplexer outputting a corresponding clk clock signal according to the switching status of each clock source, and sending the output clk clock signal to the corresponding clock switching submodule; S2, in the clock switching submodule, after the sel clock selection signal corresponding to the clk clock signal passes through an and gate, a three-level register and a first-level register, outputting a negative signal of the sel clock selection signal, and using the negative signal of the sel clock selection signal as the gate of the clk clock signal Control signal, and then the negative signal of the sel clock selection signal is output as the gating signal of the clock to be switched through the AND gate and the three-level register; the clk clock signal is turned off by the gating signal to switch the clock signal; S3, when switching the clock signal, the clk clock signal is turned off by the gating signal in a falling edge triggered manner, and a feedback signal is generated, and the feedback signal is output to the clock to be switched. After the clock to be switched receives the feedback signal, the clock to be switched is turned on by the gating signal to complete the switching; at the same time, each clock switching sub-module adds a flag signal for turning on or off each corresponding clock signal. When any clock signal is not turned on, its corresponding clock enable signal is low.

[0007] The present invention proposes a multi-clock domain glitch-free switching method suitable for low-power MCU and supporting dynamic clock switching. Multi-clock switching can be achieved by cascading multiple clock switching sub-modules, and the MCU system is supported to shut down the non-running clock source to reduce power consumption after receiving the switching completion mark.

[0008] Preferably, in step S1, each clock source comprises: an oscillator, a crystal oscillator and a phase-locked loop; wherein the oscillator and the crystal oscillator are used to generate clock signals, and the phase-locked loop is used to improve the stability and accuracy of the clock signal. The clock source can generate multiple high-precision and stable clock signals for the clock switching system.

[0009] Preferably, in step S1, the MUX multiplexer has multiple input terminals and one output terminal, and it selects a corresponding clock signal from multiple input clock signals for output according to the switching status of each clock source. The clock switching system uses the MUX multiplexer to select and output multiple clock signals, which can effectively manage the output of multiple clock signals and ensure that the clock signal entering the clock switching submodule must exist, so that each clock switching submodule can complete the clock switching normally.

[0010] Preferably, each binary code of the sel clock selection signal corresponds to a corresponding clock signal. The sel clock selection signal can enable the clock switching system to work stably and harmoniously.

[0011] Preferably, in step S2, the three-level register includes: a data register, a status register and a control register. Through the three-level register, the transmission requirements of different clock signals can be met, and the accuracy of clock signal transmission can be ensured.

[0012] Preferably, in step S2, the gating signal is used to control the output of the clock signal. When the gating signal is at a high level, the corresponding clock signal is output, and when the gating signal is at a low level, the corresponding clock signal is not output. The gating signal can effectively control the output of the clock signal, so that the clock switching system can normally complete the switching of the clock signal.

[0013] Preferably, in step S3, the falling edge trigger is triggered when the clk clock signal changes from a high level to a low level, and when triggered, the clk clock signal generates a feedback signal. The feedback signal is generated by the falling edge trigger, which solves the problem of turning off the clock source in the low power mode and avoids the generation of glitches in the switching process of the two clocks.

[0014] Preferably, in step S3, the sign of clock signal switching completion includes: the binary code of the sel clock selection signal changes and the gating signal of the clock to be switched becomes high level. By adding the clock signal switching completion sign, the problem of shutting down the clock source before the clock signal switching is completed can be avoided.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention can realize multi-clock switching by cascading multiple clock switching sub-modules, which not only solves the demand for MCU switching of more than two clocks, but also solves the problem of needing to shut down the clock source in low power consumption mode, and avoids glitches between the two clocks during the switching process. At the same time, by generating a clock switching completion flag, it can avoid the problem of shutting down the clock source before the clock switching is completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1A flowchart of a multi-clock domain glitch-free switching method supporting dynamic clock switching; Figure 2 The present invention is a schematic diagram of the clock switching submodule structure of a multi-clock domain glitch-free switching method that supports dynamic clock switching. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0018] like Figure 1 As shown, it is a flow chart of a multi-clock domain glitch-free switching method that supports dynamic clock switching. First, the MUX multiplexer outputs the clk clock signal according to the switching status of each clock source, and sends the clk clock signal to the corresponding clock switching submodule; then in the clock switching submodule, the sel clock selection signal corresponding to the clk clock signal is output as the gating signal of the clk clock signal through the AND gate, the three-level register and the first-level register, and the negative signal of the sel clock selection signal is output as the gating signal of the clock to be switched through the AND gate and the three-level register; finally, the clk clock signal is closed by the gating signal in a falling edge triggering manner, and a feedback signal is generated. After the clock to be switched receives the feedback signal, the clock to be switched is opened through the gating signal to complete the clock switching.

[0019] The method specifically comprises the following steps: S1. Generate multiple different clock signals through multiple clock sources, and input multiple clock signals into the MUX multiplexer. The MUX multiplexer has multiple input terminals and one output terminal. It selects a corresponding clock signal from multiple input clock signals according to the sel clock selection signal composed of the switching signal of the clock source. Each binary code of the sel clock selection signal corresponds to a corresponding clock signal; and then sends the output clk clock signal to the corresponding clock switching submodule. Among them, each clock source includes: an oscillator, a crystal oscillator and a phase-locked loop; the oscillator and the crystal oscillator are both used to generate clock signals. The difference between them is that the oscillator is an on-chip clock, and the frequency accuracy and stability of the generated clock signal are relatively low. The crystal oscillator is an off-chip clock, which can generate a high-precision and highly stable clock signal; the phase-locked loop is used to improve the stability and accuracy of the clock signal. MUX multiplexer, that is, Multiplexer, is a logic circuit used to select one from multiple input signals as an output signal. In the present invention, it determines the output clock signal according to the binary code of the sel clock selection signal.

[0020] In this embodiment, in the method of the present invention, a clock source can generate multiple high-precision and stable clock signals for the clock switching system, and the clock switching system uses a MUX multiplexer to select and output multiple clock signals, which can effectively manage the output of multiple clock signals and ensure that they can be transmitted through a single output channel. At the same time, the sel clock selection signal can make the clock switching system work stably and coordinately, ensuring that the clock signal entering the clock switching sub-module must exist, so that each clock switching sub-module can complete the clock switching normally.

[0021] S2. In the clock switching submodule, after the sel clock selection signal corresponding to the clk clock signal passes through the AND gate, the three-level register and the first-level register, the negative signal of the sel clock selection signal is output, and the negative signal of the sel clock selection signal is used as the gating signal of the clk clock signal, and then the negative signal of the sel clock selection signal is output as the gating signal of the clock to be switched through the AND gate and the three-level register; the clk clock signal is turned off by the gating signal to switch the clock signal. Among them, the three-level register includes: a data register, a status register and a control register. When the clk clock signal is transmitted, it passes through the control register, the status register and the data register in sequence.

[0022] In this embodiment, the three-level register used in the present invention can meet the transmission requirements of different clock signals and ensure the accuracy and stability of clock signal transmission. The gate signal is used to control the output of the clock signal. When the gate signal is at a high level, the corresponding clock signal is output, and when the gate signal is at a low level, the corresponding clock signal is not output; the gate signal can effectively control the output of the clock signal, so that the clock switching system can normally complete the switching of the clock signal.

[0023] S3, when switching the clock signal, the clk clock signal is turned off by the gating signal in the manner of falling edge triggering, and a feedback signal is generated, and the feedback signal is output to the clock to be switched. After the clock to be switched receives the feedback signal, the clock to be switched is turned on by the gating signal to complete the switching; at the same time, each clock switching submodule adds a flag signal for turning on or off each corresponding clock signal, and when any clock signal is not turned on, its corresponding clock enable signal is low level. Among them, the falling edge trigger is triggered when the clk clock signal changes from a high level to a low level, and when triggered, the clk clock signal generates a feedback signal. The feedback signal is generated by the falling edge triggering method, which solves the problem of turning off the clock source in the low power mode, and avoids the generation of glitches in the two clocks during the switching process.

[0024] In this embodiment, the present invention can realize the switching of multiple clock signals by cascading multiple clock switching submodules. Each clock switching submodule can realize the switching of two clock signals, and the gating signal of each clock signal is controlled by the feedback signal generated by the falling edge of the other clock signal. The way in which the gating signal is controlled by the other clock ensures the isolation of the two clock signals in design, so when the clock signal is switched, the running clock signal will be closed first by the gating signal.

[0025] like Figure 2 As shown, it is a schematic diagram of the clock switching submodule structure of a multi-clock domain glitch-free switching method that supports dynamic clock switching. In the figure, two clock switching submodules are cascaded, and each clock switching submodule is composed of an AND gate, an OR gate, and a three-level register R, and includes a switching circuit clk_a_switch for clk_a, a switching circuit clk_b_switch for clk_b, a switching circuit clk_o_switch for clk_o, and a switching circuit clk_c_switch for clk_c. Take the three clock sources in the figure as an example for explanation. clk_a, clk_b, and clk_c are three different clock signals generated by the three clock sources. The generated clock signals are input into the MUX multiplexer, and the output clk clock signal is selected by the sel[1:0] clock selection signal. When the sel[1:0] clock selection signal is 2'b00, the clock signal selects clk_a; when the sel[1:0] clock selection signal is 2'b01, the clock signal selects clk_b; when the sel[1:0] clock selection signal is 2'b10, the clock signal selects clk_c. Among them, the clock switching system consists of two clock switching sub-modules. Sub-module 1 selects clk_a and clk_b according to the value of sel[0] and outputs clk_o. Its circuit formula can be simplified to clk_o=(~sel[0]&clk_a)|(sel[0]&clk_b). When sel[0] is 0, clk_a is selected, and when sel[0] is 1, clk_b is selected. Sub-module 2 selects clk_o and clk_c according to the value of sel[1] and outputs clk_out. Its circuit formula can be simplified to clk_out=(~sel[1]&clk_o)|(sel[1]&clk_c). When sel[1] is 0, clk_o is selected, and when sel[1] is 1, clk_c is selected. At the same time, the two clock switching sub-modules add a flag signal for turning the clock signal on or off, including: clk_a_on, clk_b_on and clk_c_on. When the corresponding clock signal is not turned on, the corresponding enable signal is at a low level.

[0026] In this embodiment, the present invention adds a clock signal switching completion flag to avoid the erroneous operation of shutting down the clock source when the clock signal switching is not completed. The sign of the clock signal switching completion includes: the binary code of the sel clock selection signal changes and the gating signal of the clock to be switched becomes a high level. By adding the clock signal switching completion flag, the problem of shutting down the clock source before the clock signal switching is completed can be avoided.

[0027] To sum up, the present invention can realize multi-clock switching by cascading multiple clock switching sub-modules, which not only solves the demand for switching more than two clocks of the MCU, but also solves the problem of needing to shut down the clock source in low power consumption mode, and avoids glitches between the two clocks during the switching process. At the same time, by generating a clock switching completion flag, it can avoid the problem of shutting down the clock source before the clock switching is completed, which is significantly advanced.

[0028] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A multi-clock domain glitch-free switching method supporting dynamic clock switching, characterized in that: The method comprises the following steps: S1, generate multiple different clock signals through multiple clock sources, and input the multiple clock signals into the MUX multiplexer, the MUX multiplexer outputs a corresponding clk clock signal according to the switching status of each clock source, and sends the output clk clock signal to the corresponding clock switching submodule; S2. In the clock switching submodule, after the sel clock selection signal corresponding to the clk clock signal passes through the AND gate, the three-level register and the first-level register, the negative signal of the sel clock selection signal is output, and the negative signal of the sel clock selection signal is used as the gating signal of the clk clock signal. Then, the negative signal of the sel clock selection signal is output as the gating signal of the clock to be switched through the AND gate and the three-level register; the clk clock signal is turned off by the gating signal to switch the clock signal; S3. When switching the clock signal, the clk clock signal is turned off by the gating signal in a falling edge triggered manner, and a feedback signal is generated, and the feedback signal is output to the clock to be switched. After the clock to be switched receives the feedback signal, the clock to be switched is turned on by the gating signal to complete the switching; at the same time, each clock switching sub-module adds a flag signal for each corresponding clock signal to be turned on or off. When any clock signal is not turned on, its corresponding clock enable signal is at a low level.

2. The method for glitch-free switching of multiple clock domains supporting dynamic clock switching according to claim 1, characterized in that: In step S1, each clock source includes: an oscillator, a crystal oscillator and a phase-locked loop; wherein the oscillator and the crystal oscillator are both used to generate a clock signal, and the phase-locked loop is used to improve the stability and accuracy of the clock signal.

3. The method for glitch-free switching of multiple clock domains supporting dynamic clock switching according to claim 1, characterized in that: In step S1, the MUX multiplexer has multiple input terminals and one output terminal, and selects a corresponding clock signal from multiple input clock signals for output according to the switching status of each clock source.

4. The method for glitch-free switching of multiple clock domains supporting dynamic clock switching according to claim 3, characterized in that: Each binary code of the sel clock selection signal corresponds to a corresponding clock signal.

5. The method for glitch-free switching of multiple clock domains supporting dynamic clock switching according to claim 1, characterized in that: In step S2, the three-level register includes: a data register, a status register and a control register.

6. The method for glitch-free switching of multiple clock domains supporting dynamic clock switching according to claim 1, characterized in that: In step S2, the gating signal is used to control the output of the clock signal. When the gating signal is at a high level, the corresponding clock signal is output, and when the gating signal is at a low level, the corresponding clock signal is not output.

7. The method for glitch-free switching of multiple clock domains supporting dynamic clock switching according to claim 1, characterized in that: In step S3, the falling edge trigger is triggered when the clk clock signal changes from a high level to a low level, and when triggered, the clk clock signal generates a feedback signal.

8. The method for glitch-free switching of multiple clock domains supporting dynamic clock switching according to claim 1, characterized in that: In step S3, the signs indicating that the clock signal switching is completed include: the binary code of the sel clock selection signal changes and the gating signal of the clock to be switched becomes a high level.

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