Data access method and device, computing equipment, storage medium and program product

Abstract

The invention discloses a data access method and device, computing equipment, a storage medium and a program product, and belongs to the technical field of computers. The method comprises the following steps: on the premise that tasks in a task queue are executed in series, if a first response carrying first time information is received after a first task in the task queue is scheduled and a first access request is sent to a data responder, executing the first task in the task queue, and if the first time information indicates that the duration required by the data responder to return the corresponding data exceeds a threshold value, the data requester temporarily interrupts the first task and schedules the second task in the task queue. Namely, the data requester can select to continue to wait for the data or schedule other tasks according to the duration required for returning the data estimated by the data responder, so that the task queue is reasonably scheduled, unnecessary time resource waste is reduced, computing resources are reasonably scheduled, and the overall performance is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data access method, apparatus, computing device, storage medium and program product. Background Art

[0002] At present, multi-tiered memory (MTM) is usually set up in computers. Different storage media can be used for different levels of storage. The access speeds of different storage media are different. This setting makes it easy to put more commonly used data in the storage level with faster access speed. However, the data requested by the host or peripheral device may be stored in the storage media of any level, and the time it takes for MTM to return data of different levels varies greatly. Under the MTM architecture, how to further improve data access performance is a current research hotspot. Summary of the invention

[0003] The present application provides a data access method, apparatus, computing device, storage medium and program product, which can enable a processor to arrange tasks more reasonably, so as to schedule computing resources more reasonably, thereby improving data access performance. The technical solution is as follows:

[0004] In a first aspect, a data access method is provided, which is applied to a data requester, and the method comprises:

[0005] Schedule the first task in the task queue and send a first access request to the data responder, wherein the first access request carries a first address, and the first task indicates obtaining the first data corresponding to the first address, and the tasks in the task queue are executed serially; if a first response carrying first time information is received, and a first duration indicated by the first time information exceeds a threshold, schedule the second task in the task queue, wherein the first duration refers to the time estimated by the data responder to return the first data.

[0006] That is, the data requester can choose to continue waiting for data or schedule other tasks based on the data responder's estimate of how long it will take to return the data, thereby reasonably scheduling the task queue, reducing unnecessary waste of time and resources, more reasonably scheduling computing resources, and improving overall performance.

[0007] Among them, the first time information is the time information estimated by the data responder. The data responder may obtain the first data before the first duration indicated by the first time information arrives and store the first time in the cache. That is to say, the data responder may prepare the data in advance.

[0008] In the case where the data is prepared in advance, after receiving the first response carrying the first time information, the method further includes: if the first message of the data responder is received before the first time period ends, sending a second access request to the data responder, the second access request carries the first address, and the first message indicates that the first data is ready. That is, the data responder first notifies that the data is prepared in advance, and then the data requester obtains the data through the request and response method.

[0009] Alternatively, after receiving the first response carrying the first time information, the method further includes: if a second message carrying the first data is received before the first duration ends, determining that the first task is completed. That is, the data responder directly returns the data in advance.

[0010] The data responder may not have obtained the first data when the first duration indicated by the first time information arrives, that is, the data responder may also delay returning the data. In this case, after receiving the first response carrying the first time information, the method further includes: if the first data is still not obtained at the end of the first duration, sending a third access request to the data responder, the third access request carrying the first address. In other words, the data responder may not have prepared the data in advance, so the data requester initiates the request again when the estimated time arrives.

[0011] Correspondingly, after sending the third access request to the data responder, the method also includes: if a second response carrying second time information is received, and the second duration indicated by the second time information exceeds the threshold, scheduling the third task in the task queue, and the second duration refers to the time re-estimated by the data responder to return the first data.

[0012] In addition to the above-mentioned data preparation in advance and data continued delayed return, the data requester may also terminate the task in advance. In this case, after receiving the first response carrying the first time information, the method further includes: if it is determined to terminate the first task before the end of the first time period, a third message is sent to the data responder, and the third message indicates that the data responder does not need to continue to obtain the first data.

[0013] The first response and the message both carry a first delayed return flag, and a delayed return flag is used to identify a data delayed return process. That is, during the delayed return of data, the two parties interacting in data access can use the delayed return flag to identify the message.

[0014] Optionally, the first access request and the first response both carry a first session flag, and a session flag is used to identify an access request and response process; before receiving the first response carrying the first time information, the method further includes: selecting an idle flag from at least one idle flag as the first session flag, and binding the first session flag to the first access request; after receiving the first response carrying the first time information, the method further includes: releasing the first session flag as an idle flag. In this way, even if the data requester can release the session flag in time, so that the session flag can be used by other access requests, unnecessary session flag occupation is reduced.

[0015] Optionally, the first data is stored in a first storage level in a multi-level storage, and the first time information is determined according to an access speed of the first storage level, and access speeds of different storage levels are different.

[0016] Optionally, the data requester is a core of a processor.

[0017] In a second aspect, another data access method is also provided, which is applied to a data responder, and the method includes:

[0018] Receive a first access request from a data requester, the first access request carrying a first address; determine whether the first address hits a cache; if the first address does not hit the cache, send a first response to the data requester, the first response carrying first time information, the first time information indicating the estimated time required by the data responder to return first data, the first data being data corresponding to the first address.

[0019] In this way, the data requester can choose to continue waiting for data or schedule other tasks based on the data responder's estimate of how long it will take to return the data, thereby reasonably scheduling the task queue, reducing unnecessary waste of time and resources, more reasonably scheduling computing resources, and improving overall performance.

[0020] Optionally, after determining that the first address does not hit the cache, the method further includes: obtaining the first data from a storage medium outside the cache, and storing the first data in the cache; recording the state of the first data in the cache as a valid state, and the valid state is used to prevent the first data from being moved out of the cache.

[0021] The first response also carries a first delayed return flag, and the first data is stored in a first cache line included in the cache;

[0022] The recording of the state of the first data as a valid state in the cache includes: recording the state of the first data as the valid state by storing the first delayed return flag in the first field of the first cache line; or recording the state of the first data as the valid state by storing a first attribute value in the second field of the first cache line.

[0023] Since the first time information is the time information estimated by the data responder, the data responder may obtain the first data before the first duration indicated by the first time information arrives and store the first time in the cache, that is, the data responder may prepare the data in advance.

[0024] In the case where the data is prepared in advance, after storing the first data in the cache, the method further includes: sending a first message to the data requester, the first message indicating that the first data is ready. That is, the data responder first notifies that the data is prepared in advance, so that the data requester can obtain the data through a request and response method.

[0025] Correspondingly, after sending the first message to the data requester, the method also includes: receiving a second access request from the data requester, the second access request carrying the first address; determining again whether the first address hits the cache; if the first address hits the cache, sending a second response to the data requester and modifying the status of the first data to an invalid status, the second response carrying the first data.

[0026] Alternatively, when the data is prepared in advance, after storing the first data in the cache, the method further includes: sending a second message to the data requester, the second message carrying the first data. That is, the data responder directly returns the data in advance.

[0027] The data responder may also not obtain the first data when the first duration indicated by the first time information arrives, that is, the data responder may also postpone returning the data. In this case, after determining that the first address does not hit the cache, the method also includes: if a third access request from the data requester is received before returning the first data to the data requester, then determining again whether the first address hits the cache, the third access request carries the first address; if the first address still does not hit the cache, then sending a third response to the data requester, the third response carries the second time information, and the second time information indicates the data responder's re-estimated duration required to return the first data. That is, the data responder may not have prepared the data in advance, so the data responder will receive an access request for the corresponding data again when the estimated time arrives.

[0028] In addition to the above-mentioned data preparation in advance and data continued delayed return, the data requester may also terminate the task in advance. In this case, after sending the first response to the data requester, the method further includes: if a third message from the data requester is received before returning the first data to the data requester, then terminating the task of returning the first data to the data requester, and the third message indicates that the data responder does not need to continue to obtain the first data.

[0029] The termination of returning the first data to the data requester includes: if the first data has not been acquired in the cache, stopping acquiring the first data; if the first data has been stored in the cache, deleting the first data from the cache. This can reduce unnecessary storage access and unnecessary cache space usage.

[0030] Optionally, the first response and the message both carry a first delayed return flag, and a delayed return flag is used to identify a data delayed return process. That is, during the delayed return of data, the two parties interacting in data access can use the delayed return flag to identify the message.

[0031] Optionally, the first data is stored in a first storage level in a multi-level storage, and the first time information is determined according to an access speed of the first storage level, and access speeds of different storage levels are different.

[0032] Optionally, the data responder is a storage controller.

[0033] In a third aspect, a data access device is provided, wherein the data access device has the function of implementing the data access method behavior in the first aspect and / or the second aspect. The data access device includes one or more modules, and the one or more modules are used to implement the data access method provided in the first aspect and / or the second aspect.

[0034] In a fourth aspect, a computing device is provided, the computing device comprising a processor and a memory, the memory being used to store a program for executing the data access method provided in the first aspect and / or the second aspect, and storing data involved in implementing the data access method provided in the first aspect and / or the second aspect. The processor is configured to execute the program stored in the memory. The computing device may also include a communication bus, the communication bus being used to establish a connection between the processor and the memory.

[0035] In a fifth aspect, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is run on a computer, the computer executes the data access method described in the first aspect and / or the second aspect.

[0036] In a sixth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute the data access method described in the first aspect and / or the second aspect.

[0037] The technical effects obtained by the above-mentioned third, fourth, fifth and sixth aspects are similar to the technical effects obtained by the corresponding technical means in the first and second aspects, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is an architecture diagram of an MTM provided in an embodiment of the present application;

[0039] Figure 2 is a schematic diagram of a data access system using MTM provided in an embodiment of the present application;

[0040] Figure 3 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0041] Figure 4 It is a flowchart of memory access in the related technology provided by the embodiment of the present application;

[0042] Figure 5 It is another flowchart diagram of memory access in the related technology provided by the embodiment of the present application;

[0043] Figure 6 is a flow chart of a data access method provided by an embodiment of the present application;

[0044] Figure 7 This is a data access flow chart of Example 1 provided in an embodiment of the present application;

[0045] Figure 8 This is a data access flow chart of Example 2 provided in an embodiment of the present application;

[0046] Fig. 9 This is a data access flow chart of Example 3 provided in an embodiment of the present application;

[0047] Fig.10 It is a structural diagram of a data access device provided in an embodiment of the present application;

[0048] Fig.11 It is a structural diagram of another data access device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0050] For ease of understanding, before explaining in detail the memory page table caching method provided in the embodiment of the present application, the terminology and implementation environment involved in the embodiment of the present application are first introduced.

[0051] First, the terms involved in the embodiments of the present application are introduced.

[0052] 1. Multi-tiered memory (MTM): Also known as multi-tiered memory, it is a physical computer memory that combines dynamic random-access memory (DRAM), NAND flash memory, and a power source for data persistence. MTM treats non-volatile memory as DRAM and includes it in the server's memory space. MTM is currently a storage technology between NAND flash and fast DRAM storage, and large-capacity media such as hard disk drives (HDDs) and optical disks may be introduced into MTM in the future.

[0053] 2. Host or peripheral (host / device): In the embodiments of the present application, host or peripheral refers to a component that can access the memory space through the bus, and the host includes the central processing unit (CPU), graphics processing unit (GPU) or other accelerators in the computing device. Peripherals include other processors in the computing device other than the host, such as GPU, NPU or other accelerators.

[0054] 3. Session Tag: In the embodiment of the present application, it is the tag used by the data requester to initiate a data access request. The data responder will use the same tag when returning the corresponding data after receiving it. This allows the data requester to initiate multiple data access requests, and the data responder can also return data one by one. That is, the session tag is used to identify an access request and response process.

[0055] 4. Delayed return flag: In the embodiment of the present application, it is recorded as MTM Tag, which is an extension of the present solution to the related technology. If the memory needs to delay the return of data, it will use this flag to negotiate with the requester on the time to return the data. That is, the delayed return flag is used to identify a data delayed return process.

[0056] 5. Cache line (CL): Cache is hardware that caches data in memory. Cache line is the basic unit of cache.

[0057] Secondly, the relevant background and implementation environment of the embodiments of the present application are introduced.

[0058] Currently, non-volatile solid-state storage technologies, such as NAND flash memory technology, have been used for data storage in computer systems. Solid state disks (SSDs) used in computer systems can adopt the specifications and interfaces of HDDs. However, compared with HDDs, SSDs provide faster data access speeds. SSDs have recently developed alternative specifications and functions accessed through high-speed serial computer expansion bus (peripheral component interconnect express, PCIe) interfaces. In order to provide faster access to stored data, the industry has proposed solutions that directly connect to the memory bus in computer systems.

[0059] On the memory bus of a computer system, volatile DRAM is usually used due to the performance requirements of bandwidth and low latency. Recently, given the significant gap between bandwidth and latency between memory and storage in computer systems, the industry has proposed a new memory hierarchy called MTM. MTM has characteristics such as low latency and high bandwidth, which are more in line with memory requirements, and MTM will also have non-volatile properties associated with storage technology. In MTM, different levels of storage can use different storage media. Figure 1 is a schematic diagram of an MTM provided in an embodiment of the present application. Figure 1, MTM includes an MTM controller and multiple levels of storage space, which are tier 0, tier 1, tier 2, ..., tier n. Among them, the access speed of tier 0 is relatively high, and the access speed of tier n is relatively low. For example, tier 0 can refer to cache, tier 1 can refer to DRAM, tier 2 can refer to NAND, etc.

[0060] Currently, MTM is usually hung on the PCIe or compute express link (CXL) bus for access by the central processor or other accelerators. CXL is a high-performance input / output (I / O) bus architecture used for the host to connect computer external devices. These devices can include traditional I / O devices and memory devices, and can also include accelerators with additional functions. CXL has developed CXL Type 3 devices, which support CXL.io and CXL.mem protocols. MTM can be a CXL Type 3 device that provides memory expansion for the computer. Of course, MTM can also be other types of devices.

[0061] Figure 2 Schematic diagram of a data access system using MTM provided in an embodiment of the present application. Take MTM hanging on CXL bus as an example, see Figure 2 The core of the processor in the host is connected to the CXL memory expander through the CXL bus (supporting the CXL.mem protocol), and the CXL memory expander includes the MTM. Similarly, the core of the processor in the peripheral is also connected to the CXL memory expander through the CXL bus (supporting the CXL.io protocol). Among them, the host or peripheral also includes a memory controller (memory controller, MC), and the memory controller is used to exchange instructions and data with the MTM controller in the MTM through the CXL bus.

[0062] Figure 3 1 is a schematic diagram of a computing device according to an embodiment of the present application. The computing device may be a terminal device or a server, or other devices, such as a host, a personal computer, etc. The computing device may include Figure 1 or Figure 2 The MTM, processor, etc. shown in the figure. Specifically, the computing device includes at least one processor 301 , a communication bus 302 , a memory 303 , and at least one communication interface 304 .

[0063] The processor 301 may be a general-purpose central processing unit (CPU), a network processor (NP), a microprocessor, or may be one or more integrated circuits for implementing the solution of the present application, such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0064] The communication bus 302 is used to transmit information between the above components. The communication bus 302 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 1 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0065] The memory 303 may be a read-only memory (ROM), a random access memory (RAM), an electrically erasable programmable read-only memory (EEPROM), an optical disc (including a compact disc read-only memory (CD-ROM), a compressed optical disc, a laser disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 303 may exist independently and be connected to the processor 301 via the communication bus 302. The memory 303 may also be integrated with the processor 301.

[0066] The communication interface 304 uses any transceiver-like device for communicating with other devices or communication networks. The communication interface 304 includes a wired communication interface and may also include a wireless communication interface. Among them, the wired communication interface may be, for example, an Ethernet interface. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless communication interface may be a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof, etc.

[0067] As an embodiment, the processor 301 may include one or more CPUs, such as Figure 3 CPU0 and CPU1 are shown in the figure.

[0068] As an example, the computing device 300 may include multiple processors, such as Figure 3 301 and processor 305 shown in FIG. Each of these processors may be a single-core processor or a multi-core processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0069] As an embodiment, the computing device 300 may also include an output device and an input device. The output device communicates with the processor 301 and can display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 301 and can receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0070] In some embodiments, the memory 303 is used to store the program code 310 for executing the solution of the present application, and the processor 301 can execute the program code 310 stored in the memory 303. The program code 310 may include one or more software modules, and the computing device 300 can implement the data access method provided in the embodiment of the present application through the processor 301 and the program code 310 in the memory 303.

[0071] The method provided in the embodiment of the present application can be applied to a memory access scenario, which can also be referred to as a data read and write scenario or a data access scenario. In the memory access scenario, data is stored in the MTM, which includes different storage media. The access speeds of different storage media are different. This arrangement facilitates placing more commonly used data in a storage layer with a faster access speed. However, the data requested to be accessed by the host or peripheral may be stored in any level of storage media, and the time it takes for the MTM to return data at different levels is quite different.

[0072] Figure 4 and Figure 5 is a schematic diagram of the memory access process in the related art. Figure 4 In the related art, the core of the processor in the host or peripheral device acts as a data requester and sends a data access request to the MTM. The data access request carries a session tag (such as Tag X, abbreviated as TX) and the address corresponding to the requested data (such as address A, abbreviated as Addr-A). The storage controller in the MTM acts as a data responder and first searches for the data corresponding to the address in the cache. If the data is found in the cache, it means that the address hits the cache, and then returns a response to the data requester. The response carries the same session tag (i.e., Tag X) and the data (such as Data A, abbreviated as DA). After receiving the response, the data requester releases the session tag so that the session tag can be used by other data access requests.

[0073] If the data is not found in the cache, it means that the address does not hit the cache. In this case, see Figure 5 , the data responder continues to search for the data corresponding to the address from a deeper level of storage (such as NAND, etc.). Before the data responder returns the data, the data requester needs to wait for the data and keep the session flag bound to the data access request until the data requester releases the session flag after receiving the response returned by the data responder.

[0074] It can be seen that in the related art, when the core of the processor accesses the MTM, it cannot perceive the time required for data to return. For each core of the processor, the tasks in the task queue related to data access are executed serially. Therefore, the core of the processor cannot schedule other tasks while waiting for data to return, so the computing resources of the processor cannot be reasonably utilized. In addition, each access request issued by the core of the host or peripheral consumes a tag, and the number of tags is limited. If the MTM delays returning data, the corresponding tag cannot be reused. After the host / device runs out of tags, it cannot issue a new access request.

[0075] Based on this, an embodiment of the present application provides a data access method that enables a central processing unit or other accelerator to better schedule computing resources according to the time required for data return, improve task execution efficiency, and optimize processor performance.

[0076] It should be understood that the computing device architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of computing device architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0077] After introducing the terms and implementation environment involved in the embodiments of the present application, the data access method provided by the embodiments of the present application is explained in detail.

[0078] Figure 6 This is a flow chart of a data access method provided by an embodiment of the present application. The method is applied to a computing device, and specifically to a processor core and a storage controller in the computing device, wherein the processor core acts as a data requester and the storage controller acts as a data responder. Figure 6 , the method comprises the following steps.

[0079] Step 601: the data requester schedules the first task in the task queue and sends a first access request to the data responder. The first access request carries a first address. The first task indicates to obtain the first data corresponding to the first address. The tasks in the task queue are executed serially.

[0080] In an embodiment of the present application, the tasks in the task queue that the data requester needs to schedule are executed serially. When the first task in the task queue is scheduled, the data requester sends a first access request to the data responder, and the first access request carries a first address. In order to identify an access request and response process, the first access request also carries a first session flag, which is denoted as Tag. A session flag is used to identify an access request and response process. The data requester selects an idle flag from at least one idle flag as the first session flag, and binds the first session flag to the first access request.

[0081] The at least one idle flag may be a flag in a flag pool, that is, the session flag resource is stored in the form of a flag pool, and the data requester searches for an idle flag from the flag pool as the first session flag. Each flag in the flag pool corresponds to a flag state, and the flag state may be an idle state or a non-idle state. The data requester modifies an idle flag to a non-idle flag by modifying the flag state, and uses the obtained non-idle flag as the first session flag. Alternatively, the flag pool includes an idle flag set and a non-idle flag set, each flag in the idle flag set is an idle flag, and each flag in the non-idle flag set is a non-idle flag. The data requester moves a flag in the idle flag set out to the non-idle flag set, and the moved flag is used as the first session flag. Of course, the session flag resource may also be stored in other forms, and the embodiments of the present application are not limited to this.

[0082] Among them, the tasks in the task queue can be randomly selected, or scheduled according to the task priority, or one or a combination of multiple rules in the task generation order, or can be scheduled according to other rules, which is not limited in the embodiments of the present application.

[0083] Each task in the task queue indicates to obtain data corresponding to one or more addresses, and the data of the one or more addresses can be requested simultaneously or sequentially. Taking the first task as an example, if the first task indicates to obtain data corresponding to one or more addresses, and the one or more addresses include a first address and a second address, then the first access request carries the first address, or the first access request carries the first address and the second address.

[0084] Step 602: The data responder receives a first access request from the data requester, and determines whether the first address hits the cache.

[0085] After receiving the first access request, the data responder first searches the cache for the first data corresponding to the first address. If the first data is found in the cache, it indicates that the first address hits the cache. If the first data is not found in the cache, it indicates that the first address does not hit the cache.

[0086] The first address may be a virtual address, and the data responder searches for the first data from the cache through address translation (or address conversion). The cache includes multiple cache lines, and the data responder searches for the cache line where the first address is located from the cache. If the cache line where the first address is located is found, it is determined that the first address hits the cache. If the cache line where the first address is located is not found, it is determined that the first address does not hit the cache.

[0087] Step 603: If the first address does not hit the cache, the data responder sends a first response to the data requester. The first response carries first time information. The first time information indicates the estimated time required by the data responder to return the first data.

[0088] If the first address does not hit the cache, the data responder first estimates the time required to return the first data, that is, estimates the first time, and generates a first response carrying the first time information based on the first time, and returns the first response to the data requester. That is, the data responder first directly returns the estimated time required to return the first data to the data requester, without waiting for a certain period of time to obtain the data before returning a response to the data requester.

[0089] Among them, the first time information may include an absolute time, such as a first moment represented by a timestamp, such as 14:30, and the first time information may also include a relative time, that is, a duration, for example, the first time information includes a first duration, such as 500 nanoseconds.

[0090] In the embodiment of the present application, the first response also carries a first delayed return flag, and a delayed return flag is used to identify a data delayed return process. The delayed return flag can be recorded as MTM Tag.

[0091] The first data is stored in a first storage level in a multi-level storage (MTM), and the first time information is determined according to the access speed of the first storage level, and the access speeds of different storage levels are different. That is, this solution can determine the first time information according to the storage level where the first data is located.

[0092] Optionally, the computing device stores the data return time corresponding to each storage level, and the data return time corresponding to each storage level can be set to a fixed value by the manufacturer or user of the computing device. Alternatively, the storage controller can obtain the average data read time corresponding to each storage level, and the average data read time can be determined in real time, periodically, or according to a set time. The average data read time can be determined by the controller or manager of the corresponding storage medium, or by other devices, and the embodiments of the present application do not limit this.

[0093] After determining that the first address does not hit the cache, the data responder continues to obtain the first data from a storage medium outside the cache and stores the first data in the cache, that is, the data responder continues to obtain the first data from a storage medium at a deeper level.

[0094] Optionally, after storing the first data in the cache, the data responder records the state of the first data in the cache as a valid state, and the valid state is used to prevent the first data from being removed from the cache.

[0095] There may be many ways to record a valid state, which is not limited in the embodiments of the present application. For example, when the first response also carries a first delayed return flag, and the first data is stored in a first cache line included in the cache, the data responder records the state of the first data as a valid state by storing the first delayed return flag in the first field of the first cache line. It should be understood that when the first delayed return flag is stored in the first field, it indicates that the state of the first data is a valid state, and when the first delayed return flag is not stored in the first field, or when the first cache line does not include the first field, it indicates that the state of the first data is an invalid state. Data in an invalid state can be moved out of the cache on demand according to conventional cache line elimination policies.

[0096] For another example, the data responder records that the state of the first data is a valid state by storing the first attribute value in the second field of the first cache line. The first attribute value may be any set value, such as the first attribute value is 1. It should be understood that when the value of the second field is a non-first attribute value, it indicates that the state of the first data is an invalid state. The non-first attribute value may be any value other than the first attribute value, such as the non-first attribute value is 0.

[0097] As can be seen from the above, the first access request also carries the first session flag, and a session flag is used to identify an access request and response process. Correspondingly, the first response also carries the first session flag. After receiving the first response, the data responder releases the first session flag as an idle flag. For example, the data responder changes the flag state of the first session flag to an idle state, or the data responder moves the first session flag from the non-idle flag set in the flag pool to the idle flag set.

[0098] In an embodiment of the present application, when the first address does not hit the cache, the data responder first returns a first response carrying the first time information to the data requester. In other possible embodiments, when the first address does not hit the cache, if the data responder determines that the first duration indicated by the first time information exceeds the threshold, the data responder sends a first response carrying the first time information to the data requester, and if the data responder determines that the first duration indicated by the first time information does not exceed the threshold, the data responder continues to obtain the first data, and returns a second response carrying the first data to the data requester after obtaining the first data. That is, when the data responder determines that it does not take a long time to obtain the first data, it can still obtain and return the first data according to the conventional process without feeding back the estimated time required to return the first data to the data requester. When the data responder determines that it takes a long time to obtain the first data, it first feeds back the estimated time required to return the first data to the data requester, so that the data requester can schedule other tasks during the longer waiting time.

[0099] Step 604: If a first response carrying first time information is received, and a first duration indicated by the first time information exceeds a threshold, the data requester schedules a second task in the task queue.

[0100] If the data requester receives the first response carrying the first time information, the data requester can choose to wait for the first data or schedule other tasks in the task queue according to the length of the first time duration indicated by the first time information. In this way, there is no need to blindly wait for data to be returned, and the various tasks that the data requester needs to perform can be reasonably arranged, and the computing resources of the data requester can be reasonably scheduled.

[0101] If the first duration indicated by the first time information exceeds the threshold, the data requester schedules the second task in the task queue, that is, interrupts the first task and schedules the second task. If the first duration indicated by the first time information does not exceed the threshold, the data requester waits for the first data to be returned, that is, does not interrupt the first task.

[0102] In some other possible embodiments, the data requester may also select to schedule the second task in the task queue after receiving the first response carrying the first time information, regardless of whether the first duration indicated by the first time information is long or short. For example, if the first response is sent when the data responder determines that the first duration exceeds a threshold, then the data requester may directly schedule the second task in the task queue after receiving the first response carrying the first time information.

[0103] As can be seen from the above, the embodiments of the present application enable the processor to more reasonably arrange data access-related tasks and more reasonably schedule computing resources, thereby improving the utilization of computing resources, improving task execution efficiency and overall performance.

[0104] In the embodiment of the present application, the first time information is the time information estimated by the data responder. The data responder may obtain the first data before or after the first duration indicated by the first time information arrives, and store the first data in the cache. That is to say, the data responder may prepare the data in advance or delay returning the data. This will be introduced below.

[0105] First, we introduce the situation where the data responder prepares the data in advance.

[0106] In one implementation, after the data responder stores the first data in the cache, it sends a first message to the data requester, and the first message indicates that the first data is ready, for example, the first message carries 'Data ready' or other prompt information. Accordingly, after the data requester receives the first response carrying the first time information, if it receives the first message from the data responder before the end of the first time period, it sends a second access request to the data responder, and the second access request still carries the first address. In addition, the second access request also carries a second session flag, which may be the same as the first session flag or may be different from the first session flag. If the data responder receives the second access request from the data requester, it determines again whether the first address hits the cache. If the first address hits the cache, the data requester sends a second response carrying the first data to the data requester, and the second response also carries the second session flag. It should be understood that in this case, if there is no abnormality, the first address will definitely hit the cache.

[0107] From the foregoing, it can be seen that after the data responder stores the first data in the cache, it sets the state of the first data to a valid state. Correspondingly, after the data responder returns a second response carrying the first data to the data requester, it modifies the state of the first data to an invalid state, so that the first data can be moved out of the cache as needed according to the conventional cache line elimination strategy.

[0108] Optionally, the data responder modifies the state of the first data to an invalid state by deleting the first field included in the first cache line or deleting the first delayed return flag in the first field. Alternatively, the data responder modifies the state of the first data to an invalid state by modifying the value of the second field included in the second field in the first cache line to a non-first attribute value.

[0109] As can be seen from the foregoing, the first response also carries a first delayed return flag, and a delayed return flag is used to identify a data delayed return process. Correspondingly, the first message also carries the first delayed return flag.

[0110] In the above implementation, the data responder does not return data directly, but first notifies the data requester that the data is ready. Then the data requester still requests the first data in a one-request-one-response manner, so that it is compatible with related protocols.

[0111] In another implementation, after the data responder stores the first data in the cache, it sends a second message to the data requester, and the second message carries the first data. That is, the data responder returns the first data directly to the data requester without first notifying the data requester that the data is ready, which can save a certain amount of time. Accordingly, after receiving the first response carrying the first time information, if the data requester receives the second message carrying the first data before the first duration ends, it determines that the first task is completed.

[0112] In order to facilitate the data requester to know which data is carried in the second message, the second message also carries the first address, or the first delayed return flag, or the first address and the first delayed return flag, or any other information that can let the data requester know the data correspondence.

[0113] Next, we will introduce the situation where the data responder delays returning data.

[0114] After receiving the first response carrying the first time information, if the data requester still fails to obtain the first data at the end of the first time period, the data requester sends a third access request to the data responder, and the third access request still carries the first address, that is, the data requester continues to perform the first task. In addition, the third access request also carries a third session flag, and the third session flag may be the same as the first session flag, or may be different from the first session flag. Accordingly, after the data responder determines that the first address does not hit the cache, if the data responder receives the third access request from the data requester before returning the first data to the data requester, it is determined again whether the first address hits the cache. If the first address still does not hit the cache, the data responder sends a third response to the data requester, and the third response carries the second time information, and the second time information indicates the time required for the data responder to re-estimate the return of the first data. In addition, the third response also carries the first delayed return flag and the third session flag.

[0115] Among them, the way in which the data responder re-estimates the time required to return the first data can be the same as the way in which the time required to return the first data is estimated for the first time, or it can be different. For example, the data responder estimates the time required to return the first data for the first time according to a set fixed value or the average data reading time corresponding to each storage level, and the non-first time is to subtract a certain step length from the last estimated time to obtain the current estimated time. For example, the second time is to subtract a certain step length from the first estimated first time to obtain the second estimated second time. Alternatively, the non-first time is still to determine the estimated time according to the average data reading time corresponding to each storage level determined in real time, or the non-first time can also re-estimate the time in any other possible way. Among them, the second time is the time indicated by the second time information.

[0116] After the data requester sends the third access request to the data responder, if the third response carrying the second time information is received, and the second duration indicated by the second time information exceeds the threshold, the third task in the task queue is scheduled, and the second duration refers to the duration required for the data responder to re-estimate the return of the first data. The third response may also be called the second response in some other embodiments, and the words "first", "second" and the like in the embodiments of the present application do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit them to be different.

[0117] It can be seen from the embodiments described above that after the data requester sends the third access request to the data responder, it is possible to receive a response carrying the first data, that is, when the first time duration arrives, the data responder just obtains the first data.

[0118] In addition to the above-mentioned advance preparation of data and delayed return of data, the data requester may also terminate the task early, which will be introduced next.

[0119] After receiving the first response carrying the first time information, if the data requester determines to terminate the first task before the first time period ends, the data requester sends a third message to the data responder, and the third message indicates that the data responder does not need to continue to obtain the first data. Correspondingly, after sending the first response to the data requester, if the data responder receives the third message from the data requester before returning the first data to the data requester, the task of returning the first data to the data requester is terminated.

[0120] Among them, the implementation method of the data responder terminating the task of returning the first data to the data requester includes: if the first data has not yet been acquired in the cache, stop acquiring the first data; if the first data has been stored in the cache, delete the first data from the cache.

[0121] In order to let the data responder know which data to stop acquiring, the third message carries the first delayed return flag, or carries the first address, or carries the first delayed return flag and the first address, or carries any other possible information that can let the data responder know which data to stop acquiring.

[0122] In an embodiment of the present application, the first delayed return flag is generated by the data responder and is used to identify a data delayed return process, and optionally, is also used to identify the first cache line. When the data responder successfully returns the first data to the data requester, or when it is determined to terminate the first task, the first delayed return flag may be released.

[0123] Next, the present solution will be further explained by means of some embodiments.

[0124] Example 1:

[0125] Figure 7 1 is a data access flow chart of Example 1 provided in the embodiment of the present application. For example, after a certain address misses the cache, the core of the processor initiates another access request, and the access request hits the cache. Figure 7 , the core of the processor in the host or peripheral initiates request 1 to the MTM. Request 1 is a data read request for address 0x1000 (i.e., an access request). Request 1 carries 'MemRd, Tag=0x0, Address=0x1000', where 'MemRd' indicates a read operation, 'Tag=0x0' indicates a session flag, and 'Address=0x1000' indicates the above address. The MTM controller in the MTM determines that the address cache misses and returns response 1 to the core of the processor. Response 1 indicates that it needs to wait for 300 nanoseconds (ns). For example, response 1 carries 'MemData Delay, Tag=0x0, Expected time=300ns, MTM Tag=0x1', where 'MemData Delay' indicates delay prompt information, 'Expected time=300ns' indicates the estimated time required for delayed return of data, and 'MTM Tag=0x1' indicates a delayed return flag. After receiving response 1, the core of the processor releases Tag 0x0.

[0126] While waiting for the data corresponding to address 0x1000, the core of the processor initiates request 2 to the MTM. Request 2 is a request to read the data at address 0x8000. Request 2 carries 'MemRd, Tag = 0x1, Address = 0x8000'. The MTM controller determines that the address is a cache hit and immediately returns response 2 carrying the corresponding data. Response 2 carries 'MemData, Tag = 0x1, Address = 0x8000'. Among them, 'MemData' represents the data corresponding to address 0x8000, and the data is represented as D-0x8000 in the figure. After receiving response 2, the core of the processor releases Tag 0x1.

[0127] 300ns after receiving response 1, the core of the processor initiates request 3 to the MTM to initiate a data read request for address 0x1000 again. Request 3 carries 'MemRd, Tag = 0x2, Address = 0x1000'. The MTM controller finds that the address hits the cache, that is, the corresponding data is in the cache, and returns response 3 to the core of the processor and releases MTM Tag 0x1. Response 3 carries 'MemData, Tag = 0x2, Address = 0x1000'. Among them, 'MemData' represents the data corresponding to address 0x1000. After receiving response 3, the core of the processor releases Tag 0x2.

[0128] As can be seen from Example 1, the processor core can continue to schedule other tasks during the data waiting period without blindly waiting for data to return.

[0129] Example 2:

[0130] Figure 8 This is a data access flow chart of Example 2 provided in the embodiment of the present application. Take the example of MTM preparing data in advance after a certain address misses the cache, see Figure 8 , the processor core initiates request 1 to the MTM. Request 1 is a data read request for address 0x2000. Request 1 carries 'MemRd, Tag = 0x0, Address = 0x2000'. The MTM controller determines that the address is cache miss and returns response 1 to the processor core. Response 1 indicates that it needs to wait for 500ns. For example, response 1 carries 'MemDataDelay, Tag = 0x0, Expected time = 500ns, MTM Tag = 0x1'. After receiving response 1, the processor core releases Tag 0x0.

[0131] After 100ns, the MTM determines that the data is ready, that is, the MTM has obtained the data from the deeper level of storage and stored it in the cache. Then the MTM controller sends message 1 to the core of the processor to indicate that the data is ready. Message 1 carries 'MTM Message, MTM Tag = 0x1, Data ready'. After the core of the processor receives message 1, it initiates request 2 to initiate a data read request for address 0x2000 again. Request 2 carries 'MemRd, Tag = 0x1, Address = 0x2000'. The MTM controller finds that the address hits the cache, that is, the corresponding data is in the cache, then returns response 2 to the core of the processor and releases MTM Tag 0x1. Response 2 carries 'MemData, Tag = 0x1, Address = 0x2000'. Among them, 'MemData' represents the data corresponding to address 0x2000. After receiving response 2, the core of the processor releases Tag 0x1.

[0132] As can be seen from Example 1, while the core of the processor is waiting for data, if the MTM notifies the core of the processor to prepare the data in advance, the core of the processor does not need to wait until the estimated time to initiate the request, thus not delaying the task execution.

[0133] Example 3:

[0134] Fig. 9 , is a data access flow chart of Example 3 provided in the embodiment of the present application. For example, after a certain address misses the cache, the core of the processor gives up accessing the corresponding data during the waiting period for data, see Fig. 9 , the processor core initiates request 1 to the MTM. Request 1 is a data read request for address 0x5000. Request 1 carries 'MemRd, Tag = 0x0, Address = 0x5000'. The MTM controller determines that the address is a cache miss and returns response 1 to the processor core. Response 1 indicates that it needs to wait for 500ns. For example, response 1 carries 'MemData Delay, Tag = 0x0, Expected time = 500ns, MTM Tag = 0x1'. After receiving response 1, the processor core releases Tag 0x0.

[0135] Before the end of 500ns, for example, at 100ns, the processor core determines to abandon access to the data corresponding to address 0x5000 due to process termination or other reasons, and sends message 1 to MTM to indicate the termination of the corresponding task. Message 1 carries 'MTMMessage, MTM Tag = 0x1, Drop command'. After receiving message 1, the MTM controller determines to stop acquiring the data corresponding to address 0x5000 and releases MTM Tag 0x1. If the data has been stored in the cache, the MTM deletes the data in the cache. If the data has not been acquired in the cache, the MTM stops acquiring the data from a deeper level of storage.

[0136] As can be seen from Example 3, if the core of the processor determines to terminate the task during the waiting period for data, the MTM can be notified to stop acquiring the corresponding data to avoid wasting cache space.

[0137] In summary, in the embodiment of the present application, under the premise that the tasks in the task queue are executed serially, if the first response carrying the first time information is received after the first task in the scheduling task queue and the first access request is sent to the data responder, and the first time information indicates that the data responder estimates that the time required to return the corresponding data exceeds the threshold, the data requester will temporarily interrupt the first task and schedule the second task in the task queue. Simply put, the data requester can choose to continue waiting for data or schedule other tasks based on the length of time the data responder estimates to return the data, thereby reasonably scheduling the task queue, reducing unnecessary waste of time resources, more reasonably scheduling computing resources, and improving overall performance.

[0138] In addition, if the data requester gives up access to the corresponding data, the data responder can be notified to stop the corresponding task. If the data responder receives a message to stop the corresponding task, if the data is not ready yet, the data responder does not need to go to a deeper level of storage to obtain the data in order to execute the next task. If the data is ready, the data responder can move the corresponding data out of the cache to free up space to cache other data. If the data responder prepares the data in advance, the data requester can be notified to initiate the access request again in advance without waiting for the estimated time.

[0139] Fig.10 is a structural diagram of a data access device provided in an embodiment of the present application. The data access device can be implemented by software, hardware or a combination of both to become part or all of a computing device. The computing device can be Figure 3 The computing device shown. In the embodiment of the present application, the device is included in the data requester. Fig.10 The device includes: a first scheduling module 1001 and a second scheduling module 1002.

[0140] The first scheduling module 1001 is used to schedule the first task in the task queue and send a first access request to the data responder, the first access request carries a first address, the first task indicates to obtain the first data corresponding to the first address, and the tasks in the task queue are executed serially;

[0141] The second scheduling module 1002 is used to schedule the second task in the task queue if a first response carrying first time information is received and the first duration indicated by the first time information exceeds a threshold, where the first duration refers to the duration estimated by the data responder to return the first data.

[0142] Optionally, the device further comprises:

[0143] The first sending module is used to send a second access request to the data responder after receiving a first response carrying first time information, if a first message from the data responder is received before the end of a first time period, the second access request carries the first address, and the first message indicates that the first data is ready.

[0144] Optionally, the device further comprises:

[0145] The determination module is used to determine that the first task is completed if a second message carrying the first data is received before the first time period ends after receiving the first response carrying the first time information.

[0146] Optionally, the device further comprises:

[0147] The second sending module is used to send a third access request carrying the first address to the data responder after receiving the first response carrying the first time information if the first data is still not obtained at the end of the first time period.

[0148] Optionally, the device further comprises:

[0149] The third scheduling module is used to schedule the third task in the task queue after sending a third access request to the data responder, if a second response carrying second time information is received, and the second duration indicated by the second time information exceeds a threshold, where the second duration refers to the time re-estimated by the data responder to return the first data.

[0150] Optionally, the device further comprises:

[0151] The third sending module is used to send a third message to the data responder after receiving the first response carrying the first time information, if it is determined to terminate the first task before the end of the first time period, and the third message indicates that the data responder does not need to continue to obtain the first data.

[0152] Optionally, the first response and any of the above messages also carry a first delayed return flag, where a delayed return flag is used to identify a data delayed return process.

[0153] Optionally, the first access request and the first response both further carry a first session flag, where a session flag is used to identify an access request and response process;

[0154] The device also includes:

[0155] a flag binding module, configured to select an idle flag from at least one idle flag as a first session flag and bind the first session flag to the first access request before receiving a first response carrying the first time information;

[0156] The flag releasing module is used to release the first session flag as an idle flag after receiving the first response carrying the first time information.

[0157] Optionally, the first data is stored in a first storage level in a multi-level storage, and the first time information is determined according to an access speed of the first storage level, and access speeds of different storage levels are different.

[0158] Optionally, the data requester is a core of a processor.

[0159] In an embodiment of the present application, under the premise that the tasks in the task queue are executed serially, if the first response carrying the first time information is received after the first task in the task queue is scheduled and the first access request is sent to the data responder, and the first time information indicates that the data responder estimates that the time required to return the corresponding data exceeds the threshold, the data requester will temporarily interrupt the first task and schedule the second task in the task queue. In simple terms, the data requester can choose to continue waiting for data or schedule other tasks based on the estimated time required for the data responder to return the data, thereby reasonably scheduling the task queue, reducing unnecessary waste of time resources, more reasonably scheduling computing resources, and improving overall performance.

[0160] It should be noted that: the data access device provided in the above embodiment only uses the division of the above functional modules as an example to illustrate when accessing data. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the data access device provided in the above embodiment and the data access method embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0161] Fig.11is a structural diagram of a data access device provided in an embodiment of the present application. The data access device can be implemented by software, hardware or a combination of both to become part or all of a computing device. The computing device can be Figure 3 The computing device shown. In the embodiment of the present application, the device is included in the data responder. Fig.11 The device includes: a receiving module 1101, a determining module 1102 and a sending module 1103.

[0162] A receiving module 1101 is configured to receive a first access request from a data requester, where the first access request carries a first address;

[0163] A determination module 1102, configured to determine whether the first address hits the cache;

[0164] The sending module 1103 is used to send a first response to the data requester if the first address does not hit the cache. The first response carries first time information, which indicates the estimated time required for the data responder to return the first data. The first data is the data corresponding to the first address.

[0165] Optionally, the device further comprises:

[0166] an acquisition module, configured to acquire the first data from a storage medium other than the cache after determining that the first address does not hit the cache, and store the first data in the cache;

[0167] The recording module is used to record in the cache that the state of the first data is a valid state, and the valid state is used to prevent the first data from being removed from the cache.

[0168] Optionally, the first response further carries a first delayed return flag, and the first data is stored in a first cache line included in the cache;

[0169] The logging module is specifically used for:

[0170] Recording the state of the first data as a valid state by storing a first delayed return flag in a first field of the first cache line; or,

[0171] The state of the first data is recorded as a valid state by storing the first attribute value in the second field of the first cache line.

[0172] Optionally, the sending module 1103 is further used to: after storing the first data in the cache, send a first message to the data requester, where the first message indicates that the first data is ready.

[0173] Optionally, the receiving module 1101 is further configured to: after sending the first message to the data requester, receive a second access request from the data requester, where the second access request carries the first address;

[0174] The determination module 1102 is further used to: determine again whether the first address hits the cache;

[0175] The sending module 1103 is further used for: if the first address hits the cache, sending a second response to the data requester, and modifying the state of the first data to an invalid state, and the second response carries the first data.

[0176] Optionally, the sending module 1103 is further used to: after storing the first data in the cache, send a second message to the data requester, where the second message carries the first data.

[0177] Optionally, the determination module 1102 is further configured to: after determining that the first address does not hit the cache, if a third access request from the data requester is received before the first data is returned to the data requester, determine again whether the first address hits the cache, the third access request carrying the first address;

[0178] The sending module 1103 is also used to: if the first address still does not hit the cache, send a third response to the data requester, the third response carries second time information, and the second time information indicates the time length that the data responder re-estimates to be required to return the first data.

[0179] Optionally, the device further comprises:

[0180] A termination module is used to terminate the task of returning the first data to the data requester after sending a first response to the data requester and before returning the first data to the data requester if a third message from the data requester is received before returning the first data to the data requester, wherein the third message indicates that the data responder does not need to continue to obtain the first data.

[0181] Optionally, the termination module is specifically used for:

[0182] If the first data is still not acquired in the cache, stop acquiring the first data;

[0183] If the first data is already stored in the cache, the first data is deleted from the cache.

[0184] Optionally, the first response and any of the above messages also carry a first delayed return flag, where a delayed return flag is used to identify a data delayed return process.

[0185] Optionally, the first data is stored in a first storage level in a multi-level storage, and the first time information is determined according to an access speed of the first storage level, and access speeds of different storage levels are different.

[0186] Optionally, the data responder is a storage controller.

[0187] In an embodiment of the present application, under the premise that the tasks in the task queue are executed serially, if the first response carrying the first time information is received after the first task in the task queue is scheduled and the first access request is sent to the data responder, and the first time information indicates that the data responder estimates that the time required to return the corresponding data exceeds the threshold, the data requester will temporarily interrupt the first task and schedule the second task in the task queue. In simple terms, the data requester can choose to continue waiting for data or schedule other tasks based on the estimated time required for the data responder to return the data, thereby reasonably scheduling the task queue, reducing unnecessary waste of time resources, more reasonably scheduling computing resources, and improving overall performance.

[0188] It should be noted that: the data access device provided in the above embodiment only uses the division of the above functional modules as an example to illustrate when accessing data. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the data access device provided in the above embodiment and the data access method embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0189] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disc (DVD)), or a semiconductor medium (e.g., a solid state disk (SSD)). It is worth noting that the computer-readable storage medium mentioned in the embodiment of the present application may be a non-volatile storage medium, in other words, a non-transient storage medium.

[0190] It should be understood that the "at least one" mentioned herein refers to one or more, and "multiple" refers to two or more. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.

[0191] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the embodiments of this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the first data involved in the embodiments of this application are all obtained with full authorization.

[0192] The above-mentioned embodiments are provided for the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data access method, characterized in that: Applied to a data requester, the method comprises: Scheduling a first task in a task queue, and sending a first access request to a data responder, wherein the first access request carries a first address, the first task indicates obtaining first data corresponding to the first address, and the tasks in the task queue are executed serially; If a first response carrying first time information is received, and a first duration indicated by the first time information exceeds a threshold, a second task in the task queue is scheduled, wherein the first duration refers to the duration estimated by the data responder to return the first data.

2. The method according to claim 1, characterized in that After receiving the first response carrying the first time information, the method further includes: If a first message from the data responder is received before the first duration ends, a second access request is sent to the data responder, where the second access request carries the first address, and the first message indicates that the first data is ready.

3. The method according to claim 1, characterized in that After receiving the first response carrying the first time information, the method further includes: If a second message carrying the first data is received before the first duration ends, it is determined that the first task is completed.

4. The method according to any one of claims 1 to 3, characterized in that After receiving the first response carrying the first time information, the method further includes: If the first data is still not acquired at the end of the first time period, a third access request is sent to the data responder, where the third access request carries the first address.

5. The method according to claim 4, characterized in that After sending the third access request to the data responder, the method further includes: If a second response carrying second time information is received, and the second duration indicated by the second time information exceeds the threshold, the third task in the task queue is scheduled, and the second duration refers to the time re-estimated by the data responder to return the first data.

6. The method according to any one of claims 1 to 5, characterized in that After receiving the first response carrying the first time information, the method further includes: If it is determined to terminate the first task before the first duration ends, a third message is sent to the data responder, where the third message indicates that the data responder does not need to continue to obtain the first data.

7. The method according to any one of claims 2, 3 and 6, characterized in that: Both the first response and the message further carry a first delayed return flag, where a delayed return flag is used to identify a data delayed return process.

8. The method according to any one of claims 1 to 7, characterized in that The first access request and the first response both further carry a first session flag, where a session flag is used to identify an access request and response process; Before receiving the first response carrying the first time information, the method further includes: selecting an idle flag from at least one idle flag as the first session flag, and binding the first session flag to the first access request; After receiving the first response carrying the first time information, the method further includes: releasing the first session flag as an idle flag.

9. The method according to any one of claims 1 to 8, characterized in that The first data is stored in a first storage level in a multi-level storage, and the first time information is determined according to an access speed of the first storage level, and access speeds of different storage levels are different.

10. The method according to any one of claims 1 to 9, characterized in that The data requester is a core of a processor.

11. A data access method, characterized in that: Applied to the data responder, the method includes: receiving a first access request from a data requester, wherein the first access request carries a first address; Determining whether the first address hits the cache; If the first address does not hit the cache, a first response is sent to the data requester, the first response carries first time information, and the first time information indicates the estimated time required by the data responder to return the first data, the first data being the data corresponding to the first address.

12. The method according to claim 11, characterized in that After determining that the first address does not hit the cache, the method further includes: Acquire the first data from a storage medium other than the cache, and store the first data in the cache; The state of recording the first data in the cache is a valid state, and the valid state is used to prevent the first data from being removed from the cache.

13. The method according to claim 12, characterized in that The first response also carries a first delayed return flag, and the first data is stored in a first cache line included in the cache; The state of recording the first data in the cache as a valid state includes: The state of the first data is recorded as the valid state by storing the first delayed return flag in the first field of the first cache line; or, The state of the first data is recorded as the valid state by storing a first attribute value in the second field of the first cache line.

14. The method according to claim 12 or 13, characterized in that After storing the first data in the cache, the method further includes: A first message is sent to the data requester, where the first message indicates that the first data is ready.

15. The method according to claim 14, characterized in that After sending the first message to the data requester, the method further includes: receiving a second access request from the data requester, where the second access request carries the first address; Determining again whether the first address hits the cache; If the first address hits the cache, a second response is sent to the data requester and the state of the first data is modified to an invalid state, and the second response carries the first data.

16. The method according to claim 12 or 13, characterized in that: After storing the first data in the cache, the method further includes: A second message is sent to the data requester, where the second message carries the first data.

17. The method according to any one of claims 11 to 16, characterized in that After determining that the first address does not hit the cache, the method further includes: If a third access request from the data requester is received before the first data is returned to the data requester, determining again whether the first address hits the cache, the third access request carrying the first address; If the first address still does not hit the cache, a third response is sent to the data requester, the third response carries second time information, and the second time information indicates the time length that the data responder re-estimates to be required to return the first data.

18. The method according to any one of claims 11 to 17, characterized in that After sending the first response to the data requester, the method further includes: If a third message from the data requester is received before the first data is returned to the data requester, the task of returning the first data to the data requester is terminated, and the third message indicates that the data responder does not need to continue to obtain the first data.

19. The method according to claim 18, characterized in that The terminating the task of returning the first data to the data requester includes: If the first data has not yet been acquired in the cache, stop acquiring the first data; If the first data has been stored in the cache, the first data is deleted from the cache.

20. The method according to any one of claims 14, 16, 18-19, characterized in that: Both the first response and the message further carry a first delayed return flag, where a delayed return flag is used to identify a data delayed return process.

21. The method according to any one of claims 11 to 20, characterized in that The first data is stored in a first storage level in a multi-level storage, and the first time information is determined according to an access speed of the first storage level, and access speeds of different storage levels are different.

22. The method according to any one of claims 11 to 21, characterized in that The data responder is a storage controller.

23. A data access device, characterized in that: Included in the data requester, the device includes: A first scheduling module, used for scheduling a first task in a task queue, and sending a first access request to a data responder, wherein the first access request carries a first address, the first task indicates obtaining first data corresponding to the first address, and the tasks in the task queue are executed serially; The second scheduling module is used to schedule the second task in the task queue if a first response carrying first time information is received and a first duration indicated by the first time information exceeds a threshold, wherein the first duration refers to the duration estimated by the data responder to return the first data.

24. A data access device, characterized in that: Included in the data responder, the device includes: A receiving module, configured to receive a first access request from a data requester, wherein the first access request carries a first address; A determination module, used to determine whether the first address hits the cache; A sending module is used to send a first response to the data requester if the first address does not hit the cache, the first response carries first time information, the first time information indicates the estimated time required by the data responder to return the first data, and the first data is the data corresponding to the first address.

25. A computing device, characterized in that The computing device includes a memory and a processor; The memory is used to store computer programs; The processor is used to execute the computer program to implement the method according to any one of claims 1 to 22.

26. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 22 are implemented.

27. A computer program product, characterized in that The computer program product stores computer instructions, and when the computer instructions are executed by a processor, the steps of the method according to any one of claims 1 to 22 are implemented.

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