Memory management method, memory storage device and memory control circuit unit

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The memory management method comprises the following steps: recording a random read count of each of a plurality of first physical units, wherein each first physical unit stores valid data; starting a data integration program; selecting a plurality of source physical units from the first physical units according to the random read count; and moving the valid data in the source physical unit to the target physical unit. Therefore, the delay of reading can be reduced.

Description

Technical Field

[0001] The present disclosure relates to a memory management method, and more particularly to a data integration method of a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit. Background Art

[0002] Portable electronic devices such as mobile phones and notebook computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable electronic devices listed above because they have the characteristics of data non-volatility, power saving, small size, and no mechanical structure.

[0003] During the operation of rewritable non-volatile memory modules, read behavior is usually divided into random read (RandomRead) and sequential read (SequentialRead). Random read is used for non-continuous access requirements, while sequential read is suitable for accessing large-scale and continuous data. The performance of the two read modes directly affects the overall system performance.

[0004] Another core mechanism of rewritable non-volatile memory modules is garbage collection (GC), which aims to centralize valid data into a certain block to release the storage capacity of more blocks. However, garbage collection operations require data movement and block erasure, and these additional costs may conflict with normal read operations. When garbage collection and random reads overlap, the read latency will increase significantly, resulting in a decrease in user experience. Summary of the invention

[0005] The present disclosure provides a memory management method, a memory storage device, and a memory control circuit unit, which can reduce read latency.

[0006] The present disclosure proposes a memory management method for a rewritable non-volatile memory module, which includes multiple physical units. The memory management method includes: recording a random read count of each of multiple first physical units, wherein each first physical unit stores valid data; starting a data integration program; selecting multiple source physical units from the first physical units according to the random read count; and moving the valid data in the source physical unit to a target physical unit. The storage unit in the source physical unit is used to store P bits, and the storage unit in the target physical unit is used to store Q bits, where P and Q are positive integers, and Q is greater than P.

[0007] In an embodiment of the present disclosure, the random read count of the source physical unit is smaller than the random read count of the physical unit that is not selected in the first physical unit.

[0008] In one embodiment of the present disclosure, the step of selecting a source physical unit according to a random read count includes: for each first physical unit, setting a priority according to the corresponding random read count and the size of valid data, wherein the priority and the random read count are negatively correlated, and the priority and the size of valid data are negatively correlated; and selecting a source physical unit from the first physical unit according to the priority.

[0009] In one embodiment of the present disclosure, the memory management method further includes: determining a programming mode of the target physical unit according to the random read count of the source physical unit, and the programming mode is a first sub-programming mode or a second sub-programming mode. In the first sub-programming mode, the storage unit in the target physical unit is used to store Q 1 In the second sub-programming mode, the storage unit in the target physical unit is used to store Q 2 bits. Q1 and Q2 are positive integers, and Q1 is less than Q2.

[0010] In one embodiment of the present disclosure, the step of determining the programming mode of the target physical unit according to the random read count of the source physical unit includes: if the random read count of the source physical unit is less than a threshold value, setting the programming mode of the target physical unit to the second sub-programming mode; if the random read count of the source physical unit is greater than or equal to the threshold value, setting the programming mode of the target physical unit to the first sub-programming mode.

[0011] In one embodiment of the present disclosure, the step of recording the random read count of each first physical unit includes: receiving multiple read instructions from the host system; and when two consecutive read instructions read different first physical units, updating the random read count of the first physical unit read by the latter of the two read instructions.

[0012] In an embodiment of the present disclosure, the step of recording the random read count of each first physical unit includes: for each first physical unit, calculating the ratio of the corresponding random read count divided by the total random read count as the random read count.

[0013] From another perspective, an embodiment of the present invention proposes a memory storage device, including: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module, including multiple physical units; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to perform multiple steps: record the random read count of each of a plurality of first physical units, wherein each first physical unit stores valid data; start a data integration program; select a plurality of source physical units from the first physical units according to the random read count; and move the valid data in the source physical unit to the target physical unit. A storage unit in the source physical unit is used to store P bits, and a storage unit in the target physical unit is used to store Q bits, where P and Q are positive integers, and Q is greater than P.

[0014] From another perspective, an embodiment of the present invention proposes a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple physical units. The memory control circuit unit includes: a host interface for coupling to a host system; a memory interface for coupling to a rewritable non-volatile memory module; a memory management circuit coupled to the host interface and the memory interface. The memory management circuit is used to perform multiple steps: record a random read count of each of a plurality of first physical units, wherein each first physical unit stores valid data; start a data integration program; select a plurality of source physical units from the first physical units according to the random read count; and move the valid data in the source physical unit to the target physical unit. A storage unit in the source physical unit is used to store P bits, and a storage unit in the target physical unit is used to store Q bits, where P and Q are positive integers, and Q is greater than P.

[0015] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0017] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0018] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0020] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0021] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0022] Figure 7 is a flow chart showing a memory management method according to an embodiment;

[0023] Figure 8 is a schematic diagram showing recording random read counts according to an embodiment;

[0024] Fig. 9 is a schematic diagram showing selection of a source physical unit according to an embodiment;

[0025] Fig.10 FIG. 4 is a schematic diagram showing a method of determining a programming mode of a target physical unit according to an embodiment. DETAILED DESCRIPTION

[0026] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0027] The terms “first,” “second,” etc. used herein do not particularly refer to an order or sequence, but are only used to distinguish elements or operations described with the same technical term.

[0028] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0029] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0030] Please refer to Figure 1 and Figure 2The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0031] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0032] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless manner.

[0033] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless network (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0034] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 A memory storage device 30 and a host system 31.

[0035] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0036] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42 and a rewritable non-volatile memory module 43.

[0037] The connection interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0038] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware form and perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0039] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules or other memory modules with the same characteristics.

[0040] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0041] In an exemplary embodiment, the storage cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical erase units. Specifically, the storage cells on the same word line may constitute one or more physical programming cells. If each storage cell can store more than 2 bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a storage cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a storage cell belongs to the upper physical programming cell. Generally speaking, in MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0042] In an exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of erased storage cells. For example, the physical erase unit is a physical block.

[0043] Figure 5 is a schematic diagram of a memory control circuit unit drawn according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0044] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to describing the operation of the memory control circuit unit 42 and the memory storage device 10.

[0045] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0046] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data) in the form of program code. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

[0047] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0048] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0049] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations (for example, changing the read voltage level or performing a garbage collection (GC) operation, etc.). These instruction sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0050] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0051] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 obtains a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correcting code and / or error detecting code. For example, the error checking and correction circuit 54 may use various encoding / decoding algorithms such as low density parity check code (LDPC code), BCH code, Reed-solomon code (RS code), exclusive OR (XOR) code, etc. to encode and decode data.

[0052] The buffer memory 55 is coupled to the memory management circuit 51 and used for temporarily storing data. The power management circuit 56 is coupled to the memory management circuit 51 and used for controlling the power of the memory storage device 10 .

[0053] In an exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0054] Figure 6 FIG. 1 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 610 ( 0 ) to 610 (C) in the rewritable non-volatile memory module 43 into a storage area 601 , a spare area 602 , and a system area 603 .

[0055] In an exemplary embodiment, a physical unit is composed of a plurality of consecutive or discontinuous physical addresses. In an exemplary embodiment, a physical unit may also refer to a virtual block (VB), and a virtual block may include one or more physical erase units.

[0056] In an exemplary embodiment, the physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g., from Figure 1 The free area 602 may store user data of the host system 11). For example, the physical units 610(0)~610(A) in the storage area 601 may store valid data and invalid data. The physical units 610(A+1)~610(B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the free area 602. In addition, the physical units in the free area 602 (or the physical units that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the free area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool.

[0057] In an exemplary embodiment, the memory management circuit 51 may configure the logical units 612(0)-612(D) to map the physical units 610(0)-610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In an exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple continuous or discontinuous logical addresses.

[0058] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data currently stored in the physical unit includes valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in the physical unit is invalid data.

[0059] In an exemplary embodiment, the memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table (L2Ptable). When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in the logical-to-physical mapping table.

[0060] In an exemplary embodiment, the memory management circuit 51 may store a specific type of data in the system area 603. For example, the physical units 610 (B+1) to 610 (C) in the system area 603 may be dedicated to store data of higher importance and / or data that is not intended to be accessed or modified by the host system 11. For example, the data of higher importance and / or data that is not intended to be accessed or modified by the host system 11 may include a logical-to-physical mapping table, a bad block management table, a wear leveling management table, a valid data management table, and / or other types of management data, which are not limited by the present invention. The logical-to-physical mapping table is used to record mapping information. This mapping information may reflect the mapping relationship between the logical unit and the physical unit. The bad block management table is used to record information related to at least one bad block in the rewritable non-volatile memory module 43. The wear leveling management table may be used to record information related to the wear status of at least one physical unit in the rewritable non-volatile memory module 43 (e.g., read count, write count, and / or erase count). The valid data management table may be used to record information related to a valid count of at least one physical unit in the rewritable non-volatile memory module 43 , wherein the valid count indicates the number of valid data in the physical unit.

[0061] In an exemplary embodiment, the memory management circuit 51 may not map any logical unit to a physical unit in the system area 603. Thus, the data stored in the system area 603 may be prevented from being accessed or modified by the host system 11.

[0062] In an exemplary embodiment, the physical units 610(0)-610(C) in the rewritable non-volatile memory module 43 may include first-type physical units and second-type physical units. For example, each physical unit in the rewritable non-volatile memory module 43 may be one of the first-type physical unit and the second-type physical unit. The data access speed of each first-type physical unit may be higher than the data access speed of each second-type physical unit, and / or the data capacity of each first-type physical unit may be less than the data capacity of each second-type physical unit.

[0063] In an exemplary embodiment, the first type of physical unit can be regarded as a temporary storage area or buffer area for data, and the second type of physical unit can be regarded as a storage area for data. In an exemplary embodiment, data from the host system 11 can be quickly stored in the first type of physical unit through higher write efficiency. In response to the data from the host system 11 being stored in the first type of physical unit, a write completion message can be returned to the host system 11. Thereafter, the data stored in the first type of physical unit can be copied to the second type of physical unit with larger data capacity for storage in the background operation. Then, the used first type of physical unit can be released and erased to continuously receive (i.e., store) new data from the host system 11.

[0064] In an exemplary embodiment, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to program the first type of physical cells based on a certain programming mode (also referred to as the first programming mode) to store data in the first type of physical cells. On the other hand, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to program the second type of physical cells based on another programming mode (also referred to as the second programming mode) to store data in the second type of physical cells. The first programming mode is different from the second programming mode.

[0065] In an exemplary embodiment, the first programming mode is used to store P bits in a single memory cell in a first type of physical cell, and the second programming mode is used to store Q bits in a single memory cell in a second type of physical cell. P and Q are both positive integers, and P is not equal to Q.

[0066] In an exemplary embodiment, P is less than Q. For example, P may be "1", and Q may be "2", "3", or "4". In an exemplary embodiment, when the number of storage units is the same, the data capacity of each first-type physical unit may be P / Q of the data capacity of each second-type physical unit. For example, assuming that P and Q are "1" and "4" respectively, the data capacity of each first-type physical unit may be 1 / 4 of the data capacity of each second-type physical unit.

[0067] In an exemplary embodiment, the first programming mode refers to one of an SLC programming mode, a pseudo SLC programming mode, a lower physical programming mode, a mixture programming mode, and a less layer memory cell mode. In the SLC programming mode and the pseudo SLC programming mode, a memory cell stores only one bit of data. In the lower physical programming mode, only the lower physical programming cell will be programmed, and the upper physical programming cell corresponding to the lower physical programming cell may not be programmed. In the mixture programming mode, valid data (or real data) will be programmed in the lower physical programming cell, and at the same time, dummy data will be programmed into the upper physical programming cell corresponding to the lower physical programming cell storing the valid data. In the less layer memory cell mode, a memory cell stores a first number of bits of data. For example, this first number can be set to "1".

[0068] In an exemplary embodiment, the second programming mode includes a plurality of sub-programming modes, in which a storage unit can store different numbers of bits. For example, these sub-programming modes include MLC programming mode, TLC programming mode, QLC programming mode or similar modes. In particular, when the memory management circuit 51 writes data to a physical unit, a parameter can be added to the write instruction to determine the sub-programming mode, that is, the sub-programming mode of a physical unit can be dynamically determined.

[0069] Figure 7 is a flow chart showing a memory management method according to an embodiment. Figure 7 Steps 701 to 705 are executed by the memory management circuit 51 and will not be repeated hereafter. In step 701, a random read count of each of a plurality of first physical units is recorded, wherein each first physical unit stores valid data. For example, these first physical units are the first type of physical units mentioned above, and these first physical units store data in a first programming mode (e.g., SLC programming mode).

[0070] Figure 8 is a schematic diagram showing recording random read counts according to an embodiment. Figure 8 , it is assumed that there are three first physical units 811~813, and the host system 11 issues read instructions 801~805. Each read instruction has a logical address. According to the logical-to-physical mapping table, the logical address can be converted into a physical address and the corresponding physical unit can be found. In this example, the read instruction 801 is used to read the valid data in the physical unit 811; the read instruction 802 is used to read the valid data in the physical unit 811; the read instruction 803 is used to read the valid data in the physical unit 812; the read instruction 804 is used to read the valid data in the physical unit 813; and the read instruction 805 is used to read the valid data in the physical unit 812.

[0071] In this example, when two consecutive read instructions read valid data in the same physical unit, it is considered a sequential read; when two consecutive read instructions read valid data in different physical units, it is considered a random read. Specifically, the memory management circuit 51 receives read instructions 801-805 from the host system 11. When there are two consecutive read instructions that read different physical units 811-813, the random read count of the physical unit read by the latter of the two read instructions is updated. For example, the read instructions 801-802 read the same physical unit 811, so the random read count is not updated. The read instructions 802 and 803 read different physical units 811 and 812 respectively, so the random read count of the physical unit 812 read by the read instruction 803 is updated, such as increasing the random read count. The larger the random read count is, the higher the frequency (or probability) of the valid data stored in the corresponding physical unit being randomly read. The definition of the random read count will be further explained below. Read instructions 803 and 804 read different physical units 812 and 813, respectively, so the random read count of physical unit 813 read by read instruction 804 is updated. Read instructions 804 and 805 read different physical units 813 and 812, respectively, so the random read count of physical unit 812 read by read instruction 805 is updated.

[0072] In some embodiments, if two consecutive read instructions read different physical units, but the physical addresses to be accessed by the two read instructions are continuous, it will not be considered as a random read. For example, the physical address to be accessed by read instruction 802 is PBA, and the physical address to be accessed by read instruction 803 is PBA+1. Although read instructions 802 and 803 read different physical units 811 and 812 respectively, since the two physical addresses to be accessed are continuous, they are not considered as random reads, and the random read count of physical unit 812 will not be updated. In addition, it is assumed that the physical address to be read by read instruction 804 is PBA+K, where K is a positive integer greater than 2. In such an example, read instructions 803 and 804 read different physical units, and the physical addresses to be accessed are not continuous, so they are considered as random access, and the random read count of physical unit 813 will be updated.

[0073] In some embodiments, the random read count is defined as the ratio of the number of random reads divided by the total number of random reads. Each time the random read count is updated, the number of random reads is increased by 1. Figure 8In the example, the random read count of physical unit 811 is 0, the random read count of physical unit 812 is 2, and the random read count of physical unit 813 is 1. The total number of random reads is 2+1=3. Therefore, the random read count of physical unit 811 is 0, the random read count of physical unit 812 is 2 / 3, and the random read count of physical unit 813 is 1 / 3. In such an example, valid data in physical unit 812 has a higher frequency of being randomly read, while valid data in physical unit 813 has a lower frequency of being randomly read.

[0074] In other embodiments, the random read count may be directly set to be equal to the random read count, or the ratio of the random read count divided by the total read count (including random reads and sequential reads) may be set as the random read count.

[0075] When data is stored in physical units in the first programming mode, the read latency is usually lower (compared to the second programming mode). For sequential reads, because of the interleave mechanism, other operations can be performed while waiting for a physical unit to be read, which has less impact on the read performance. However, when reading randomly, it is more difficult to rely on the interleave mechanism, which makes it impossible for the read latency to be hidden in other operations. In this embodiment, the randomly read data is kept in the physical units of the first programming mode as much as possible, which can reduce the read latency. The specific approach is to select the source physical unit according to the random read count when performing the data integration operation, or to set the programming mode of the target physical unit according to the random read count. This approach will be described in detail below.

[0076] Please refer to Figure 7 , in step 702, a data integration program is started. The data integration program is also called garbage collection, which is used to select source physical units and move valid data in the source physical units to target physical units, and then erase the source physical units to release these memory spaces. In some embodiments, it can be determined whether the number of physical units in the free area 602 is less than a threshold, and if so, the data integration program is started. However, in other embodiments, the data integration program can also be started according to other mechanisms, and the present invention is not limited thereto.

[0077] In step 703, multiple source physical units are selected from the above-mentioned first physical unit according to the random read count. As described above, the first physical unit stores valid data in a first programming mode (e.g., an SLC programming mode). When reading valid data in the first physical unit, the read latency is low. Here, a first physical unit with a smaller random read count can be selected as a source physical unit. In other words, the random read count of the source physical unit will be smaller than the random read count of the first physical unit that has not been selected. In this way, the randomly read data can be retained in the first physical unit in the first programming mode, and the read latency can be reduced.

[0078] Fig. 9 is a schematic diagram showing the selection of a source physical unit according to an embodiment. Fig. 9 , data from the host system 11 will be written into the physical unit 910, and this physical unit 910 is operated in the first programming mode. When the physical unit 910 is full, the physical unit 910 will be added to a set 920. When the data integration program is to be performed, the source physical unit is selected from the set 920. In this example, the set 920 includes physical units 921~926, and these physical units 921~926 all store data in the first programming mode. Among them, the random read counts of physical units 921, 922, 924, and 925 will be less than the random read counts of physical units 923 and 926. Therefore, in this embodiment, physical units 921, 922, 924, and 925 are selected as source physical units.

[0079] In some embodiments, when selecting the source physical unit, not only the random read count will be referred to, but also the size of the valid data (for example, expressed as the number of physical pages). If there is less valid data in the source physical unit, the amount of data that needs to be moved is smaller, so that the physical unit can be released quickly. Therefore, for each first physical unit, the priority can be set according to the corresponding random read count and the size of the valid data, and the physical unit with a higher priority will be selected as the source physical unit first (or with a higher probability). On the other hand, the priority and the random read count are negatively correlated, and the priority and the size of the valid data are negatively correlated. In other words, when performing the data integration program, physical units with lower random read counts and less valid data are preferentially selected as source physical units.

[0080] In some embodiments, the priority can be set by designing a process or calculating an indicator, but the present invention is not limited thereto. For example, the physical unit with a lower random read count can be selected first, and then the physical unit with less valid data can be selected therefrom. Alternatively, the physical unit with less valid data can be selected first, and then the physical unit with a lower random read count can be selected therefrom. Alternatively, the random read count and the valid data size can be substituted into a function to calculate the priority, and this function can be a linear function, a polynomial function, an exponential function, etc.

[0081] In step 704, a target physical unit is obtained, and a programming mode of the target physical unit is determined according to the random read count of the source physical unit. The programming mode of the target physical unit is the second programming mode described above. In other words, a storage unit in the source physical unit is used to store P bits, and a storage unit in the target physical unit is used to store Q bits, where P and Q are positive integers, and Q is greater than P.

[0082] In some embodiments, the second programming mode can be further divided into multiple sub-programming modes, such as MLC, TLC, QLC, etc. In this embodiment, assuming there is a first sub-programming mode and a second sub-programming mode, in the first sub-programming mode a memory cell can store Q 1 bits, and in the second subprogramming mode a memory cell can store Q 2 bits, where Q 1 , Q 2 is a positive integer greater than 1, and Q 1 Less than Q 2 For example, Q 1 =3 and Q 2 =4, in this example, the first sub-programming mode is also called TLC programming mode, and the second sub-programming mode is also called QLC programming mode. 1 =2 and Q 2 =3, in such an example the first sub-programming mode is also called the MLC programming mode, and the second sub-programming mode is also called the TLC programming mode.

[0083] In order to reduce the read latency, the randomly read data may be moved to the target physical unit of the MLC or TLC programming mode, and the other data may be moved to the target physical unit of the QLC programming mode. Fig.10 is a schematic diagram showing a programming mode for determining a target physical unit according to an embodiment. Fig.10, set 920 includes physical units 1001-1007, wherein the random read counts of physical units 1001, 1002, 1005, 1006 are low, while the random read counts of physical units 1003, 1004, 1007 are high. In some embodiments, when the random read count of the source physical unit is greater than or equal to a threshold, the programming mode of the target physical unit is set to the first sub-programming mode; when the random read count of the source physical unit is less than a threshold, the programming mode of the target physical unit is set to the second sub-programming mode. For example, after starting the data integration program, physical units 1001, 1002, 1005, 1006 can be selected as source physical units, and the programming mode of the target physical unit is set to the second sub-programming mode. If the physical units in the free area 602 are still insufficient and the data integration process needs to be continued, the physical units 1003, 1004, and 1007 can be selected as source physical units. Since the random read counts of these source physical units are higher, the programming mode of the target physical unit 1020 can be set to the first sub-programming mode. In other words, the number of bits stored in each storage unit in the target physical unit 1020 will be less than the number of bits stored in each storage unit in the target physical unit 1010. Since the storage capacity of the target physical unit 1010 is larger and the target physical unit 1020 has a lower read latency, this approach is to balance the trade-off between space and read latency.

[0084] Please go back Figure 7 In step 705, the valid data in the source physical unit is moved to the target physical unit. Fig. 9 In the above, data without random read (or with low random read degree) is moved to the target physical unit 930. Fig.10 The data with a lower random read degree is moved to the target physical unit 1010, and the data with a higher random read degree is moved to the target physical unit 1020. The above methods are to make the random read data stored in the physical unit with lower read latency as much as possible.

[0085] Figure 7 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 7 The method can be used in conjunction with the above embodiment or can be used alone. In other words, Figure 7 Other steps may also be added between the steps. In some embodiments, the source physical unit may be selected based on the random read count only, but the programming mode of the target physical unit is not set based on the random read count. In some embodiments, on the contrary, the programming mode of the target physical unit may be set based on the random read count, but the source physical unit is not selected based on the random read count.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the memory management method includes: recording a random read count of each of a plurality of first physical cells in the plurality of physical cells, wherein each of the plurality of first physical cells stores valid data; Initiate data integration process; selecting a plurality of source physical units from the plurality of first physical units according to the plurality of random read counts; The valid data in the multiple source physical units are moved to the target physical unit in the multiple physical units, wherein the storage unit in each of the multiple source physical units is used to store P bits, and the storage unit in the target physical unit is used to store Q bits, P and Q are positive integers, and Q is greater than P.

2. The memory management method according to claim 1, characterized in that: The multiple random read counts of the multiple source physical units are smaller than the random read counts of the physical units that are not selected in the multiple first physical units.

3. The memory management method according to claim 1, characterized in that: The step of selecting the plurality of source physical units from the plurality of first physical units according to the plurality of random read counts comprises: For each of the plurality of first physical units, setting a priority according to the corresponding random read count and the size of the valid data, wherein the priority and the random read count are negatively correlated, and the priority and the size of the valid data are negatively correlated; and The plurality of source physical units are selected from the plurality of first physical units according to the priority.

4. The memory management method according to claim 1, characterized in that: Also includes: determining a programming mode of the target physical unit according to the plurality of random read counts of the plurality of source physical units, wherein the programming mode is a first sub-programming mode or a second sub-programming mode, wherein in the first sub-programming mode, the storage unit in the target physical unit is used to store Q1 bits, In the second sub-programming mode, the storage unit in the target physical unit is used to store Q2 bits, where Q1 and Q2 are positive integers and Q1 is smaller than Q2.

5. The memory management method according to claim 4, characterized in that: The step of determining the programming mode of the target physical unit according to the random read counts of the source physical units comprises: If the plurality of random read counts of the plurality of source physical units are less than a threshold, setting the programming mode of the target physical unit to the second sub-programming mode; If the random read counts of the source physical units are greater than or equal to the threshold, the programming mode of the target physical unit is set to the first sub-programming mode.

6. The memory management method according to claim 1, characterized in that: The step of recording the random read count of each of the plurality of first physical units in the plurality of physical units comprises: receiving a plurality of read commands from a host system; and When two consecutive read instructions among the plurality of read instructions read different first physical units, the random read count of the first physical unit read by the latter of the two read instructions is updated.

7. The memory management method according to claim 6, characterized in that: The step of recording the random read count of each of the plurality of first physical units in the plurality of physical units comprises: For each of the plurality of first physical units, a ratio of the corresponding random read count divided by the total random read count is calculated as the random read count.

8. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; as well as a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, The memory control circuit unit is used to perform multiple steps: recording a random read count of each of a plurality of first physical cells in the plurality of physical cells, wherein each of the plurality of first physical cells stores valid data; Initiate data integration process; selecting a plurality of source physical units from the plurality of first physical units according to the plurality of random read counts; The valid data in the multiple source physical units are moved to a target physical unit in the multiple physical units, wherein a storage unit in each of the multiple source physical units is used to store P bits, and a storage unit in the target physical unit is used to store Q bits, P and Q are positive integers, and Q is greater than P.

9. The memory storage device according to claim 8, characterized in that: The multiple random read counts of the multiple source physical units are smaller than the random read counts of the physical units that are not selected in the multiple first physical units.

10. The memory storage device according to claim 8, characterized in that The step of selecting the plurality of source physical units from the plurality of first physical units according to the plurality of random read counts comprises: For each of the plurality of first physical units, setting a priority according to the corresponding random read count and the size of the valid data, wherein the priority and the random read count are negatively correlated, and the priority and the size of the valid data are negatively correlated; and The plurality of source physical units are selected from the plurality of first physical units according to the priorities.

11. The memory storage device according to claim 8, characterized in that The multiple steps also include: determining a programming mode of the target physical unit according to the plurality of random read counts of the plurality of source physical units, wherein the programming mode is a first sub-programming mode or a second sub-programming mode, wherein in the first sub-programming mode, the storage unit in the target physical unit is used to store Q1 bits, In the second sub-programming mode, the storage unit in the target physical unit is used to store Q2 bits, where Q1 and Q2 are positive integers and Q1 is smaller than Q2.

12. The memory storage device according to claim 11, characterized in that The step of determining the programming mode of the target physical unit according to the random read counts of the source physical units comprises: If the plurality of random read counts of the plurality of source physical units are less than a threshold, setting the programming mode of the target physical unit to the second sub-programming mode; If the random read counts of the source physical units are greater than or equal to the threshold, the programming mode of the target physical unit is set to the first sub-programming mode.

13. The memory storage device according to claim 8, characterized in that The step of recording the random read count of each of the plurality of first physical units in the plurality of physical units comprises: receiving a plurality of read commands from the host system; and When two consecutive read instructions among the plurality of read instructions read different first physical units, the random read count of the first physical unit read by the latter of the two read instructions is updated.

14. The memory storage device according to claim 13, characterized in that: The step of recording the random read count of each of the plurality of first physical units in the plurality of physical units comprises: For each of the plurality of first physical units, a ratio of the corresponding random read count divided by the total random read count is calculated as the random read count.

15. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, characterized in that: The memory control circuit unit comprises: A host interface for coupling to a host system; A memory interface for coupling to the rewritable non-volatile memory module; A memory management circuit is coupled to the host interface and the memory interface, The memory management circuit is used to perform multiple steps: recording a random read count of each of a plurality of first physical cells in the plurality of physical cells, wherein each of the plurality of first physical cells stores valid data; Initiate data integration process; selecting a plurality of source physical units from the plurality of first physical units according to the plurality of random read counts; The valid data in the multiple source physical units are moved to the target physical unit in the multiple physical units, wherein the storage unit in each of the multiple source physical units is used to store P bits, and the storage unit in the target physical unit is used to store Q bits, P and Q are positive integers, and Q is greater than P.

16. The memory control circuit unit according to claim 15, characterized in that: The multiple random read counts of the multiple source physical units are smaller than the random read counts of the physical units that are not selected in the multiple first physical units.

17. The memory control circuit unit according to claim 15, characterized in that: The step of selecting the plurality of source physical units from the plurality of first physical units according to the plurality of random read counts comprises: For each of the plurality of first physical units, setting a priority according to the corresponding random read count and the size of the valid data, wherein the priority and the random read count are negatively correlated, and the priority and the size of the valid data are negatively correlated; and The plurality of source physical units are selected from the plurality of first physical units according to the priorities.

18. The memory control circuit unit according to claim 15, characterized in that: The multiple steps also include: determining a programming mode of the target physical unit according to the plurality of random read counts of the plurality of source physical units, wherein the programming mode is a first sub-programming mode or a second sub-programming mode, wherein in the first sub-programming mode, the storage unit in the target physical unit is used to store Q1 bits, In the second sub-programming mode, the storage unit in the target physical unit is used to store Q2 bits, where Q1 and Q2 are positive integers and Q1 is smaller than Q2.

19. The memory control circuit unit according to claim 18, characterized in that: The step of determining the programming mode of the target physical unit according to the random read counts of the source physical units comprises: If the plurality of random read counts of the plurality of source physical units are less than a threshold, setting the programming mode of the target physical unit to the second sub-programming mode; If the random read counts of the source physical units are greater than or equal to the threshold, the programming mode of the target physical unit is set to the first sub-programming mode.

20. The memory control circuit unit according to claim 15, characterized in that: The step of recording the random read count of each of the plurality of first physical units in the plurality of physical units comprises: receiving a plurality of read commands from the host system; and When two consecutive read instructions among the plurality of read instructions read different first physical units, the random read count of the first physical unit read by the latter of the two read instructions is updated.

21. The memory control circuit unit according to claim 20, characterized in that: The step of recording the random read count of each of the plurality of first physical units in the plurality of physical units comprises: For each of the plurality of first physical units, a ratio of the corresponding random read count divided by the total random read count is calculated as the random read count.

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