A floating-point to integer transmission and conversion fused instruction set processor

Abstract

The application relates to a floating-point number to integer transmission and conversion fusion instruction set processor, which comprises an instruction emission control component for sending instruction control information; a memory execution component for generating target register write port control information, generating instruction execution completion information and delivering the information to an instruction submission component; a floating-point execution component for reading floating-point source operands from a floating-point register file, performing floating-point number exception checking and data mapping, and submitting generated exception code information to the instruction submission component; and an integer execution component for converting the floating-point source operands into integers and writing the converted integer results into an integer register file. The application can improve the processing efficiency of the processor for floating-point number to integer transmission and conversion.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processor design, and in particular to a floating-point-to-integer transmission and conversion fusion instruction set processor. BACKGROUND

[0002] In a processor, integers are usually stored in memory or integer registers, and floating-point numbers are usually stored in memory or floating-point registers. In the implementation of a modern processor microstructure, independent integer register files and floating-point register files are usually provided, and integer operations are mainly performed on integer registers, and floating-point operations are mainly performed on floating-point registers. In order to save the number of read-write ports of the register file, a direct read-write transmission path is usually not provided between the integer register file and the floating-point register file, but other data paths are used instead. If an integer operation instruction needs to use a floating-point number in a floating-point register, usually multiple instructions are needed to achieve the transmission and conversion of the floating-point number to an integer. Usually, a floating-point-to-integer exponent conversion instruction is used to convert the floating-point number in the floating-point register to an integer, and then a floating-point-to-integer transmission instruction is used to transmit the integer in the floating-point register to the integer register. In such a transmission and conversion method, at least two instructions are needed to achieve the transmission and conversion of the floating-point number to the integer. This not only wastes the instruction processing resources of the instruction unit of the processor and reduces the instruction processing efficiency, but also requires reading the register twice and writing the register twice, which greatly increases the execution delay of data transmission and conversion, and is not conducive to improving the operation performance of the processor. In order to improve the performance of the processor, a method for speeding up the transmission and conversion of the floating-point number to the integer is needed. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a floating-point-to-integer transmission and conversion fusion instruction set processor, which can improve the processing efficiency of the processor for the transmission and conversion of the floating-point number to the integer.

[0004] The technical solution adopted by the present application to solve the technical problem is: providing a floating-point-to-integer transmission and conversion fusion instruction set processor, comprising:

[0005] An instruction emission control component is configured to send instruction control information of a floating-point-to-integer transmission and conversion instruction to a corresponding execution component;

[0006] A memory execution component is configured to generate target register write port control information according to the instruction control information, generate instruction execution completion information, and deliver the instruction execution completion information to an instruction submission component;

[0007] a floating point execution component configured to decode the instruction control information to obtain first instruction execution control information, read floating point source operands from a floating point register file according to the first instruction execution control information, perform floating point number exception check and data mapping on the floating point source operands to obtain an equivalent double precision floating point number, and submit generated exception encoding information to the instruction submission component;

[0008] an integer execution component configured to decode the first instruction execution control information to obtain second instruction execution control information, convert the equivalent double precision floating point number into an integer according to the second instruction execution control information, and write the converted integer result into an integer register file according to the write port control information.

[0009] Further, the floating point execution component comprises:

[0010] a first decoder configured to decode the instruction control information to obtain the first instruction execution control information;

[0011] a floating point register reading control module configured to generate read port control information of the floating point register file according to the first instruction execution control information, and read the floating point source operands from the floating point register file according to the read port control information;

[0012] a floating point data mapping module configured to map single precision floating point numbers and half precision floating point numbers into an intermediate data format with a data bit width equal to that of the double precision floating point number to obtain the equivalent double precision floating point number;

[0013] a floating point control status register configured to set a floating point exception trap control bit, a rounding mode control bit, a DNOE control bit, and a floating point exception status bit according to an exception state in a floating point number to integer conversion process;

[0014] an exception handling module configured to perform floating point number exception check on the floating point source operands according to the first instruction execution control information and the DNOE control bit, and generate corresponding exception encoding information to submit to the instruction submission component.

[0015] Further, the rounding mode control bit is configured to set a rounding mode of a result of the floating point number to integer conversion, the floating point exception trap control bit is configured to set a processing strategy when an exception occurs in the floating point number to integer conversion process, and the floating point exception status bit is configured to record an exception state occurring in the floating point number to integer conversion process.

[0016] Further, the integer execution component comprises:

[0017] a second decoder configured to decode the first instruction execution control information to obtain second instruction execution control information, the second instruction execution control information comprising instruction type, converted integer format, rounding mode code, overflow occurrence of conversion result, and special operand result processing control information;

[0018] a floating-point-to-integer transmission conversion sub-component configured to convert the equivalent double-precision floating-point number into an integer according to the second instruction execution control information to obtain the integer result;

[0019] an integer register write control module configured to write the integer result into an integer register file according to the target register write port control information.

[0020] Further, the floating-point-to-integer transmission conversion sub-component comprises:

[0021] a left shift shifter configured to perform a left shift operation on a mantissa of the equivalent double-precision floating-point number when an exponent of the equivalent double-precision floating-point number is greater than or equal to a set value;

[0022] a right shift shifter configured to perform a right shift operation on the mantissa of the equivalent double-precision floating-point number when the exponent of the equivalent double-precision floating-point number is less than the set value;

[0023] a selector configured to select data generated by the left shift shifter when the exponent of the equivalent double-precision floating-point number is greater than or equal to the set value, or select data generated by the right shift shifter otherwise;

[0024] a rounding module configured to perform a rounding operation on the data selected by the selector according to the converted integer format and the rounding mode to obtain a rounded result;

[0025] a completer configured to perform a complement operation on the data output by the rounding module, i.e., perform a bitwise inversion and then add 1, when the equivalent double-precision floating-point number is negative and the corresponding integer result is a signed integer, and output the complemented data;

[0026] an exception result generation module configured to generate a corresponding exception result according to the overflow occurrence of conversion result and the special operand result processing control information in the second instruction execution control information;

[0027] a result selection module configured to select the rounded result, the output of the completer, or the exception result as the integer result according to the second instruction execution control information.

[0028] Further, the exception result comprises:

[0029] when the equivalent double-precision floating-point number is not a number, the exception result is 0;

[0030] When the equivalent double-precision floating-point number is positive infinity, the abnormal result is the maximum representable value of the integer format after transmission conversion;

[0031] When the equivalent double-precision floating-point number is negative infinity, the abnormal result is the minimum representable value of the integer format after transmission conversion;

[0032] When the equivalent double-precision floating-point number is a Denormal number, if converted into a signed integer and an unsigned integer, the positive Denormal number is rounded to positive infinity to obtain the abnormal result as positive 1, if converted into a signed integer, the negative Denormal number is rounded to negative infinity to obtain the abnormal result as negative 1, otherwise, the abnormal result is 0;

[0033] When integer overflow occurs, the abnormal result is the boundary value of the integer format after transmission conversion.

[0034] Further, the boundary value of the integer format after transmission conversion includes:

[0035] If positive overflow occurs, the abnormal result is the maximum positive integer that can be represented by the integer format after transmission conversion;

[0036] If negative underflow occurs and the integer after transmission conversion is an unsigned integer, the abnormal result is 0;

[0037] Otherwise, the abnormal result is the minimum negative integer that can be represented by the integer format after transmission conversion.

[0038] Further, the floating-point register file includes a plurality of floating-point registers, each of which stores a double-precision floating-point number or two single-precision floating-point numbers or four half-precision floating-point numbers, and each of the double-precision floating-point number, the single-precision floating-point number and the half-precision floating-point number as a floating-point source operand can be used individually, and the half-precision floating-point number includes FP16 half-precision floating-point number and BF16 half-precision floating-point number.

[0039] Further, the instruction control information of the floating-point number to integer transmission conversion instruction is sent by a floating-point number storage instruction data transmission port FSTD.

[0040] Further, the floating-point-to-integer transmission conversion instruction reuses the same floating-point storage instruction data transmission port FSTD of the instruction transmission component, the same load instruction report completion port of the instruction submission component, and the same read port, data line, and address line of the floating-point register file of the floating-point storage instruction; the floating-point-to-integer transmission conversion instruction reuses the data path from the floating-point execution component to the integer execution component of the floating-point-to-integer transmission instruction; and the floating-point-to-integer transmission conversion instruction reuses the same write port, data line, and address line of the integer register file of the floating-point-to-integer transmission instruction and the integer load instruction.

[0041] Beneficial effects

[0042] Compared with the prior art, the present application has the following advantages and positive effects:

[0043] (1) The present application integrates the functions of the original floating-point-to-integer transmission instruction and the floating-point-to-integer conversion instruction, without adding new data paths, floating-point register read ports, and integer register write ports. The floating-point-to-integer transmission conversion can be realized by one instruction, the function of a single instruction is expanded, the execution speed of floating-point-to-integer transmission and conversion in the processor is accelerated, and thus the performance of the processor is improved.

[0044] (2) The floating-point-to-integer transmission conversion instruction saves the processor instruction processing resources, increases the instruction processing efficiency, and does not require twice reading and writing and twice register, so that the execution delay of the transmission conversion operation is less than the sum of the execution delays of the original transmission instruction and the conversion instruction, which is beneficial to accelerating the execution speed and thus improving the operation performance of the processor.

[0045] (3) The present application not only supports the transmission conversion of double-precision floating-point numbers, single-precision floating-point numbers into long-word integers and word integers, but also supports the transmission conversion of half-precision floating-point numbers into word integers and half-word integers, and reuses the same conversion circuit for conversion of different data formats, which not only saves hardware costs, but also is beneficial to improving the applicability of the processor in emerging fields such as artificial intelligence. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 is a structural schematic diagram of an embodiment of the present application;

[0047] Figure 2 is a structural schematic diagram of a floating-point-to-integer transmission conversion sub-component of an embodiment of the present application. DETAILED DESCRIPTION

[0048] The application will be further described in connection with the following embodiments. It should be understood that these embodiments are only used for illustrating the application and not for limiting the scope of the application. Furthermore, it should be understood that after reading the content of the application, those skilled in the art can make various modifications or changes to the application, and these equivalent forms also fall within the scope defined by the appended claims.

[0049] Embodiments of the application relate to a floating-point-to-integer conversion and transmission fused instruction set processor, as shown in the accompanying drawings, comprising: Figure 1

[0050] A fetch unit (101) comprising an internal level-1 instruction cache and its access control, for fetching instructions from the instruction cache or a lower level cache or even the main memory, and decoding the fetched instructions;

[0051] An instruction issue control unit (102) comprising register renaming and issue control, for implementing the mapping of all instruction logical registers to physical registers, dependency detection and issue control, and for different instruction types, a plurality of issue ports are provided, corresponding to different execution units;

[0052] A floating-point store instruction data issue queue (103) for controlling and issuing floating-point store (Store) instruction data and the floating-point-to-integer conversion instruction; the Store instruction address and data issue are separated, the Store instruction address is issued and executed by the memory instruction address calculation issue queue, and the Store instruction data is issued and executed by a dedicated data issue queue;

[0053] A floating-point register file (104) for storing floating-point source operands and operation results, a plurality of read ports are provided for providing source operands for floating-point operations, and a plurality of write ports are provided for writing back register results of floating-point operations or floating-point load (Load) instructions; this unit contains 32 floating-point registers, each floating-point register has a data width of 64 bits, can store one double-precision floating-point number or 2 single-precision floating-point numbers or 4 half-precision floating-point numbers, and instructions can also use only 1 single-precision floating-point number (low 32 bits) or 1 half-precision floating-point number (low 16 bits) at a time;

[0054] A floating-point execution unit (105) for receiving instruction execution requests, reading source operands from the floating-point register file (104) or receiving data input from other units, performing corresponding operations according to instructions, obtaining execution results and writing them back to the floating-point register file (104) or outputting them to other units, and passing instruction execution completion information to the instruction commit unit (117), which is often referred to as a Reorder Buffer (ROB); ​

[0055] a first decoder (106) configured to decode the received floating-point instruction further to generate control information required for floating-point instruction execution;

[0056] a read floating-point register control module (107) configured to generate read port control information of the floating-point register file (104) according to the instruction execution control information, including read enable and read register number, bypass selection control signal and the like;

[0057] a floating-point data mapping module (108) configured to map a single-precision floating-point number or a half-precision floating-point number into an intermediate data format with a data bit width of 64 bits to generate equivalent double-precision floating-point format data; the specific implementation method is to map the single-precision floating-point number, the BF16 half-precision floating-point number and the FP16 half-precision floating-point number into a double-precision floating-point number specified in the IEEE 754 standard, and the sign bit remains unchanged in the mapping process; mainly, the 8-bit exponent of the single-precision floating-point number or the BF16 half-precision floating-point number or the 5-bit exponent of the FP16 half-precision floating-point number is mapped into an 11-bit exponent of the double-precision floating-point number, and the number of bits of the insufficient mantissa is directly filled with zero to expand to 52 bits;

[0058] The exponent mapping relationship of the BF16 half-precision floating-point number and the single-precision floating-point number mapped into the double-precision floating-point number is shown in Table 1:

[0059] Table 1 Exponent mapping relationship of the BF16 half-precision floating-point number and the single-precision floating-point number and the double-precision floating-point number

[0060] BF16 half-precision floating-point number Single-precision floating-point number Double-precision floating-point number Data [14:7] bits Data [30:23] bits Data [62:52] bits 11111111 11111111 11111111111 1000xxxx (xxxx not all "1") 1000xxxx (xxxx not all "1") 1000000xxxx (xxxx not all "1") 0111xxxx (xxxx not all "0") 0111xxxx (xxxx not all "0") 0111111xxxx (xxxx not all "0") 00000000 00000000 00000000000

[0061] The exponent mapping relationship of the FP16 half-precision floating-point number mapped into the double-precision floating-point number is shown in Table 2:

[0062] Table 2 Exponent mapping relationship of the FP16 half-precision floating-point number and the double-precision floating-point number (the numbers in the table are in binary)

[0063] FP16 half-precision floating-point number Double-precision floating-point number Data [14:10] bits Data [62:52] bits 11111 11111111111 1xxxx 1000000xxxx (xxxx not all "1") 0xxxx 0111111xxxx (xxxx not all "0") 00000 00000000000

[0064] Floating-point control status register (109) contains the information of the status bits of floating-point exception, the bits of rounding mode, the bits of floating-point exception trap control, the bits of whether the hardware supports Denormal number control DNOE and the bits of half-precision floating-point data, etc., also known as FPCR (Floating-Point Control Register); when floating-point number to integer conversion, the result needs to be rounded according to the floating-point rounding mode bits; if floating-point number to integer conversion occurs an exception, the exception code information needs to be generated, the exception status bits of FPCR are registered, and whether to generate an arithmetic trap is decided according to the floating-point exception trap control bits to enter the software processing; the exception processing module (110) is used for performing exception check on the floating-point number to be converted and transmitted according to the instruction execution control information and the exception trap control bits of the floating-point control status register, analyzing the integer overflow exception and the non-precise result exception possibly occurring after conversion, generating the corresponding exception code and submitting to the instruction submission component (117); the specific checking method of performing exception check on the floating-point data to be converted and transmitted is that: when the floating-point number to be converted and transmitted is non-number, positive infinity or negative infinity, the invalid operation exception occurs; when the floating-point number to be converted and transmitted is Denormal number, the Denormal exception and the non-precise result exception occur; if the real value of the floating-point number to be converted and transmitted is not equal to the integer after conversion, the floating-point number to integer conversion instruction will occur the non-precise result exception; if the conversion result exceeds the representation range of the integer after conversion, the floating-point number to integer conversion instruction will occur the integer overflow exception;

[0065] The memory execution component (111) is used for processing the memory instruction from the instruction emission control component (102), completing the memory address calculation, accessing the internal first-level data Cache, judging whether the data Cache is hit, further generating the request of accessing the next-level Cache or the main memory when not hit, and submitting the instruction execution completion information to the instruction submission component (117); for the floating-point to integer transmission instruction, the transmission and conversion fusion instruction, the address calculation or the data Cache access is not needed, only the report completion interface of the memory instruction execution and the write port of the Load instruction writing the integer register file are borrowed to complete the instruction submission and the register file backwriting;

[0066] The integer execution component (112) is used for executing the integer operation instruction, reading the source operand from the integer register file (116) or selecting the bypass result data of other operation sub-components, performing the corresponding operation according to the instruction execution, obtaining the execution result and writing back to the integer register file (116) or bypassing to other operation sub-components, and submitting the instruction execution completion information to the instruction submission component (117);

[0067] a second decoder (113) configured to decode the first instruction execution control information to obtain second instruction execution control information, the second instruction execution control information including instruction type, converted integer format, rounding mode code, overflow occurrence of conversion result, and special operand result processing control information;

[0068] a floating-point-to-integer transmission conversion sub-component (114) configured to complete data conversion and abnormal result processing of the floating-point-to-integer transmission conversion instruction according to the instruction execution control information generated by the second decoder (113), and generate an execution result of the instruction;

[0069] an integer register write control module (115) configured to select, according to the instruction control information, the execution result of the floating-point-to-integer transmission conversion instruction, the floating-point-to-integer transmission instruction, or the integer load instruction to be written into the integer register file (116);

[0070] an integer register file (116) configured to store integer source operands and operation results, and provided with a plurality of read ports for providing source operands for integer operations, and a plurality of write ports for writing back register results of integer operations or integer load instructions; the component includes 32 integer registers, each integer register having a data bit width of 64 bits, and an unsigned word integer being stored in the lower 32 bits of the integer register with the upper 32 bits being zero-extended; a signed word integer being stored in the lower 32 bits of the integer register with the upper 32 bits being extended according to a sign bit; an unsigned half-word integer being stored in the lower 16 bits of the integer register with the upper 48 bits being zero-extended; and a signed half-word integer being stored in the lower 16 bits of the integer register with the upper 48 bits being extended according to a sign bit;

[0071] an instruction submission component (117) configured to receive instruction completion information submitted by the integer, floating-point, or memory execution component, and complete exit of the instruction according to program order.

[0072] The embodiment supports the floating-point-to-integer transmission and conversion fusion instruction set for implementing transmission and conversion of a floating-point number in a floating-point register into an integer in an integer register. The source register of the instruction set is a floating-point register, the source operand is a floating-point number, the target register is an integer register, and the execution result is an integer.

[0073] Specific instructions are shown in Table 3.

[0074] Table 3: A floating-point-to-integer transmission and conversion fusion instruction set

[0075] Number Instruction mnemonic Instruction description Instruction format 1 CMOVDL Double-precision floating-point number transfer conversion to signed longword integer instruction CMOVDLFa.rd, Rb.wl 2 CMOVDUL Double-precision floating-point number transfer conversion to unsigned longword integer instruction CMOVDULFa.rd, Rb.wl 3 CMOVDW Double-precision floating-point number transfer conversion to signed word integer instruction CMOVDWFa.rd, Rb.ww 4 CMOVDUW Double-precision floating-point number transfer conversion to unsigned word integer instruction CMOVDUWFa.rd, Rb.ww 5 CMOVSL Single-precision floating-point number transfer conversion to signed longword integer instruction CMOVSLFa.rs, Rb.wl 6 CMOVSUL Single-precision floating-point number transfer conversion to unsigned longword integer instruction CMOVSULFa.rs, Rb.wl 7 CMOVSW Single-precision floating-point number transfer conversion to signed word integer instruction CMOVSWFa.rs, Rb.ww 8 CMOVSUW Single-precision floating-point number transfer conversion to unsigned word integer instruction CMOVSUWFa.rs, Rb.ww 9 CMOVHFW Half-precision floating-point number transfer conversion to signed word integer instruction CMOVHFWFa.rh, Rb.ww 10 CMOVHFUW Half-precision floating-point number transfer conversion to unsigned word integer instruction CMOVHFUWFa.rh, Rb.ww 11 CMOVHFH Half-precision floating-point number transfer conversion to signed halfword integer instruction CMOVHFHFa.rh, Rb.wh 12 CMOVHFUH Half-precision floating-point number transfer conversion to unsigned halfword integer instruction CMOVHFUHFa.rh, Rb.wh

[0076] Among them, the signed integer is represented and stored by 2's complement, and the integer includes 64-bit unsigned long word integer, 32-bit unsigned word integer, 16-bit unsigned half word integer, and 64-bit signed long word integer, 32-bit signed word integer and 16-bit signed half word integer represented by 2's complement, the floating point number includes 64-bit double precision floating point number, 32-bit single precision floating point number, 16-bit FP16 half precision floating point number and 16-bit BF16 half precision floating point number, the FP16 half precision floating point number includes 1-bit sign bit (S), 5-bit exponent (E) and 10-bit mantissa (F), and the BF16 half precision floating point number includes 1-bit sign bit (S), 8-bit exponent (E) and 7-bit mantissa (F).

[0077] The instruction set supports four rounding modes of nearest rounding, rounding to zero, rounding to positive infinity and rounding to negative infinity defined by IEEE-754 floating point standard, wherein the rounding mode can be directly determined by the instruction code or dynamically controlled by the rounding mode bit of the FPCR.

[0078] The floating point number to integer transmission conversion instruction is executed by the following components:

[0079] The floating point number to integer transmission conversion instruction is transmitted by the floating point storage instruction data transmission port FSTD of the floating point storage instruction data transmission queue (103) in the instruction transmission control component (102), and the instruction control information is simultaneously transmitted to the memory access execution component (111) and the floating point execution component (105);

[0080] The memory access execution component (111) generates execution completion information of the floating point number to integer transmission conversion instruction according to the instruction control information, and transmits the execution completion information to the instruction submission component (117); and generates integer target register write port control information and transmits the integer target register write port control information to the integer register write control module (115);

[0081] The floating point execution component (105) reads the source operand in the floating point register file (104) according to the instruction control information, performs exception processing and data mapping according to the instruction execution control information and the state of the floating point control state register, and transmits the mapped equivalent double precision floating point number and the instruction execution control information to the integer execution component (112), and transmits the exception code to the instruction submission component (117);

[0082] The floating point number to integer transmission conversion sub-component (114) in the integer execution component (112) completes the conversion of the floating point number to the integer and the exception result processing under the control of the instruction execution control information, and generates the transmission converted integer result; and the integer register write control module (115) selects the execution result of the floating point number to integer transmission conversion instruction, the floating point number to integer transmission instruction or the integer load instruction to write into the integer register file (116) according to the instruction control information.

[0083] The floating-point-to-integer transmission conversion instruction and the floating-point-to-integer transmission instruction, and the floating-point storage instruction multiplex the same instruction transmission port FSTD of the instruction transmission part (102) of the floating-point storage instruction submission part (117), and multiplex the same read port and data line and address line of the floating-point register file (104) of the floating-point-to-integer transmission conversion instruction and the floating-point-to-integer transmission instruction; the floating-point-to-integer transmission conversion instruction and the floating-point-to-integer transmission instruction multiplex the data transmission line from the floating-point execution part (105) to the integer execution part (112) of the floating-point-to-integer transmission conversion instruction and the floating-point-to-integer transmission instruction; the floating-point-to-integer transmission conversion instruction and the floating-point-to-integer transmission instruction, and the integer load instruction multiplex the same write port and data line and address line of the integer register file (116).

[0084] Because the representation ranges of the single-precision floating-point number and the half-precision floating-point number are both subsets of the double-precision floating-point number, the single-precision floating-point number and the half-precision floating-point number can be mapped to equivalent double-precision floating-point numbers, and then the double-precision floating-point number transmission conversion into an integer circuit is multiplexed, so the floating-point-to-integer transmission conversion instruction can multiplex the same set of conversion circuits, as shown in the following table: Figure 2 As shown in the table, the floating-point-to-integer transmission conversion subpart (114) comprises:

[0085] A left shift shifter (201) performs a left shift operation on the mantissa of the equivalent double-precision floating-point number by at most 64 bits when the exponent of the equivalent double-precision floating-point number is greater than or equal to 0x3FF (hexadecimal number);

[0086] A right shift shifter (202) performs a right shift operation on the mantissa of the equivalent double-precision floating-point number by 1 or 2 bits when the exponent of the equivalent double-precision floating-point number is 0x3FE (hexadecimal number) or less than 0x3FE;

[0087] A selector (203) selects the data generated by the left shift shifter (201) when the exponent of the equivalent double-precision floating-point number is greater than or equal to 0x3FF (hexadecimal number), and otherwise selects the data generated by the right shift shifter (202);

[0088] A rounding module (204) performs a rounding operation on the data generated by the selector (203) according to the data format type and the rounding mode code generated by the second decoder (113);

[0089] A completer (205) performs a complement operation of bit-by-bit inversion and addition of 1 on the data output by the rounding module (204) if the floating-point number to be converted is negative and the converted integer is a signed integer, and the data bit width of the completer (205) is 64 bits;

[0090] The abnormal result generating module (206) is configured to generate corresponding abnormal results according to whether overflow of the conversion result and special operand result processing control information in the second instruction execution control information. The specific method of generating the abnormal result is as follows: when the floating point number to be transmitted and converted is non-number, the transmission conversion result is 0; when the floating point number to be transmitted and converted is positive infinity, the transmission conversion result is the maximum representable value of the integer format after transmission conversion; when the floating point number to be transmitted and converted is negative infinity, the transmission conversion result is the minimum representable value of the integer format after transmission conversion; when the floating point number to be transmitted and converted is Denormal number, the transmission conversion result is jointly controlled by the floating point number sign, the rounding mode, the hardware whether to support the Denormal number control bit DNOE and the integer format type after transmission conversion. If the conversion is signed integer and unsigned integer, the positive Denormal number is rounded to positive infinity, and the result is positive 1; if the conversion is signed integer, the negative Denormal number is rounded to negative infinity, and the result is negative 1; and the result of the remaining cases is 0; when integer overflow occurs, the transmission conversion result is the boundary value of the integer format after transmission conversion, that is, when positive overflow occurs, the transmission conversion result is the maximum positive integer that can be represented by the integer format after transmission conversion; when negative underflow occurs, if the integer after transmission conversion is unsigned integer, the transmission conversion result is 0, otherwise, the transmission conversion result is the minimum negative integer that can be represented by the integer format after transmission conversion; the specific value of the transmission conversion result after integer overflow is shown in Table 4:

[0091] Table 4: Transmission conversion instruction result of floating point number to integer overflow (the numbers in the table are in hexadecimal)

[0092]

[0093] The result selection module (308) selects the abnormal result generated by the abnormal result generating module (206) if the floating point number has source operand abnormality or the result of the rounding module (204) has integer overflow; otherwise, if the floating point number to be transmitted and converted is negative and the integer after conversion is signed integer, the integer result generated by the complementer (205) is selected, otherwise, the result generated by the rounding module (204) is selected as the execution result of the floating point number to integer transmission conversion instruction.

[0094] With reference to the embodiment, the application can be used in various processors, which can be general-purpose CPU, GPU or special-purpose processor.

Claims

1. A floating-point-to-integer transmission and conversion fused instruction set processor, characterized by, include: The instruction issuance control unit is used to send instruction control information for floating-point to integer conversion instructions to the corresponding execution unit; The memory access execution unit is used to generate target register write port control information based on the instruction control information, generate instruction execution completion information and pass it to the instruction submission unit; The floating-point execution unit is used to decode the instruction control information to obtain first instruction execution control information, and read floating-point source operands from the floating-point register file according to the first instruction execution control information, and then perform floating-point number anomaly checks and data mapping on the floating-point source operands to obtain equivalent double-precision floating-point numbers, and submit the generated anomaly encoding information to the instruction submission unit. An integer execution unit is used to decode the first instruction execution control information to obtain the second instruction execution control information, and then convert the equivalent double-precision floating-point number into an integer according to the second instruction execution control information, and write the converted integer result into an integer register file according to the write port control information; The floating-point to integer transfer conversion instruction and the floating-point to integer transfer instruction and floating-point storage instruction share the same floating-point storage instruction data transmission port (FSTD) of the instruction issuance control unit, the same load instruction completion port of the instruction submission unit, and the same read port, data lines, and address lines of the floating-point register file; The floating-point to integer conversion instruction and the floating-point to integer transmission instruction multiplex the data path from the floating-point execution unit to the integer execution unit; The floating-point to integer transfer instruction, the floating-point to integer transfer instruction, and the integer load instruction share the same write port, data lines, and address lines of the integer register file.

2. The processor of claim 1, wherein, The floating-point execution unit includes: A first decoder is used to decode the instruction control information to obtain the first instruction execution control information; The floating-point register read control module is used to generate read port control information of the floating-point register file according to the first instruction execution control information, and read the floating-point source operand from the floating-point register file according to the read port control information; A floating-point data mapping module is used to map single-precision floating-point numbers and half-precision floating-point numbers into an intermediate data format with a data bit width equal to that of the double-precision floating-point number, thereby obtaining the equivalent double-precision floating-point number. The floating-point control status register is used to set the floating-point trap control bit, rounding mode control bit, DNOE control bit, and to set the floating-point exception status bit according to the exception status during the conversion from floating-point to integer. The exception handling module is used to perform floating-point number exception checks on the floating-point source operand according to the first instruction execution control information and the DNOE control bit, and generate corresponding exception code information to submit to the instruction submission component.

3. The processor of claim 2, wherein, The rounding mode control bit is used to set the rounding mode of the result of the floating-point to integer conversion, the floating-point exception trap control bit is used to set the handling strategy when an exception occurs during the floating-point to integer conversion, and the floating-point exception status bit is used to record the exception status that occurs during the floating-point to integer conversion.

4. The processor of claim 1, wherein, The integer execution unit includes: a second decoder configured to decode the first instruction execution control information to obtain second instruction execution control information, the second instruction execution control information comprising instruction type, converted integer format, rounding mode encoding, overflow of conversion result, and special operand result handling control information; a floating-point-to-integer conversion subunit configured to convert the equivalent double-precision floating-point number into an integer according to the second instruction execution control information to obtain the integer result; an integer register write control module configured to write the integer result into an integer register file according to the target register write port control information.

5. The processor of claim 4, wherein, The floating-point-to-integer conversion subunit comprises: a left shift shifter configured to perform a left shift operation on a mantissa of the equivalent double-precision floating-point number when an exponent of the equivalent double-precision floating-point number is greater than or equal to a set value; a right shift shifter configured to perform a right shift operation on the mantissa of the equivalent double-precision floating-point number when the exponent of the equivalent double-precision floating-point number is less than the set value; a selector configured to select data generated by the left shift shifter when the exponent of the equivalent double-precision floating-point number is greater than or equal to the set value, or select data generated by the right shift shifter otherwise; a rounding module configured to perform a rounding operation on the data generated by the selector according to the converted integer format and the rounding mode to obtain a rounded result; a completer configured to perform a complement operation on the data output by the rounding module by performing a bitwise inversion and then adding 1 when the equivalent double-precision floating-point number is negative and the corresponding integer result is a signed integer; an exception result generation module configured to generate a corresponding exception result according to the overflow of conversion result and the special operand result handling control information in the second instruction execution control information; a result selection module configured to select the output result of the rounding module, the completer, or the exception result as the integer result according to the second instruction execution control information.

6. The processor of claim 5, wherein, The exception result comprises: when the equivalent double-precision floating-point number is not a number, the exception result is 0; when the equivalent double-precision floating-point number is positive infinity, the exception result is a maximum representable value of the converted integer format; when the equivalent double-precision floating-point number is negative infinity, the exception result is a minimum representable value of the converted integer format; when the equivalent double-precision floating-point number is a denormal number, if converted into a signed integer and an unsigned integer, a positive denormal number is rounded to positive infinity to obtain the exception result as positive 1, if converted into a signed integer, a negative denormal number is rounded to negative infinity to obtain the exception result as negative 1, or otherwise, the exception result is 0; when an integer overflow occurs, the exception result is a boundary value of the converted integer format.

7. The processor of claim 6, wherein, The boundary value of the converted integer format comprises: if positive overflow occurs, the exception result is a maximum positive integer of the converted integer format; if negative underflow occurs and the converted integer is an unsigned integer, the exception result is 0; otherwise, the exception result is a minimum negative integer of the converted integer format.

8. The processor of claim 1, wherein, The floating-point register file includes a plurality of floating-point registers, each of which stores a double-precision floating-point number or two single-precision floating-point numbers or four half-precision floating-point numbers, and each of the double-precision floating-point number, the single-precision floating-point number and the half-precision floating-point number can be used as a floating-point source operand.

9. The processor of claim 1, wherein, The instruction control information of the floating-point number to integer transmission conversion instruction is sent by a floating-point number storage instruction data transmission port FSTD.

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