FPGA-based four-core DSP external flash configuration method

Abstract

The application discloses a four-core DSP external Flash configuration method based on FPGA, which comprises boot loading configuration and normal operation configuration. When there is only one Flash chip outside the four-core DSP, according to the DSP reset and bootstrap process, the FPGA is used to connect the bus of the four cores of the DSP to the bus of the Flash in time sharing mode, so that the boot of the four-core DSP and the access to the Flash data are realized.

Description

Technical Field

[0001] This invention relates to a method for configuring external Flash memory for a quad-core DSP based on FPGA, belonging to the field of quad-core DSP chip application technology. Background Technology

[0002] The FT-Q6713J / 500 is a high-performance 32-bit quad-core floating-point DSP chip with a 500MHz operating frequency, 16 GIPS fixed-point performance, 12 GFLOPS floating-point performance, and over 2MB of on-chip memory. The four DSP cores can communicate via SDP or a crossbar switch. An external Flash chip is used to store the DSP's boot program and other data. For a single-core DSP, simply connecting the DSP's EMIF bus to the Flash bus completes the DSP's power-on boot and access to Flash data. For a quad-core DSP, since each core corresponds to a separate EMIF bus, the four EMIF buses cannot be directly connected to a single Flash. A control flow needs to be designed in the FPGA to connect the four buses to the Flash bus in a time-sharing manner, enabling the four cores to boot sequentially and access Flash. In common quad-core DSP reset and bootstrap methods, Core0 is the master core, loading the programs of the other cores. This boot method is highly dependent on Core0; if Core0 fails, all cores will fail to boot, resulting in poor reliability. Summary of the Invention

[0003] The technical problem solved by the present invention is to overcome the shortcomings of the prior art and provide an FPGA-based method for configuring external Flash for a quad-core DSP. When there is only one Flash chip outside the quad-core DSP, according to the DSP reset and boot process, the FPGA is used to connect the buses of the four cores of the DSP to the Flash bus in a time-division manner, so as to realize the boot of the quad-core DSP and access to Flash data.

[0004] The technical solution of this invention is:

[0005] A method for configuring external Flash memory for a quad-core DSP based on FPGA, comprising:

[0006] Perform bootloader configuration: The bootloader configuration is executed only once after the DSP is powered on, in the following order: DSPCore0 connects to Flash for bootloader, DSP Core1 connects to Flash for bootloader, DSP Core2 connects to Flash for bootloader, and DSP Core3 connects to Flash for bootloader.

[0007] Normal operation configuration: The normal operation configuration is performed after the DSP boot is completed and when accessing Flash data begins. The process is repeated in a loop: DSP Core0 requests to occupy Flash, DSP Core0 relinquishes Flash, DSP Core1 requests to occupy Flash, DSP Core1 relinquishes Flash, DSP Core2 requests to occupy Flash, DSP Core2 relinquishes Flash, DSP Core3 requests to occupy Flash, DSP Core3 relinquishes Flash, DSP Core0 requests to occupy Flash, DSP Core0 relinquishes Flash, and so on.

[0008] Furthermore, the FPGA-based quad-core DSP external Flash configuration method is implemented using a hardware platform composed of FPGA, DSP, and Flash. In this hardware platform,

[0009] The DSP bus includes four sets of address lines, four sets of data lines, four sets of write enable signal lines, four sets of read enable signal lines, four sets of output enable signal lines, and four reset signal lines.

[0010] The Flash bus includes Flash data lines, Flash address lines, Flash chip select signal lines, Flash read enable signal lines, and Flash write enable signal lines;

[0011] Both the DSP bus and the Flash bus are connected to the FPGA's I / O pins. According to the DSP's Flash access process, the FPGA connects the DSP bus to the Flash bus in a time-sharing manner, enabling the four cores of the DSP to access the external Flash in a time-sharing manner.

[0012] Furthermore, the specific steps for configuring the bootloader include:

[0013] S1: After power-on, the FPGA connects the DSP's Core0 to Flash partition 1, the reset signal of Core0 is pulled high, and Core0 starts booting from Flash partition 1; after booting is complete, the DSP issues a command for Core0 to relinquish its Flash memory.

[0014] S2: The FPGA connects the DSP's Core1 to Flash partition 2. The reset signal of Core1 is pulled high, and Core1 starts booting from Flash partition 2. After booting is complete, the DSP issues an instruction for Core1 to relinquish its Flash memory.

[0015] S3: The FPGA connects the DSP's Core2 to Flash partition 3. The reset signal of Core2 is pulled high, and Core2 starts booting from Flash partition 3. After booting is complete, the DSP issues a command for Core2 to relinquish its Flash memory.

[0016] S4: The FPGA connects the DSP's Core3 to Flash partition 4. The reset signal of Core3 is pulled high, and Core3 starts booting from Flash partition 4. After booting is complete, the DSP gives Core3 the instruction to relinquish its Flash memory.

[0017] Furthermore, the steps for performing normal operation configuration are as follows:

[0018] S5: DSP Core0 requests and occupies Flash memory, and Core0 operates on the entire address space of Flash.

[0019] S6: Core0 relinquishes its Flash memory usage;

[0020] S7: Core1 requests to use Flash, and Core1 only operates on Flash partition 2;

[0021] S8: Core1 relinquishes its Flash memory usage;

[0022] S9: Core2 requests Flash memory, but Core2 only operates on Flash partition 3;

[0023] S10: Core2 relinquishes its Flash memory usage;

[0024] S11: Core3 requests Flash memory, but Core3 only operates on Flash partition 4;

[0025] S12: Core3 relinquishes its Flash memory usage;

[0026] S13: The DSP accesses the Flash memory in a loop according to steps S5 to S12.

[0027] Furthermore, the bootloader configuration and normal operation configuration are implemented in the FPGA; a state machine is designed in the FPGA to connect the EMIF bus of DSP Core0 to Core3 to the Flash bus in a time-division multiplexing manner, so as to realize the quad-core DSP's access to the external Flash.

[0028] Secondly, the present invention also proposes a processor for running a program, wherein the program executes the FPGA-based quad-core DSP external Flash configuration method during runtime.

[0029] Thirdly, the present invention also proposes a non-volatile storage medium, comprising: a computer program product, which executes the FPGA-based quad-core DSP external Flash configuration method when the computer program product is executed.

[0030] Fourthly, the present invention also proposes a computer program product that, when executed by a processor, implements the aforementioned FPGA-based quad-core DSP external Flash configuration method.

[0031] The advantages of this invention compared to the prior art are:

[0032] Compared to the DSP where all four cores rely on Core0 for startup, this invention allows each of the four cores to be sequentially connected to Flash and then started independently, reducing the coupling between the cores and improving the system's reliability and flexibility. By using an FPGA to connect the DSP EMIF bus and Flash bus, the logic becomes simple and the FPGA program is highly maintainable. Attached Figure Description

[0033] Figure 1 This is a hardware block diagram of the present invention;

[0034] Figure 2 This invention provides commands for a quad-core DSP to access external Flash memory.

[0035] Figure 3 This invention describes the process of a quad-core DSP accessing external Flash memory. Detailed Implementation

[0036] The specific embodiments of the present invention will now be described in further detail with reference to the accompanying drawings.

[0037] This invention proposes a configuration method for a quad-core DSP to access external Flash memory based on an FPGA, implemented on a hardware platform of FPGA, DSP, and Flash memory, such as... Figure 1 As shown.

[0038] In this hardware platform, the DSP bus includes four sets of address lines, four sets of data lines, four sets of write enable signals, four sets of read enable signals, four sets of output enable signals, and four sets of reset signals. The Flash bus includes Flash data lines, Flash address lines, Flash chip select signals, Flash read enable signals, and Flash write enable signals. All signal lines are connected to the FPGA's I / O pins. According to the DSP's Flash access procedure, the FPGA connects the four EMIF buses (Core0 to Core3) to the Flash bus, enabling the four DSP cores to access the external Flash in a time-sharing manner.

[0039] like Figure 2 and Figure 3 As shown, the configuration method for a quad-core DSP based on FPGA to access external Flash includes boot loading configuration and normal operation configuration.

[0040] The bootloader configuration is executed only once after power-on, and is configured in the following order: DSP Core0 connects to Flash, DSP Core1 connects to Flash, DSP Core2 connects to Flash, and DSP Core3 connects to Flash.

[0041] Normal operation configuration follows a cycle of DSP Core0 requesting Flash memory, DSP Core0 relinquishing Flash memory, DSP Core1 requesting Flash memory, DSP Core1 relinquishing Flash memory, DSP Core2 requesting Flash memory, DSP Core2 relinquishing Flash memory, DSP Core3 requesting Flash memory, DSP Core3 relinquishing Flash memory, DSP Core0 requesting Flash memory, DSP Core0 relinquishing Flash memory, and so on.

[0042] Specifically, such as Figure 2 and Figure 3 As shown, the steps for configuring a quad-core DSP based on FPGA to access external Flash memory are as follows:

[0043] S1: After power-on, the FPGA connects DSP Core0 to Flash partition 1, the reset signal of DSP Core0 is pulled high, and Core0 starts booting from Flash partition 1; after booting, the DSP gives Core0 the instruction to relinquish Flash by writing address 0xB0000C02; if DSP Core0 does not give the instruction to relinquish Flash, the FPGA will wait for 2 seconds and then automatically connect DSP Core1 to Flash.

[0044] S2: The FPGA connects DSP Core1 to Flash partition 2, the reset signal of DSP Core1 is pulled high, and Core1 starts booting from Flash partition 2; after booting, the DSP gives Core1 the instruction to relinquish Flash by writing address 0xB000 0C02; if DSP Core1 does not give the instruction to relinquish Flash, the FPGA waits for 2 seconds and then automatically connects DSP Core2 to Flash.

[0045] S3: The FPGA connects DSP Core2 to Flash partition 3, the reset signal of DSP Core2 is pulled high, and Core2 starts booting from Flash partition 3; after booting, the DSP gives Core2 the instruction to relinquish Flash access by writing address 0xB0000C02; if DSP Core2 does not give the instruction to relinquish Flash access, the FPGA will automatically connect DSP Core3 to Flash after waiting for 2 seconds.

[0046] S4: The FPGA connects DSP Core3 to Flash partition 4, the reset signal of DSP Core3 is pulled high, and Core3 starts booting from Flash partition 4; after booting, the DSP gives Core3 the instruction to relinquish Flash by writing address 0xB0000C02; if DSP Core3 does not give the instruction to relinquish Flash, the FPGA will automatically connect DSP Core0 to Flash after waiting for 2 seconds.

[0047] S5: DSP Core0 can request to occupy Flash partition 1 by reading address 0xB0001A02, or Flash partition 2 by reading address 0xB0001A06, or Flash partition 3 by reading address 0xB0001A0A, or Flash partition 4 by reading address 0xB0001A0E.

[0048] S6: DSP Core0 relinquishes its Flash memory access by writing to address 0xB0000C02;

[0049] S7: DSP Core1 requests access to Flash partition 2 by reading address 0xB0001A06;

[0050] S8: DSP Core1 relinquishes its Flash memory access by writing to address 0xB0000C02;

[0051] S9: DSP Core2 requests access to Flash partition 3 by reading address 0xB0001A0A;

[0052] S10: DSP Core2 relinquishes its Flash memory access by writing to address 0xB0000C02;

[0053] S11: DSP Core3 requests access to Flash partition 4 by reading address 0xB0001A0E;

[0054] S12: DSP Core3 relinquishes its Flash memory access by writing to address 0xB0000C02;

[0055] S13: If necessary, the DSP will access the Flash memory in a loop following steps S5 to S12.

[0056] The parts of this invention not described in detail are common knowledge to those skilled in the art.

Claims

1. A method for configuring external Flash memory for a quad-core DSP based on FPGA, characterized in that... include: Perform bootloader configuration: The bootloader configuration is executed only once after the DSP is powered on, in the following order: DSP Core0 connects to Flash for bootloader, DSP Core1 connects to Flash for bootloader, DSP Core2 connects to Flash for bootloader, and DSP Core3 connects to Flash for bootloader. Normal operation configuration: The normal operation configuration is performed after the DSP boot is complete and when access to Flash data begins. The process is as follows: DSP Core0 requests Flash access, DSP Core0 relinquishes Flash access, DSP Core1 requests Flash access, DSP Core1 relinquishes Flash access, DSP Core2 requests Flash access, DSP Core2 relinquishes Flash access, DSP Core3 requests Flash access, DSP Core3 relinquishes Flash access, DSP Core0 requests Flash access, DSP Core0 relinquishes Flash access, and so on, in a loop. The aforementioned FPGA-based quad-core DSP external Flash configuration method is implemented using a hardware platform composed of FPGA, DSP, and Flash. Within this hardware platform, The DSP bus includes four sets of address lines, four sets of data lines, four sets of write enable signal lines, four sets of read enable signal lines, four sets of output enable signal lines, and four reset signal lines. The Flash bus includes Flash data lines, Flash address lines, Flash chip select signal lines, Flash read enable signal lines, and Flash write enable signal lines; Both the DSP bus and the Flash bus are connected to the FPGA's I / O pins. According to the DSP's Flash access process, the FPGA connects the DSP bus to the Flash bus in a time-sharing manner, so that the four cores of the DSP can access the external Flash in a time-sharing manner. The specific steps for configuring bootloader include: S1: After power-on, the FPGA connects the DSP's Core0 to Flash partition 1, the reset signal of Core0 is pulled high, and Core0 starts booting from Flash partition 1; after booting is complete, the DSP issues a command for Core0 to relinquish its Flash memory. S2: The FPGA connects the DSP's Core1 to Flash partition 2. The reset signal of Core1 is pulled high, and Core1 starts booting from Flash partition 2. After booting is complete, the DSP issues a command for Core1 to relinquish its Flash memory. S3: The FPGA connects the DSP's Core2 to Flash partition 3. The reset signal of Core2 is pulled high, and Core2 starts booting from Flash partition 3. After booting is complete, the DSP issues an instruction for Core2 to relinquish its Flash memory. S4: The FPGA connects the DSP's Core3 to Flash partition 4. The reset signal of Core3 is pulled high, and Core3 starts booting from Flash partition 4. After booting is complete, the DSP gives Core3 an instruction to relinquish its Flash usage.

2. The method for configuring external Flash memory for a quad-core DSP based on FPGA according to claim 1, characterized in that: The steps for normal operation configuration are as follows: S5: DSP Core0 requests to occupy Flash, and Core0 operates on Flash partition 1, partition 2, partition 3 or partition 4; S6: Core0 relinquishes its Flash memory usage; S7: Core1 requests to use Flash, and Core1 only operates on Flash partition 2; S8: Core1 relinquishes its Flash memory usage; S9: Core2 requests Flash memory, but Core2 only operates on Flash partition 3; S10: Core2 relinquishes its Flash memory usage; S11: Core3 requests Flash memory, but Core3 only operates on Flash partition 4; S12: Core3 relinquishes its Flash memory usage; S13: The DSP accesses the Flash memory in a loop according to steps S5~S12.

3. A method for configuring external Flash memory for a quad-core DSP based on an FPGA according to claim 1 or 2, characterized in that: The boot loading configuration and normal operation configuration are implemented in the FPGA; a state machine is designed in the FPGA to connect the EMIF bus of DSPCore0~Core3 to the Flash bus in a time-division multiplexing manner, so as to realize the quad-core DSP access to the external Flash.

4. A processor, characterized in that, The processor is used to run a program, wherein the program executes the FPGA-based quad-core DSP external Flash configuration method according to any one of claims 1 to 3.

5. A non-volatile storage medium, characterized in that, include: A computer program product that, when executed, performs the FPGA-based quad-core DSP external Flash configuration method according to any one of claims 1 to 3.

6. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 3.

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