Semiconductor device for monitoring address error and electronic system including same

Abstract

The invention relates to a semiconductor device for monitoring address errors and an electronic system including the same. The electronic system includes a controller configured to: output a command, an external row address, and an external column address; receiving a flag signal; and outputting the flag signal to the host. The electronic system may also include a semiconductor device configured to: correct an error of internal data output from a memory cell selected based on the command, the external row address, and the external column address to output the corrected internal data as data; and outputting a flag signal that is enabled when the number of error settings in the internal data is corrected.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0139062, filed on October 17, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic system which monitors error occurrence in real time by providing a host with a flag signal generated when error correction of internal data output for each of the same row address and the same column address is performed a set number of times. Background Art

[0004] Recently, DDR2, DDR3, DDR4 and DDR5 methods of inputting / outputting multiple bits of data per clock cycle are being used to increase the operating speed of semiconductor devices. Since the probability of errors occurring during data transmission increases with the increase in data input / output speed, additional devices and methods are required to ensure the reliability of data transmission.

[0005] A method is used to ensure the reliability of data transmission by generating an error check code capable of checking whether an error has occurred each time data is sent and sending the error check code together with the data. The error check code includes an error detection code (EDC) that can detect an error that has occurred and an error correction code (ECC) that can self-correct when an error occurs. Summary of the invention

[0006] According to an embodiment of the present disclosure, an electronic system may include a controller configured to: output a command, an external row address, and an external column address; receive a flag signal; and output the flag signal to a host. The electronic system may also include a semiconductor device configured to: correct an error of internal data output from a storage unit selected based on the command, the external row address, and the external column address to output the error-corrected internal data as data; and output an enabled flag signal when an error set number of times in the internal data is corrected.

[0007] In addition, according to another embodiment of the present disclosure, the semiconductor device may include an error correction circuit configured to: correct an error of internal data based on an internal parity check and internal data output from a storage unit selected based on a row address and a column address to generate data; and generate a correction enable signal when the error of the internal data is correctable. The semiconductor device may also include a fault detection circuit configured to: latch a column address having a different combination in one combination of row addresses whenever the correction enable signal is enabled; and generate an enabled flag signal when the column address is latched a set number of times.

[0008] In addition, according to another embodiment of the present disclosure, the semiconductor device may include an error correction circuit configured to: correct an error of internal data based on an internal parity check and internal data output from a storage unit selected based on a row address and a column address to generate data; and generate a correction enable signal when the error of the internal data is correctable. The semiconductor device may also include a fault detection circuit configured to: latch a row address having a different combination in one combination of column addresses each time the correction enable signal is enabled; and generate an enabled flag signal when the row address is latched a set number of times. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram showing a configuration of an electronic system according to an embodiment of the present disclosure.

[0010] Figure 2 It shows that according to Figure 1 FIG. 1 is a block diagram showing a configuration of an embodiment of a semiconductor device included in an electronic system.

[0011] Figure 3 It shows that according to Figure 2 A block diagram showing a configuration of an embodiment of an error correction circuit included in a semiconductor device shown.

[0012] Figure 4 It shows that according to Figure 2 A block diagram showing a configuration of an embodiment of a fault detection circuit included in a semiconductor device is shown.

[0013] Figure 5 It shows that according to Figure 4 FIG. 2 is a block diagram of a configuration of an embodiment of a row control circuit included in a fault detection circuit.

[0014] Figure 6 It shows that according to Figure 5 A circuit diagram showing a configuration of an embodiment of a row comparison circuit included in a row control circuit is shown.

[0015] Figure 7 It shows that according to Figure 4 FIG. 2 is a block diagram of a configuration of an embodiment of a column control circuit included in a fault detection circuit.

[0016] Figure 8 It shows that according to Figure 4 FIG. 2 is a block diagram showing a configuration of an embodiment of a flag signal generating circuit included in a fault detection circuit.

[0017] Fig. 9 It is shown Figure 8 A table showing the operation of the flag signal generating circuit.

[0018] Fig.10 It shows that according to Figure 2 A block diagram showing a configuration of another embodiment of a fault detection circuit included in a semiconductor device shown in FIG.

[0019] Fig.11 It shows that according to Fig.10 FIG. 2 is a block diagram of a configuration of an embodiment of a column control circuit included in a fault detection circuit.

[0020] Fig.12 It shows that according to Fig.10 FIG. 2 is a block diagram of a configuration of an embodiment of a row control circuit included in a fault detection circuit.

[0021] Fig.13 is a diagram illustrating an error correction operation of a semiconductor device according to an embodiment of the present disclosure.

[0022] Fig.14 It shows that according to the application Figures 1 to 13 The electronic system shown is a block diagram of a configuration of another embodiment of an electronic system. DETAILED DESCRIPTION

[0023] In the description of the following embodiments, when a parameter is referred to as "predetermined", it may be intended to mean that when the parameter is used in a process or algorithm, the value of the parameter is determined in advance. The value of the parameter may be set at the start of the process or algorithm, or may be set during the period in which the process or algorithm is executed.

[0024] It should be understood that although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element and are not intended to imply the order or quantity of the elements. Therefore, without departing from the teachings of the present disclosure, the first element in some embodiments may be referred to as the second element in other embodiments.

[0025] In addition, it should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0026] A logic "high" level and a logic "low" level may be used to describe the logic level of an electrical signal. A signal having a logic "high" level may be distinguished from a signal having a logic "low" level. For example, when a signal having a first voltage corresponds to a signal having a logic "high" level, a signal having a second voltage corresponds to a signal having a logic "low" level. In an embodiment, a logic "high" level may be set to a voltage level having a voltage level higher than a logic "low" level. In addition, depending on the embodiment, the logic level of a signal may be set to be different or opposite. For example, a signal having a logic "high" level in one embodiment may be set to have a logic "low" level in another embodiment.

[0027] The term "logic bit group" may mean a combination of logic levels of bits included in a signal. When the logic level of each bit included in the signal changes, the logic bit group of the signal may be set differently. For example, when the signal includes two bits, when the logic level of each of the two bits included in the signal is "logic low level, logic low level", the logic bit group of the signal may be set to a first logic bit group, and when the logic level of each of the two bits included in the signal is "logic low level and logic high level", the logic bit group of the signal may be set to a second logic bit group.

[0028] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0029] Figure 1 1 is a block diagram showing the configuration of an electronic system 1 according to an embodiment of the present disclosure. Figure 1 As shown, the electronic system 1 may include a host 10 , a controller 20 , and a semiconductor device 30 .

[0030] The host 10 may include a first host pin 11_1 and a second host pin 11_2. The controller 20 may include a first control pin 21_1, a second control pin 21_2, a third control pin 22_1, a fourth control pin 22_2, a fifth control pin 22_3, a sixth control pin 22_4, a seventh control pin 22_5, and an eighth control pin 22_6. The semiconductor device 30 may include a first device pin 31_1, a second device pin 31_2, a third device pin 31_3, a fourth device pin 31_4, a fifth device pin 31_5, and a sixth device pin 31_6. The first transmission line L11 may be connected between the first host pin 11_1 and the first control pin 21_1. The second transmission line L12 may be connected between the second host pin 11_2 and the second control pin 21_2. The third transmission line L21 may be connected between the third control pin 22_1 and the first device pin 31_1. The fourth transmission line L22 may be connected between the fourth control pin 22_2 and the second device pin 31_2. A fifth transmission line L23 may be connected between the fifth control pin 22_3 and the third device pin 31_3. A sixth transmission line L24 may be connected between the sixth control pin 22_4 and the fourth device pin 31_4. A seventh transmission line L25 may be connected between the seventh control pin 22_5 and the fifth device pin 31_5. An eighth transmission line L26 may be connected between the eighth control pin 22_6 and the sixth device pin 31_6.

[0031] The host 10 may transmit a request signal REQ to the controller 20 through the first transmission line L11. The host 10 may receive a flag signal FLAG from the controller 20 through the second transmission line L12. The request signal REQ may be set as a signal including a plurality of bits for generating a command and an address during a write operation and a read operation.

[0032] The controller 20 may transmit a clock CLK to the semiconductor device 30 through the third transmission line L21. The controller 20 may transmit a command for controlling the semiconductor device 30 to the semiconductor device 30 through the fourth transmission line L22 based on the request signal REQ. The controller 20 may transmit an external row address ERAD for controlling the semiconductor device 30 to the semiconductor device 30 through the fifth transmission line L23 based on the request signal REQ. The controller 20 may transmit an external column address ECAD for controlling the semiconductor device 30 to the semiconductor device 30 through the sixth transmission line L24 based on the request signal REQ. The controller 20 may transmit data DATA to the semiconductor device 30 through the seventh transmission line L25 during a write operation based on the request signal REQ. The controller 20 may also receive data DATA from the semiconductor device 30 through the seventh transmission line L25 during a read operation based on the request signal REQ. The controller 20 may receive a flag signal FLAG from the semiconductor device 30 through the eighth transmission line L26. The controller 20 may output the flag signal FLAG to the host 10 through the second transmission line L12.

[0033] The clock CLK may be set as a signal that is periodically triggered to synchronize the operations of the controller 20 and the semiconductor device 30. The command CMD may be set as a signal that includes a plurality of bits and controls the operation of the semiconductor device 30. Each of the external row address ERAD and the external column address ECAD may be set as a signal that includes a plurality of bits and selects a plurality of storage cells ( Figure 2 The data DATA may be set to include a plurality of bits and be output to and input from the storage circuit 320. The flag signal FLAG may be set to be internal data ( Figure 2 A signal enabled when an error in ID<1:8> in the external column address ECAD is corrected a set number of times. Depending on the embodiment, the flag signal FLAG may be set to be a signal enabled when an internal data ( Figure 2 A signal that is enabled when an error in ID<1:8> in FIG. 1 is corrected a set number of times. For example, the semiconductor device 300 can enable the flag signal FLAG.

[0034] The semiconductor device 30 may include a storage circuit 320 , an error correction circuit 330 , and a failure detection circuit 340 .

[0035] The storage circuit 320 may generate internal data ( Figure 2ID<1:8> in the external row address ERAD and the external column address ECAD selected memory cell ( Figure 2 The storage circuit 320 can output the storage cell ( MC in ) stored in the external row address ERAD and the external column address ECAD selected during the read operation based on the command CMD. Figure 2 Internal data in MC Figure 2 ID<1:8>) and internal parity ( Figure 2 IP<1:3> in the .

[0036] The error correction circuit 330 can be used during a read operation based on the internal data ( Figure 2 ID<1:8>) and internal parity ( Figure 2 IP<1:3> in the correct internal data ( Figure 2 When the internal data ( Figure 2 When an error in ID<1:8> in FIG. 1 is correctable during a read operation, the error correction circuit 330 may generate a correction enable signal ( Figure 2 CE in ).

[0037] The fault detection circuit 340 can latch the row address ( Figure 2 RAD<1:L> in the ) and the column address generated from the external column address ECAD ( Figure 2 Whenever the correction enable signal ( Figure 2 When CE in is enabled, the fault detection circuit 340 can latch the row address ( Figure 2 There are multiple column addresses with different combinations in one combination of RAD<1:L> in Figure 2 Whenever the correction enable signal ( Figure 2 When the CE in the column is enabled, the fault detection circuit 340 can latch the column address ( Figure 2 There are multiple row addresses with different combinations in one combination of CAD<1:M> ( Figure 2 The fault detection circuit 340 can respectively detect the RAD<1:L> in the latched row address ( Figure 2 RAD<1:L>) and the column address ( Figure 2 CAD<1:M> in the CAD<1:M>) to generate the pre-row address ( Figure 5 and Fig.12 P_RAD<1:L>) and the pre-column address ( Figure 7 and Fig.11 When the correction enable signal ( Figure 2When CE in is enabled, the fault detection circuit 340 can Figure 2 RAD<1:L>) and the column address ( Figure 2 CAD<1:M>) in the previous row address ( Figure 5 and Fig.12 P_RAD<1:L> in the Figure 7 and Fig.11 The fault detection circuit 340 may compare the P_CAD<1:M> in ...

[0038] The semiconductor device 30 may correct the memory cell ( 100 ) selected by the external row address ERAD and the external column address ECAD during the read operation based on the command CMD. Figure 2 Internal data output by MC in Figure 2 ID<1:8>) to output the internal data of error correction ( Figure 2 When correcting the internal data ( Figure 2 When the number of erroneous settings of ID<1:8> in FIG. 1 is reached, the semiconductor device 30 may output an enabled flag signal FLAG to the controller 20.

[0039] Figure 2 It shows that according to Figure 1 0 is a block diagram of a configuration of an embodiment of a semiconductor device 30 included in an electronic system 1 shown in . The semiconductor device 30 may include an input circuit 310 , a storage circuit 320 , an error correction circuit 330 , and a failure detection circuit 340 .

[0040] The input circuit 310 may include a command decoder 311 , a row address generation circuit 312 , and a column address generation circuit 313 .

[0041] The command decoder 311 may receive a command CMD in synchronization with the clock CLK. The command decoder 311 may decode the command CMD in synchronization with the clock CLK to generate a read signal RD for performing a read operation. The command CMD is shown as a single signal, but may be set as a signal including a plurality of bits for controlling the operation of the semiconductor device 30. Depending on the embodiment, the command decoder 311 may be implemented to generate a write signal for performing a write operation.

[0042] The row address generation circuit 312 may receive the first to "L"th external row addresses ERAD<1:L> in synchronization with the clock CLK. The row address generation circuit 312 may buffer the first to "L"th external row addresses ERAD<1:L> in synchronization with the clock CLK to generate the first to "L"th row addresses RAD<1:L>. The number of bits "L" of the first to "L"th external row addresses ERAD<1:L> and the first to "L"th row addresses RAD<1:L> may be set to a variety of number of bits according to embodiments, and the number of bits "L" may be set to a positive integer.

[0043] The column address generation circuit 313 may receive the first to "M"th external column addresses ECAD<1:M> in synchronization with the clock CLK. The column address generation circuit 313 may buffer the first to "M"th external column addresses ECAD<1:M> in synchronization with the clock CLK to generate the first to "M"th column addresses CAD<1:M>. The number of bits "M" of the first to "M"th external column addresses ECAD<1:M> and the first to "M"th column addresses CAD<1:M> may be set to a variety of number of bits according to the embodiment, and the number of bits "M" may be set to a positive integer.

[0044] The input circuit 310 may receive a command CMD, first to "L"th external row addresses ERAD<1:L>, and first to "M"th external column addresses ECAD<1:M> in synchronization with a clock CLK. The input circuit 310 may generate a read signal RD, first to "L"th row addresses RAD<1:L>, and first to "M"th column addresses CAD<1:M> based on the command CMD, the first to "L"th external row addresses ERAD<1:L>, and the first to "M"th external column addresses ECAD<1:M>.

[0045] The storage circuit 320 may include a plurality of storage cells MC. When the read signal RD is enabled, the storage circuit 320 may output the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> stored in the storage cells MC selected by the first to "L"th row addresses RAD<1:L> and the first to "M"th column addresses CAD<1:M>. The storage circuit 320 may be implemented to store the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> in the storage cells MC selected by the first to "L"th row addresses RAD<1:L> and the first to "M"th column addresses CAD<1:M> during a write operation. The first to third internal parity IP<1:3> may be set to a signal containing error information included in the first to eighth internal data ID<1:8>. The first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> may be stored in and output from the same storage cell MC or different storage cells MC.

[0046] The error correction circuit 330 may correct errors of the first to eighth internal data ID<1:8> based on the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> to generate data DATA<1:8> during a read operation. During a read operation, when the errors of the first to eighth internal data ID<1:8> are correctable, the error correction circuit 330 may generate a correction enable signal CE. Each of the first to eighth internal data ID<1:8> and the first to eighth data DATA<1:8> is set to have eight bits, but the number of bits of each of the first to eighth internal data ID<1:8> and the first to eighth data DATA<1:8> may be set in various ways according to an embodiment. The first to third internal parity IP<1:3> is set to have 3 bits, but the number of bits of the first to third internal parity IP<1:3> may be set in various ways according to an embodiment.

[0047] The fault detection circuit 340 may latch the first to "L"th row addresses RAD<1:L> and the first to "M"th column addresses CAD<1:M>. Whenever the correction enable signal CE is enabled, the fault detection circuit 340 may latch a plurality of first to "M"th column addresses CAD<1:M> having different combinations in one combination of the first to "L"th row addresses RAD<1:L>. Whenever the correction enable signal CE is enabled, the fault detection circuit 340 may latch a plurality of first to "L"th row addresses RAD<1:L> having different combinations in one combination of the first to "M"th column addresses CAD<1:M>. The fault detection circuit 340 may generate the first to "L"th previous row addresses ( Figure 5 and Fig.12 P_RAD<1:L> in the Figure 7 and Fig.11 When the correction enable signal CE is enabled, the fault detection circuit 340 can respectively compare the first to the "L"th row address RAD<1:L> and the first to the "M"th column address CAD<1:M> with the first to the "L"th previous row address ( Figure 5 and Fig.12 P_RAD<1:L> in the Figure 7 and Fig.11 The fault detection circuit 340 compares the P_CAD<1:M> in ...

[0048] The semiconductor device 30 may correct errors of the first to eighth internal data <1:8> output from the memory cells selected by the first to Lth external row addresses ERAD<1:L> and the first to Mth external column addresses ECAD<1:M> during the read operation to output the error-corrected first to eighth internal data as the first to eighth data DATA<1:8> based on the command CMD. When the number of error setting times of the first to eighth internal data ID<1:8> output by the same first to Lth external row addresses ERAD<1:L> and the same first to Mth external column addresses ECAD<1:M> is corrected, the semiconductor device 30 may output an enabled flag signal FLAG to the controller 20.

[0049] Figure 3 It shows that according to Figure 2 FIG. 1 is a block diagram of a configuration of an embodiment of an error correction circuit 330 included in the semiconductor device 30 . The error correction circuit 330 may include an error processing circuit 331 and a correction enable signal generating circuit 332 .

[0050] The error processing circuit 331 may include a calculation parity generation circuit 331_1 , a syndrome generation circuit 331_2 , an error correction signal generation circuit 331_3 , and a data processing circuit 331_4 .

[0051] The calculated parity generation circuit 331_1 may generate first to third calculated parities CP<1:3> including error information of the first to eighth internal data ID<1:8>. The calculated parity generation circuit 331_1 may perform an ECC encoding operation based on the first to eighth internal data ID<1:8> to generate first to third calculated parities CP<1:3> during a read operation.

[0052] The ECC encoding operation may be set as an operation of comparing bits of data using an error correction code (ECC) in a general error correction circuit and generating parity bits according to the comparison result.

[0053] The syndrome generation circuit 331_2 may compare the first to third calculated parities CP<1:3> with the first to third internal parities IP<1:3> during reading to generate first to third syndromes SYN<1:3>.

[0054] The error correction signal generation circuit 331_3 may perform an ECC decoding operation on the first to third syndromes SYN<1:3> to generate first to eighth error correction signals CR<1:8>.

[0055] The ECC decoding operation may be set to an operation of comparing parity bits of data generated in an ECC encoding operation using an error correction code (ECC) in a general error correction circuit with parity bits generated a previous time to generate syndrome bits, and decoding the syndrome bits to correct errors included in the data.

[0056] The data processing circuit 331_4 may correct errors of the first to eighth internal data ID<1:8> input from the storage circuit 320 based on the first to eighth error correction signals CR<1:8> to output the error-corrected data as the first to eighth data DATA<1:8>. The data processing circuit 331_4 may invert bits in which errors occur in the first to eighth internal data ID<1:8> based on the first to eighth error correction signals CR<1:8> to output the first to eighth internal data ID<1:8> including the inverted bits as the first to eighth data DATA<1:8>. The data processing circuit 331_4 may output the error-corrected first to eighth data DATA<1:8> to the controller 20 during a read operation.

[0057] The error processing circuit 331 may perform an ECC encoding operation and an ECC decoding operation based on the first to eighth internal data ID<1:8> and the first to third internal parities IP<1:3> to generate first to eighth error correction signals CR<1:8>. The error processing circuit 331 may correct errors of the first to eighth internal data ID<1:8> based on the first to eighth error correction signals CR<1:8> to output the error-corrected first to eighth internal data as the first to eighth data DATA<1:8>.

[0058] The correction enable signal generation circuit 332 may generate an enabled correction enable signal CE based on the first to eighth error correction signals CR<1:8>. When one of the first to eighth error correction signals CR<1:8> is generated at a logic "high" level, the correction enable signal generation circuit 332 may generate the correction enable signal CE enabled at a logic "high" level.

[0059] The error correction circuit 330 may detect errors of the first to eighth internal data ID<1:8> and correct the errors of the first to eighth internal data ID<1:8> to output the error-corrected first to eighth internal data as the first to eighth data DATA<1:8>. The error correction circuit 330 may perform an ECC encoding operation and an ECC decoding operation on the first to eighth internal data ID<1:8> and correct the errors of the first to eighth internal data ID<1:8> to output the error-corrected first to eighth internal data as the first to eighth data DATA<1:8>. The error correction circuit 330 may output the error-corrected first to eighth data DATA<1:8> to the controller 20 during a read operation. When correcting the errors of the first to eighth internal data ID<1:8>, the error correction circuit 330 may generate a correction enable signal CE enabled at a logic “high” level.

[0060] Figure 4 It shows that according to Figure 2 FIG. 1 is a block diagram showing a configuration of an embodiment of a fault detection circuit 340 included in the semiconductor device 30 . The fault detection circuit 340 may include a row control circuit 341 , a column control circuit 342 , and a flag signal generation circuit 343 .

[0061] The row control circuit 341 may latch the first to “L”th row addresses RAD<1:L> to generate the first to “L”th previous row addresses ( Figure 5 The row control circuit 341 can generate the first to the "L"th row addresses ( Figure 5The first to "L"th row address RAD<1:L> input after the first to "L"th row address RAD<1:L> is compared with the first to "L"th previous row address P_RAD<1:L> to generate a reset signal RST. Figure 5 When the first to "L"th row addresses RAD<1:L> and the first to "L"th previous row addresses ( Figure 5 When the P_RAD<1:L> in FIG. 1 has the same combination, the row control circuit 341 may generate a disabled reset signal RST.

[0062] When the correction enable signal CE is enabled, the column control circuit 342 may latch the first to the "M"th column addresses CAD<1:L> to generate the first to the "M"th front column addresses ( Figure 7 The column control circuit 342 may generate the first to the "M"th column addresses ( Figure 7 The first to Mth column addresses CAD<1:M> input after P_CAD<1:M> in the table are combined with the first to Mth column addresses ( Figure 7 When the first to Mth column addresses CAD<1:M> and the first to Mth front column addresses ( Figure 7 When the first to the Mth column addresses CAD<1:M> and the first to the Mth front column addresses ( Figure 7 When the P_CAD<1:M> in the column control circuit 342 has the same combination, the column control circuit 342 can generate a disabled comparison signal CMP. When the reset signal RST is enabled, the column control circuit 342 can initialize the first to the "M"th column addresses ( Figure 7 in P_CAD<1:M>).

[0063] When the correction enable signal CE is enabled and the comparison signal CMP is enabled, the flag signal generating circuit 343 may generate the first count signal and the second count signal ( Figure 8 When the first count signal and the second count signal ( Figure 8 When the first count signal and the second count signal (CNT<1:2> in FIG. 1 ) are counted a set number of times, the flag signal generating circuit 343 can generate an enabled flag signal FLAG. Figure 8When the CNT<1:2> in (CNT<1:2>) is counted less than the set number of times, the flag signal generating circuit 343 can generate a disabled flag signal FLAG. When the reset signal RST is enabled, the flag signal generating circuit 343 can initialize the first counting signal and the second counting signal ( Figure 8 CNT<1:2> in ).

[0064] Figure 5 It shows that according to Figure 4 FIG. 3 is a block diagram of a configuration of an embodiment of a row control circuit 341 included in the fault detection circuit 340. The row control circuit 341 may include a row register 341_1 and a row comparison circuit 341_2.

[0065] The row register 341_1 may latch the first to "L"th row addresses RAD<1:L> to generate the first to "L"th previous row addresses. Whenever the first to "L"th row addresses RAD<1:L> are input, the row register 341_1 may latch the first to "L"th row addresses RAD<1:L> to generate the first to "L"th previous row addresses P_RAD<1:L>. The row register 341_1 may include a plurality of registers. The row register 341_1 may latch the first to "L"th row addresses RAD<1:L> through a plurality of registers to generate the first to "L"th previous row addresses P_RAD<1:L>.

[0066] The row comparison circuit 341_2 may compare the first to "L"th row addresses RAD<1:L> with the first to "L"th previous row addresses P_RAD<1:L> to generate a reset signal RST. When the first to "L"th row addresses RAD<1:L> and the first to "L"th previous row addresses P_RAD<1:L> have different combinations, the row comparison circuit 341_2 may generate the reset signal RST enabled at a logic "high" level. When the first to "L"th row addresses RAD<1:L> and the first to "L"th previous row addresses P_RAD<1:L> have the same combination, the row comparison circuit 341_2 may generate the reset signal RST disabled at a logic "low" level.

[0067] Figure 6 It shows that according to Figure 5 2 is a circuit diagram showing a configuration of an embodiment of a row comparison circuit 341_2 included in a row control circuit 341 shown.

[0068] The row comparison circuit 341_2 can be composed of a plurality of XOR gates 341 <2> ~341 <7> When the first row address RAD <1> and the first previous row address P_RAD <1> At different logic levels, the XOR gate 341 <1> A logic "high" level output signal can be generated. When the first row address RAD <1> and the first previous row address P_RAD <1> At the same logic level, XOR gate 341 <1> Can generate a logic "low" level output signal. XOR gate 341 <2> ~341 <7> Can perform AND XOR gate 341 <1> The operations are the same, so detailed description will be omitted.

[0069] When the first to "L"th row addresses RAD<1:L> and the first to "L"th previous row addresses P_RAD<1:L> have different combinations, the row comparison circuit 341_2 may generate a reset signal RST enabled at a logic "high" level. When the first to "L"th row addresses RAD<1:L> and the first to "L"th previous row addresses P_RAD<1:L> have the same combination, the row comparison circuit 341_2 may generate a reset signal RST disabled at a logic "low" level.

[0070] Figure 7 It shows that according to Figure 4 FIG. 3 is a block diagram of a configuration of an embodiment of a column control circuit 342 included in the fault detection circuit 340. The column control circuit 342 may include a column register 342_1, a column comparison circuit 342_2, and a comparison signal generation circuit 342_3.

[0071] When the correction enable signal CE is enabled, the column register 342_1 can latch the first to the "M"th column addresses CAD<1:M> to generate the first to the "M"th front column addresses P_CAD<1:M>. Whenever the correction enable signal CE is enabled, the column register 342_1 can latch the first to the "M"th column addresses CAD<1:M> to generate the first to the "M"th front column addresses P_CAD<1:M>. The column register 342_1 may include a plurality of registers. The column register 342_1 may latch the first to the "M"th column addresses CAD<1:M> through a plurality of registers to generate the first to the "M"th front column addresses P_CAD<1:M>. When the reset signal RST is enabled, the column register 342_1 may generate the initialized first to the "M"th front column addresses P_CAD<1:M>. When the reset signal RST is enabled at a logic “high” level, the column register 342_1 may generate first to “M” front column addresses P_CAD<1:M> all initialized at a logic “low” level.

[0072] The column comparison circuit 342_2 may compare the first to "M"th column addresses CAD<1:M> with the first to "M"th front column addresses P_CAD<1:M> to generate a column detection signal CA_DET. When the first to "M"th column addresses CAD<1:M> and the first to "M"th front column addresses P_CAD<1:M> have different combinations, the column comparison circuit 342_2 may generate a column detection signal CA_DET enabled at a logic "high" level. When the first to "M"th column addresses CAD<1:M> and the first to "M"th front column addresses P_CAD<1:M> have the same combination, the column comparison circuit 342_2 may generate a column detection signal CA_DET disabled at a logic "low" level. The column comparison circuit 342_2 may be compatible only in terms of input signals and output signals. Figure 6 The row comparison circuit 341_2 shown is different and can be implemented using the same circuit and perform the same operation, so a detailed description will be omitted.

[0073] The comparison signal generation circuit 342_3 may generate a comparison signal CMP based on the correction enable signal CE and the column detection signal CA_DET. When the correction enable signal CE is enabled, the comparison signal generation circuit 342_3 may generate a comparison signal CMP based on the column detection signal CA_DET. When the correction enable signal CE is enabled and the column detection signal CA_DET is enabled, the comparison signal generation circuit 342_3 may generate a comparison signal CMP enabled at a logic "high" level. When the correction enable signal CE is enabled and the column detection signal CA_DET is disabled, the comparison signal generation circuit 342_3 may generate a comparison signal CMP disabled at a logic "low" level.

[0074] Figure 8 It shows that according to Figure 4 FIG. 3 is a block diagram of a configuration of an embodiment of a flag signal generating circuit 343 included in the fault detection circuit 340. The flag signal generating circuit 343 may include a counting circuit 343_1 and a counting signal detecting circuit 343_2.

[0075] When the correction enable signal CE is enabled and the comparison signal CMP is enabled, the counting circuit 343_1 may generate a first counting signal and a second counting signal CNT<1:2> that count sequentially. Whenever the correction enable signal CE is enabled at a logic "high" level and the comparison signal CMP is enabled at a logic "high" level, the counting circuit 343_1 may generate a first counting signal and a second counting signal CNT<1:2> that count sequentially upward. When the reset signal RST is enabled, the counting circuit 343_1 may generate a first counting signal and a second counting signal CNT<1:2> that are initialized. When the reset signal RST is enabled at a logic "high" level, the counting circuit 343_1 may generate a first counting signal and a second counting signal CNT<1:2> that are both initialized to a logic "low" level.

[0076] The count signal detection circuit 343_2 may detect the logic levels of the first count signal and the second count signal CNT<1:2> to generate a flag signal FLAG. When the first count signal and the second count signal CNT<1:2> are counted a set number of times, the count signal detection circuit 343_2 may generate a flag signal FLAG enabled at a logic "high" level. The set number of times according to an embodiment of the present disclosure may mean that the first count signal and the second count signal CNT<1:2> are counted up three times.

[0077] Fig. 9 It is shown Figure 8 A table showing the operation of the flag signal generating circuit 343 is shown.

[0078] When the correction enable signal CE is enabled at a logic “high” level and the first comparison signal first CMP is enabled at a logic “high” level, the counting circuit 343_1 may generate a first counting signal CNT of a logic “high” level. <1> and the second counting signal CNT of logic “low” level <2> When the correction enable signal CE is enabled at a logic “high” level and the second comparison signal second CMP is enabled at a logic “high” level, the counting circuit 343_1 may generate a first counting signal CNT of a logic “low” level. <1> and the second counting signal CNT of logic "high" level <2> When the correction enable signal CE is enabled at a logic “high” level and the third comparison signal third CMP is enabled at a logic “high” level, the counting circuit 343_1 may generate a first counting signal CNT of a logic “high” level. <1> and the second counting signal CNT of logic "high" level <2> .

[0079] When the reset signal RST is enabled at a logic “high” level, the counting circuit 343_1 may generate the initialized first and second counting signals CNT<1:2>. When the reset signal RST is enabled at a logic “high” level, the counting circuit 343_1 may generate the first counting signal CNT<1:2> at a logic “low” level. <1> and the second counting signal CNT of logic “low” level <2> .

[0080] The set number of times according to an embodiment of the present disclosure may mean that the first count signal and the second count signal CNT<1:2> are counted up three times and the first count signal CNT<1:2> of the logic “high” level is <1> and the second counting signal CNT of logic "high" level <2> is generated.

[0081] When the first counting signal and the second counting signal CNT<1:2> are counted a set number of times and the first counting signal CNT<1:2> of the logic “high” level is <1> and the second counting signal CNT of logic "high" level <2> When φ 2 is generated, the count signal detection circuit 343_2 may generate a flag signal FLAG enabled at a logic “high” level.

[0082] Fig.10 It shows that according to Figure 2 FIG. 2 is a block diagram showing a configuration of a fault detection circuit 340 a of another embodiment of the fault detection circuit 340 included in the semiconductor device 20 . The fault detection circuit 340 a may include a column control circuit 344 , a row control circuit 345 , and a flag signal generation circuit 346 .

[0083] The column control circuit 344 may latch the first to the "M"th column addresses CAD<1:M> to generate the first to the "M"th front column addresses ( Fig.11 The column control circuit 344 may generate the first to the "M"th column addresses ( Fig.11 The first to Mth column addresses CAD<1:M> input after P_CAD<1:M> in the table are combined with the first to Mth front column addresses ( Fig.11 The reset signal RST is generated by comparing the first to the Mth column address CAD<1:M> with the first to the Mth front column address ( Fig.11 When the first to the "M"th column address CAD<1:M> and the first to the "M"th front column address ( Fig.11 When P_CAD<1:M> in the column control circuit 344 has the same combination, the column control circuit 344 may generate a disabled reset signal RST.

[0084] When the correction enable signal CE is enabled, the row control circuit 345 may latch the first to “L”th row addresses RAD<1:L> to generate the first to “L”th previous row addresses ( Fig.12 The row control circuit 345 may generate the first to the "L"th row addresses ( Fig.12 The first to Lth row addresses RAD<1:L> input after P_RAD<1:L> in the table are combined with the first to Lth previous row addresses ( Fig.12 When the first to the "L"th row address RAD<1:L> and the first to the "L"th previous row address ( Fig.12 When the first to "L"th row addresses RAD<1:L> and the first to "L"th previous row addresses ( Fig.12 When the P_RAD<1:L> in the row control circuit 345 has the same combination, the row control circuit 345 can generate a disabled comparison signal CMP. When the reset signal RST is enabled, the row control circuit 345 can initialize the first to the "L"th previous row addresses ( Fig.12 1:L> in the P_RAD<1:L> register).

[0085] When the correction enable signal CE is enabled and the comparison signal CMP is enabled, the flag signal generation circuit 346 may generate the first count signal and the second count signal ( Figure 8 When the first count signal and the second count signal ( Figure 8 When the first count signal and the second count signal (CNT<1:2> in FIG. 1 ) are counted a set number of times, the flag signal generating circuit 346 can generate an enabled flag signal FLAG. Figure 8 When the CNT<1:2> in (CNT<1:2>) is counted less than the set number of times, the flag signal generating circuit 346 can generate a disabled flag signal FLAG. When the reset signal RST is enabled, the flag signal generating circuit 346 can initialize the first counting signal and the second counting signal ( Figure 8 The flag signal generation circuit 346 can be used with Figure 8 The flag signal generating circuit 343 shown is implemented by the same circuit and performs the same operation, so a detailed description will be omitted.

[0086] Fig.11 It shows that according to Fig.10 FIG. 3 is a block diagram of a configuration of an embodiment of a column control circuit 344 included in a fault detection circuit 340 a shown in FIG. Column control circuit 344 may include a column register 344_1 and a column comparison circuit 344_2 .

[0087] The column register 344_1 may latch the first to "M"th column addresses CAD<1:M> to generate the first to "M"th front column addresses P_CAD<1:M>. Whenever the first to "M"th column addresses CAD<1:M> are input, the column register 344_1 may latch the first to "M"th column addresses CAD<1:M> to generate the first to "M"th front addresses P_CAD<1:M>. The column register 344_1 may include a plurality of registers. The column register 344_1 may latch the first to "M"th column addresses CAD<1:M> to generate the first to "M"th front column addresses P_CAD<1:M> through a plurality of registers.

[0088] The column comparison circuit 344_2 may compare the first to "M"th column addresses CAD<1:M> with the first to "M"th front column addresses P_CAD<1:M> to generate a reset signal RST. When the first to "M"th column addresses CAD<1:M> and the first to "M"th front column addresses P_CAD<1:M> have different combinations, the column comparison circuit 344_2 may generate the reset signal RST enabled at a logic "high" level. When the first to "M"th column addresses CAD<1:M> and the first to "M"th front column addresses P_CAD<1:M> have the same combination, the column comparison circuit 344_2 may generate the reset signal RST disabled at a logic "low" level.

[0089] Fig.12 It shows that according to Fig.10 FIG. 3 is a block diagram of a configuration of an embodiment of a row control circuit 345 included in a fault detection circuit 340 a shown in FIG. The row control circuit 345 may include a row register 345_1 , a row comparison circuit 345_2 , and a comparison signal generation circuit 345_3 .

[0090] When the correction enable signal CE is enabled, the row register 345_1 may latch the first to "L"th row addresses RAD<1:L> to generate the first to "L"th previous row addresses P_RAD<1:L>. Whenever the correction enable signal CE is enabled, the row register 345_1 may latch the first to "L"th row addresses RAD<1:L> to generate the first to "L"th previous row addresses P_RAD<1:L>. The row register 345_1 may include a plurality of registers. The row register 345_1 may latch the first to "L"th row addresses RAD<1:L> through a plurality of registers to generate the first to "L"th previous row addresses P_RAD<1:L>. When the reset signal RST is enabled, the row register 345_1 may generate the initialized first to "L"th previous row addresses P_RAD<1:L>. When the reset signal RST is enabled at a logic “high” level, the row register 345_1 may generate the first to “L” previous row addresses P_RAD<1:L> all initialized to a logic “low” level.

[0091] The row comparison circuit 345_2 may compare the first to "L"th row addresses RAD<1:L> with the first to "L"th previous row addresses P_RAD<1:L> to generate a row detection signal RA_DET. When the first to "L"th row addresses RAD<1:L> and the first to "L"th previous row addresses P_RAD<1:L> have different combinations, the row comparison circuit 345_2 may generate the row detection signal RA_DET enabled at a logic "high" level. When the first to "L"th row addresses RAD<1:L> and the first to "L"th previous row addresses P_RAD<1:L> have the same combination, the row comparison circuit 345_2 may generate the row detection signal RA_DET disabled at a logic "low" level.

[0092] The comparison signal generation circuit 345_3 may generate a comparison signal CMP based on the correction enable signal CE and the row detection signal RA_DET. When the correction enable signal CE is enabled, the comparison signal generation circuit 345_3 may generate a comparison signal CMP based on the row detection signal RA_DET. When the correction enable signal CE is enabled and the row detection signal RA_DET is enabled, the comparison signal generation circuit 345_3 may generate a comparison signal CMP enabled at a logic "high" level. When the correction enable signal CE is enabled and the row detection signal RA_DET is disabled, the comparison signal generation circuit 345_3 may generate a comparison signal CMP disabled at a logic "low" level.

[0093] Fig.13 is a diagram showing an error correction operation of the semiconductor device 30 according to an embodiment of the present disclosure. Fig.13 The error correction operation is described as follows by taking the operation when the error correction operation is performed 3 times, ie, the set number of times, during the read operation as an example.

[0094] The command decoder 311 of the input circuit 310 may decode the command CMD in synchronization with the clock CLK to generate a read signal RD enabled at a logic "high" level to perform a read operation. The row address generation circuit 312 of the input circuit 310 may buffer the first to "L"th external row addresses ERAD<1:L> of the "A" combination in synchronization with the clock CLK to generate the first to "L"th row addresses RAD<1:L> of the "A" combination. The column address generation circuit 313 of the input circuit 310 may buffer the first to "M"th external column addresses ECAD<1:M> of the "B" combination in synchronization with the clock CLK to generate the first to "M"th column addresses CAD<1:M> of the "B" combination.

[0095] When the read signal RD is enabled at a logic “high” level, the storage circuit 320 can output the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> stored in the memory cells MC selected by the first to “L”th row addresses RAD<1:L> and the first to “M”th column addresses CAD<1:M>.

[0096] The error correction circuit 330 may correct errors of the first to eighth internal data ID<1:8> based on the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> during a read operation to generate first to eighth data DATA<1:8>. The error correction circuit 330 may output the error-corrected first to eighth data DATA<1:8> to the controller 20. When errors in the first to eighth internal data ID<1:8> are correctable during a read operation, the error correction circuit 330 may generate a correction enable signal CE enabled at a logic "high" level.

[0097] When the correction enable signal CE is enabled at a logic "high" level, the fault detection circuit 340 may latch the first to "L"th row addresses RAD<1:L> of the "A" combination and the first to "M"th column addresses CAD<1:M> of the "B" combination. Because the correction enable signal CE is enabled once (the first time), the fault detection circuit 340 may generate a flag signal FLAG of a logic "low" level. The fault detection circuit 340 may output the flag signal FLAG to the controller 20.

[0098] The command decoder 311 of the input circuit 310 may decode the command CMD in synchronization with the clock CLK to generate a read signal RD enabled at a logic "high" level to perform a read operation. The row address generation circuit 312 of the input circuit 310 may buffer the first to "L"th external row addresses ERAD<1:L> of the "A" combination in synchronization with the clock CLK to generate the first to "L"th row addresses RAD<1:L> of the "A" combination. The column address generation circuit 313 of the input circuit 310 may buffer the first to "M"th external column addresses ECAD<1:M> of the "C" combination in synchronization with the clock CLK to generate the first to "M"th column addresses CAD<1:M> of the "C" combination. The first to "M"th column addresses CAD<1:M> of the "C" combination may represent a different combination from the first to "M"th column addresses CAD<1:M> of the "B" combination.

[0099] When the read signal RD is enabled at a logic “high” level, the storage circuit 320 may output the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> stored in the memory cells MC selected by the first to “L”th row addresses RAD<1:L> and the first to “M”th column addresses CAD<1:M>.

[0100] The error correction circuit 330 may correct errors of the first to eighth internal data ID<1:8> based on the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> during a read operation to generate first to eighth data DATA<1:8>. The error correction circuit 330 may output the error-corrected first to eighth data DATA<1:8> to the controller 20. When errors in the first to eighth internal data ID<1:8> are correctable during a read operation, the error correction circuit 330 may generate a correction enable signal CE enabled at a logic "high" level.

[0101] When the correction enable signal CE is enabled at a logic “high” level, the fault detection circuit 340 may latch the first to “L”th row addresses RAD<1:L> of the “A” combination and the first to “M”th column addresses CAD<1:M> of the “C” combination. When the correction enable signal CE is enabled at a logic “high” level for the second time, the fault detection circuit 340 may compare the first to “L”th row addresses RAD<1:L> of the “A” combination and the first to “M”th column addresses CAD<1:M> of the “C” combination with the first to “L”th previous row addresses ( Figure 5 and 12 P_RAD<1:L> in the Figure 7 and 11The fault detection circuit 340 compares the P_CAD<1:M> in ...

[0102] The command decoder 311 of the input circuit 310 may decode the command CMD in synchronization with the clock CLK to generate a read signal RD enabled at a logic "high" level to perform a read operation. The row address generation circuit 312 of the input circuit 310 may buffer the first to "L"th external row addresses ERAD<1:L> of the "A" combination in synchronization with the clock CLK to generate the first to "L"th row addresses RAD<1:L> of the "A" combination. The column address generation circuit 313 of the input circuit 310 may buffer the first to "M"th external column addresses ECAD<1:M> of the "D" combination in synchronization with the clock CLK to generate the first to "M"th column addresses CAD<1:M> of the "D" combination. The first to "M"th column addresses CAD<1:M> of the "D" combination may represent a combination different from the first to "M"th column addresses CAD<1:M> of the "B" combination and the first to "M"th column addresses CAD<1:M> of the "C" combination.

[0103] When the read signal RD is enabled at a logic “high” level, the storage circuit 320 may output the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> stored in the memory cells MC selected by the first to “L” row addresses RAD<1:L> and the first to “M” column addresses CAD<1:M>.

[0104] The error correction circuit 330 may correct errors of the first to eighth internal data ID<1:8> based on the first to eighth internal data ID<1:8> and the first to third internal parity IP<1:3> to generate the first to eighth data DATA<1:8>. The error correction circuit 330 may output the error-corrected first to eighth data DATA<1:8> to the controller 20. When the errors of the first to eighth internal data ID<1:8> are correctable during the read operation, the error correction circuit 330 may generate a correction enable signal CE enabled at a logic "high" level. The correction enable signal CE may be enabled a set number of times (3 times enabled).

[0105] When the correction enable signal CE is enabled at a logic "high" level, the fault detection circuit 340 can latch the first to "L"th row addresses RAD<1:L> of the "A" combination and the first to "M"th column addresses CAD<1:M> of the "D" combination. Because the correction enable signal CE is enabled a set number of times (enabled 3 times), the fault detection circuit 340 can latch the first to "L"th row addresses RAD<1:L> of the "A" combination and the first to "M"th column addresses CAD<1:M> of the "D" combination with the first to "L"th previous row addresses ( Figure 5 and Fig.12 P_RAD<1:L> in the ) and the first to the first "M" column addresses of the "C" combination ( Figure 7 and Fig.11 P_CAD<1:M> in the figure is compared and a flag signal FLAG of a logic “high” level is generated. Fig.13 The fault detection circuit 340 may output a flag signal FLAG to the controller 20 .

[0106] The controller 20 may output a flag signal FLAG of a logic “high” level to the host 10 .

[0107] The host 10 may receive the flag signal FLAG of a logic "high" level and detect that the error correction operation is performed a set number of times. That is, the host 10 may monitor the occurrence of errors in real time.

[0108] When the error correction operation for the internal data outputted for each of the same row address and the same column address is performed a set number of times, the electronic system 1 according to the embodiment of the present disclosure can provide an enabled flag signal to the host. The electronic system 1 can monitor the occurrence of errors in real time by providing the host with a flag signal generated when the error correction operation for the internal data outputted for each of the same row address and the same column address input in real time is performed a set number of times. The electronic system 1 can monitor the occurrence of errors by providing the host with a flag signal, which occurs when the number of error correction operations for errors occurring in the internal data outputted by the same column address among multiple column addresses for a row address exceeds the set number of times. The electronic system 1 can monitor the occurrence of errors by providing the host with a flag signal, which occurs when the number of error correction operations for errors occurring in the internal data outputted by the same row address among multiple row addresses for a column address exceeds the set number of times.

[0109] Fig.14 1 is a block diagram showing a configuration of an embodiment of an electronic system 1000 according to an embodiment of the present disclosure. Fig.14 As shown, the electronic system 1000 may include a host 1100 and a semiconductor system 1200 .

[0110] The host 1100 and the semiconductor system 1200 may transmit signals to each other by using an interface protocol. The interface protocol used between the host 1100 and the semiconductor system 1200 may include a multimedia card (MMC), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), and a universal serial bus (USB), etc.

[0111] The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400 (1:K). The controller 1300 may control the semiconductor device 1400 (1:K) to perform a write operation and a read operation. When an error correction operation of internal data outputted for each of the same first to "L"th row addresses RAD<1:L> and the same first to "M"th column addresses CAD<1:M> is performed a set number of times, each semiconductor device 1400 (1:K) may generate an enabled flag signal FLAG. When an error correction operation of internal data outputted for each of the same first to "L"th row addresses RAD<1:L> and the same first to "M"th column addresses CAD<1:M> input in real time is performed a set number of times, each semiconductor device 1400 (1:K) may generate an enabled flag signal FLAG. When an error correction operation of an error occurring in internal data outputted by the same first to "M"th column address CAD<1:M> among a plurality of first to "M"th column addresses CAD<1:M> for one of the first to "L"th row addresses RAD<1:L> is performed a set number of times, each semiconductor device 1400(1:K) may generate an enabled flag signal FLAG. When an error correction operation of an error occurring in internal data outputted by the same first to "L"th row address RAD<1:L> among a plurality of first to "M"th row addresses RAD<1:L> for one of the first to "M"th column addresses CAD<1:M> is performed a set number of times, each semiconductor device 1400(1:K) may generate an enabled flag signal FLAG. Each semiconductor device 1400(1:K) may output the flag signal FLAG to the controller 1300. The controller 1300 may output the flag signal FLAG to the host 1100. The host 1100 may receive the flag signal FLAG to detect that the error correction operation is performed a set number of times for each of the same first to "L"th row addresses RAD<1:L> and the same first to "M"th column addresses CAD<1:M>. The host 1100 may monitor the error occurrence in real time.

[0112] Host 1100 can be used Figure 1 The controller 1300 can be implemented by the host 10 shown in FIG. Figure 1Each semiconductor device 1400 (1:K) can be implemented by the controller 20 shown in FIG. Figure 1 The semiconductor device 30 shown is implemented. Each semiconductor device 1400 (1:K) can be implemented by one of a dynamic random access memory (DRAM), a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

[0113] Concepts have been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will appreciate that multiple modifications, additions and / or substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered restrictive, but exemplary. The scope of the concept is not limited to the above description, but is defined by the appended claims, and all distinguishing features within the scope of equivalents should be interpreted as being included in the concept.

Claims

1. An electronic system comprising: a controller that: outputs a command, an external row address, and an external column address; receives a flag signal; and outputs the flag signal to a host; and A semiconductor device, which: corrects an error of internal data output from a storage unit to output the error-corrected internal data as data, the storage unit being selected based on the command, the external row address and the external column address; and outputs the enabled flag signal when the error set number of times in the internal data is corrected.

2. The electronic system according to claim 1, wherein: The semiconductor device enables the flag signal when the error in the internal data outputted by the external column addresses having different combinations in one combination of the external row addresses is corrected the set number of times.

3. The electronic system according to claim 1, wherein: The semiconductor device enables the flag signal when the error in the internal data outputted by the external row addresses having different combinations in one combination of the external column addresses is corrected the set number of times.

4. The electronic system according to claim 1, wherein: The semiconductor device comprises: an input circuit that: receives the command, the external row address, and the external column address in synchronization with a clock; and generates a read signal, a row address, and a column address based on the command, the external row address, and the external column address; a storage circuit that outputs the internal data and internal parity in the storage cell selected based on the read signal, the row address, and the column address; an error correction circuit that: corrects the error of the internal data based on the internal data and the internal parity to generate the data; and generates a correction enable signal when the error of the internal data is correctable; and A fault detection circuit is provided, which: latches the row address and the column address to generate a previous row address and a previous column address; and compares the row address and the column address with the previous row address and the previous column address, respectively, to generate the flag signal.

5. The electronic system according to claim 4, wherein: The error correction circuit comprises: an error processing circuit which: generates an error correction signal based on the internal data and the internal parity; and corrects the error of the internal data based on the error correction signal to output the error-corrected internal data as the data; and A correction enable signal generating circuit is configured to generate the correction enable signal based on the error correction signal.

6. The electronic system according to claim 5, wherein: The error handling circuit comprises: a computational parity generation circuit that compares bits included in the internal data to generate a computational parity; a syndrome generation circuit that compares the calculated parity with the internal parity to generate a syndrome; an error correction signal generating circuit, which decodes the syndrome to generate the error correction signal; and A data processing circuit inverts an erroneous bit of the internal data based on the error correction signal to generate the data.

7. The electronic system according to claim 4, wherein: The fault detection circuit comprises: a row control circuit that: latches the row address to generate the previous row address; and generates an enabled reset signal when the row address input after the previous row address is generated and the previous row address have different combinations; a column control circuit that: latches the column address to generate the previous column address when the correction enable signal is enabled; and generates an enabled comparison signal when the column address input after the previous column address is generated has a different combination from the previous column address; and A flag signal generating circuit that: counts a count signal when the correction enable signal is enabled and the comparison signal is enabled; and generates the enabled flag signal when the count signal is counted a set number of times.

8. The electronic system according to claim 7, in, When the reset signal is enabled, the column control circuit initializes the front column address, and Wherein, when the reset signal is enabled, the flag signal generating circuit initializes the counting signal.

9. The electronic system according to claim 7, wherein: The row control circuit comprises: a row register that latches the row address to generate the previous row address; and A row comparison circuit generates the enabled reset signal when the row address and the previous row address have different combinations.

10. The electronic system according to claim 7, wherein: The column control circuit comprises: a column register which: latches the column address to generate the previous column address when the correction enable signal is enabled; and initializes the previous column address when the reset signal is enabled; a column comparison circuit, which: generates an enabled column detection signal when the column address and the previous column address have different combinations; and A comparison signal generating circuit generates the comparison signal based on the column detection signal when the correction enable signal is enabled.

11. The electronic system according to claim 7, wherein: The flag signal generating circuit comprises: a counting circuit which: generates the counting signal of sequential counting when the correction enable signal is enabled and the comparison signal is enabled; and initializes the counting signal when the reset signal is enabled; and The counting signal detection circuit generates the flag signal when the counting signal is counted the set number of times.

12. A semiconductor device comprising: an error correction circuit that: corrects an error of the internal data based on an internal parity and internal data output from a memory cell selected based on a row address and a column address to generate data; and generates a correction enable signal when the error of the internal data is correctable; and A fault detection circuit that: latches the column address, which has a different combination in one combination of the row addresses, each time the correction enable signal is enabled; and generates an enabled flag signal when the column address is latched a set number of times.

13. The semiconductor device according to claim 12, wherein: The fault detection circuit comprises: a row control circuit that: latches the row address to generate a previous row address; and generates an enabled reset signal when the row address and the previous row address input after the previous row address is generated have different combinations; a column control circuit that: latches the column address to generate a previous column address when the correction enable signal is enabled; and generates an enabled comparison signal when the column address input after the previous column address is generated has a different combination from the previous column address; and A flag signal generating circuit is configured to: count a count signal when the correction enable signal is enabled and the comparison signal is enabled; and generate the enabled flag signal when the count signal is counted the set number of times.

14. The semiconductor device according to claim 13, in, When the reset signal is enabled, the column control circuit initializes the front column address, and Wherein, when the reset signal is enabled, the flag signal generating circuit initializes the counting signal.

15. The semiconductor device according to claim 13, wherein: The row control circuit comprises: a row register that latches the row address to generate the previous row address; and A row comparison circuit generates the enabled reset signal when the row address and the previous row address have different combinations.

16. The semiconductor device according to claim 13, wherein: The column control circuit comprises: a column register which: latches the column address to generate the previous column address when the correction enable signal is enabled; and initializes the previous column address when the reset signal is enabled; a column comparison circuit, which: generates an enabled column detection signal when the column address and the previous column address have different combinations; and A comparison signal generating circuit generates the comparison signal based on the column detection signal when the correction enable signal is enabled.

17. The semiconductor device according to claim 13, wherein: The flag signal generating circuit comprises: a counting circuit which: generates the counting signal of sequential counting when the correction enable signal is enabled and the comparison signal is enabled; and initializes the counting signal when the reset signal is enabled; and The counting signal detection circuit generates the flag signal when the counting signal is counted the set number of times.

18. A semiconductor device comprising: an error correction circuit that: corrects an error of the internal data based on an internal parity and internal data output from a memory cell selected based on a row address and a column address to generate data; and generates a correction enable signal when the error of the internal data is correctable; A fault detection circuit that: latches the row address, which has a different combination in one combination of the column addresses, each time the correction enable signal is enabled; and generates an enabled flag signal when the row address is latched a set number of times.

19. The semiconductor device according to claim 18, wherein: The fault detection circuit comprises: a column control circuit that: latches the column address to generate a previous column address; and generates an enabled reset signal when the column address input after the previous column address is generated has a different combination from the previous column address; a row control circuit that: latches the row address to generate a previous row address when the correction enable signal is enabled; and generates an enabled comparison signal when the row address input after the previous row address is generated and the previous row address have different combinations; and A flag signal generating circuit is configured to: count a count signal when the correction enable signal is enabled and the comparison signal is enabled; and generate the enabled flag signal when the count signal is counted the set number of times.

20. The semiconductor device according to claim 19, in, When the reset signal is enabled, the row control circuit initializes the previous row address, and Wherein, when the reset signal is enabled, the flag signal generating circuit initializes the counting signal.

21. The semiconductor device according to claim 19, wherein The column control circuit comprises: a column register that latches the column address to generate the previous column address; and A column comparison circuit generates the enabled reset signal when the column address and the previous column address have different combinations.

22. The semiconductor device according to claim 19, wherein The row control circuit comprises: a row register which: latches the row address to generate the previous row address when the correction enable signal is enabled; and initializes the previous row address when the reset signal is enabled; a column comparison circuit, which: generates an enabled column detection signal when the column address and the previous column address have different combinations; and A comparison signal generating circuit generates the comparison signal based on the column detection signal when the correction enable signal is enabled.

23. The semiconductor device according to claim 19, wherein The flag signal generating circuit comprises: a counting circuit which: generates the counting signal of sequential counting when the correction enable signal is enabled and the comparison signal is enabled; and initializes the counting signal when the reset signal is enabled; and The counting signal detection circuit generates the flag signal when the counting signal is counted the set number of times.

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