Semiconductor memory device with error correction

Abstract

A memory system includes a semiconductor memory device and a memory controller that controls the semiconductor memory device. The semiconductor memory device includes a memory cell array divided into a plurality of sub-array blocks arranged in a first direction and a second direction. The memory controller includes an error correction code (ECC) engine. In a write operation, the ECC engine generates parity data by performing ECC encoding on user data including a plurality of sub-data units, and generates main data by interleaving the sub-data units based on mapping information such that two sub-data units to be stored in a row of a target sub-array block are included in one symbol. The mapping information indicates a mapping relationship between the plurality of sub-data units and a row of a target sub-array block storing the plurality of sub-data units.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0139296, filed on October 18, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of the present disclosure relate to semiconductor memory devices. Background Art

[0004] Semiconductor memory devices can be classified into non-volatile memory devices such as flash memory devices, and volatile memory devices such as dynamic random access memory (DRAM) devices. DRAM devices are often used for system memory due to their high-speed operation and cost effectiveness. Due to the continuous reduction of manufacturing design rules for DRAM devices, bit errors of memory cells in DRAM devices may increase, and the yield of DRAM devices may decrease. Summary of the invention

[0005] Some embodiments according to the present disclosure provide a memory system and a semiconductor memory device capable of performing error correction with reduced complexity.

[0006] According to some embodiments, a memory system includes a semiconductor memory device and a memory controller for controlling the semiconductor memory device. The semiconductor memory device includes a memory cell array, which includes a plurality of memory cells connected to a word line and a bit line, and is divided into a plurality of sub-array blocks arranged in a first direction and a second direction intersecting the first direction. The memory controller includes an error correction code (ECC) engine. In a write operation, the ECC engine generates parity data by performing ECC encoding on user data including a plurality of sub-data units, each of which includes a plurality of data bits, and generates main data by interleaving the plurality of sub-data units based on mapping information, so that two sub-data units in a row of a target sub-array block to be stored in the plurality of sub-array blocks are included in one symbol, and the main data and parity data are sent to the semiconductor memory device. The mapping information indicates a mapping relationship between the plurality of sub-data units and the row of the target sub-array block storing the plurality of sub-data units.

[0007] According to some embodiments, a memory system includes a semiconductor memory device and a memory controller that controls the semiconductor memory device. The semiconductor memory device includes a memory cell array, the memory cell array includes a plurality of memory cells connected to a word line and a bit line, and is divided into a plurality of sub-array blocks arranged in a first direction and a second direction intersecting the first direction. The memory controller includes an error correction code (ECC) engine. In a write operation, the ECC engine generates parity data by performing ECC encoding on user data including a plurality of sub-data units based on a selected ECC selected from a plurality of ECCs according to mapping information, and sends the parity data and main data corresponding to the user data to the semiconductor memory device, each sub-data unit including a plurality of data bits. The mapping information indicates a mapping relationship between a plurality of sub-data units and a row of a target sub-array block storing the plurality of sub-data units. The selected ECC is configured so that two sub-data units in a row of a target sub-array block to be stored in the plurality of sub-array blocks among the plurality of sub-data units are included in one symbol.

[0008] According to some embodiments, a semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, an input / output (I / O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of memory cells connected to word lines and bit lines, and the memory cell array is divided into a plurality of sub-array blocks arranged in a first direction and a second direction intersecting the first direction. The on-die ECC engine generates parity data based on main data including a plurality of sub-data units, each of which includes a plurality of data bits, by using an ECC represented by a generation matrix in a write operation. The I / O gating circuit is coupled between the memory cell array and the on-die ECC engine, and stores the main data and the parity data in the memory cell array. The control logic circuit controls the on-die ECC engine and the I / O gating circuit. The on-die ECC engine generates parity data by performing a first interleaved matrix multiplication on a plurality of sub-data units and a sub-code group of a plurality of code groups based on mapping information so that two sub-data units in a row of a target sub-array block to be stored in the plurality of sub-array blocks among the plurality of sub-data units are included in one symbol. The mapping information indicates a mapping relationship between the plurality of sub-data units and the sub-code groups.

[0009] According to some embodiments, by interleaving a plurality of sub-data units based on mapping information indicating a core structure of a semiconductor memory device, two sub-data units in a row of a target sub-array block to be stored in a plurality of sub-array blocks among the plurality of sub-data units are included in one symbol, when a defect occurs in a sub-word line or a sub-word line driver, an ECC engine in a memory controller can perform symbol ECC decoding to correct an error bit in one symbol. Therefore, the ECC engine can enhance the error correction capability of the symbol ECC and can prevent reliability degradation due to defects in the sub-word line or the sub-word line driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Features of the present disclosure will become more apparent by describing examples of the present disclosure in detail with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a memory system according to some embodiments.

[0012] Figure 2 Main data corresponding to multiple burst lengths is shown according to some embodiments.

[0013] Figure 3A is a block diagram illustrating an example of a memory controller according to some embodiments.

[0014] Figure 3B is a block diagram illustrating an example of an ECC engine according to some implementations.

[0015] Figure 4 is a block diagram illustrating an example of an ECC decoder according to some implementations.

[0016] Figure 5 is a block diagram illustrating an example of a semiconductor memory device according to some embodiments.

[0017] Figure 6 An example of a bank array in a semiconductor memory device according to some embodiments is shown.

[0018] Figure 7 is an example of a table showing mapping information according to some implementations.

[0019] Figure 8 Example operation of an ECC engine according to some implementations is shown.

[0020] Fig. 9 An example of a memory bank array according to some embodiments is shown.

[0021] Fig.10 A portion of a memory bank array is shown in accordance with some embodiments.

[0022] Fig.11 The mapping configuration between the data bits input through the I / O pads and the sub-array blocks storing the data bits during the burst length is shown.

[0023] Fig.12 Shows errors that may occur due to defects.

[0024] Fig.13 An example of a parity generator matrix stored in a memory in an ECC engine is shown.

[0025] Fig.14 An example of a unit sub-matrix is ​​shown.

[0026] Fig.15 An example of an alpha matrix is ​​shown.

[0027] Fig.16 An example of a parity check matrix stored in the memory of an ECC engine is shown.

[0028] Fig.17 is a block diagram illustrating an example of an ECC engine according to some implementations.

[0029] Fig.18 is a block diagram illustrating a memory system according to some embodiments.

[0030] Fig.19 is a block diagram illustrating a semiconductor memory device according to some embodiments.

[0031] Fig. 20 is a block diagram illustrating an example of an on-die ECC engine according to some embodiments.

[0032] Fig.21 is a block diagram illustrating an ECC decoder in an on-die ECC engine according to some embodiments.

[0033] Fig. 22 The relationship of ECC and parity bits used in an on-die ECC engine according to some embodiments is shown.

[0034] Fig.23 An example of ECC according to some embodiments is shown.

[0035] Fig.24 An example of mapping information according to some embodiments is shown.

[0036] Fig.25 is a block diagram illustrating a semiconductor memory device according to some embodiments.

[0037] Fig.26 is a configuration diagram illustrating a semiconductor package including stacked memory devices according to some embodiments.

[0038] Fig. 27 is an example of a computing system that includes a Type 3 memory system.

[0039] Fig.28 is a block diagram illustrating an example of a data center according to some implementations. DETAILED DESCRIPTION

[0040] Examples according to the present disclosure will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0041] Figure 1 is a block diagram illustrating a memory system according to some embodiments.

[0042] refer to Figure 1 , the memory system 20 may include a memory controller 100 (eg, an external memory controller) and a semiconductor memory device 200 .

[0043] The memory controller 100 may control the overall operation of the memory system 20. The memory controller 100 may control the overall data exchange between the external host and the semiconductor memory device 200. For example, in response to a request from the host, the memory controller 100 may write data to the semiconductor memory device 200 or read data from the semiconductor memory device 200.

[0044] In addition, the memory controller 100 may issue an operation command to the semiconductor memory device 200 for controlling the semiconductor memory device 200 .

[0045] In some embodiments, the semiconductor memory device 200 may be a memory device including a plurality of dynamic (volatile) memory cells, such as dynamic random access memory (DRAM), double data rate 5 (DDR5) synchronous DRAM (SDRAM), DDR6 SDRAM, or a stacked memory device such as high bandwidth memory (HBM).

[0046] The memory controller 100 may transmit a command CMD and an address (signal) ADDR to the semiconductor memory device 200, and may exchange main data MD with the semiconductor memory device 200. Although not shown, the memory controller 100 may transmit a clock signal CLK to the semiconductor memory device 200.

[0047] The semiconductor memory device 200 may include a control logic circuit 210 and a memory cell array 310 .

[0048] The memory controller 100 may include a central processing unit (CPU) 110 and an error correction code (ECC) engine 120 .

[0049] The CPU 110 may control the overall operation of the memory controller 100 .

[0050] In a write operation, the ECC engine 120 may generate parity data PRT1 by performing ECC encoding on user data including a plurality of sub-data units, each of which includes a plurality of data bits, and may generate main data MD by interleaving the plurality of sub-data units based on mapping information MPI so that two sub-data units in a row of a target sub-array block in a memory cell array 310 to be stored in the plurality of sub-array blocks among the plurality of sub-data units are included in one symbol, and the main data and parity data may be transmitted to the semiconductor memory device 200. The mapping information MPI may indicate a mapping relationship between the plurality of sub-data units and a row of a target sub-array block storing the plurality of sub-data units.

[0051] In a read operation, the ECC engine 120 may receive main data MD and parity data PRT1 from the semiconductor memory device 200, may generate intermediate main data by deinterleaving the main data based on mapping information MPI, and may correct at least one error in the intermediate main data on a per-symbol basis by performing ECC decoding on the intermediate main data using the parity data PRT1.

[0052] The memory cell array 310 may store main data MD and parity data PRT1. The memory cell array 310 may be divided into a plurality of sub-array blocks arranged in a first direction and a second direction crossing the first direction.

[0053] The control logic circuit 210 may control access to the memory cell array 310 based on a command CMD and an address ADDR.

[0054] The semiconductor memory device 200 may perform a burst operation. Here, a burst operation may refer to an operation of writing or reading a large amount of data by sequentially increasing or decreasing an initial address provided from the memory controller 100. A basic unit of a burst operation may be referred to as a burst length BL. In some embodiments, the burst length BL refers to the number of operations of continuously reading or writing data by sequentially increasing or decreasing an initial address.

[0055] Each of the plurality of sub data units may correspond to a burst length BL, and the burst length BL may indicate an amount of data input / output at one time between the memory controller 100 and the semiconductor memory device 200 .

[0056] The semiconductor memory device 200 may provide mapping information MPI to the memory controller 100 .

[0057] Figure 2 According to some embodiments, Figure 1 The memory system includes main data corresponding to multiple burst lengths.

[0058] refer to Figure 2 , main data MD corresponding to a plurality of burst lengths is input to / output from the semiconductor memory device 200. The main data MD includes data segments MD_SG1-MD_SGt (t is a natural number equal to or greater than 8), each data segment corresponding to each of the plurality of burst lengths. Figure 2 , the burst length is assumed to be 8. Each of the data segments MD_SG1-MD_SGt may include data bits input / output through the input / output pads DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DQ7. Main data MD corresponding to a plurality of burst lengths may be stored in the memory cell array 310 of the semiconductor memory device 200.

[0059] Figure 3A FIG. 2 is a diagram showing a memory controller (eg, Figure 1 A block diagram of an example of a memory controller).

[0060] refer to Figure 3A , the memory controller 100 may include a CPU 110, an ECC engine 120a, a command CMD buffer 180, and an address buffer 190. The ECC engine 120a may include a data interleaver 125, an ECC encoder 130, a buffer 135, a memory 140, a data deinterleaver 150, and an ECC decoder 160.

[0061] The CPU 110 may receive a request REQ and user data DTA from the host, and may provide the user data DTA to the data interleaver 125 and the ECC encoder 130 .

[0062] The data interleaver 125 can generate main data MD11 by interleaving multiple sub-data units based on mapping information MPI, so that two sub-data units in a row of a target sub-array block in a memory cell array 310 to be stored in multiple sub-array blocks among the multiple sub-data units are included in one symbol, and the main data MD11 can be stored in the buffer 135.

[0063] The ECC encoder 130 may generate parity data PRT1 by performing ECC encoding on the user data DTA using the parity generation matrix PGM stored in the memory 140 , and may store the parity data PRT1 in the buffer 135 .

[0064] The buffer 135 may provide the main data MD11 and the parity data PRT1 as a codeword CW11 to the semiconductor memory device 200 , may receive mapping information MPI from the semiconductor memory device 200 during a power-on sequence, and may provide the mapping information MPI to the data interleaver 125 and the data deinterleaver 150 .

[0065] The data deinterleaver 150 may receive a codeword CW12 including main data MD12 and parity data PRT1 from the semiconductor memory device 200 in a read operation, may generate intermediate main data DRMD by deinterleaving the main data MD12 based on mapping information MPI, and may provide the intermediate main data DRMD and parity data PRT1 to the ECC decoder 160.

[0066] The ECC decoder 160 may correct at least one error in the intermediate main data DRMD on a per symbol basis by performing ECC decoding on the intermediate main data DRMD using the parity data PRT1 and the parity check matrix PCM stored in the memory 140 , and may provide the CPU 110 with corrected main data C_MD12 .

[0067] The command buffer 180 may store a command CMD corresponding to the request REQ and may transmit the command CMD to the semiconductor memory device 200 under the control of the CPU 110. The address buffer 190 may store an address ADDR and may transmit the address ADDR to the semiconductor memory device 200 under the control of the CPU 110.

[0068] Figure 3B is a diagram showing an ECC engine (e.g., Figure 3A A block diagram of an example of an ECC engine in a memory controller.

[0069] refer to Figure 3B , the ECC engine 120a_1 may include an ECC encoder 130a, a buffer 135a, a memory 140a, and an ECC decoder 155a.

[0070] The ECC encoder 130a may include encoding logic 131 and a data interleaver 133. The ECC decoder 155a may include a data deinterleaver 157 and decoding logic 159.

[0071] The buffer 135 a may receive the mapping information MPI from the semiconductor memory device 200 or the CPU 110 during a power-on sequence and may provide the mapping information MPI to the data interleaver 133 and the data deinterleaver 157 .

[0072] The memory 140a may store a parity check generation matrix PGM and a parity check matrix PCM.

[0073] In a write operation, the encoding logic may generate parity data PRT1 by performing ECC encoding on the user data DTA using the parity generation matrix PGM stored in the memory 140 a , and may provide the user data DTA and the parity data PRT1 to the data interleaver 133 .

[0074] The data interleaver 125 can generate main data MD11a by interleaving multiple sub-data units based on mapping information MPI, so that two sub-data units in a row of a target sub-array block in a memory cell array 310 in multiple sub-array blocks, among the multiple sub-data units, are included in one symbol, can generate interleaved parity data PRT1a by interleaving parity data PRT1 based on mapping information MPI, and can send an interleaved codeword CW11a including the main data MD11a and the interleaved parity data PRT1a to the semiconductor memory device 200.

[0075] The operations of the encoding logic 131 and the data interleaver 133 may correspond to the operations of the ECC encoder 130a.

[0076] In a read operation, the data deinterleaver 157 may receive an interleaved codeword CW12a including main data MD12a and interleaved parity data PRT1a from the semiconductor memory device 200, may generate intermediate main data DRMDa and parity data PRT1 by deinterleaving the main data MD12a and the interleaved parity data PRT1a respectively based on the mapping information MPI, and may provide the intermediate main data DRMDa and parity data PRT1 to the decoding logic 159.

[0077] The decoding logic 159 may correct at least one error in the intermediate main data DRMDa on a per-symbol basis by performing ECC decoding on the intermediate main data DRMDa using the parity data PRT1 and the parity check matrix PCM stored in the memory 140a, and may provide the corrected main data C_MD12 to the CPU 110.

[0078] The operations of data deinterleaver 157 and decoding logic 159 may correspond to the operations of ECC decoder 155a.

[0079] Figure 4 FIG. 2 is a diagram showing an ECC decoder (eg, Figure 3A A block diagram of an example of an ECC decoder in FIG.

[0080] refer to Figure 4 The ECC decoder 160 may include a check bit generator 161 , a syndrome generator 163 , and a data corrector 165 .

[0081] The check bit generator 161 may receive the intermediate main data DRMD and may generate the check bits CHB1 corresponding to the intermediate main data DRMD using the parity check matrix PCM.

[0082] The syndrome generator 163 may compare the parity data PRT1 and the check bit CHB1 on a symbol-by-symbol basis to generate syndrome data SDR1 indicating whether the intermediate main data DRMD includes at least one error bit and indicating a position of the at least one error bit.

[0083] The data corrector 165 may receive the main data MD12 and may correct error bits in the main data MD12 on a symbol-by-symbol basis based on the syndrome data SDR1 to output corrected main data C_MD12.

[0084] Figure 5 FIG. 2 is a diagram showing a semiconductor memory device (eg, Figure 1 A block diagram of a semiconductor memory device in FIG.

[0085] refer to Figure 5 , the semiconductor memory device 200 may include a control logic circuit 210, an address register 220, a memory body control logic 230, a row address RA multiplexer 240, a column address CA latch 250, a row decoder 260, a column decoder 270, a memory cell array 310, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, a data input / output (I / O) buffer 295 and a refresh counter 245.

[0086] The memory cell array 310 may include first to sixteenth memory bank arrays 310a-310p. The row decoder 260 may include first to sixteenth row decoders 260a-260p coupled to the first to sixteenth memory bank arrays 310a-310p, respectively. The column decoder 270 may include first to sixteenth column decoders 270a-270p coupled to the first to sixteenth memory bank arrays 310a-310p, respectively. The sense amplifier unit 285 may include first to sixteenth sense amplifiers 285a-285p coupled to the first to sixteenth memory bank arrays 310a-310p, respectively. The first to sixteenth memory bank arrays 310a-310p, the first to sixteenth row decoders 260a-260p, the first to sixteenth column decoders 270a-270p, and the first to sixteenth sense amplifiers 285a-285p may form the first to sixteenth memory banks. Furthermore, each of the first to sixteenth memory bank arrays 310 a - 310 p may be divided into a plurality of sub-array blocks arranged in the first direction and the second direction.

[0087] Each of the first to sixteenth memory bank arrays 310 a - 310 p may include a plurality of memory cells MC coupled to word lines WL and bit lines BTL.

[0088] Although the semiconductor memory device 200 is Figure 5 2 is shown as including 16 memory banks, but the present disclosure is not limited thereto, and the semiconductor memory device 200 may include any number of memory banks.

[0089] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100 .

[0090] The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230 , may provide the received row address ROW_ADDR to the row address multiplexer 240 , and may provide the received column address COL_ADDR to the column address latch 250 .

[0091] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. One of the first to sixteenth row decoders 260a-260p corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal, and one of the first to sixteenth column decoders 270a-270p corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal.

[0092] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and may receive the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output one of the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to sixteenth row decoders 260a-260p.

[0093] The activated one of the first to sixteenth row decoders 260a-260p may decode the row address RA output from the row address multiplexer 240 and may activate a word line corresponding to the row address RA. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address RA.

[0094] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In some embodiments, in the burst mode, the column address latch 250 may generate a column address COL_ADDR' incremented from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored column address COL_ADDR or the generated column address COL_ADDR' to the first to sixteenth column decoders 270a-270p.

[0095] The activated one of the first to sixteenth column decoders 270 a - 270 p may decode the column address COL_ADDR or COL_ADDR′ output from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR or COL_ADDR′.

[0096] The I / O gating circuit 290 may include a circuit for gating input / output data. The I / O gating circuit 290 may also include a read data latch for storing data output from the first to sixteenth memory bank arrays 310a-310p, and a write driver for writing data to the first to sixteenth memory bank arrays 310a-310p.

[0097] The main data MD and parity data PRT1 to be read from one of the first to sixteenth memory bank arrays 310a-310p can be read by a sense amplifier coupled to one of the memory bank arrays from which the codeword is to be read, and can be stored in the read data latch. The main data MD and parity data PRT1 stored in the read data latch can be provided to the memory controller 100 via the data I / O buffer 295.

[0098] The main data MD and the parity data PRT1 to be written into one of the first to sixteenth memory bank arrays 310a-310p may be provided to the data I / O buffer 295 from the memory controller 100. The data I / O buffer 295 may provide the main data MD and the parity data PRT1 to the I / O gating circuit 290. The I / O gating circuit 290 may store the main data MD and the parity data PRT1 in a target storage area of ​​the memory cell array 310 based on the control signal CTL11 from the control logic circuit 210.

[0099] The control logic circuit 210 may control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 may generate a control signal for the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 100, and a mode register 212 that sets an operation mode of the semiconductor memory device 200.

[0100] For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 210 may generate a control signal CTL11 .

[0101] The mapping information MPI may be set in the mode register 212 , and the control logic circuit 210 may provide the mapping information MPI to the memory controller 100 during a power-on sequence of the semiconductor memory device 200 .

[0102] Figure 6 An example of a memory bank array according to some embodiments is shown, for example Figure 5 A first memory bank array in a semiconductor memory device.

[0103] refer to Figure 6 , the first memory bank array 310a may include a plurality of word lines WL0-WLm-1 (m is a natural number greater than two), a plurality of bit lines BTL0-BTLn-1 (n is a natural number greater than two), and a plurality of memory cells MC disposed at intersections between the word lines WL0-WLm-1 and the bit lines BTL0-BTLn-1. Each memory cell MC may include a cell transistor coupled to each word line WL0-WLm-1 and each bit line BTL0-BTLn-1 and a cell capacitor coupled to the cell transistor. Each memory cell MC may have a DRAM cell structure. Each word line WL0-WLm-1 extends in a first direction D1, and each bit line BTL0-BTLn-1 extends in a second direction D2 intersecting the first direction D1.

[0104] The word lines WL0 -WLm-1 coupled to the plurality of memory cells MCs may be referred to as rows of the first bank array 310 a , and the bit lines BTL0 -BTLn-1 coupled to the plurality of memory cells MCs may be referred to as columns of the first bank array 310 a .

[0105] Figure 7 is an example of a table showing mapping information according to some implementations.

[0106] refer to Figure 7 , the mapping information MPIa may indicate a mapping relationship between data bits (i.e., sub-data units) input / output at one time through the data pads DQ0-DQ7 corresponding to the burst length BL and word lines WL (i.e., rows or sub-word lines of the target sub-array block storing the data bits). Data bits (i.e., sub-data units) input / output at one time through the data pads DQ0-DQ7 corresponding to the burst length BL may be referred to as sub-data units.

[0107] Data bits corresponding to burst length BL0 and data bits corresponding to burst length BL4 can be stored in memory cells in a sub-array block (first sub-array block) coupled to word line WL0, data bits corresponding to burst length BL1 and data bits corresponding to burst length BL5 can be stored in memory cells in the first sub-array block coupled to word line WL1, data bits corresponding to burst length BL2 and data bits corresponding to burst length BL6 can be stored in memory cells in the first sub-array block coupled to word line WL2, and data bits corresponding to burst length BL3 and data bits corresponding to burst length BL7 can be stored in memory cells in the first sub-array block coupled to word line WL3.

[0108] Figure 8 An ECC engine (e.g., Figure 3A Example operation of the ECC engine in .

[0109] refer to Figure 3A and Figure 8 , the user data DTA may include a plurality of sub-data units SDU0, SDU1, SDU2, SDU3, SDU4, SDU5, SDU6, and SDU7, and each of the plurality of sub-data units SDU0, SDU1, SDU2, SDU3, SDU4, SDU5, SDU6, and SDU7 may include a plurality of data bits. In addition, each of the plurality of sub-data units SDU0, SDU1, SDU2, SDU3, SDU4, SDU5, SDU6, and SDU7 may correspond to Figure 7The burst lengths in BL0, BL1, BL2, BL3, BL5, BL6, and the corresponding burst lengths in BL7.

[0110] The two sub-data units SDU0 and SDU1 may correspond to the symbol SB11, the two sub-data units SDU2 and SDU3 may correspond to the symbol SB12, the two sub-data units SDU4 and SDU5 may correspond to the symbol SB13, and the two sub-data units SDU6 and SDU7 may correspond to the symbol SB14.

[0111] In a write operation, Figure 3A The data interleaver 125 in the user data DTA may generate the main data MD11 by interleaving a plurality of sub-data units SDU0, SDU1, SDU2, SDU3, SDU4, SDU5, SDU6, and SDU7 in the user data DTA based on the mapping information MPI so that two sub-data units in a row (i.e., memory cells coupled to one word line) of a target sub-array block to be stored in the memory cell array 310 are included in one symbol. The sub-data units SDU0 and SDU1 may be sequentially stored in a memory cell row (memory cell) coupled to the word line WL0, the sub-data units SDU2 and SDU3 may be sequentially stored in a memory cell row (memory cell) coupled to the word line WL1, the sub-data units SDU4 and SDU5 may be sequentially stored in a memory cell row (memory cell) coupled to the word line WL2, and the sub-data units SDU6 and SDU7 may be sequentially stored in a memory cell row (memory cell) coupled to the word line WL3.

[0112] Two sub data units constituting one symbol (eg, two sub data units SDU0 and SDU1) may be stored in a memory cell coupled to a first word line WL1 driven by one sub word line driver.

[0113] Figure 8 Assume that a defect (error) occurs in a memory cell coupled to the word line WL0. Therefore, data bits of the sub-data units SDU0 and SDU1 may include error bits.

[0114] Figure 3A The data deinterleaver 150 can receive the main data MD12 including multiple sub-data units SDU0, SDU2, SDU4, SDU6, SDU1, SDU3, SDU5 and SDU7 in a read operation, and can generate intermediate main data DRMD corresponding to the user data DTA by deinterleaving the multiple sub-data units SDU0, SDU2, SDU4, SDU6, SDU1, SDU3, SDU5 and SDU7 based on the mapping information MPI, and the intermediate main data DRMD can be provided to the ECC decoder 160.

[0115] The ECC decoder 160 may correct errors in the intermediate main data DRMD (eg, error bits in the sub-data units SDU0 and SDU1 ) on a per-symbol basis by performing ECC decoding on the intermediate main data DRMD based on the parity data PRT1 , and may provide corrected main data C_MD12 .

[0116] Fig. 9 A memory bank array (eg, Figure 6 An example of a first storage array).

[0117] refer to Fig. 9 In the first memory bank array 310a, I sub-array blocks SCB may be arranged in a first direction D1, and J sub-array blocks SCB may be arranged in a second direction D2 perpendicular to the first direction D1. I and J represent the number of sub-array blocks SCB in the first direction D1 and the second direction D2, respectively, and are natural numbers greater than 2.

[0118] I sub-array blocks SCB arranged in a first direction D1 in one row may be referred to as a row block. A plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the bit lines and the word lines are arranged in each sub-array block SCB.

[0119] I+1 sub-word line driver regions SWB may be arranged between the sub-array blocks SCB in the first direction D1 and on each side of each sub-array block SCB in the first direction D1. The sub-word line drivers may be arranged in the sub-word line driver regions SWB. J+1 bit line sense amplifier regions BLSAB may be arranged, for example, between the sub-array blocks SCB in the second direction D2 and above and below each sub-array block SCB in the second direction D2. A bit line sense amplifier that senses data stored in a memory cell may be arranged in the bit line sense amplifier region BLSAB.

[0120] A plurality of sub word line drivers may be provided in each sub word line driver region SWB. One sub word line driver region SWB may be associated with two sub array blocks SCB adjacent to the sub word line driver region SWB in the first direction D1.

[0121] A plurality of connection regions CONJ may be disposed adjacent to the sub word line driver region SWB and the bit line sense amplifier region BLSAB. A voltage generator may be disposed in each connection region CONJ.

[0122] The following will refer to Fig.10 A portion 390 in the first memory bank array 310a is depicted.

[0123] Fig.10 According to some embodiments, Fig. 9 A portion of a first memory bank array.

[0124] refer to Fig. 9 and Fig.10 In the portion 390 of the first memory bank array 310a, sub-array blocks SCBa and SCBb, a bit line sense amplifier region BLSAB, four sub-word line driver regions SWBa1, SWBa2, SWBb1 and SWBb2, and two connection regions CONJ are arranged.

[0125] The sub-array block SCBa may include a plurality of word lines WL0-WL3 extending in a first direction D1 and a plurality of bit lines BTL0-BTL3 extending in a second direction D2. The sub-array block SCBa may include a plurality of memory cells MC disposed at intersections of the word lines WL0-WL3 and the bit lines BTL0-BTL3. The sub-array block SCBb may include a plurality of word lines WL4-WL7 extending in a first direction D1 and a plurality of bit lines BTL0-BTL3 extending in a second direction D2. The sub-array block SCBb may include a plurality of memory cells MC disposed at intersections of the word lines WL4-WL7 and the bit lines BTL0-BTL3.

[0126] refer to Fig.10 , the sub-word line driver regions SWBa1 and SWBa2 may include a plurality of sub-word line drivers 631, 632, 633, and 634 that respectively drive the word lines WL0-WL3. The sub-word line driver regions SWBb1 and SWBb2 may include a plurality of sub-word line drivers 641, 642, 643, and 644 that respectively drive the word lines WL4-WL7.

[0127] The bit line sense amplifier region BLSAB may include a bit line sense amplifier BLSA 650 coupled to the bit line BTL0 in the sub-array block SCBb and the bit line BTL1 in the sub-array block SCBa, and a local sense amplifier LSA circuit 680. The bit line sense amplifier 650 may sense and amplify a voltage difference between the bit lines BTL0 and BTL1 to provide the amplified voltage difference to the local I / O line pair LIO1 and LIOB1.

[0128] The local sense amplifier circuit 680 may control electrical connections between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIOB1.

[0129] like Fig.10As shown, a connection region CONJ may be disposed adjacent to the bit line sense amplifier region BLSAB and the sub word line driver regions SWBa1, SWBb1, SWBa2, and SWBb2. Voltage generators 610 and 620 may be disposed in the connection region CONJ.

[0130] Fig.11 The mapping configuration between the data bits input through the I / O pads and the sub-array blocks storing the data bits during the burst length is shown.

[0131] Fig.11 A mapping configuration MAPC between data bits input through I / O pads DQ0-DQ7 during burst lengths BL0-BL7 and sub-array blocks storing the data bits is shown.

[0132] refer to Fig.11 ,Note that the data bits input through I / O pads DQ0-DQ7 during burst length BL0-BL7 are stored in the sub-array block.

[0133] exist Fig.11 , reference numeral 511 denotes a defect of a sub-word line driver associated with two sub-array blocks.

[0134] Fig.12 It shows that it may be due to Fig.11 Errors caused by defects in the

[0135] refer to Fig.12 , due to the defect 511 of the sub word line driver, errors may occur in data bits corresponding to the burst lengths BL0 and BL4 and the I / O pads DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DQ7.

[0136] Fig.13 The parity check generator matrix is ​​shown. For example, the parity check generator matrix can be stored in Figure 3A The ECC engine in the memory.

[0137] refer to Fig.13 , the parity-check generator matrix PGM may include a first parity-check submatrix HS 11 and the second parity check submatrix HS 12 .

[0138] The first parity check submatrix HS 11 The plurality of unit sub-matrices ISM include k (k is a natural number greater than one) symbols in one codeword. Each of the plurality of unit sub-matrices ISM includes p×p elements (p is a natural number greater than one).

[0139] The second parity check sub-matrix HS 12A plurality of alpha matrices α corresponding to k symbols in a codeword are included i0 , α i1 ,……,α i(k-2) , α i(k-1) . Alpha matrix α i0 It can be obtained based on the p-order primitive polynomial. Alpha matrix α i1 The α matrix α i0 It is obtained by raising it to the power of , and the elements of the alpha matrix can be generated based on the Reed-Solomon (RS) code.

[0140] Fig.14 Shows Fig.13 Example of the identity submatrix in the parity generator matrix in .

[0141] refer to Fig.14 , the identity submatrix ISM includes p high-order elements arranged in a diagonal direction. Each of the other elements except the high-order element has zero.

[0142] Fig.15 Shows Fig.13 Example of the alpha matrix in the parity generator matrix.

[0143] refer to Fig.15 , alpha matrix α i(k-1) This can be done by shifting the alpha matrix α in the right-hand direction i(k-2) To obtain.

[0144] exist Fig.14 and Fig.15 , p corresponds to 16, and corresponds to a plurality of data bits in one symbol including two sub-data units.

[0145] Fig.16 An example of a parity check matrix is ​​shown. For example, the parity check matrix can be stored in Figure 3A The ECC engine in the memory.

[0146] refer to Fig.16 , the parity check matrix PCM may include a first parity check submatrix HS 21 and the second parity check submatrix HS 22 .

[0147] The first parity check submatrix HS 21 The plurality of identity submatrices ISM include a plurality of identity submatrices ISM corresponding to k symbols in one codeword and an identity submatrix ISM corresponding to parity check data. Each of the plurality of identity submatrices ISM includes p×p elements.

[0148] The second parity check sub-matrix HS 22A plurality of alpha matrices α corresponding to k symbols in a codeword are included i0 , α i1 ,……,α i(k-2) and α i(k-1) , and the alpha matrix α corresponding to the parity data 0 (=ISM).

[0149] Fig.17 is a diagram showing an ECC engine (e.g., Figure 1 A block diagram of an example of an ECC engine in FIG.

[0150] refer to Fig.17 , the ECC engine 120 b may include an ECC encoder 125 b , an ECC decoder 160 b , a memory 170 , and a buffer 175 .

[0151] The memory 170 may be connected to the ECC encoder 125b and the ECC decoder 160b and may store a plurality of ECC EEC1-ECCq. Here, q is an integer greater than one. The memory 170 may provide the selected ECC selected from the plurality of ECC EEC1-ECCq to the ECC encoder 125b and the ECC decoder 160b in response to the mapping information MPI.

[0152] Buffer 175 can be used during the power-up sequence from Figure 1 The semiconductor memory device 200 or Figure 1 The CPU 110 in the memory 170 receives the mapping information MPI, may store the mapping information MPI, and may provide the mapping information MPI to the memory 170 in a write operation and a read operation.

[0153] In a write operation, the ECC encoder 125b can generate parity data PRT2 by performing ECC encoding on user data DTA including multiple sub-data units based on the selected ECC, each sub-data unit including multiple data bits, and can send a codeword CW21 including the parity data PRT2 and main data MD21 corresponding to the user data DTA to the semiconductor memory device 200.

[0154] In a read operation, the ECC decoder 160b can receive a codeword CW22 including main data MD22 and parity data PRT2 from the semiconductor memory device 200, and can correct at least one error in the main data MD22 on a per-symbol basis by performing ECC decoding on the main data MD22 using the parity data PRT2 and the selected ECC, and can output the corrected main data C_MD22.

[0155] The mapping information MPI may indicate a mapping relationship between a plurality of sub-data units and rows (sub-word lines) of a target sub-array block storing the plurality of sub-data units.

[0156] The selected ECC may be configured such that two sub-data units in one row of a target sub-array block to be stored in the plurality of sub-array blocks among the plurality of sub-data units are included in one symbol.

[0157] Because the ECC engine 120b performs ECC encoding and the ECC decoder 160b performs ECC decoding using the selected ECC, which is selected based on the mapping information MPI indicating a mapping relationship between a plurality of sub-data units and rows of a target sub-array block storing the plurality of sub-data units, the ECC engine 120b can correct an error in one symbol including two sub-data units on a per-symbol basis from among the plurality of sub-data units.

[0158] Fig.18 is a block diagram illustrating a memory system according to some embodiments.

[0159] refer to Fig.18 , the memory system 20a may include a memory controller 100a (eg, an external memory controller) and a semiconductor memory device 200a.

[0160] The memory controller 100a may control the overall operation of the memory system 20a. The memory controller 100a may control the overall data exchange between the external host and the semiconductor memory device 200a. For example, in response to a request from the host, the memory controller 100a may write data in the semiconductor memory device 200a or read data from the semiconductor memory device 200a.

[0161] In addition, the memory controller 100 a may issue an operation command to the semiconductor memory device 200 a for controlling the semiconductor memory device 200 a .

[0162] In some embodiments, the semiconductor memory device 200a is a memory device including a plurality of dynamic (volatile) memory cells, such as DRAM, DDR5 SDRAM, DDR6 SDRAM, or a stacked memory device such as HBM.

[0163] The memory controller 100 a may transmit a clock signal CLK, a command CMD, and an address (signal) ADDR to the semiconductor memory device 200 a , and exchange main data MD3 with the semiconductor memory device 200 a .

[0164] The memory controller 100 a may include a CPU 110 that controls overall operations of the memory controller 100 a .

[0165] Semiconductor memory device 200a may include memory cell array 310 storing main data MD, on-die ECC engine 400, and control logic circuit 210a. Memory cell array 310 may be divided into a plurality of sub-array blocks arranged in a first direction and a second direction crossing the first direction.

[0166] The on-die ECC engine 400 may generate parity data by performing ECC encoding on main data MD including a plurality of sub-data units (each of which includes a plurality of data bits), using an ECC represented by a generator matrix, and may generate parity data by performing a first interleaving matrix multiplication on the plurality of sub-data units and a sub-code group of the plurality of code groups based on mapping information (i.e., by performing index interleaving), so that two sub-data units in a row of a target sub-array block to be stored in the plurality of sub-array blocks among the plurality of sub-data units are included in one symbol. The mapping information may indicate a mapping relationship between the plurality of sub-data units and a row of the target sub-array block storing the plurality of sub-data units.

[0167] Fig.19 is a diagram showing that according to some embodiments Fig.18 Block diagram of a semiconductor memory device in FIG.

[0168] refer to Fig.19 , the semiconductor memory device 200a may include a control logic circuit 210a, an address register 220, a memory body control logic 230, a row address RA multiplexer 240, a column address CA latch 250, a row decoder 260, a column decoder 270, a memory cell array 310, a sense amplifier unit 285, an I / O gating circuit 290a, a data I / O buffer 295a, an on-die ECC engine 400 and a refresh counter 245.

[0169] The memory cell array 310 may include first to sixteenth memory bank arrays 310a-310p. The row decoder 260 may include first to sixteenth row decoders 260a-260p coupled to the first to sixteenth memory bank arrays 310a-310p, respectively. The column decoder 270 may include first to sixteenth column decoders 270a-270p coupled to the first to sixteenth memory bank arrays 310a-310p, respectively. The sense amplifier unit 285 may include first to sixteenth sense amplifiers 285a-285p coupled to the first to sixteenth memory bank arrays 310a-310p, respectively. The first to sixteenth memory bank arrays 310a-310p, the first to sixteenth row decoders 260a-260p, the first to sixteenth column decoders 270a-270p, and the first to sixteenth sense amplifiers 285a-285p may form the first to sixteenth memory banks. Furthermore, each of the first to sixteenth memory bank arrays 310 a - 310 p may be divided into a plurality of sub-array blocks arranged in the first direction and the second direction.

[0170] Each of the first to sixteenth memory bank arrays 310a-310p may include a plurality of memory cells MC coupled to word lines WL and bit lines BTL. Each of the plurality of memory cells MC may have a DRAM cell configuration.

[0171] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100 a .

[0172] The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230 , may provide the received row address ROW_ADDR to the row address multiplexer 240 , and may provide the received column address COL_ADDR to the column address latch 250 .

[0173] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. One of the first to sixteenth row decoders 260a-260p corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal, and one of the first to sixteenth column decoders 270a-270p corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal.

[0174] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and may receive the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output one of the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to sixteenth row decoders 260a-260p.

[0175] The activated one of the first to sixteenth row decoders 260a-260p may decode the row address RA output from the row address multiplexer 240 and may activate a word line corresponding to the row address RA. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address RA.

[0176] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In some embodiments, in the burst mode, the column address latch 250 may generate a column address COL_ADDR' incremented from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored column address COL_ADDR or the generated column address COL_ADDR' to the first to sixteenth column decoders 270a-270p.

[0177] The activated one of the first to sixteenth column decoders 270 a - 270 p may decode the column address COL_ADDR or COL_ADDR′ output from the column address latch 250 and may control the I / O gating circuit 290 a to output data corresponding to the column address COL_ADDR or COL_ADDR′.

[0178] The I / O gating circuit 290a may include a circuit for gating input / output data. The I / O gating circuit 290a may also include a read data latch for storing data output from the first to sixteenth memory bank arrays 310a-310p, and a write driver for writing data to the first to sixteenth memory bank arrays 310a-310p.

[0179] The codeword CW3 to be read from one of the first to sixteenth memory bank arrays 310a-310p can be sensed by a sense amplifier coupled to the one memory bank array from which the codeword is to be read and can be stored in the read data latch. The codeword CW3 stored in the read data latch is ECC decoded by the on-die ECC engine 400 and can be provided to the memory controller 100a via the data I / O buffer 295a.

[0180] The main data MD3 to be written into one of the first to sixteenth memory bank arrays 310a-310p may be provided from the memory controller 100a to the data I / O buffer 295a. The main data MD3 is provided to the on-die ECC engine 400.

[0181] The on-die ECC engine 400 may perform ECC encoding on the main data MD3 to generate parity data, and provide a codeword CW3 including the main data MD3 and the parity data to the I / O gating circuit 290a. The I / O gating circuit 290a may store the main data MD3 and the parity data in a target sub-array block in the memory cell array 310 based on a control signal CTL21 from the control logic circuit 210a.

[0182] The on-die ECC engine 400 may perform ECC decoding on the main data MD3 using the parity data read from the memory cell array 310 .

[0183] The on-die ECC engine 400 can perform ECC encoding and ECC decoding by performing index interleaving on multiple sub-data units and multiple sub-code groups of multiple code groups in the ECC based on the mapping information MPI, so that two sub-data units in a row of a target sub-array block to be stored in the multiple sub-array blocks among the multiple sub-data units are included in one symbol.

[0184] The control logic circuit 210a may control the operation of the semiconductor memory device 200a. For example, the control logic circuit 210a may generate a control signal for the semiconductor memory device 200a to perform a write operation or a read operation. The control logic circuit 210a may include a command decoder 211 that decodes a command CMD received from the memory controller 100a, and a mode register 212 that sets an operation mode of the semiconductor memory device 200a.

[0185] For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 210 a may generate a first control signal CTL21 for controlling the I / O gating circuit 290 a and a second control signal CTL22 for controlling the on-die ECC engine 400 .

[0186] The mapping information MPI may be set in the mode register 212 by the memory controller 100 a , and the control logic circuit 210 a may provide the mapping information MPI to the on-die ECC engine 400 during a power-on sequence of the semiconductor memory device 200 a .

[0187] Fig. 20FIG. 2 is a diagram showing an on-die ECC engine (eg, Fig.19 Block diagram of an example of an on-die ECC engine in a semiconductor memory device.

[0188] refer to Fig. 20 , the on-die ECC engine 400 may include an ECC memory 410 , an ECC encoder 430 , and an ECC decoder 450 .

[0189] The ECC memory 410 stores the ECC 415. The ECC 415 may be represented by a generator matrix (eg, the data format / structure of the ECC 415 may be the generator matrix), and may include a plurality of column vectors corresponding to data bits in the main data (eg, MD3) and the parity data.

[0190] The ECC encoder 430 may be connected to the memory 410 and may perform ECC encoding on the main data MD3 using the ECC 415 stored in the memory 410 to generate the parity data PRT3 in a write operation of the semiconductor memory device 200a. The ECC encoder 430 may provide a codeword CW3 including the main data MD3 and the parity data PRT3 to the I / O gating circuit 290a.

[0191] The ECC decoder 450 may be connected to the memory 410, may receive a codeword CW3 including the main data MD3 and the parity data PRT3, may perform ECC decoding on the main data MD3 based on the parity data PRT3 using the ECC 415 to correct and / or detect an error bit in the main data MD3, and may output the corrected main data C_MD3. The ECC 415 may be a Reed-Solomon (RS) code that corrects an error bit in one symbol of the main data MD3.

[0192] When the ECC encoder 430 and the ECC decoder 450 perform ECC encoding and ECC decoding, respectively, the ECC encoder 430 and the ECC decoder 450 may perform interleaving matrix multiplication on a plurality of sub-data units and a sub-code group in a plurality of code groups in the ECC 415 based on the mapping information MPI. The ECC encoder 430 may generate parity data PRT3 by performing a first interleaving matrix multiplication on a plurality of sub-data units and sub-code groups based on the mapping information MPI. The ECC decoder 450 may generate check bits by performing a second interleaving matrix multiplication on a plurality of sub-data units and sub-code groups based on the mapping information MPI.

[0193] Although reference Fig. 20The memory 410 is described as being coupled to the ECC encoder 430 and the ECC decoder 450 , but in some implementations, the memory 410 may be implemented with XOR gates within the ECC encoder 430 and the ECC decoder 450 .

[0194] Fig.21 FIG. 2 is a diagram showing an ECC decoder (eg, Fig. 20 Block diagram of an ECC decoder in an on-die ECC engine.

[0195] refer to Fig.21 , the ECC decoder 450 may include a check bit generator 451 , a syndrome generator 453 , and a data corrector 455 .

[0196] The check bit generator 451 can generate the check bit CHB3 based on the data bits in the main data MD3 using the ECC 415 and the mapping information MPI. The syndrome generator 453 can generate syndrome data SDR3 indicating whether an error bit occurs and the position of the error bit based on the comparison of the check bit CHB3 and the parity bit of the parity data PRT3.

[0197] The data corrector 455 may receive the main data MD3 and the syndrome data SDR3, may correct error bits in the main data MD3, and may output corrected main data C_MD3.

[0198] Fig. 22 According to some embodiments, Fig. 20 The relationship between the ECC and parity bits used in the on-die ECC engine.

[0199] exist Fig. 22 In FIG. 1 , it is assumed that the main data MD3 includes a plurality of sub-data units SDU0-SDU2x-1, and the parity data PRT3 includes 8 parity bits PB1-PB8. Fig. 22 In FIG. 1 , it is assumed that x is a natural number equal to or greater than eight, but the scope of the present disclosure is not limited thereto.

[0200] refer to Fig. 22, ECC 415 may be divided into a plurality of code groups CG1-CGx and PCG corresponding to a plurality of sub-data units SDU0-SDU2x-1 and parity data PRT. Code group PCG may include a plurality of column vectors PV1-PV8 corresponding to parity bits PB1-PB8 of parity data PRT. Each of the plurality of code groups CG1-CGx may correspond to corresponding two sub-data units of the plurality of sub-data units SDU0-SDU2x-1. For example, code group CG1 may correspond to two sub-data units SDU0 and SDU1, code group CG2 may correspond to two sub-data units SDU2 and SDU3, and code group CGx may correspond to two sub-data units SDU2x-2 and SDU2x-1.

[0201] Fig.23 According to some embodiments, Fig. 22 Example of ECC.

[0202] exist Fig.23 In FIG. 1 , it is assumed that the main data MD3 includes 64 data bits d0-d63. That is, in Fig. 22 Assume x is 4.

[0203] refer to Fig.23 , data bits d0-d63 of the main data MD3 may correspond to code groups CG11, CG12, CG13, and CG14 of ECC ECCa in units of 16 bits.

[0204] Code group CG11 can be divided into two sub-code groups SCG11 and SCG12, code group CG12 can be divided into two sub-code groups SCG21 and SCG22, code group CG13 can be divided into two sub-code groups SCG31 and SCG32, and code group CG14 can be divided into two sub-code groups SCG41 and SCG42.

[0205] Code groups CG11, CG12, CG13 and CG14 may correspond to Fig.13 The parity check generator matrix PGM in . Each of the code groups CG11, CG12, CG13 and CG14 may include an identity submatrix ISM and an alpha matrix. Therefore, each of the subcode groups SCG11 and SCG12 may include half of the identity submatrix ISM and half of the corresponding alpha matrix, each of the subcode groups SCG21 and SCG22 may include half of the identity submatrix ISM and half of the corresponding alpha matrix, each of the subcode groups SCG31 and SCG32 may include half of the identity submatrix ISM and half of the corresponding alpha matrix, and each of the subcode groups SCG41 and SCG42 may include half of the identity submatrix ISM and half of the corresponding alpha matrix.

[0206] Fig.24 An example of mapping information according to some embodiments is shown.

[0207] refer to Fig.24 , the on-die ECC engine 400 can generate parity data PRT3 and check bits CHB3 respectively by performing index interleaving on a plurality of sub-data units SDU0, SDU1, SDU2, SDU3, SDU4, SDU5, SDU6 and SDU7 and sub-code groups SCG11, SCG12, SCG21, SCG22, SCG31, SCG32, SCG41 and SCG42 based on the mapping information MPIb, so that the corresponding two sub-data units SDU0 and SDU4, SDU1 and SDU5, SDU2 and SDU6, and SDU3 and SDU7 to be stored in one row of the target sub-array block correspond to the sub-code groups SCG11 and SCG12, SCG21 and SCG22, and SCG31, SCG32, and SCG41 and SCG42 in each code group, respectively. Therefore, when an error occurs in a memory cell in one memory cell row, the ECC decoder 450 can correct an error bit in one symbol.

[0208] For example, Fig. 20 The ECC encoder 430 can generate the corresponding parity check bits of the parity check data PRT3 by performing matrix multiplication on the subcode group SCG11 and the sub-data unit SDU0, can generate the corresponding parity check bits of the parity check data PRT3 by performing matrix multiplication on the subcode group SCG12 and the sub-data unit SDU4, can generate the corresponding parity check bits of the parity check data PRT3 by performing matrix multiplication on the subcode group SCG21 and the sub-data unit SDU1, and can generate the corresponding parity check bits of the parity check data PRT3 by performing matrix multiplication on the subcode group SCG22 and the sub-data unit SDU5.

[0209] The ECC encoder 430 can generate the corresponding parity check bits of the parity check data PRT3 by performing matrix multiplication on the subcode group SCG31 and the sub-data unit SDU3, can generate the corresponding parity check bits of the parity check data PRT3 by performing matrix multiplication on the subcode group SCG32 and the sub-data unit SDU6, can generate the corresponding parity check bits of the parity check data PRT3 by performing matrix multiplication on the subcode group SCG41 and the sub-data unit SDU3, and can generate the corresponding parity check bits of the parity check data PRT3 by performing matrix multiplication on the subcode group SCG42 and the sub-data unit SDU7.

[0210] also, Fig. 20The ECC decoder 450 can generate the corresponding bits of the check bit CHB3 by performing matrix multiplication on the subcode group SCG11 and the sub-data unit SDU0, can generate the corresponding bits of the check bit CHB3 by performing matrix multiplication on the subcode group SCG12 and the sub-data unit SDU4, can generate the corresponding bits of the check bit CHB3 by performing matrix multiplication on the subcode group SCG21 and the sub-data unit SDU1, and can generate the corresponding bits of the check bit CHB3 by performing matrix multiplication on the subcode group SCG22 and the sub-data unit SDU5.

[0211] The ECC decoder 450 can generate corresponding bits of the check bit CHB3 by performing matrix multiplication on the subcode group SCG31 and the sub-data unit SDU3, can generate corresponding bits of the check bit CHB3 by performing matrix multiplication on the subcode group SCG32 and the sub-data unit SDU6, can generate corresponding bits of the check bit CHB3 by performing matrix multiplication on the subcode group SCG41 and the sub-data unit SDU3, and can generate corresponding bits of the check bit CHB3 by performing matrix multiplication on the subcode group SCG42 and the sub-data unit SDU7.

[0212] When the ECC encoder 430 and the ECC decoder 450 generate parity data PRT3 and check bits CHB3 respectively by performing matrix multiplication on the corresponding two sub-data units SDU0 and SDU4, SDU1 and SDU5, SDU2 and SDU6, and SDU3 and SDU7 to be stored in a row of the target sub-array block and the sub-code groups SCG11 and SCG12, SCG21 and SCG22, and SCG31, SCG32, and SCG41 and SCG42 in each code group, the ECC decoder 450 can correct error bits on a per-symbol basis because the parity bits and check bits associated with one symbol are associated with one code group.

[0213] Fig.25 is a block diagram illustrating a semiconductor memory device according to some embodiments.

[0214] refer to Fig.25 , the semiconductor memory device 800 may include at least one buffer die 810 and a plurality of memory dies 820 - 1 to 820 - s (s is a natural number equal to or greater than three), thereby providing a soft error analysis and correction function in a stacked chip structure.

[0215] A plurality of memory dies 820 - 1 to 820 - s are stacked on the buffer die 810 and communicate data through a plurality of through-silicon via (TSV) lines.

[0216] Each of the plurality of memory dies 820-1 to 820-s may include a cell core 821 storing data and a cell core ECC engine 823 generating a transmission parity bit (e.g., transmission parity data) based on transmission data transmitted to at least one buffer die 810. The cell core 821 may include a plurality of memory cells having a DRAM cell structure.

[0217] The unit core ECC engine 823 can use Fig. 20 The unit core ECC engine 823 can perform ECC encoding on data to be stored in the unit core 821 and perform ECC decoding on data read from the unit core 821 by performing interleaving matrix multiplication on a plurality of sub-data units and a sub-code group of a plurality of code groups included in the ECC. Therefore, the unit core ECC engine 823 can correct error bits in data on a per-symbol basis without increasing complexity.

[0218] The buffer die 810 may include a through-via ECC engine 812 that corrects the transmission error using a transmission parity bit and generates error-corrected data when a transmission error is detected from transmission data received through the TSV line.

[0219] The buffer die 810 may further include a data I / O buffer 816. The data I / O buffer 816 may temporarily store data MD from the through-hole ECC engine 812, and may output the data MD to the outside.

[0220] The semiconductor memory device 800 may be a stacked chip type memory device or a stacked memory device that communicates data and control signals through TSV lines. The TSV lines may also be referred to as "through electrodes."

[0221] The unit core ECC engine 823 may perform error correction on data output from the memory die 820 - s before sending the transmission data.

[0222] The data TSV line group 832 formed at one memory die 820-s may include TSV lines L1, L2, ..., Ls, and the parity TSV line group 834 may include TSV lines L10 to Lt. The TSV lines L1, L2, ..., Ls of the data TSV line group 832 and the parity TSV lines L10 to Lt of the parity TSV line group 834 may be connected to micro bumps MCB correspondingly formed between the memory dies 820-1 to 820-s.

[0223] The semiconductor memory device 800 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a host through a data bus B10. The buffer die 810 may be connected to a memory controller through the data bus B10.

[0224] According to some embodiments, Fig.25 As shown, the cell core ECC engine 823 may be included in the memory die and the through-hole ECC engine 812 may be included in the buffer die. Thus, soft data failures may be detected and corrected. Soft data failures may include transmission errors generated due to noise when data is sent through TSV lines.

[0225] Fig.26 is a diagram showing a stacked memory device (eg, Fig.25 Configuration diagram of a semiconductor package having a stacked memory device).

[0226] refer to Fig.26 , the semiconductor package 900 may include one or more stacked memory devices 910 and a graphics processing unit (GPU) 920 .

[0227] The stacked memory device 910 and the GPU 920 may be mounted on an interposer 930, and the interposer 930 on which the stacked memory device 910 and the GPU 920 are mounted may be mounted on a package substrate 940 mounted on solder balls 950. The GPU 920 may correspond to a semiconductor device that may perform a memory control function, and, for example, the GPU 920 may be implemented as an application processor (AP). The GPU 920 may include a memory controller (CTRL) 921 having a scheduler.

[0228] The stacked memory device 910 may be implemented in various forms, and the stacked memory device 910 may be a memory device in the form of a high bandwidth memory (HBM) stacking multiple layers. Therefore, the stacked memory device 910 may include a buffer die and a plurality of memory dies, and each of the plurality of memory dies includes a cell core and a cell core ECC engine.

[0229] A plurality of stacked memory devices 910 may be mounted on the interposer 930, and the GPU 920 may communicate with the plurality of stacked memory devices 910. For example, each of the stacked memory device 910 and the GPU 920 may include a physical region, and communication may be performed between the stacked memory device 910 and the GPU 920 through the physical region. When the stacked memory device 910 includes a direct access region, a test signal may be provided to the stacked memory device 910 through a conductive member (e.g., a solder ball 950) mounted below the package substrate 940 and the direct access region.

[0230] Fig. 27 is an example of a computing system in which a memory system according to some embodiments corresponds to a Type 3 memory system defined by the Compute Express Link (CXL) protocol.

[0231] refer to Fig. 27 , computing system 1300 may include a root complex 1310, a CXL memory expander 1320 connected to root complex 1310, and memory resources 1330. Memory resources 1330 may correspond to Figure 1 A semiconductor memory device 200 in FIG.

[0232] Root complex 1310 may include a home agent 1311 and an I / O bridge 1313, and home agent 1311 may communicate with CXL memory expander 1320 based on a coherent protocol CXL.mem. I / O bridge 1313 may communicate with CXL memory expander 1320 based on a non-coherent protocol, i.e., an I / O protocol CXL.io. In the CXL protocol base, home agent 1311 may correspond to an agent on the host side that is arranged to solve the overall coherence of computing system 1300 for a given address.

[0233] CXL memory expander 1320 may include memory controller 1321, and memory controller 1321 may use Figure 1 1321. Therefore, the memory controller 1321 may include an ECC engine 1325, and the ECC engine 1325 may interleave or deinterleave data based on mapping information indicating a mapping relationship between a plurality of sub-data units in the user data and memory cell rows of the memory regions MR1, MR2, ..., MRf. Here, f is an integer greater than two.

[0234] Furthermore, CXL memory expander 1320 may output data to root complex 1310 via I / O bridge 1313 based on I / O protocol CXL.io or PCIe.

[0235] The memory resource 1330 may include a plurality of memory regions MR1, MR2, . . . , MRf, and each of the plurality of memory regions MR1, MR2, . . . , MRf may be implemented as a memory of various units.

[0236] Fig.28 is a block diagram illustrating a data center including a computing system according to some implementations.

[0237] refer to Fig.28, the data center 2000 may be a facility that collects various types of data and provides various services, and may be referred to as a data storage center. The data center 2000 may be a system for operating a search engine and a database, and may be a computing system used by a company such as a bank or a government agency. The data center 2000 may include application servers 2100_1 to 2100_U and storage servers 2200_1 to 2200_V. The number of application servers 2100_1 to 2100_U and the number of storage servers 2200_1 to 2200_V may be selected differently according to some embodiments, and the number of application servers 2100_1 to 2100_U and the number of storage servers 2200_1 to 2200_V may be different from each other.

[0238] Below, for the convenience of description, an example of the storage server 2200_1 will be described.

[0239] The storage server 2200_1 may include a processor 2210_1, a memory 2220_1, a switch 2230_1, a network interface controller (NIC) 2240_1, a storage device 2250_1, and a CXL interface 2260_1. The storage server 2200_V may include a processor 2210_v, a memory 2220_v, a switch 2230_v, a NIC 2240_v, a storage device 2250_v, and a CXL interface 2260_v.

[0240] The processor 2210_1 may control the overall operation of the storage server 2200_1. The memory 2220_1 may store various instructions or data under the control of the processor 2210_1. The processor 2210_1 may be configured to access the memory 2220_1 to execute various instructions or process data. In some embodiments, the memory 2220_1 may include at least one of various memory devices, such as a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, or a non-volatile DIMM.

[0241] In some embodiments, the number of processors 2210_1 included in the storage server 2200_1 and the number of memories 2220_1 included in the storage server 2200_1 may be changed or modified differently. In some embodiments, the processor 2210_1 and the memory 2220_1 included in the storage server 2200_1 may constitute a processor-memory pair, and the number of processor-memory pairs included in the storage server 2200_1 may be changed or modified differently. In some embodiments, the number of processors 2210_1 included in the storage server 2200_1 and the number of memories 2220_1 included in the storage server 2200_1 may be different. The processor 2210_1 may include a single-core processor and a multi-core processor.

[0242] Under the control of the processor 2210_1 , the switch 2230_1 may selectively connect the processor 2210_1 and the storage device 2250_1 , or may selectively connect the NIC 2240_1 , the storage device 2250_1 , and the CXL interface 2260_1 .

[0243] NIC 2240_1 can connect storage server 2220_1 to network NT. NIC 2240_1 may include a network interface card, a network adapter, etc. NIC 2240_1 may be connected to network NT through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. NIC 2240_1 may include an internal memory, a digital signal processor (DSP), a host bus interface, etc., and may be connected to processor 2210_1 or switch 2230_1 through a host bus interface. The host bus interface may include at least one of various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI express (PCIe), NVMe, Compute Express Link (CXL), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, Universal Flash (UFS) interface, Embedded UFS (eUFS) interface, Compact Flash (CF) card interface, etc. In some embodiments, the NIC 2240_1 may be integrated with at least one of the processor 2210_1, the switch 2230_1, and the storage device 2250_1.

[0244] Under the control of the processor 2210_1, the storage device 2250_1 may store data or may output the stored data. The storage device 2250_1 may include a controller CTRL 2251_1, a non-volatile memory NAND 2252_1, a DRAM 2253_1, and an interface I / F 2254_1. In some embodiments, the storage device 2250_1 may also include a security element SE for security or privacy. The storage device 2250_v may include a controller CTRL 2251_v, a non-volatile memory NAND 2252_v, a DRAM 2253_v, and an interface I / F 2254_v. In some embodiments, the storage device 2250_v may also include a security element SE for security or privacy.

[0245] The controller 2251_1 may control the overall operation of the storage device 2250_1. The controller 2251_1 may include an SRAM. In response to a signal received through the interface 2254_1, the controller 2251_1 may store data in the nonvolatile memory 2252_1, or may output data stored in the nonvolatile memory 2252_1. The controller 2251_1 may be configured to control the nonvolatile memory 2252_1 based on a switching interface or ONFI.

[0246] DRAM 2253_1 may be configured to temporarily store data to be stored in non-volatile memory NAND 2252_1 or data read from non-volatile memory NAND 2252_1. DRAM 2253_1 may be configured to store various data (e.g., metadata and mapping data) necessary for the operation of storage controller 2251_1. Interface 2254_1 may provide a physical connection between controller 2251_1 and processor 2210_1, switch 2230_1, or NIC 2240_1. Interface 2254_1 may be implemented to support a direct-attached storage (DAS) method that allows direct connection of storage device 2250_1 via a dedicated cable. Interface 2254_1 may be implemented based on at least one of the various above-mentioned interfaces via a host interface bus.

[0247] The above components of the storage server 2200_1 are provided as examples, and the present disclosure is not limited thereto. The above components of the storage server 2200_1 can be applied to each of the other storage servers or each of the application servers 2100_1 to 2100_U. In each application server 2100_1 to 2100_U, the storage device 2150_1 can be selectively omitted.

[0248] The application server 2100_1 may include a processor 2110_1, a memory 2120_1, a switch 2130_1, a NIC 2140_1, and a CXL interface 2160_1. The application server 2100_U may include a processor 2110_u, a memory 2120_u, a switch 2130_u, a NIC 2140_u, a storage device 2150_u, and a CXL interface 2160_u.

[0249] Application servers 2100_1 to 2100_U and storage servers 2200_1 to 2200_V can communicate with each other through network NT. Network NT can be implemented using fiber channel (FC) or Ethernet. FC can be a medium for relatively high-speed data transmission, and optical switches that provide high performance and / or high availability can be used. According to the access scheme of network NT, storage servers 2200_1 to 2200_V can be provided as file storage, block storage, or object storage.

[0250] In some embodiments, the network NT may be a storage-only network or a network dedicated to storage such as a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to an FC protocol (FCP). For another example, the SAN may be an IP-SAN implemented using a transmission control protocol / Internet protocol (TCP / IP) network and according to an iSCSI (SCSI or Internet SCSI over TCP / IP) protocol. In some embodiments, the network NT may be a general network such as a TCP / IP network. For example, the network NT may be implemented according to at least one of protocols such as FC over Ethernet (FCoE), network attached storage (NAS), non-volatile memory express (NVMe) over fabric (NVMe-oF), and the like.

[0251] In some embodiments, at least one of the plurality of application servers 2100_1 to 2100_U may be configured to access at least one of the remaining application servers or at least one of the storage servers 2200_1 to 2200_V through the network NT.

[0252] For example, the application server 2100_1 may store the data requested by the user or client in at least one of the storage servers 2200_1 to 2200_V through the network NT. Alternatively, the application server 2100_1 may obtain the data requested by the user or client in at least one of the storage servers 2200_1 to 2200_V through the network NT. In this case, the application server 2100_1 may be implemented with a web server, a database management system (DBMS), etc.

[0253] The application server 2100_1 can access the memory 2120_1 or the storage device 2105_1 of the application server 2100_1 or the storage device 2250_1 of the storage server 2000_1 through the network NT. Therefore, the application server 2100_1 can perform various operations on the data stored in the application servers 2100_1 to 2100_U and / or the storage servers 2200_1 to 2200_V. For example, the application server 2100_1 can execute a command for moving or copying data between the application servers 2100_1 to 2100_U and / or the storage servers 2200_1 to 2200_V. Data may be transmitted from the storage devices 2250_1 to 2250_v of the storage servers 2200_1 to 2200_V to the storage 2120_1 to 2120_u of the application servers 2100_1 to 2100_U directly or through the storage 2220_1 to 2220_v of the storage servers 2200_1 to 2200_V. For example, data transmitted over the network NT may be encrypted data for security or privacy.

[0254] The storage servers 2200_1 to 2200_V and the application servers 2100_1 to 2100_U may be connected to the memory expander 2300 through the CXL interfaces 2260_1 to 2260_v and 2160_1 to 2160_u. The memory expander 2300 may be used as an extended memory for each of the storage servers 2200_1 to 2200_V, and the application servers 2100_1 to 2100_U or virtualization components included therein may communicate with each other through the CXL interfaces 2260_1 to 2260_v and 2160_1 to 2160_u and the memory expander 2300.

[0255] The present disclosure can be applied to various semiconductor memory devices and systems using ECC. For example, the present disclosure can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0256] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of possible claims. Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. On the contrary, the various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, in some cases, one or more features from a combination may be deleted from the combination, and the combination may point to a sub-combination or a variant of a sub-combination.

[0257] While the present disclosure has been particularly shown and described with reference to examples thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A memory system, comprising: A semiconductor memory device comprising a memory cell array, wherein the memory cell array comprises a plurality of memory cells connected to word lines and bit lines, and wherein the memory cell array is divided into a plurality of sub-array blocks arranged in a first direction and a second direction crossing the first direction; and a memory controller configured to control the semiconductor memory device, The memory controller includes an error correction code (ECC) engine, and the ECC engine is configured to: generating parity data by performing ECC encoding on user data including a plurality of sub-data units, each of the plurality of sub-data units including a plurality of data bits; generating main data by interleaving the plurality of sub-data units based on mapping information so that two sub-data units of the plurality of sub-data units are included in one symbol, wherein the two sub-data units are stored in a row of a target sub-array block of the plurality of sub-array blocks; and sending the main data and the parity data to the semiconductor memory device, and The mapping information indicates a mapping relationship between the plurality of sub-data units and corresponding rows of the target sub-array block storing the plurality of sub-data units.

2. The memory system according to claim 1, wherein: The ECC engine is configured to, in a read operation: receiving the main data and the parity data from the semiconductor memory device; generating intermediate master data by deinterleaving the master data based on the mapping information; as well as At least one error in the intermediate main data is corrected on a per symbol basis by performing ECC decoding on the intermediate main data using the parity data.

3. The memory system according to claim 1, in, At least one of the central processing unit of the semiconductor memory device or the memory controller is configured to control the ECC engine and provide the mapping information to the ECC engine, and The ECC engine is configured to store the mapping information in a buffer included in the ECC engine.

4. The memory system according to claim 1, wherein: The two sub-data units included in the one symbol are stored in memory cells coupled to a first word line in the target sub-array block, and A sub-word line driver of the semiconductor memory device is configured to drive the first word line.

5. The memory system according to claim 1, wherein: Each of the plurality of sub-data units corresponds to a burst length indicating an amount of data input or output at one time between the memory controller and the semiconductor memory device.

6. The memory system according to claim 1, wherein: The semiconductor memory device further includes a control logic circuit configured to control access to the memory cell array based on a command received from the memory controller and an address received from the memory controller.

7. The memory system according to claim 1, wherein: The ECC engine comprises: An ECC encoder configured to generate the parity data by performing the ECC encoding on the user data by using a parity generation matrix; a data interleaver configured to generate the main data by interleaving the plurality of sub-data units based on the mapping information; and A buffer is configured to store the main data and the parity data, transmit a codeword including the main data and the parity data to the semiconductor memory device, and store the mapping information.

8. The memory system according to claim 7, wherein: The ECC engine also includes: a data deinterleaver configured to receive the main data and the parity data from the semiconductor memory device and generate intermediate main data by deinterleaving the main data based on the mapping information; an ECC decoder configured to correct at least one error in the intermediate main data on a per-symbol basis by performing ECC decoding on the intermediate main data using the parity check data and a parity check matrix; and a memory configured to store the parity-check generator matrix and the parity-check matrix, The ECC decoder is configured to correct errors in the two sub-data units included in the one symbol by performing the ECC decoding.

9. The memory system according to claim 7, wherein: The data interleaver is configured to interleave the plurality of sub-data units based on the mapping information so that the two sub-data units included in the one symbol are stored in a memory cell coupled to a first word line in the target sub-array block, and A sub-word line driver of the semiconductor memory device is configured to drive the first word line.

10. The memory system according to claim 1, wherein: The ECC engine comprises: a buffer configured to store the mapping information; The ECC encoder is configured to, in the write operation: generating the parity data by performing the ECC encoding on the user data using a parity generation matrix; generating the main data by interleaving the plurality of sub-data units based on the mapping information; generating interleaved parity data by interleaving the parity data based on the mapping information; and sending an interleaved codeword including the main data and the interleaved parity data to the semiconductor memory device; and The ECC decoder is configured to, during a read operation: receiving the main data and the interleaved parity data from the semiconductor memory device; generating intermediate main data and the parity data by deinterleaving the main data and the interleaved parity data based on the mapping information; and At least one error in the intermediate main data is corrected on a per symbol basis by performing ECC decoding on the intermediate main data using the parity data.

11. A memory system comprising: A semiconductor memory device comprising a memory cell array, wherein the memory cell array comprises a plurality of memory cells connected to word lines and bit lines, and wherein the memory cell array is divided into a plurality of sub-array blocks arranged in a first direction and a second direction crossing the first direction; and a memory controller configured to control the semiconductor memory device, The memory controller includes an error correction code (ECC) engine, and the ECC engine is configured to: generating parity data by performing ECC encoding on user data including a plurality of sub-data units, each of the plurality of sub-data units including a plurality of data bits, based on a selected ECC, the selected ECC being selected from the plurality of ECCs based on the mapping information, and transmitting the parity data and main data corresponding to the user data to the semiconductor memory device, The mapping information indicates a mapping relationship between the plurality of sub-data units and corresponding rows of a target sub-array block in the plurality of sub-array blocks, and the plurality of sub-array blocks store the plurality of sub-data units; and wherein the selected ECC is configured such that two sub-data units of the plurality of sub-data units are included in one symbol, and wherein the two sub-data units are stored in one row of the target sub-array block.

12. The memory system according to claim 11, wherein: The ECC engine is configured to, in a read operation: receiving the main data and the parity data from the semiconductor memory device; as well as At least one error in the main data is corrected on a per symbol basis by performing ECC decoding on the main data using the parity data and the selected ECC.

13. The memory system according to claim 11, in, At least one of the central processing unit of the semiconductor memory device or the memory controller is configured to control the ECC engine and provide the mapping information to the ECC engine, and The ECC engine is configured to store the mapping information in a buffer included in the ECC engine.

14. The memory system according to claim 11, wherein: The semiconductor memory device further includes a control logic circuit configured to control access to the memory cell array based on a command received from the memory controller and an address received from the memory controller.

15. The memory system according to claim 11, wherein: The ECC engine comprises: an ECC encoder configured to generate the parity data by performing the ECC encoding on the user data using the selected ECC in the write operation; an ECC decoder configured to correct at least one error in the main data on a per-symbol basis by using the parity data received from the memory controller and performing ECC decoding on the main data using the selected ECC in a read operation; a memory configured to store the plurality of ECCs; and A buffer is configured to store the mapping information.

16. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells connected to word lines and bit lines, the memory cell array being divided into a plurality of sub-array blocks arranged in a first direction and a second direction intersecting the first direction; an on-die error correction code (ECC) engine configured to generate parity data based on main data including a plurality of sub-data units, each of the plurality of sub-data units including a plurality of data bits, in a write operation by using an ECC represented by a generator matrix; an input / output I / O gating circuit coupled between the memory cell array and the on-die ECC engine, the I / O gating circuit being configured to store the main data and the parity data in the memory cell array; and a control logic circuit configured to control the on-die ECC engine and the I / O gating circuit, wherein the on-die ECC engine is configured to generate the parity data by performing a first interleaved matrix multiplication on the plurality of sub-data units and sub-code groups of the plurality of code groups based on mapping information, so that two sub-data units of the plurality of sub-data units are included in one symbol, wherein the two sub-data units are stored in a row of a target sub-array block of the plurality of sub-array blocks, and The mapping information indicates a mapping relationship between the multiple sub-data units and the sub-code groups.

17. The semiconductor memory device according to claim 16, wherein: The on-die ECC engine is configured to, in a read operation: receiving the main data and the parity data from the memory cell array; generating a check bit by performing a second interleaving matrix multiplication on the plurality of sub-data units and the sub-code group based on the mapping information; as well as At least one error in the main data is corrected on a per symbol basis based on comparing the parity data with the check bits.

18. The semiconductor memory device according to claim 16, wherein: The on-die ECC engine comprises: an ECC encoder configured to generate the parity data by performing the first interleaving matrix multiplication on the plurality of sub-data units and the sub-code group based on the mapping information in the write operation, Wherein, the ECC encoder is configured to, in a read operation, reading the main data and the parity data from the memory cell array, generating a check bit by performing a second interleaving matrix multiplication on the plurality of sub-data units and the sub-code group based on the mapping information, and correcting at least one error in the main data on a per symbol basis based on comparing the parity data to the check bits; and The memory is configured to store the ECC.

19. The semiconductor memory device according to claim 18, in, Each code group of the plurality of code groups corresponds to respective two sub-data units of the plurality of sub-data units; and Each of the plurality of code groups includes a unit sub-matrix and an alpha matrix corresponding to the two corresponding sub-data units.

20. The semiconductor memory device according to claim 19, in, Each of the plurality of code groups includes a first sub-code group and a second sub-code group, and wherein each of the first sub-code group and the second sub-code group includes half of the identity sub-matrix and half of the alpha matrix, and The ECC encoder is configured to perform the first interleaving matrix multiplication on the corresponding two sub-data units, the first sub-code group and the second sub-code group.

Images