Synchronous real-time simulation test platform based on FPGA

Abstract

The invention discloses a synchronous real-time simulation test platform based on an FPGA (Field Programmable Gate Array), and relates to the field of simulation test. The platform comprises a satellite time service module, a main synchronous time service module, a switch, computer equipment and an FPGA simulation test front end, the satellite time service module is used for acquiring time information through a satellite signal and transmitting the time information to the main synchronous time service module; the switch is used for respectively transmitting the time information to the computer equipment and the FPGA simulation test front end; the computer equipment is used for establishing a simulation test model according to the tested equipment, generating a simulation test process instruction and a process trigger timestamp mark according to the simulation test model and the time information, and sending the simulation test process instruction and the process trigger timestamp mark to the FPGA simulation test front end; and the FPGA simulation test front end is used for executing a simulation test to obtain a simulation test result and process execution timestamp information, and transmitting the simulation test result and the process execution timestamp information to the computer equipment. According to the invention, the simulation test process and data acquisition can be accurately controlled in real time.

Description

Technical Field

[0001] The present invention relates to the technical field of simulation testing, and in particular to a synchronous real-time simulation testing platform based on FPGA. Background Art

[0002] Before actually deploying a hardware system or physical device, it is usually necessary to verify the correctness of its design, performance indicators and stability through simulation testing. Through the simulation test platform, various operating conditions and possible failure modes can be simulated to discover and correct potential problems in a risk-free and cost-effective environment, thereby reducing development costs, shortening development cycles and improving system reliability.

[0003] With the development of communication technology, the significant increase in data transmission rate requires the simulation test platform to more accurately simulate the system behavior in a high-speed communication environment. Therefore, higher requirements are placed on the synchronization and real-time performance of the simulation test to ensure that the test results can accurately reflect the performance and performance of the system or equipment in actual operation.

[0004] Traditional simulation test platforms usually rely on computer systems running general-purpose or real-time operating systems to simulate the behavior of physical devices or systems. They generally implement simulation logic through software algorithms and use interface cards and external devices for data exchange. Due to the limitations of computer processing power and communication delays, there are many time delays in communication and data processing, which cannot meet the high-precision synchronization and real-time requirements of simulation tests. Summary of the invention

[0005] In view of the above technical problems and defects, the purpose of the present invention is to provide a synchronous real-time simulation test platform based on FPGA, which can solve the technical problems of how to achieve accurate synchronization of time information in simulation testing and efficient test process control.

[0006] To achieve the above-mentioned purpose, the present invention provides a synchronous real-time simulation test platform based on FPGA, including a satellite timing module, a main synchronous timing module, a switch, a computer device and an FPGA simulation test front end; the satellite timing module is used to obtain time information through satellite signals, and transmit the time information to the main synchronous timing module; the switch is connected to the main synchronous timing module, and is used to transmit the time information to the computer device and the FPGA simulation test front end respectively; the computer device is used to establish a simulation test model according to a device under test, and generate a simulation test process instruction and a process trigger timestamp mark according to the simulation test model and the time information, and then send the simulation test process instruction and the process trigger timestamp mark to the FPGA simulation test front end; the FPGA simulation test front end is used to perform a simulation test on the device under test according to the time information, the process trigger timestamp mark and the simulation test process instruction, obtain a simulation test result and a process execution timestamp information, and transmit the simulation test result and the process execution timestamp information to the computer device.

[0007] The present invention realizes high-precision time synchronization and efficient simulation test process by integrating satellite timing module, main synchronization timing module, switch, computer equipment and FPGA simulation test front end. The satellite timing module of the platform obtains accurate time information through satellite signals and transmits it to the main synchronization timing module, which distributes the time information to the computer equipment and FPGA simulation test front end through the switch to ensure the time synchronization of the entire system. The computer equipment is responsible for establishing a simulation test model, generating simulation test process instructions and process trigger timestamp marks, and then sending them to the FPGA simulation test front end. The FPGA simulation test front end can perform multiple operations and perform simulation tests at the same time according to the received time information, process trigger timestamp marks and simulation test process instructions, using the real-time parallel processing capability of FPGA, obtain test results and process execution timestamp information, and transmit these information back to the computer equipment, thereby realizing accurate and efficient simulation tests, meeting the strict requirements of synchronization and real-time performance in modern communication systems.

[0008] In some embodiments, the FPGA simulation test front end includes a slave synchronization timing module and an FPGA simulation test board; the slave synchronization timing module is connected between the FPGA simulation test board and the switch for transmitting the time information; the FPGA simulation test board is connected to the computer device.

[0009] The technical solution of the above-mentioned embodiment is adopted, in which the FPGA simulation test front end is composed of a synchronous timing module and an FPGA simulation test board, which ensures that time information can be efficiently and accurately transmitted from the switch to the FPGA system, and simulation test process instructions are transmitted from the computer device to the FPGA system, thereby achieving precise time synchronization and instruction transmission, and improving the accuracy and reliability of the simulation test.

[0010] In some embodiments, the FPGA simulation test board includes an FPGA system, an ADC acquisition module, a DAC output module and an interface module; the FPGA system is connected to the computer device and the slave synchronization timing module respectively; the ADC acquisition module is connected to the FPGA system, used to acquire the analog signal of the device under test and convert it into a device test digital signal and transmit it to the FPGA system; the DAC output module is connected to the FPGA system, used to convert the digital signal output by the FPGA system into an analog signal and transmit it to the device under test; the interface module is connected to the FPGA system, used for information interaction between the FPGA system and the device under test.

[0011] By adopting the technical solution of the above embodiment, multiple functional modules, including ADC acquisition module, DAC output module and interface module, are integrated on the FPGA simulation test board, thereby enhancing the data interaction capability between the FPGA system and the device under test. This integrated design makes signal acquisition, processing and output more efficient, and improves the flexibility and real-time response capability of the simulation test.

[0012] In some embodiments, the FPGA system includes a time parsing module, an instruction decoding module, a simulation test process model state machine, an interface driver module, a simulation test calculation module, a data encoding module, an ADC driver module and a DAC driver module; the time parsing module is connected to the slave synchronization timing module, and is used to convert the time information into a format that can be recognized and processed by the FPGA system; the instruction decoding module is connected to the computer device, and is used to decode the simulation test process instruction to obtain a simulation test process decoding instruction; the simulation test process model state machine is connected to the instruction decoding module, and is used to execute a test process on the device under test according to the simulation test process decoding instruction and the time information; the interface driver module is connected to the interface module, and is used to transmit the interaction information of the device under test to the computer device. A simulation test process model state machine; the simulation test calculation module is connected to the simulation test process model state machine, used to calculate and process the device test digital signal, obtain the simulation test result and the process execution timestamp information, and transmit them to the simulation test process model state machine; the data encoding module is connected to the simulation test process model state machine, used to encode the simulation test result and the process execution timestamp information to obtain encoded data, and transmit the encoded data to the computer device; the ADC driver module is connected to the ADC acquisition module, used to transmit the device test digital signal to the simulation test process model state machine; the DAC driver module is connected to the DAC output module, used to transmit the test control analog signal of the simulation test process model state machine to the device under test.

[0013] By adopting the technical solution of the above embodiment, accurate test process control and data processing are achieved through the coordinated work of key modules such as the time analysis module, the instruction decoding module, and the simulation test process model state machine. This modular design improves the scalability and maintainability of the system and ensures the efficient execution of the simulation test.

[0014] In some embodiments, the interface module includes an IO interface and a bus interface. The IO interface is used for data interaction between the device under test and the FPGA system, and the bus interface is used for the FPGA system to communicate with the outside using multiple data transmission protocols.

[0015] By adopting the technical solution of the above embodiment, the data interaction capability between the FPGA system and the device under test and external devices is expanded through the interface module including the IO interface and the bus interface. This design enables the FPGA system to adapt to various communication protocols and data transmission requirements, and enhances the compatibility and application scope of the system.

[0016] In some embodiments, the interface driver module includes an IO interface driver module and a bus interface driver module; the IO interface driver module is connected between the IO interface and the simulation test process model state machine, and the bus interface driver module is connected between the bus interface and the simulation test process model state machine.

[0017] By adopting the technical solution of the above embodiment, the data interaction process between the FPGA system and the external device is further refined through the interface driver module. The addition of the IO interface driver module and the bus interface driver module ensures the accurate and efficient transmission of data between the FPGA system and the external device, and improves the stability of the system and the reliability of the test.

[0018] In some embodiments, the time analysis module includes a analysis processing module and a counter. The slave synchronization timing module is used to generate a second pulse signal according to the time information, the analysis processing module is used to analyze the time information, and the counter is used to synchronize the internal time of the FPGA simulation test board according to the second pulse signal.

[0019] By adopting the technical solution of the above embodiment, the FPGA system's ability to process time information is enhanced through the analysis processing module and the counter inside the time analysis module. This design enables the FPGA system to synchronize the internal time based on the precise second pulse signal, providing an accurate time reference for the simulation test, thereby improving the synchronization and accuracy of the test.

[0020] In some embodiments, the slave synchronization timing module transmits the time information to the analysis processing module via a UART time protocol.

[0021] By adopting the technical solution of the above embodiment, the transmission process of time information is simplified by specifying that the slave timing module transmits time information through the UART time protocol. This standardized communication protocol reduces the complexity of system design, improves the stability and compatibility of time information transmission, and ensures the synchronization of the entire test platform.

[0022] In some embodiments, the switch and the slave synchronization timing module are connected via a timing bus, and the timing bus includes an Ethernet bus.

[0023] By adopting the technical solution of the above embodiment, the switch and the slave synchronization timing module are connected through a timing bus, wherein the timing bus includes an Ethernet bus, so that the time information is efficiently distributed in the test platform. This design utilizes the wide compatibility and high-speed characteristics of Ethernet, and improves the coverage and accuracy of time synchronization.

[0024] In some embodiments, the computer device is connected to the FPGA simulation test board via a data bus, and the data bus includes a PCI bus, a PXI bus, or an Ethernet bus.

[0025] By adopting the technical solution of the above embodiment, the computer device and the FPGA simulation test board are connected through a data bus, wherein the data bus includes a PCI bus, a PXI bus or an Ethernet bus, providing flexible data transmission options. This diversified connection mode enables the system to select a suitable data transmission scheme according to different test requirements and environments, thereby enhancing the adaptability and performance of the system.

[0026] One or more technical solutions provided by the present invention have at least the following technical effects or advantages: 1. High-precision time synchronization: By integrating the satellite timing module, the master synchronization timing module, and the slave synchronization timing module, high-precision time synchronization of the entire test platform is achieved. This solution uses satellite signals to obtain time information and transmits the time information to computer equipment and FPGA simulation test front-end through a timing bus (such as Ethernet bus). This synchronization mechanism ensures that all devices share a unified time reference, meeting the strict requirements of real-time simulation testing for time accuracy, thereby improving the accuracy and reliability of the test.

[0027] 2. Flexible simulation test process control: Flexible control of the simulation test process is achieved through the simulation test process model state machine inside the FPGA system. The state machine triggers each test state in a predetermined time sequence and performs corresponding test operations according to the simulation test process instructions and time information received from the computer device. This design allows the test process to be customized and adjusted as needed while maintaining strict time control, greatly enhancing the flexibility and adaptability of simulation testing.

[0028] 3. Efficient data interaction and processing capabilities: By integrating multiple functional modules (such as ADC acquisition module, DAC output module, interface module, simulation test calculation module, etc.) and corresponding driver modules in the FPGA system, efficient data interaction and processing with the device under test is achieved. These modules work together to achieve functions such as analog signal acquisition, digital signal output, data processing and analysis, and support multiple data transmission protocols. This integrated design improves the efficiency of data interaction, shortens the test cycle, and improves the overall performance of simulation testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings herein are incorporated into and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 It is a schematic diagram of the architecture of a synchronous real-time simulation test platform based on FPGA according to an embodiment of the present invention; Figure 2 is a schematic diagram of a synchronization time configuration process in an embodiment of the present invention; Figure 3 It is a schematic diagram of the architecture of an FPGA simulation test board in an embodiment of the present invention; Figure 4 It is a schematic diagram of the architecture of an FPGA system in an embodiment of the present invention; Figure 5 This is a workflow diagram of a real-time simulation test in an embodiment of the present invention; Figure 6 It is a system flow chart of a synchronous real-time simulation test in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The terms used in the following embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to be limiting of the present invention. As used in the specification of the present invention, the singular expressions "a", "a", "above", "the" and "this" are intended to also include plural expressions, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in the present invention refers to any or all possible combinations comprising one or more of the listed items.

[0031] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, unless otherwise specified, the meaning of "plurality" is two or more.

[0032] It should also be noted that, unless otherwise clearly specified and limited, in the embodiments of the present invention, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two components; it can be a wired communication connection or a wireless communication connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances. The embodiments of the present invention are described in detail below.

[0033] The embodiment of the present invention provides a synchronous real-time simulation test platform based on FPGA, such as Figure 1 As shown, it includes a satellite timing module 1, a main synchronization timing module 2, a switch 3, a computer device 4 and an FPGA simulation test front end 5.

[0034] This embodiment realizes high-precision time synchronization and efficient simulation test process by integrating satellite timing module 1, main synchronization timing module 2, switch 3, computer device 4 and FPGA (Field Programmable Gate Array) simulation test front end. Satellite timing module 1 obtains accurate time information through satellite signals and transmits it to main synchronization timing module 2. Main synchronization timing module 2 distributes time information to computer device 4 and FPGA simulation test front end 5 through switch 3 to ensure time synchronization of the whole system. Computer device 4 is responsible for establishing simulation test model, generating simulation test process instruction and process trigger timestamp mark, and then sending them to FPGA simulation test front end 5. FPGA simulation test front end 5 can perform multiple operations and perform simulation tests at the same time according to the received time information, process trigger timestamp mark and simulation test process instruction, and utilizes FPGA real-time parallel processing capability, obtains test results and process execution timestamp information, and transmits this information back to computer device 4, thereby realizing accurate and efficient simulation test, meeting the strict requirements of synchronization and real-time in modern communication systems.

[0035] Specifically, the satellite timing module 1 is used to obtain time information through satellite signals and transmit the time information to the main synchronization timing module 2.

[0036] Among them, the satellite timing module 1 can include a Beidou timing module, a GPS (Global Positioning System) timing module, a GLONASS (Russia's Global Satellite Navigation System) timing module, a Galileo (European Union's Galileo Satellite Navigation System) timing module, a QZSS (Japan's Quasi-Zenith Satellite System) timing module, and a NavIC (India's Navigation Satellite System) timing module.

[0037] The function of the satellite timing module 1 is to obtain accurate time information by receiving high-precision time signals transmitted by satellites, and transmit this time information to the main synchronization timing module 2 through the timing bus, so as to achieve time synchronization in the entire test system. This process ensures that the test platform can use accurate time data from satellites, thereby improving the accuracy and reliability of simulation tests.

[0038] The switch 3 is connected to the main synchronous timing module 2 and is used to transmit time information to the computer device 4 and the FPGA simulation test front end 5 respectively.

[0039] Among them, the switch 3 is connected to the main synchronization timing module 2, which is responsible for transmitting the time information obtained from the satellite timing module 1 and processed by the main synchronization timing module 2 to the computer device 4 and the FPGA simulation test front end 5 through the Ethernet timing bus, ensuring that the entire test system achieves accurate time synchronization.

[0040] In this embodiment, the switch 3 includes a switch that supports the IEEE1588 protocol. This switch can use the IEEE1588 precision time protocol to further improve the accuracy of time synchronization, so that the computer device 4 and the FPGA simulation test front end 5 can perform high-precision simulation test operations based on a unified time reference.

[0041] The computer device 4 is used to establish a simulation test model according to the device under test, and generate simulation test process instructions and process trigger timestamp marks according to the simulation test model and time information, and then send the simulation test process instructions and process trigger timestamp marks to the FPGA simulation test front end 5.

[0042] The simulation test model refers to a virtual model created by the computer device 4 according to the characteristics of the device under test and the test requirements. The simulation test model defines in detail the operating environment, input conditions, expected outputs, and performance evaluation criteria of the system under test in the simulation test, and is used to simulate the actual operation of the device under test during the simulation test to ensure the accuracy and effectiveness of the test. The simulation test model includes the mathematical representation, logical relationships, time series, and interface definitions of the system, so that the test can be carried out in a controlled virtual environment, thereby verifying the correctness and performance indicators of the system design before actual deployment.

[0043] In this embodiment, the computer device 4 can serve as the control center of the simulation test, responsible for establishing an accurate simulation test model based on the characteristics and requirements of the device under test, and then using this model and the time information received from the main synchronization timing module 2 through the switch 3 to generate detailed simulation test process instructions and corresponding process trigger timestamp marks, which are then sent to the FPGA simulation test front end 5 via the data bus to ensure that the test process can be accurately executed according to the predetermined time and sequence.

[0044] The FPGA simulation test front end 5 is used to perform simulation testing on the device under test according to time information, process trigger timestamp mark and simulation test process instructions, obtain simulation test results and process execution timestamp information, and transmit the simulation test results and process execution timestamp information to the computer device 4.

[0045] In this embodiment, the FPGA simulation test front end 5 plays the role of an executor in the synchronous real-time simulation test platform. The FPGA simulation test front end 5 directly interacts with the device under test to implement accurate simulation tests. The FPGA simulation test front end 5 uses the time information received from the main synchronization timing module 2 through the switch 3 to ensure that the test action is synchronized with the global time. Using this time information, the FPGA simulation test front end 5 can parse the simulation test process instructions sent by the computer device 4, which contain detailed steps, operating conditions and expected actions of the test process.

[0046] At the same time, the FPGA simulation test front end 5 also determines the exact time to execute the test process based on the process trigger timestamp mark. When executing the test process, the FPGA front end will simulate various operations according to the simulation test process instructions, such as signal generation, acquisition, processing and output, as well as data interaction and control with the device under test. During the test process, the FPGA simulation test front end records the timestamp information of key operations, which, together with the simulation test results, are transmitted back to the computer device 4 through a data bus such as Ethernet / PCI / PXI. The computer device 4 then analyzes these data to evaluate whether the performance and function of the device under test meet the predetermined standards.

[0047] In this way, the FPGA simulation test front end 5 not only realizes the accurate simulation test of the device under test, but also provides detailed test results and timestamp information, so that engineers can conduct in-depth analysis and verification of the test process, thereby ensuring the accuracy and reliability of the test.

[0048] In this embodiment, the FPGA simulation test front end 5 adopts FPGA as the core processing unit and utilizes its built-in parallel processing capabilities to simultaneously perform multiple operations, such as signal acquisition, data processing and output control, without relying on traditional serial processing computers; at the same time, the real-time performance of FPGA ensures that it can respond to time synchronization signals at the nanosecond level, thereby directly performing process model operations at the hardware level, avoiding the communication time between the computer and the hardware board and the computer processing time. In this way, when the system receives accurate timestamp information and triggers FPGA to execute the simulation test process, FPGA can quickly and in parallel execute all predetermined test operations, and upload the test results together with the accurate timestamp to the computer, thereby greatly reducing the time delay caused by communication and data processing, and achieving the technical effect of synchronous real-time simulation testing.

[0049] In some embodiments, the FPGA simulation test front end 5 includes a slave synchronization timing module 51 and an FPGA simulation test board 52; the slave synchronization timing module 51 is connected between the FPGA simulation test board 52 and the switch 3 for transmitting time information; the FPGA simulation test board 52 is connected to the computer device 4.

[0050] The FPGA simulation test front end 5 is composed of a slave synchronization timing module 51 and an FPGA simulation test board 52, wherein the slave synchronization timing module 51 acts as a transfer station for time information, is connected between the FPGA simulation test board 52 and the switch 3, and is responsible for punctually transmitting the high-precision time information from the switch 3 to the FPGA simulation test board 52 to ensure that the test process is synchronized with the global time; and the FPGA simulation test board 52 establishes a connection with the computer device 4, receives the simulation test process instructions and process trigger timestamp marks generated by the computer according to the characteristics of the device under test and the test requirements, executes the simulation test, and feeds back the test results and process execution timestamp information to the computer device 4 in real time, thereby realizing an accurate and efficient simulation test process.

[0051] In this embodiment, the synchronization time configuration process refers to Figure 2As shown, the satellite timing module 1 first receives the time information, and then passes the information to the main synchronization timing module 2. The main synchronization timing module is responsible for time networking, and works with the switch 3 through the IEEE1588 protocol to distribute the time information to each FPGA simulation test front end 5. The computer device 4 is responsible for receiving and parsing the timestamp information in this process, and the slave synchronization module receives and parses the timestamp information in each FPGA simulation test front end 5, ensuring that all devices in the entire test system can be synchronized to a unified time reference, providing the necessary time synchronization for high-precision simulation testing. This process ensures that the test platform can perform test operations according to a unified time standard and meet the requirements of real-time simulation testing for time accuracy.

[0052] In some embodiments, Figure 3 As shown, the FPGA simulation test board 52 includes an FPGA system 521, an ADC acquisition module 522, a DAC output module 523 and an interface module 524; the FPGA system 521 is connected to the computer device 4 and the slave synchronization timing module 51 respectively; the ADC acquisition module 522 is connected to the FPGA system 521, and is used to acquire the analog signal of the device under test and convert it into a device test digital signal and transmit it to the FPGA system 521; the DAC output module 523 is connected to the FPGA system 521, and is used to convert the digital signal output by the FPGA system 521 into an analog signal and transmit it to the device under test; the interface module 524 is connected to the FPGA system 521, and is used for information interaction between the FPGA system 521 and the device under test.

[0053] This embodiment adopts the above design. The FPGA system 521 is responsible for processing and coordinating the operations of each module. It is connected to the computer device 4 and the slave synchronization timing module 51 through a high-speed data bus, receives the test instructions and time synchronization signals issued by the computer, and ensures the accurate execution of the test process. The ADC acquisition module 522 is closely connected to the FPGA system 521, and is responsible for collecting analog signals (such as voltage, current, etc.) from the device under test, and converting them into digital signals for further processing and analysis by the FPGA system 521. The DAC output module 523 is also connected to the FPGA system 521, and it converts the digital signals generated by the FPGA system 521 into analog signals so as to provide the required excitation signals to the device under test. The interface module 524 provides a channel for information exchange between the FPGA system 521 and the device under test, and supports various communication protocols and data transmission formats to adapt to different types of test requirements; among them, the interface module 524 can support serial port, CAN, 1553B, 429, 1394, FC and other data transmission bus modes.

[0054] The coordinated operation of these modules enables the FPGA simulation test board 52 to accurately simulate various situations of the device under test in actual operation, thereby achieving efficient and reliable simulation testing.

[0055] In some embodiments, Figure 4 As shown, the FPGA system 521 includes a time analysis module 5211, an instruction decoding module 5212, a simulation test process model state machine 5213, an interface driver module 5214, a simulation test calculation module 5215, a data encoding module 5216, an ADC driver module 5217 and a DAC driver module 5218.

[0056] The integration of these modules enables the FPGA system 521 to implement a highly automated and precisely controlled simulation test process, meeting the strict requirements of synchronization and real-time performance in modern communication systems.

[0057] In this embodiment, the time analysis module 5211 is connected to the slave synchronization timing module 51 and is used to convert the time information into a format that can be recognized and processed by the FPGA system 521.

[0058] The time resolution module 5211 is directly connected to the slave synchronization timing module 51, which is responsible for receiving and transmitting accurate time information. The main function of the time resolution module 5211 is to convert the time information, such as the network time or PPS (one pulse per second) signal transmitted through the IEEE1588 protocol, into a format that can be recognized and processed by the FPGA system 521. This conversion process ensures the accuracy and availability of the time information, so that the FPGA system 521 can perform the predetermined test operation at every precise moment.

[0059] In this way, the time resolution module 5211 provides the necessary time reference for the entire simulation test process, so that the test activities can be synchronized with the global time and achieve accurate timing control. This synchronization is essential for performing complex simulation tests, especially in application scenarios that have strict requirements on time accuracy.

[0060] The instruction decoding module 5212 is connected to the computer device 4 and is used to decode the simulation test process instructions to obtain simulation test process decoding instructions.

[0061] Specifically, the instruction decoding module 5212 establishes a connection with the computer device 4 and is responsible for receiving the simulation test process instructions sent by the computer. These instructions usually contain the detailed steps, operating conditions and expected actions of the simulation test. The instruction decoding module 5212 decodes these complex instructions and converts them into internal commands or signals that the FPGA system 521 can understand and execute. The decoded instructions, i.e., the simulation test process decoding instructions, will guide the FPGA system 521 to accurately control the ADC acquisition module 522, the DAC output module 523 and the interface module 524 according to the predetermined test plan, and perform operations such as signal acquisition, data processing, and output control. This process ensures the accuracy and effectiveness of the simulation test, so that the test results can truly reflect the performance of the device under test under actual working conditions.

[0062] The simulation test process model state machine 5213 is connected to the instruction decoding module 5212, and is used to decode instructions and time information according to the simulation test process and execute the test process on the device under test.

[0063] Specifically, the simulation test process model state machine 5213 is directly connected to the instruction decoding module 5212, and is used to receive and execute the decoded simulation test process instructions. The state machine controls the execution of the entire test process according to the simulation test process decoding instructions and time information provided by the instruction decoding module 5212. The simulation test process model state machine 5213 triggers each module in the FPGA system 521, such as the ADC acquisition module 522, the DAC output module 523 and the interface module 524, according to the predetermined time sequence and operation steps, and performs accurate test operations on the device under test. The simulation test process model state machine 5213 ensures that each step of the test process can be executed on time by monitoring the current state and waiting for the next trigger time point, thereby realizing synchronous testing of the device under test.

[0064] In this way, the simulation test process model state machine 5213 ensures the automation and precise control of the test process, meeting the simulation test requirements of high-precision synchronization and real-time requirements.

[0065] The interface driver module 5214 is connected to the interface module 524 and is used to transmit the interaction information of the device under test to the simulation test process model state machine 5213 .

[0066] Among them, the interface driver module 5214 plays a crucial bridge role in the FPGA system. The interface driver module 5214 is directly connected to the interface module 524 and is responsible for accurately transmitting the interactive information collected from the device under test, such as input signals and output responses, to the simulation test process model state machine 5213. This process ensures that the simulation test process model state machine 5213 can execute, monitor and adjust the test process according to real-time data feedback, thereby achieving accurate test control and data collection.

[0067] The simulation test calculation module 5215 is connected to the simulation test process model state machine 5213 and is used to calculate and process the device test digital signal, obtain the simulation test result and process execution timestamp information, and transmit it to the simulation test process model state machine 5213.

[0068] Among them, the simulation test calculation module 5215 is the key part responsible for data processing and analysis in the FPGA system 521. It is connected to the simulation test process model state machine 5213 and is responsible for performing complex calculations and processing on the device test digital signals transmitted from the interface module 524.

[0069] The simulation test calculation module 5215 uses built-in algorithms and mathematical models, such as signal processing, statistical analysis or machine learning technology, to analyze the collected data to extract useful information and performance indicators. After the calculation is completed, the simulation test calculation module 5215 will generate simulation test results, and combine the timestamp information provided by the time analysis module 5211 to form a complete data set containing test results and accurate execution time. Subsequently, these results and timestamp information are sent back to the simulation test process model state machine 5213 for further test decisions, state transitions or process control to ensure the continuity and synchronization of the test process.

[0070] The ADC driving module 5217 is connected to the ADC acquisition module 522 and is used to transmit the device test digital signal of the ADC acquisition module 522 to the simulation test process model state machine 5213 .

[0071] Among them, the ADC driver module 5217, as the driving part in the FPGA system, is closely connected to the ADC acquisition module 522. Its main function is to ensure that the analog signals collected from the device under test can be converted into digital signals and efficiently transmitted to the simulation test process model state machine 5213 for further processing and analysis, thereby realizing accurate data acquisition and test process control.

[0072] The DAC driving module 5218 is connected to the DAC output module 523 and is used to transmit the test control analog signal of the simulation test process model state machine 5213 to the device under test.

[0073] Among them, the DAC driving module 5218 is connected to the DAC output module 523. Its function is to receive the digital control signal generated by the simulation test process model state machine 5213, convert it into an analog signal, and transmit it to the device under test to implement the required test stimulus or control command to ensure that the test process can be carried out according to the predetermined simulation environment.

[0074] In some embodiments, Figure 5 As shown, the workflow of the simulation test process model state machine 5213 for real-time simulation testing is as follows: (1) State definition and design: The state machine contains multiple states (state 1, state 2, and so on to state N), each state corresponding to a specific operation in the test flow.

[0075] (2) Initial waiting: The state machine is initially in IDLE mode, waiting for the scheduled time point T2 to arrive.

[0076] (3) Time trigger and state transition: The time analysis module 5211 continuously monitors the time, and when the system time reaches T2, the state machine is triggered to enter the first state (state 1).

[0077] (4) Status execution and timestamp recording: In state 1, the FPGA drives the IO interface module 524 to make the designated channel output a high level and records the timestamp of this operation.

[0078] When the system time reaches T 2-1 When the state machine switches to state 2, the FPGA drives the ADC acquisition interface to collect analog data and record the timestamp.

[0079] As the time data is updated, the state machine transitions to subsequent states in a predetermined timestamp sequence until state N.

[0080] (5) Analog processing: In state N, the FPGA drives the DAC simulation interface to output analog data and records the timestamp of this operation.

[0081] (6) Test completion and data upload: After all states are executed, the state machine returns to the IDLE state and waits for the next test flow instruction.

[0082] During the test, the FPGA performs the necessary simulation test calculations and uploads the calculation results together with the timestamp information to the computer.

[0083] In the workflow of the real-time simulation test process state machine, if the operation in any state (state 1, state 2, ..., state N) fails to execute successfully or does not achieve the expected result, the state machine will not continue to execute the operation of the next state. Instead, it will determine that the test process has failed and return to the initial waiting mode, that is, the IDLE state. This design ensures the robustness and reliability of the test process. By returning to the initial state when a failure is detected, the system can avoid error propagation, prevent possible system damage, and provide opportunities for troubleshooting and system recovery. In addition, this also allows the system to flexibly handle test interruptions and failures, improving the overall efficiency and effectiveness of the test process.

[0084] Through the above process, the real-time simulation test process state machine ensures the precise timing and sequential execution of test operations, while using the high-speed processing capability of FPGA to achieve efficient simulation testing. The parallel processing capability of FPGA allows all modules to run simultaneously without interfering with each other, realizing nanosecond-level real-time simulation test process. This precisely controlled and automated test process greatly improves the efficiency and accuracy of simulation testing.

[0085] The data encoding module 5216 is connected to the simulation test process model state machine 5213 and is used to encode the simulation test results and process execution timestamp information to obtain encoded data, and transmit the encoded data to the computer device 4.

[0086] Among them, the data encoding module 5216 plays a key role in the FPGA system 521 to convert the simulation test results and process execution timestamp information into a format suitable for transmission.

[0087] The data encoding module 5216 is closely connected to the simulation test process model state machine 5213. Once the state machine completes the test process of the device under test and receives the results and corresponding timestamp information from the simulation test calculation module 5215, the data encoding module 5216 encodes the data. The encoding process may involve data compression, formatting or encapsulation into packets of a specific protocol to ensure the integrity and reliability of the data during transmission. The encoded data, or encoded data, is then transmitted back to the computer device 4 through the communication interface between the FPGA system 521 and the computer device 4, such as a data bus such as Ethernet / PCI / PXI.

[0088] In the computer device 4, these encoded data are further decoded, stored and analyzed to provide the tester with a detailed report on the performance of the device under test, thereby completing the data loop of the entire simulation test process.

[0089] In some embodiments, the interface module 524 includes an IO interface 5241 and a bus interface 5242. The IO interface 5241 is used for data interaction between the device under test and the FPGA system 521, and the bus interface 5242 is used for the FPGA system 521 to communicate with the outside using multiple data transmission protocols.

[0090] Specifically, the IO interface 5241 directly connects the device under test and the FPGA system 521, enabling them to perform data interaction, including sending control commands, reading status information, and exchanging test data, etc. This interface provides the FPGA system 521 with the ability to communicate directly with the device under test, supporting input and output operations of digital or analog signals.

[0091] The bus interface 5242 expands the communication capability between the FPGA system 521 and external devices. It supports multiple standard serial or parallel data transmission protocols, such as serial port, CAN, USB, Ethernet, etc., allowing the FPGA system 521 to communicate with a wider range of external devices or networks at high speed. Through the bus interface 5242, the FPGA system 521 can be integrated into a more complex test environment to achieve data sharing and collaborative work with external devices.

[0092] The combination of the two interface modules 524 provides the FPGA system 521 with flexible data interaction capabilities, enabling it to adapt to various testing requirements and application scenarios.

[0093] In some embodiments, the interface driver module 5214 includes an IO interface driver module 52141 connected between the IO interface 5241 and the simulation test process model state machine 5213 , and a bus interface driver module 52142 connected between the bus interface 5242 and the simulation test process model state machine 5213 .

[0094] The IO interface driver module 52141 connects the IO interface 5241 and the simulation test process model state machine 5213 to process the input and output of digital signals to ensure that the state machine can control and monitor the state of the device under test.

[0095] The bus interface driver module 52142 is responsible for connecting the bus interface 5242 and the simulation test process model state machine 5213, supporting multiple data transmission protocols, so that the FPGA system 521 can perform complex data exchange with external systems.

[0096] These driver modules act as bridges to ensure that the simulation test process model state machine 5213 can accurately control the operation of the interface module 524, achieve effective communication with the device under test, and thus drive the entire simulation test process to proceed smoothly. Through this modular design, the FPGA system 521 can flexibly adapt to different test requirements and provide efficient and reliable test solutions.

[0097] In some embodiments, the time analysis module 5211 includes a analysis processing module 52111 and a counter 52112. The synchronization timing module 51 is used to generate a second pulse signal according to the time information, the analysis processing module 52111 is used to analyze the time information, and the counter 52112 is used to synchronize the internal time of the FPGA simulation test board 52 according to the second pulse signal.

[0098] Specifically, the time analysis module 5211 is composed of two parts: the analysis processing module 52111 and the counter 52112, which are responsible for realizing the time synchronization within the system. The slave synchronization timing module 51 plays the role of providing accurate time reference in this process. It generates a second pulse signal (PPS) with one pulse per second based on the received high-precision time information.

[0099] The function of the parsing and processing module 52111 is to parse the received time information and convert it into a format that can be recognized and processed by the FPGA system 521 to ensure the accuracy and availability of the time information.

[0100] The counter 52112 uses the second pulse signal sent from the synchronous timing module 51 to synchronize the internal clock of the FPGA simulation test board 52 to ensure that all test operations can be performed at the correct time point.

[0101] Through this mechanism, the time resolution module 5211 provides a stable time base for the entire simulation test process, so that the test activities can be synchronized with the global time and achieve precise timing control, which is crucial for simulation tests that require high-precision synchronization.

[0102] In some embodiments, time information is transmitted from the synchronous timing module 51 to the parsing processing module 52111 via the UART time protocol.

[0103] The slave synchronization timing module 51 transmits the precise time information obtained from the master synchronization timing module 2 or the satellite timing module 1 (such as the Beidou timing module) to the analysis processing module 52111 through the UART time protocol. The UART (Universal Asynchronous Receiver / Transmitter) time protocol is a serial communication protocol that allows time information to be transmitted between devices in digital form.

[0104] The parsing processing module 52111 then parses the received time information and converts it into a form that can be understood and used by the FPGA system 521. This conversion process may involve format conversion, timestamp extraction, or synchronization with other system time bases.

[0105] Once the parsing is completed, the time information can be used to synchronize the internal clock of the FPGA simulation test board 52, drive the simulation test process model state machine 5213 to trigger the test process at the predetermined time, and trigger the ADC acquisition module 522 and the DAC output module 523 to perform operations at the correct time point.

[0106] In this way, the slave timing synchronization module 51 ensures that the entire simulation test platform can operate under a unified time reference, thereby achieving precise time control and synchronization, which is essential for performing high-precision and high-reliability simulation tests.

[0107] In some embodiments, the switch 3 is connected to the slave synchronization timing module 51 via a timing bus, and the timing bus includes an Ethernet bus.

[0108] In this embodiment, the connection between the switch 3 and the slave synchronization timing module 51 is realized through the timing bus, where the timing bus refers to a physical and logical channel for transmitting time synchronization signals. The Ethernet bus is a form of timing bus, which uses standard Ethernet technology to transmit IEEE1588 Precision Time Protocol (PTP) information, thereby achieving high-precision time synchronization of devices in the network.

[0109] In this way, the slave timing module 51 can receive time synchronization signals from the switch 3 and convert these signals into time information suitable for use by the FPGA system 521, thereby ensuring the clock synchronization of all devices in the entire test platform and meeting the needs of high-precision simulation testing. This Ethernet-based timing bus method is not only cost-effective, but also easy to integrate into the existing network infrastructure, providing a reliable and flexible time synchronization solution for the test platform.

[0110] In some embodiments, the computer device 4 is connected to the FPGA simulation test board 52 via a data bus, and the data bus includes a PCI bus, a PXI bus, or an Ethernet bus.

[0111] In this embodiment, the connection between the computer device 4 and the FPGA simulation test board 52 is realized through a data bus, and such a design allows high-speed and efficient data transmission and communication. The data bus may include multiple types of buses to adapt to different transmission requirements and system architectures.

[0112] The PCI (Peripheral Component Interconnect) bus is a high-speed serial computer expansion bus standard, commonly used to connect high-performance hardware components such as graphics cards and network cards.

[0113] The PXI (PCI eXtensions for Instrumentation) bus is a computer bus designed for measurement and automation applications. It supports synchronous clock and trigger signals and is very suitable for test and measurement systems that require precise time control.

[0114] The Ethernet bus is a widely used local area network technology that transmits data through standard network protocols. It has the characteristics of high cost-effectiveness, good compatibility and easy expansion.

[0115] These data buses provide a stable and reliable communication path between the computer device 4 and the FPGA simulation test board 52, allowing the computer to issue test instructions and configuration parameters while receiving test data and results from the FPGA board, thereby realizing a complex simulation test process.

[0116] In some embodiments, the synchronous real-time simulation test system process can refer to Figure 6 , Figure 6 The simulation test execution process from the computer device to the FPGA system is described. First, the computer device is responsible for establishing the simulation test model and generating simulation test process instructions and start time instructions T2 based on this model. These instructions are then sent to the FPGA system, which parses these instructions and establishes the corresponding simulation test process state machine. Inside the FPGA system, the state machine waits until the system time reaches the predetermined timestamp T2, triggering the state machine to run and execute the simulation test process. After the test is completed, the FPGA system will store the test results and the corresponding timestamp information, and upload this information back to the computer device, thus completing the entire simulation test cycle. This process ensures the precise timing and automated execution of the test, improving the efficiency and accuracy of the test.

[0117] The calculation processing time of the software in this embodiment under the window platform is at least in the millisecond level, and the calculation processing time of the software under the RTOS real-time system is at least in the microsecond level. The platform of the embodiment of the present invention runs under the synchronous system, and each simulation test process model runs at the set timestamp moment, eliminating the communication time between the computer and the hardware board and the processing time of the computer. The parallelism and real-time performance of the FPGA are used to directly operate the process model, and the test results and timestamps are directly uploaded. The real-time performance can reach the nanosecond level, and the simulation test process can be responded to in a timely manner.

[0118] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A synchronous real-time simulation test platform based on FPGA, characterized in that: It includes satellite timing module, main synchronization timing module, switch, computer equipment and FPGA simulation test front end; The satellite timing module is used to obtain time information through satellite signals and transmit the time information to the main synchronization timing module; The switch is connected to the main synchronous timing module, and is used to transmit the time information to the computer device and the FPGA simulation test front end respectively; The computer device is used to establish a simulation test model according to the device under test, and generate a simulation test flow instruction and a flow trigger timestamp mark according to the simulation test model and the time information, and then send the simulation test flow instruction and the flow trigger timestamp mark to the FPGA simulation test front end; The FPGA simulation test front end is used to perform simulation testing on the device under test according to the time information, the process trigger timestamp mark and the simulation test process instructions, obtain simulation test results and process execution timestamp information, and transmit the simulation test results and the process execution timestamp information to the computer device.

2. The platform according to claim 1, characterized in that The FPGA simulation test front end includes a slave synchronization timing module and an FPGA simulation test board; the slave synchronization timing module is connected between the FPGA simulation test board and the switch, and is used to transmit the time information; The FPGA simulation test board is connected to the computer device.

3. The platform according to claim 2, characterized in that: The FPGA simulation test board includes an FPGA system, an ADC acquisition module, a DAC output module and an interface module; The FPGA system is connected to the computer device and the slave synchronization timing module respectively; The ADC acquisition module is connected to the FPGA system, and is used to collect the analog signal of the device under test and convert it into a device test digital signal and transmit it to the FPGA system for connection; The DAC output module is connected to the FPGA system and is used to convert the digital signal output by the FPGA system into a test control analog signal and transmit it to the device under test; The interface module is connected to the FPGA system and is used for information exchange between the FPGA system and the device under test.

4. The platform according to claim 3, characterized in that: The FPGA system includes a time analysis module, an instruction decoding module, a simulation test process model state machine, an interface driver module, a simulation test calculation module, a data encoding module, an ADC driver module and a DAC driver module; The time analysis module is connected to the slave synchronization timing module and is used to convert the time information into a format that can be recognized and processed by the FPGA system; The instruction decoding module is connected to the computer device and is used to decode the simulation test process instruction to obtain the simulation test process decoding instruction; The simulation test process model state machine is connected to the instruction decoding module, and is used to decode the instruction and the time information according to the simulation test process, and execute the test process on the device under test; The interface driver module is connected to the interface module and is used to transmit the interaction information of the device under test to the simulation test process model state machine; The simulation test calculation module is connected to the simulation test process model state machine, and is used to calculate and process the device test digital signal, obtain the simulation test result and the process execution timestamp information, and transmit them to the simulation test process model state machine; The data encoding module is connected to the simulation test process model state machine, and is used to encode the simulation test result and the process execution timestamp information to obtain encoded data, and transmit the encoded data to the computer device; The ADC driving module is connected to the ADC acquisition module and is used to transmit the device test digital signal to the simulation test process model state machine; The DAC driving module is connected to the DAC output module and is used to transmit the test control simulation signal of the simulation test process model state machine to the device under test.

5. The platform according to claim 4, characterized in that The interface module includes an IO interface and a bus interface. The IO interface is used for data interaction between the device under test and the FPGA system, and the bus interface is used for the FPGA system to communicate with the outside through multiple data transmission protocols.

6. The platform according to claim 5, characterized in that The interface driver module includes an IO interface driver module and a bus interface driver module. The IO interface driver module is connected between the IO interface and the simulation test process model state machine, and the bus interface driver module is connected between the bus interface and the simulation test process model state machine.

7. The platform according to claim 4, characterized in that The time analysis module includes a analysis processing module and a counter. The slave synchronization timing module is used to generate a second pulse signal according to the time information. The analysis processing module is used to analyze the time information. The counter is used to synchronize the internal time of the FPGA simulation test board according to the second pulse signal.

8. The platform according to claim 7, characterized in that The slave synchronous timing module transmits the time information to the analysis processing module through the UART time protocol.

9. The platform according to claim 2, characterized in that: The switch is connected to the slave synchronous timing module via a timing bus, and the timing bus includes an Ethernet bus.

10. The platform according to claim 2, characterized in that The computer device is connected to the FPGA simulation test board through a data bus, and the data bus includes a PCI bus, a PXI bus or an Ethernet bus.

Images