CPU bottleneck analysis model based on performance counter

Abstract

The invention belongs to the field of computer system construction, and particularly relates to a CPU bottleneck analysis model based on a performance counter. The technical problems that in a method for discovering the performance bottleneck of the CPU by building a CPI stack in the prior art, average delay evaluation of failure events needed by performance evaluation is limited, failure delay is difficult to fully expose due to the streamline technology of a modern processor, and therefore discovering of the performance bottleneck of the CPU by the CPI stack is affected are solved. According to the method, each clock cycle pause of a program instruction is allocated to a corresponding failure event, and a relationship between the instruction pause and the failure event is obtained by extracting a key performance signal in a program execution process based on an interactive analogy model, so that a performance model is constructed and is used for guiding program optimization and processor hardware iteration. The CPIstack algorithm constructed by using the performance counter can be deployed on a prototype verification platform, and the performance of the processor can be accurately evaluated.

Description

Technical Field

[0001] The present invention belongs to the field of computer system construction, and in particular relates to a method for constructing a multi-issue processor performance model by using a performance counter. Background Art

[0002] Performance analysis has always been an important basis for processor design iteration and software optimization, and is also a hot research topic in the field of computer architecture. However, how to accurately identify the performance bottleneck of a processor is a very challenging problem. Performance counters are a series of key performance information visible to programmers, such as the number of instructions, memory access failure rate, branch prediction failure rate, etc. How to analyze performance from this information, find performance bottlenecks, and optimize software and hardware accordingly is a hot issue in CPU performance analysis.

[0003] CPU performance bottlenecks usually include computing resource competition, memory access failures, branch prediction failures, TLB failures, etc. The CPI stack is an important means of analyzing CPU performance bottlenecks. The CPI stack presents the cycle number distribution of instructions in the form of a bar graph, including the basic cycle number (the number of instruction cycles under ideal hardware conditions) and the instruction delay caused by various failure events. By building a CPI stack, the performance bottleneck of the CPU can be quickly discovered. The traditional CPI stack is obtained by multiplying the number of failure events (such as memory access failures) by the average delay of the failure event. However, this method has two significant disadvantages: (1) The average delay of the failure event is difficult to evaluate (2) Modern processors hide the failure delay through pipeline technology. In addition, existing work only supports the construction of CPI stacks for single-issue processors. In fact, in order to improve the performance of the processor, modern commercial processors support multi-issue technology, that is, to achieve instruction parallelism through multiple pipelines. Summary of the invention

[0004] (I) Purpose of the invention

[0005] The purpose of the present invention is to propose a method for constructing a multi-issue processor performance model using performance counters, so as to solve the technical problem in the prior art of discovering the performance bottleneck of the CPU by constructing a CPI stack, that the average delay evaluation of the failure events required for performance evaluation is limited and the pipeline technology of modern processors makes it difficult to fully expose the failure delay, thereby affecting the CPI stack to discover the performance bottleneck of the CPU.

[0006] (II) Technical solution

[0007] In order to achieve the above objectives and solve the above technical problems, the technical solutions of the present invention are as follows:

[0008] The CPU bottleneck analysis model based on performance counters includes the following steps:

[0009] Step 1: Build a multi-issue processor performance model

[0010] The multi-issue processor supports four pipelines: scalar fixed-point, scalar floating-point, vector fixed-point, and vector floating-point;

[0011] There is no resource conflict between multiple pipelines. When one pipeline is paused, other pipelines can run normally.

[0012] The CPI of the multi-issue processor depends on the pipeline with the longest cycle number;

[0013] For pipeline i, the number of cycles it executes is:

[0014] Cycles i =CPI i *Instructions i

[0015] The execution cycle number of the multi-issue processor is: Cycles_tot = Max (Cycles i )

[0016] The CPI of a multi-issue processor is:

[0017] Instructions i is the number of instructions of the i-th pipeline;

[0018] Step 2: Build a CPI stack model using key performance counter signals

[0019] Build a CPI stack, insert a monitor in the instruction issuance phase, and use key performance counting signals to monitor the issuance status of instructions in each cycle of the processor; key performance counting signals include: no instruction is issued in the current cycle FXU_stall, whether there is a RAW stall in the current cycle RAW_stall, whether there is a dcache invalidation operation in the current cycle dcache_stall, whether icache is invalid in the current cycle icache_stall, branch prediction invalidation Branch_miss, and multiplication and division operation unit conflict multi_div_contention;

[0020] Ideally, instructions can be issued to the execution unit without stopping, and the processor's CPI = 1;

[0021] Instruction failure includes the following two situations:

[0022] Front-end failure: Pipeline stalls caused before the transmitter, including instruction fetch failures and stalls caused by dependencies;

[0023] Back-end failure: that is, pipeline stalls caused after the transmitter, including branch prediction failures, ALU component conflicts that generate FLUSH signals, flushing the pipeline and causing stalls;

[0024] When a pause occurs, monitor whether there is a RAW pause;

[0025] If it exists, it further determines whether it is a dcache access failure, that is, a stall caused by a load instruction. If so, dcache stall increases by 1; otherwise, dep stall increases by 1;

[0026] If there is no RAW stall, first check whether there is an instruction cache access failure. If so, icachestall is incremented by 1. Otherwise, determine whether there is a branch prediction failure. If so, branch pred stall is incremented by branch prediction failure delay. If not, the failure is attributed to a computing unit conflict, that is, ALU stall is incremented by 1.

[0027] Step 3: For a multi-issue processor, the four pipelines work in parallel. Use step 2 to build the CPI stack model of each pipeline. At the same time, count the number of instructions in each pipeline, and use the formula in step 1 to calculate the CPI of the multi-issue processor.

[0028] (III) Effective income

[0029] 1. The present invention constructs CPIstack to quickly obtain processor performance bottlenecks and understand program optimization and processor hardware iteration.

[0030] 2. The present invention proposes a performance model for modern processors;

[0031] 3. The algorithm of constructing CPIstack using performance counters in the present invention can be deployed on a prototype verification platform and accurately evaluate processor performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 : Schematic diagram of interval analysis model;

[0033] Figure 2 :It is a code example of the present invention;

[0034] Figure 3 , is a logic block diagram of a 4-transmit processor;

[0035] Figure 4 , is a schematic diagram of the CPI stack construction of the shaping pipeline of the present invention;

[0036] Figure 5 , a flow chart for constructing the CPI stack of the present invention. DETAILED DESCRIPTION

[0037] The present invention is explained and described in detail below with reference to the accompanying drawings.

[0038] The basic idea of ​​the present invention is as follows: The present invention allocates each clock cycle pause of a program instruction to a corresponding failure event. The method is based on the interval analysis model, and by extracting key performance signals during program execution, the relationship between instruction pauses and failure events is obtained, thereby constructing its performance model, which is used to guide program optimization and processor hardware iteration.

[0039] Modern processors use superscalar pipeline technology to achieve overlapping execution of multiple instructions, thereby improving the throughput of the processor. In superscalar processors, multiple instructions are executed in parallel to hide the failure delay. In other words, when one of the instructions fails to access memory, subsequent unrelated instructions can still be issued normally and will not cause the pipeline to stall. Therefore, the processor performance model focuses on the entire pipeline rather than each instruction. In order to describe this behavioral feature of the processor, Stijn et al. proposed the interval analysis model, such as Figure 1 As shown in Figure 1. This model uses the concept of "interval" to describe the IPC of the processor. The execution of the processor is divided into multiple intervals caused by failure events. Each interval consists of an issue phase and a stall phase. Figure 1 The interval analysis model is shown, and the processor stalls are caused by events such as branch prediction failure and icache failure.

[0040] The following is an analysis of the causes of failure events: Ideally, the processor can execute at the maximum emission rate, but due to factors such as hardware overhead limitations, many types of failure events often cause the processor to pause. Among them, cache failure is the most typical type. Modern processors use cache technology to effectively reduce data access latency, but due to limited capacity and other reasons, the following cache failures often occur:

[0041] ① Long d-cache miss: When a load instruction fails to cache, if subsequent read-after-write instructions need to use the memory access data, the processor will pause until the data is ready. Figure 2 As shown, instructions 1 and 4 are dependent on read-after-write, that is, instruction 4 can be issued only when register x1 is ready. If the load implementation delay is 100 cycles, the issuance cycle of instruction ④ is 101.

[0042] ②Branch misprediction: When branch prediction fails, the processor flushes the wrong branch instruction and starts executing instructions from the correct branch, causing the processor to stall.

[0043] ③Barrier / syn instructions: During program execution, synchronization instructions are often required to maintain the atomicity of operations. Synchronization instructions will block the issuance of subsequent instructions until they are completed, thus causing a pause in the pipeline.

[0044] ④ALU operation unit conflict: Long-delay ALU instructions such as MULT, DIV, etc. will occupy the operation unit for multiple beats, thus causing the pipeline to pause.

[0045] A method for constructing a multi-issue processor performance model using performance counters specifically comprises the following steps:

[0046] Step 1: Build a multi-issue processor performance model

[0047] like Figure 3 , is the logic block diagram of a 4-issue processor. The processor supports scalar fixed-point, scalar floating-point, vector fixed-point, and vector floating-point pipelines. There is no resource conflict between multiple pipelines. When one of the pipelines is stalled, the other pipelines can still execute normally. In fact, the CPI of a multi-issue processor depends on the pipeline with the longest cycle number. For pipeline i, the number of cycles it executes is:

[0048] Cycles i =CPI i *Instructions i

[0049] The execution cycle number of the multi-issue processor is: Cycles_tot = Max (Cycles i )

[0050] The CPI of a multi-issue processor is:

[0051] Step 2: Build a CPI stack model using performance counter signals

[0052] Hardware performance counters are a set of registers that can record the number of times (micro)architecture events occur. These events usually include the number of clock cycles, the number of executed instructions, the number of branch prediction failures, the number of misses / hit counts of caches at all levels, the number of misses / hit counts of TLB (Translation Look-aside Buffer), etc. In addition, the number of blocking cycles caused by events can also be obtained through performance counters. Using this information, we can more efficiently monitor the system status, efficiently utilize hardware resources, and optimize the computer system structure. Therefore, almost all modern processors are equipped with performance counter units (PMUs). How to use the provided hardware performance counters to build a CPI stack and identify the performance bottleneck of the program based on this is the key technology of the present invention. Figure 4 Taking the integer pipeline as an example, a monitor is inserted in the instruction issuance stage to monitor the issuance of instructions in each cycle. Ideally, instructions can be issued to the execution unit without pause, and at this time, the processor's CPI = 1. However, due to reasons such as instruction cache access failure, some cycles cannot issue instructions, which will cause stalls. The basic idea of ​​building a CPI stack is to count the number of cycles in which instructions cannot be issued and the reasons for stalls. According to the analysis of the pipeline, the reasons for stalls are divided into two categories: front-end misses, which are pipeline stalls caused before the launch end, mainly including instruction fetch failures, correlation-induced stalls, etc.; back-end misses, which are pipeline stalls caused after the launch end, including branch prediction failures, ALU component conflicts, etc., which generate FLUSH signals, flush the pipeline, and thus cause stalls.

[0053] The processor status is monitored using key performance count signals, which are shown in Table 1.

[0054] Table 1: Key performance counter signals

[0055]

[0056] Figure 5 Schematic diagram of the CPI stack construction algorithm flow of the present invention.

[0057] When a pause occurs, monitor whether there is a RAW pause;

[0058] If it exists, it is further determined whether the stall is caused by dcache access failure (i.e. load instruction). If so, dcache stall is incremented by 1; otherwise, dep stall is incremented by 1.

[0059] If there is no RAW stall, first check whether there is an instruction cache access failure. If so, icachestall is incremented by 1. Otherwise, determine whether there is a branch prediction failure. If so, branch pred stall is added with branch prediction failure delay. If not, the failure is attributed to the conflict of the computing unit, that is, ALU stall is incremented by 1.

[0060] Step 3: For a multi-issue processor, the four pipelines work in parallel. Use step 2 to build the CPI stack model of each pipeline. At the same time, count the number of instructions in each pipeline, and use the formula in step 1 to calculate the CPI of the multi-issue processor.

[0061] The above algorithm covers most of the causes of processor failure. Other causes such as TLB stall and barrier stall are not counted because of their low proportion.

[0062] The above contents are further detailed descriptions of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A CPU bottleneck analysis model based on performance counters, characterized in that: The construction of the CPU bottleneck analysis model includes the following steps: Step 1: Build a multi-issue processor performance model The multi-issue processor supports four pipelines: scalar fixed-point, scalar floating-point, vector fixed-point, and vector floating-point; There is no resource conflict between multiple pipelines. When one pipeline is paused, other pipelines can run normally. The CPI of the multi-issue processor depends on the pipeline with the longest cycle number; For pipeline i, the number of cycles it executes is: Cycles i =CPI i *Instructions i The execution cycle number of the multi-issue processor is: Cycles_tot = Max (Cycles i ) The CPI of a multi-issue processor is: Among them: Instuctions i is the number of instructions of the i-th pipeline; Step 2: Build a CPI stack model using key performance counter signals Build a CPI stack, insert a monitor in the instruction issuance phase, and use key performance counting signals to monitor the issuance status of instructions in each cycle of the processor; key performance counting signals include: no instruction is issued in the current cycle FXU_stall, whether there is a RAW stall in the current cycle RAW_stall, whether there is a dcache invalidation operation in the current cycle dcache_stall, whether icache is invalid in the current cycle icache_stall, branch prediction invalidation Branch_miss, and multiplication and division operation unit conflict multi_div_contention; Ideally, instructions can be issued to the execution unit without stopping, and the processor's CPI = 1; Instruction failure includes the following two situations: Front-end failure: Pipeline stalls caused before the transmitter, including instruction fetch failures and stalls caused by dependencies; Back-end failure: that is, pipeline stalls caused after the transmitter, including branch prediction failures, ALU component conflicts that generate FLUSH signals, flushing the pipeline and causing stalls; When a pause occurs, monitor whether there is a RAW pause; If it exists, it further determines whether it is a dcache access failure, that is, a stall caused by a load instruction. If so, dcache stall increases by 1; otherwise, dep stall increases by 1; If there is no RAW stall, first check whether there is an instruction cache access failure. If so, icache stall is incremented by 1. Otherwise, determine whether there is a branch prediction failure. If so, branch pred stall is incremented by branch prediction failure delay. If not, the failure is attributed to the conflict of the computing unit, that is, ALU stall is incremented by 1. Step 3: For a multi-issue processor, the four pipelines work in parallel. Use step 2 to build the CPI stack model of each pipeline. At the same time, count the number of instructions in each pipeline, and use the formula in step 1 to calculate the CPI of the multi-issue processor.

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