Performance counter based cpu bottleneck analysis model

Abstract

The present application belongs to the field of computer system construction, and particularly relates to a CPU bottleneck analysis model based on performance counter. The present application solves the technical problem that in the prior art, the average delay evaluation of the failure event required for performance evaluation is limited, and the pipeline technology of modern processors makes the failure delay difficult to be fully exposed, thereby affecting the CPI stack to discover the performance bottleneck of the CPU. In the present application, each clock cycle pause of the program instruction is assigned to the corresponding failure event, the relationship between the instruction pause and the failure event is obtained based on the interval analysis model by extracting the key performance signal in the program execution process, so as to construct the performance model and guide the program optimization and processor hardware iteration. The algorithm for constructing the CPI stack by using the performance counter can be deployed on the prototype verification platform and accurately evaluate the processor performance.

Description

Technical Field

[0001] This invention belongs to the field of computer architecture construction, specifically relating to a method for constructing a performance model of a multi-issue processor using performance counters. Background Technology

[0002] Performance analysis has always been a crucial basis for processor design iteration and software optimization, and a hot research topic in the field of computer architecture. However, accurately identifying the performance bottlenecks of a processor remains extremely challenging. Performance counters provide programmers with a series of key performance information, such as instruction count, memory access miss rate, and branch prediction miss rate. Analyzing performance from this information, identifying performance bottlenecks, and optimizing hardware and software accordingly is a key area of ​​research in CPU performance analysis.

[0003] CPU performance bottlenecks typically include computational resource contention, memory access failures, branch prediction failures, and TLB failures. The CPI stack is an important tool for CPU performance bottleneck analysis. The CPI stack presents the instruction cycle distribution in a bar chart, including the basic cycle count (the number of instruction cycles under ideal hardware conditions) and the instruction latency caused by various failure events. By constructing a CPI stack, CPU performance bottlenecks can be quickly identified. The traditional CPI stack is obtained by multiplying the number of failure events (such as memory access failures) by the average latency of the failure events. However, this method has two significant drawbacks: (1) the average latency of failure events is difficult to evaluate; (2) modern processors hide failure latency through pipeline technology. In addition, existing work only supports the construction of CPI stacks for single-issue processors. In fact, in order to improve processor performance, modern commercial processors support multi-issue technology, that is, instruction parallelism is achieved through multiple pipelines. Summary of the Invention

[0004] (I) Purpose of the Invention

[0005] The purpose of this invention is to propose a method for constructing a multi-issue processor performance model using performance counters. This addresses the technical problem in existing methods for discovering CPU performance bottlenecks using CPI stacks, where the average latency assessment of failure events required for performance evaluation is limited, and the pipeline technology of modern processors makes it difficult to fully expose failure latency, thus affecting the discovery of CPU performance bottlenecks using CPI stacks.

[0006] (II) Technical Solution

[0007] To achieve the above objectives and solve the above technical problems, the technical solution of the present invention is as follows:

[0008] The CPU bottleneck analysis model based on performance counters is constructed through the following steps:

[0009] Step 1: Construct a multi-issue processor performance model

[0010] The multi-issue processor supports four pipelines: scalar fixed-point, scalar floating-point, vector fixed-point, and vector floating-point.

[0011] There are no resource conflicts between multiple production lines, and when one production line stops, the other production lines can continue to operate normally.

[0012] The CPI of the multi-issue processor depends on the pipeline with the longest cycle count;

[0013] For pipeline i, the number of cycles it executes is:

[0014] Cycles i =CPI i *Instructions i

[0015] The number of execution cycles for the multi-issue processor is: Cycles_tot = Max(Cycles i )

[0016] The CPI of the multi-issue processor is:

[0017] Among them: Instructions i Let be the number of instructions in the i-th pipeline;

[0018] Step 2: Construct a CPI stack model using key performance indicator (KPI) count signals.

[0019] A CPI stack is constructed, and a monitor is inserted during the instruction issue phase to monitor the instruction issue status of each processor cycle using key performance counter signals. Key performance counter signals include: no instruction issued in the current cycle (FXU_stall), RAW pause (RAW_stall) in the current cycle, dcache invalidation operation (dcache_stall) in the current cycle, icache invalidation (icache_stall) in the current cycle, branch prediction failure (Branch_miss), and multiplication / division unit conflict (multi_div_contention).

[0020] Ideally, instructions can be issued to the execution unit without interruption, and the processor's CPI = 1;

[0021] Instruction failure includes the following two situations:

[0022] Front-end failure: Pipeline stalls caused by previous issues at the transmitter, including instruction fetch failures and stalls caused by correlations;

[0023] Back-end failure: refers to pipeline stalls caused after the transmitter, including branch prediction failure, ALU component collisions generating FLUSH signals, which flush the pipeline and cause stalls;

[0024] When a pause occurs, monitor for the presence of a RAW pause;

[0025] If it exists, then further determine whether it is a dcache access failure, i.e., a pause caused by a load instruction. If so, increment dcache stall by 1; otherwise, increment dep stall by 1.

[0026] If there is no RAW pause, first check if there is an instruction cache access failure. If there is, increment icachestall by 1. Otherwise, determine if there is a branch prediction failure. If there is, add the branch prediction failure delay to the branch prediction stall. If there is no failure, attribute the failure to an arithmetic unit conflict, i.e., increment the ALU stall by 1.

[0027] Step 3: For a multi-issue processor, the four pipelines work in parallel. Use Step 2 to build the CPI stack model for each pipeline, count the number of instructions in each pipeline, and use the formula in Step 1 to calculate the CPI of the multi-issue processor.

[0028] (III) Effective Returns

[0029] 1. This invention uses CPIstack to quickly identify processor performance bottlenecks and to determine program optimization and processor hardware iteration.

[0030] 2. This invention proposes a performance model for modern processors;

[0031] 3. The algorithm of this invention, which uses performance counters to build CPIstack, can be deployed on a prototype verification platform and accurately evaluate processor performance. Attached Figure Description

[0032] Figure 1 : This is a schematic diagram of the interval analysis model;

[0033] Figure 2 This is a code example for the present invention;

[0034] Figure 3 Here is a logic block diagram of a 4-transmitter processor;

[0035] Figure 4 A schematic diagram of the CPI stack construction of the integral pipeline of the present invention;

[0036] Figure 5 The diagram below shows the CPI stack construction process of this invention. Detailed Implementation

[0037] The present invention will now be explained and described in detail with reference to the accompanying drawings.

[0038] The basic idea of ​​this invention is as follows: This invention assigns each clock cycle pause of a program instruction to a corresponding failure event. Based on an interval analysis model, this method extracts key performance signals during program execution to obtain the relationship between instruction pauses and failure events, thereby constructing a performance model to guide program optimization and processor hardware iteration.

[0039] Modern processors utilize superscalar pipelines to achieve overlapping execution of multiple instructions, thereby improving throughput. Superscalar processors hide latency by executing multiple instructions in parallel. In other words, if one instruction experiences a memory access failure, subsequent unrelated instructions can still be issued normally without causing pipeline stalls. Therefore, processor performance models focus on the entire pipeline, rather than individual instructions. To describe this behavioral characteristic of processors, Stijn et al. proposed the interval analysis model, such as... Figure 1 As shown, this model uses the concept of "interval" to characterize the processor's IPC. The processor's execution is divided into multiple intervals caused by failure events. Each interval consists of an issue phase and a stall phase. Figure 1 The interval analysis model shows that processor pauses are caused by events such as branch prediction failure and icache failure.

[0040] The causes of these failure events are analyzed below: Ideally, a processor can execute at its maximum emit rate, but due to hardware overhead limitations and other factors, various failure events often cause processor stalls. Cache misses are the most typical type. Modern processors utilize caching technology to effectively reduce data access latency, but due to limited capacity and other reasons, the following cache misses often occur:

[0041] ① Long D-Cache Miss: When a cache miss occurs during a load instruction, if a subsequent write-after-read instruction needs to access the same memory data, the processor will pause until the data is ready. For example... Figure 2 As shown, instructions 1 and 4 are read-after-write related, meaning that instruction 4 can only be issued when register x1 is ready. If the load implementation delay is 100 cycles, the issue cycle of instruction 4 is 101 cycles.

[0042] ②Branch misprediction: When a branch prediction failure occurs, the processor will flush out the erroneous branch instructions and start execution from the correct branch, thus causing the processor to pause.

[0043] ③ Barrier / syn instructions: To maintain the atomicity of operations during program execution, synchronization instructions are often introduced. Synchronization instructions block the issuance of subsequent instructions until they are completed, thus causing pipeline stalls.

[0044] ④ ALU unit conflicts: Long-latency ALU instructions such as MULT and DIV will occupy the arithmetic unit for multiple cycles, thus causing pipeline stalls.

[0045] A method for constructing a multi-issue processor performance model using performance counters includes the following steps:

[0046] Step 1: Construct a multi-issue processor performance model

[0047] like Figure 3 This is a logic block diagram of a 4-issue processor. This processor supports four pipelines: scalar fixed-point, scalar floating-point, vector fixed-point, and vector floating-point. There are no resource conflicts between the pipelines. When one pipeline stalls, the others can still execute normally. In fact, the CPI of a multi-issue processor depends on the pipeline with the longest number of cycles. For pipeline i, its number of cycles is:

[0048] Cycles i =CPI i *Instructions i

[0049] The number of execution cycles for a multi-issue processor is: Cycles_tot = Max(Cycles i )

[0050] The CPI of the multi-issue processor is:

[0051] Step 2: Construct a CPI stack model using performance counting signals

[0052] Hardware performance counters are a set of registers that record the number of (micro)architectural events that occur. These events typically include clock cycles, number of instructions executed, number of branch prediction failures, number of cache misses / hits at each level, and number of TLB (Translation Look-aside Buffer) misses / hits. Furthermore, the number of blocking cycles caused by these events can also be obtained through performance counters. Using this information, we can more efficiently monitor system status, utilize hardware resources effectively, and optimize computer system architecture. Therefore, almost all modern processors are equipped with a Performance Counter Unit (PMU). The key technology of this invention is how to utilize the provided hardware performance counters to construct a CPI stack and thereby identify program performance bottlenecks. Figure 4 Taking an integer pipeline as an example, a monitor is inserted during the instruction issue phase to monitor the instruction issuance in each cycle. Ideally, instructions can be issued to the execution unit without interruption, at which point the processor's CPI = 1. However, due to reasons such as instruction cache access misses, some cycles may fail to issue instructions, resulting in pauses. The basic idea of ​​CPI stack construction is to count the number of cycles where instructions cannot be issued and the reasons for the pauses. Based on pipeline analysis, pause causes are divided into two categories: front-end misses, which are pipeline pauses caused before the issue phase, mainly including instruction fetch failures and pauses caused by dependencies; and back-end misses, which are pipeline pauses caused after the issue phase, including pauses caused by branch prediction failures and ALU conflicts that generate FLUSH signals, flushing the pipeline and causing pauses.

[0053] The processor status is monitored using key performance counting signals, which are shown in Table 1.

[0054] Table 1: Key Performance Counter Signals

[0055]

[0056] Figure 5 This is a schematic diagram of the CPI stack construction algorithm of the present invention.

[0057] When a pause occurs, monitor for the presence of a RAW pause;

[0058] If it exists, then further determine whether the pause was caused by a invalid dcache access (i.e., a load instruction). If so, increment dcache stall by 1; otherwise, increment dep stall by 1.

[0059] If there is no RAW pause, first check if there is an instruction cache access failure. If so, increment icachestall by 1. Otherwise, determine if there is a branch prediction failure. If so, add the branch prediction failure delay to the branch pred stall. If not, attribute the failure to an arithmetic unit conflict, and increment the ALU stall by 1.

[0060] Step 3: For a multi-issue processor, the four pipelines work in parallel. Use Step 2 to build the CPI stack model for each pipeline, count the number of instructions in each pipeline, and use the formula in Step 1 to calculate the CPI of the multi-issue processor.

[0061] The above algorithm covers most of the causes of processor failure. Other causes, such as TLB stall and barrier stall, are not included in the statistics because they account for a small percentage.

[0062] The above description, in conjunction with specific embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A CPU bottleneck analysis model based on performance counters, characterized in that, The construction of the CPU bottleneck analysis model includes the following steps: Step 1: Construct a multi-issue processor performance model The multi-issue processor supports four pipelines: scalar fixed-point, scalar floating-point, vector fixed-point, and vector floating-point. There are no resource conflicts between multiple production lines, and when one production line stops, the other production lines can continue to operate normally. The CPI of the multi-issue processor depends on the pipeline with the longest cycle count; For pipeline i, the number of cycles it executes is: Cycles i =CPI i *Instructions i The number of execution cycles for the multi-issue processor is: Cycles_tot = Max(Cycles i ) The CPI of the multi-issue processor is: Among them: Installations i Let be the number of instructions in the i-th pipeline; Step 2: Construct a CPI stack model using key performance indicator (KPI) count signals. A CPI stack is constructed, and a monitor is inserted during the instruction issue phase to monitor the instruction issue status of each processor cycle using key performance counter signals. Key performance counter signals include: no instruction issued in the current cycle (FXU_stall), RAW pause (RAW_stall) in the current cycle, dcache invalidation operation (dcache_stall) in the current cycle, icache invalidation (icache_stall) in the current cycle, branch prediction failure (Branch_miss), and multiplication / division unit conflict (multi_div_contention). Ideally, instructions can be issued to the execution unit without interruption, and the processor's CPI = 1; Instruction failure includes the following two situations: Front-end failure: Pipeline stalls caused by previous issues at the transmitter, including instruction fetch failures and stalls caused by correlations; Back-end failure: refers to pipeline stalls caused after the transmitter, including branch prediction failure, ALU component collisions generating FLUSH signals, which flush the pipeline and cause stalls; When a pause occurs, monitor for the presence of a RAW pause; If it exists, then further determine whether it is a dcache access failure, i.e., a pause caused by a load instruction. If so, increment dcache stall by 1; otherwise, increment dep stall by 1. If there is no RAW pause, first check if there is an instruction cache access failure. If there is, increment the icache stall by 1. Otherwise, determine if there is a branch prediction failure. If there is, add the branch prediction failure delay to the branch prediction stall. If there is no failure, attribute the failure to an arithmetic unit conflict, i.e., increment the ALU stall by 1. Step 3: For a multi-issue processor, the four pipelines work in parallel. Use Step 2 to build the CPI stack model for each pipeline, count the number of instructions in each pipeline, and use the formula in Step 1 to calculate the CPI of the multi-issue processor.

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