Computing storage device and data processing system including same

Abstract

The invention relates to a computing storage device and a data processing system including the same. The computing storage device includes: a memory device configured to store a data unit group including a plurality of data units; and a controller configured to calculate one or more logical addresses based on the calculation operation request, to which a target data unit included in the data unit group is allocated, the target data unit being a target to perform a calculation operation in response to the calculation operation request, a starting logical address and a starting offset of the target data unit are calculated based on the information, the starting logical address being included in one or more logical addresses, data corresponding to the one or more logical addresses is read from the memory device, and the target data unit in the read data is identified.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0139537, filed on October 18, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a computing storage device and a data processing system including the computing storage device. Background Art

[0004] The storage device may be configured to store data provided by the host device in response to a write request from an external host device. In addition, the storage device may be configured to provide the stored data to the host device in response to a read request from the host device. The host device is an electronic device capable of processing data, and may include a computer, a digital camera, or a mobile phone. The storage device may be operated by being embedded in the host device, or may be manufactured in a detachable form and operated by being electrically connected to the host device. The storage device may include a memory device for storing data.

[0005] A computing storage device may be a storage device that can perform data processing and computing operations under the control of a host device. The computing storage device may reduce the data processing burden and data processing latency of the host device. In addition, if the computing storage device processes large data, the computing storage device may effectively reduce the bandwidth burden by minimizing the movement of data to the host device. Summary of the invention

[0006] In an embodiment of the present disclosure, a computing storage device may include: a memory device configured to store a data unit group including a plurality of data units; and a controller configured to calculate one or more logical addresses based on a computing operation request, a target data unit included in the data unit group is assigned to the one or more logical addresses, the target data unit is a target to be subjected to a computing operation in response to the computing operation request, calculate a starting logical address and a starting offset of the target data unit based on information, the starting logical address is included in the one or more logical addresses, read data corresponding to the one or more logical addresses from the memory device, and identify the target data unit in the read data. The computing operation request may include information on the starting logical address of the data unit group and the size of each of the plurality of data units.

[0007] In an embodiment of the present disclosure, a computing storage device may include: a memory device configured to store a data unit group including a plurality of data units; and a controller configured to calculate a first logical address to which a selected portion of a target data unit included in the data unit group has been assigned and a misalignment flag of the target data unit, and when the target data unit is determined to be misaligned data based on the misalignment flag, calculate a second logical address assigned to a remaining portion of the target data unit, read first read data corresponding to the first logical address and second read data corresponding to the second logical address from the memory device, and obtain the target data unit from the first read data and the second read data.

[0008] In an embodiment of the present disclosure, a data processing system may include: a computing storage device that allocates continuous logical addresses to data unit groups when storing data unit groups; and a host device that is configured to send a computing operation request for the data unit group to the computing storage device. The computing storage device may perform a computing operation on the data unit group in response to the computing operation request.

[0009] Other features, aspects, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a data processing system including a computing storage device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram for describing a logical address of an allocation table according to an embodiment of the present disclosure.

[0012] Figure 3 The present invention is a diagram showing an embodiment of the present invention. Figure 1 Block diagram of a computing function accelerator.

[0013] Figure 4 The present invention is a diagram showing an embodiment of the present invention. Figure 2 Schematic diagram of a first computing operation request of a table and operation information included in the first computing operation request.

[0014] Figure 5A and Figure 5B is used to describe the computing function accelerator processing according to an embodiment of the present disclosure Figure 4 FIG. 1 is a diagram of a method for requesting a first computing operation.

[0015] Figure 6 is a diagram for describing a method in which a computing function accelerator according to an embodiment of the present disclosure performs a MODIFY operation by outputting only a required logical address.

[0016] Figure 7is a diagram for describing a method in which a computing function accelerator allocates another data to be added to a table to one or more logical addresses according to an embodiment of the present disclosure.

[0017] Figure 8 : is a diagram for describing a method in which a computing function accelerator invalidates an index stored in an index cache according to an embodiment of the present disclosure.

[0018] Fig. 9A and Fig. 9B is a diagram for describing a logical address of an allocation table according to an embodiment of the present disclosure.

[0019] Fig. 10A and Fig. 10B is a diagram illustrating a process of a vector data unit 3 and a vector data unit 4 of a computing function accelerator acquisition table according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 is a block diagram illustrating a data processing system 10 including a computing storage device 200 according to an embodiment of the present disclosure.

[0022] The data processing system 10 may include a host device 100 and a computing storage device 200 .

[0023] The host device 100 may control the computing storage device 200 by sending an operation request RQ to the computing storage device 200. The operation request RQ may include a write operation request, a read operation request, and a computing operation request. For example, the host device 100 may store data in the computing storage device 200 through a write operation request. In addition, the host device 100 may read data stored in the computing storage device 200 through a read operation request.

[0024] In addition, the host device 100 can control the computing storage device 200 to perform a computing operation on the data stored in the computing storage device 200 through a computing operation request. For example, the computing operation request can be a request to perform a computing operation on one or more data units of the data unit group 221 stored in the computing storage device 200. The data unit can be a unit for performing a computing operation on the data unit group 221 according to the computing operation type. As will be described later, the data unit can be a unit for which the computing function accelerator 212 generates an index. The data unit group 221 can be composed of multiple data units.

[0025] For example, when the data unit group 221 is a database table, the data unit may be each row or column included in the database table. When the data unit group 221 is an embedded table, the data unit may be each vector data unit included in the embedded table. Hereinafter, the data unit to be executed by the computing operation request among the data units of the data unit group 221 may be referred to as the target data unit.

[0026] The operation request RQ may include operation information IF, that is, information required for the computing storage device 200 to perform the operation requested by the operation request RQ. The operation information IF of the computing operation request may include data unit group information and computing operation information.

[0027] The data unit group information may selectively include information about the starting logical address of the data unit group 221, the number of data units included in the data unit group 221, the number of elements included in each data unit, the size of the data unit, and the size of the element. The starting logical address of the data unit group 221 may be the frontmost logical address to which the data unit group 221 is allocated among the logical addresses.

[0028] According to an embodiment, if the computing storage device 200 previously knows the starting logical address of the data unit group 221 , the starting logical address of the data unit group 221 may not be transmitted as the operation information IF.

[0029] The computing operation information may optionally include information about the computing operation type, respective sequence numbers of one or more target data units, the number of target data units, one or more target offsets, the number of target offsets, one or more conditional operations, the number of conditional operations, one or more constants, and the number of constants.

[0030] Specifically, the computing operation type may be the type of computing operation requested by the computing operation request. The computing operation type of the database table may include a select (SELECT) operation, a map (PROJECT) operation, a remove (REMOVE) operation, an add (ADD) operation, or a modify (MODIFY) operation. The computing operation type of the embedded table may include an average aggregation operation, a weighted average aggregation operation, a maximum aggregation operation, or a sum aggregation operation.

[0031] When each target data unit consists of multiple elements, the target offset may indicate the element on which the computing operation is to be performed in the corresponding target data unit. The conditional operation may be an operation included in the condition of the computing operation request (e.g., a WHERE syntax in a computing operation request that has been written in structured query language (SQL) or an IF statement in a computing operation request that has been written in various programming languages). The constant may be a constant included in the condition of the computing operation request.

[0032] The computing storage device 200 may receive a computing operation request from the host device 100 and perform the computing operation requested by the computing operation request. For example, the computing storage device 200 may perform a write operation on the memory device 220 in response to a write operation request from the host device 100. In addition, the computing storage device 200 may perform a read operation on the memory device 220 in response to a read operation request from the host device 100.

[0033] Furthermore, the computing storage device 200 may perform a computing operation on one or more target data units included in the data unit group 221 in response to a computing operation request for the data unit group 221, and may send an operation result RS to the host device 100 as an execution result of the computing operation.

[0034] Computational storage device 200 may include a controller 210 and a memory device 220 .

[0035] The controller 210 may control the memory device 220 in response to the operation request RQ. The controller 210 may calculate one or more logical addresses assigned to the target data unit included in the data unit group 221 in response to the calculation operation request for the data unit group 221, may read read data corresponding to the one or more logical addresses from the memory device 220, may identify the target data unit in the read data, and may perform a calculation operation on the target data unit.

[0036] The controller 210 can effectively calculate the one or more logical addresses to which the target data unit has been allocated, regardless of whether the size of the target data unit is greater than or less than the maximum size that can be allocated to each logical address (i.e., the data size that the host device 100 can allocate to one logical address, for example, 512B). Although the target data unit is unaligned data allocated to two or more logical addresses, the controller 210 can effectively calculate the one or more logical addresses to which the target data unit has been allocated.

[0037] The controller 210 may include a main controller 211 and a computing function accelerator 212 .

[0038] The main controller 211 may receive an operation request RQ from the host device 100 and may perform an operation requested by the operation request RQ. The main controller 211 may perform a write operation and a read operation on the memory device 220 in response to the operation request RQ.

[0039] When receiving a computing operation request from the host device 100, the main controller 211 may send the computing operation request or the operation information IF to the computing function accelerator 212. In addition, the main controller 211 may receive a logical address of an allocation target data unit from the computing function accelerator 212, and may access the memory device 220 based on the logical address. Specifically, the main controller 211 may convert the logical address received from the computing function accelerator 212 into a physical address, and may access a memory area corresponding to the physical address in the memory device 220. The main controller 211 may manage mapping information between the logical address and the physical address.

[0040] Although not shown, the main controller 211 may selectively include a host interface electrically coupled to the host device 100 , a memory controller, a memory, and a processor electrically coupled to the memory device 220 .

[0041] The computing function accelerator 212 may determine a target data unit included in the data unit group 221 based on the operation information IF of the computing operation request, and may determine one or more logical addresses to which the target data unit has been allocated.

[0042] In addition, the computing function accelerator 212 can determine the starting offset and the last offset of the target data unit based on the operation information IF of the computing operation request. The starting offset of the target data unit can correspond to the number of bytes from the front position of the read data to the position where the target data unit starts, and the front position of the read data corresponds to the starting logical address of the target data unit. The last offset of the target data unit can correspond to the number of bytes from the front position of the read data to the position where the target data unit ends, and the front position of the read data corresponds to the last logical address of the target data unit. In the present disclosure, the front position of a data unit can refer to the position where the data unit starts within the read data corresponding to the starting logical address of the data unit.

[0043] In addition, when the memory device 220 outputs read data corresponding to one or more logical addresses to which the target data unit is allocated under the control of the main controller 211, the computing function accelerator 212 may obtain the target data unit from the read data based on the start offset and the last offset of the target data unit. The computing function accelerator 212 may perform a computing operation on the target data unit.

[0044] The computing function accelerator 212 may generate an index of the target data unit in response to the operation request RQ, and may store the index of the target data unit in a separate location (eg, Figure 3The index of the target data unit may include information about the target data unit. The index of the target data unit may include a starting logical address and a last logical address among one or more logical addresses to which the target data unit is allocated, a starting offset of the target data unit, and a last offset of the target data unit. When another computing operation request is received, if the index of the target data unit of the other computing operation request has been stored in the index cache 303, the computing function accelerator 212 may confirm the information of the target data unit with reference to the index already stored in the index cache 303.

[0045] In addition, when the data unit group 221 changes in response to the operation request RQ of the host device 100 (for example, when another data unit is added to the data unit group 221, or when a particular data unit is removed from the data unit group 221), the computing function accelerator 212 can effectively manage the data unit group 221 by modifying the index stored in the index cache 303.

[0046] According to an embodiment, when the data unit group 221 is stored in the memory device 220 under the control of the host device 100, the main controller 211 may allocate continuous logical addresses to the data unit group 221. The main controller 211 may map the logical addresses of the allocated data unit group 221 to the physical addresses of the memory areas in the memory device 220 where the data unit groups 221 are respectively stored. The main controller 211 may send the foremost logical address among the logical addresses of the allocated data unit group 221, that is, the starting logical address of the data unit group 221, to the host device 100. The host device 100 may specify in advance for the main controller 211 a range of logical addresses to which the data unit group 221 may be allocated. The main controller 211 may store the data unit group 221 in the memory device 220, and then may calculate one or more logical addresses that have been allocated to the target data unit in response to a calculation operation request for the data unit group 221.

[0047] According to an embodiment, when storing the data unit group 221 in the computing storage device 200, the host device 100 may allocate the data unit group 221 to consecutive logical addresses. The host device 100 may send a write operation request for the data unit group 221 and the logical address to which the data unit group 221 has been allocated to the computing storage device 200.

[0048] The memory device 220 may operate under the control of the controller 210. The memory device 220 may perform a read operation, a write operation (ie, a program operation), and an erase operation under the control of the controller 210. The memory device 220 may receive a physical address from the controller 210 and may access a memory area corresponding to the physical address.

[0049] According to an embodiment, the host device 100 may be an electronic device capable of processing data, and may include a computer, a digital camera, a mobile phone, a drone, a server, and a transmission system.

[0050] According to an embodiment, the computing storage device 200 may be a storage device including the computing function accelerator 212. The storage device may include a Personal Computer Memory Card International Association (PCMCIA) card, a smart media card, a memory stick, various multimedia cards (e.g., MMC, eMMC, RS-MMC, and micro MMC), a secure digital (SD) card (e.g., SD, mini SD, and micro SD), a universal flash memory (UFS), or a solid state drive (SSD).

[0051] According to an embodiment, the memory device 220 may include various types of memory, such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STTRAM).

[0052] Figure 2 is a diagram for describing the logical addresses of the allocation table DT according to an embodiment of the present disclosure. The table DT may be Figure 1 An example of data unit group 221 is shown.

[0053] Reference Figure 2 , the table DT may be a database table DT including rows and columns. For example, the table DT may include seven row data units R0 to R6, each of which has a size of 560B. The size of each element included in the table DT may be 8B. That is, each of the row data units R0 to R6 may include seventy elements, and therefore, the table DT may include seventy columns. The size of each row data unit may be greater than the maximum data size that can be allocated to each logical address, for example, 512B.

[0054] The table DT may be stored in the memory device 220 in row-major order. When the table DT is stored in the memory device 220 under the control of the host device 100, the main controller 211 may assign the row data units R0 to R6 listed in sequence to the consecutive logical addresses LBA0 to LBA7 in units of 512B. In this case, each of the row data units R0 to R6 may be assigned to two logical addresses. The frontmost logical address among the logical addresses to which each row data unit has been assigned may be referred to as the starting logical address of the row data unit. The last logical address among the logical addresses to which each row data unit has been assigned may be referred to as the last logical address of the row data unit. When the data assigned to each logical address is stored in the memory area of ​​the memory device 220, the main controller 211 may map each logical address to the physical address of the memory area.

[0055] For example, row data unit 0 (R0) may be assigned to logical addresses LBA0 and LBA1. Logical address 0 (LBA0) may be the starting logical address of row data unit 0 (R0). Logical address 1 (LBA1) may be the last logical address of row data unit 0 (R0). The first 512B of row data unit 0 (R0), i.e., sixty-four elements from column 0 to column 63, may be assigned to logical address 0 (LBA0). In addition, the last 48B of row data unit 0 (R0), i.e., six elements from column 64 to column 69, may be assigned to logical address 1 (LBA1). In this case, after the last 48B of row data unit 0 (R0), the first 464B of row data unit 1 (R1), i.e., 58 elements from column 0 to column 57, may be assigned to logical address 1 (LBA1).

[0056] In this way, row data units R0 to R6 can be allocated sequentially from logical address 0 (LBA0) to logical address 7 (LBA7). The starting logical address of table DT can be the front logical address 0 (LBA0) among the logical addresses LBA0 to LBA7 allocated to table DT. The last logical address of table DT can be the last logical address 7 (LBA7) among the logical addresses LBA0 to LBA7 allocated to table DT. For example, the starting logical address of table DT is logical address 0 (LBA0). In the logical address space of the data processing system 10, the number of bytes from the starting position of logical address 0 (LBA0) to the starting position of each logical address can be expressed as each logical address, as shown below. Logical addresses LBA0 to LBA7 can be expressed as 0x0, 0x200, 0x400, 0x600, 0x800, 0xA00, 0xC00 and 0xE00, respectively.

[0057] According to an embodiment, when the size of each row data unit of the table is greater than 1024B, each row data unit may be allocated to three or more logical addresses. Each row data unit allocated to a plurality of logical addresses may be unaligned data.

[0058] When the table DT is stored in a storage device that does not have a calculation function, the host device 100 can directly assign each row data unit of the table DT to the logical addresses LBA0 to LBA7, and can manage the allocation information. In addition, if the calculation operation of the row data unit 0 (R0) of the table DT must be modified, the host device 100 can send a read operation request for the logical addresses LBA0 and LBA1 to the storage device. In addition, the host device 100 can obtain all the read data corresponding to the logical address 0 (LBA0) among the read data output by the storage device and the first 48B of the read data corresponding to the logical address 1 (LBA1) as the row data unit 0 (R0). However, according to an embodiment, the calculation storage device 200, rather than the host device 100, can more efficiently perform a calculation operation on the row data unit 0 (R0) by directly calculating the logical addresses LBA0 and LBA1 to which the row data unit 0 (R0) is assigned.

[0059] Figure 3 The present invention is a diagram showing an embodiment of the present invention. Figure 1 A block diagram of the computing function accelerator 212 is shown.

[0060] Reference Figure 3 , the computing function accelerator 212 may include an operation information buffer 301, an index controller 302, an index cache 303, a metadata buffer 304, a read data buffer 305, an operator 306, a write data buffer 307, and a merge controller 308. All components included in the computing function accelerator 212 may be implemented as hardware, software, firmware, or a combination thereof, and they may perform operations described later.

[0061] The operation information buffer 301 may store the operation information IF transmitted by the main controller 211. The operation information buffer 301 may transmit the operation information IF to a corresponding component under the control of another component (eg, the index controller 302, the operator 306, or the merge controller 308).

[0062] The index controller 302 may calculate one or more logical addresses to which the target data unit in the data unit group 221 has been allocated based on the operation information IF, and may output each of the one or more logical addresses as an output logical address OLBA to the main controller 211. The one or more logical addresses of the target data unit may include a start logical address and a last logical address of the target data unit.

[0063] Specifically, the index controller 302 may generate an index IDX of the target data unit based on the operation information IF, and store the index IDX in the index cache 303. The index controller 302 may generate the index IDX in units of target data units. Therefore, if the table DT is stored in the memory device 220 in row-major order, the index IDX may include information about the target row data unit. The index controller 302 may generate a plurality of indexes corresponding to a plurality of target row data units, respectively, based on the operation information IF. The index cache 303 may store the indexes of a plurality of row data units corresponding to the respective target row data units.

[0064] Specifically, the index IDX of each row data unit may include information about the corresponding row data unit, such as validity information, a sequence number of the row data unit, a starting logical address of the row data unit, a starting offset of the row data unit, a last logical address of the row data unit, and a last offset of the row data unit. The validity information may indicate whether the corresponding index IDX is valid.

[0065] According to an embodiment, the index controller 302 may calculate information to be included in the index IDX of each row data unit based on equations F1 to F9. Equations F1 to F9 may be applied to a case where a data unit group or table DT is assigned to consecutive logical addresses and each size of the row data unit is larger than the data size assignable to each logical address.

[0066] Equation 1 (F1): The size of the row data unit (row_size) = col_total*val_size.

[0067] Equation 2 (F2): The starting address of the row data unit (row_start_addr) = start_addr + (row_size*row_num).

[0068] Equation 3 (F3): The last address of the row data unit (row_last_addr) = row_start_addr + row_size - val_size.

[0069] Equation 4 (F4): The starting logical address of the row data unit (start_lba) = (row_start_addr>>9)<<9.

[0070] Equation 5 (F5): The last logical address of the row data unit (last_lba) = (row_last_addr>>9)<<9.

[0071] Equation 6 (F6): Number of logical addresses (lba_total)=(last_lba−start_lba)>>9+1.

[0072] Equation 7 (F7): size difference (size_diff) = max (lba_size, row_size) – min (lba_size, row_size).

[0073] Equation 8 (F8): The starting offset of the row data unit (start_offset) = size_diff*row_num.

[0074] Equation 9 (F9): The last offset of the row data unit (last_offset) = size_diff*(row_num+1).

[0075] In Equation 1 (F1), the size of the row data unit (row_size) may be the size of one row data unit. The parameter "col_total" may be the number of columns included in the table DT, and the parameter "val_size" may be the size of one element.

[0076] In Equation 2 (F2), the starting address (row_start_addr) of the row data unit may be the number of bytes from the frontmost position (i.e., the first element) of the table DT to the position where the row data unit starts. start_addr may be the starting logical address of the table DT. Parameter "row_num" may be the sequence number of the row data unit.

[0077] In Equation 3 (F3), the last address (row_last_addr) of the row data unit may be the number of bytes from the first element of the table DT to a position before the last 8B of the row data unit (ie, the last element).

[0078] In Equation 4 (F4), the start logical address (start_lba) of the row data unit may be the frontmost logical address to which the row data unit is allocated among the logical addresses.

[0079] In Equation 5 (F5), the last logical address (last_lba) of the row data unit may be the last logical address to which the row data unit is allocated among the logical addresses.

[0080] In Equation 6 (F6), the number of logical addresses (lba_total) may be the number of logical addresses to which row data units are allocated.

[0081] In Equation 7 (F7), the size difference (size_diff) may be a difference between a size of a row data unit (row_size) and a size (lba_size) corresponding to one logical address.

[0082] In Equation 8 (F8), the start offset (start_offset) of the row data unit may be the number of bytes from the frontmost position corresponding to the start logical address (start_lba) of the row data unit in the data to the position where the row data unit starts.

[0083] In Equation 9 (F9), the last offset (last_offset) of the row data unit may be the number of bytes from the frontmost position corresponding to the last logical address (last_lba) of the row data unit in the data to the position where the row data unit ends.

[0084] If the index IDX of the target data unit has been stored in the index cache 303, the index controller 302 may skip the process of generating the index IDX. In addition, the index controller 302 may refer to the index IDX already stored in the index cache 303 in order to obtain the target data unit. According to an embodiment, the index already stored in the index cache 303 may be backed up in the memory device 220.

[0085] The index controller 302 may sequentially output each of the one or more logical addresses to which the target data unit has been allocated as an output logical address OLBA based on the index IDX. The main controller 211 may access the memory device 220 based on the output logical address OLBA output by the index controller 302. Specifically, the main controller 211 may convert the output logical address OLBA into a physical address of the memory device 220, and may control a read operation or a write operation to a memory area corresponding to the physical address in the memory device 220.

[0086] For example, for a computing operation requiring a read operation of the memory device 220, the index controller 302 may sequentially output each of the one or more logical addresses to which the target row data unit has been assigned as an output logical address OLBA. The main controller 211 may control the memory device 220 to output the read data RD including the target row data unit based on the output logical address OLBA. The read data RD output by the memory device 220 may be stored in the read data buffer 305.

[0087] In addition, the index controller 302 may determine whether the read data RD including the target data unit has been stored in the read data buffer 305. For example, the index controller 302 may check the read data buffer 305 through a buffer controller (not shown) to know whether the read data RD has been stored in the read data buffer 305. If the read data RD has been stored in the read data buffer 305, the index controller 302 may not output a logical address corresponding to the read data RD as an output address. Therefore, the memory device 220 may not perform an unnecessary read operation. The index controller 302 may notify other constituent units of the computing function accelerator 212 that a computing operation may be performed by using the read data RD that has been stored in the read data buffer 305.

[0088] In addition, the index controller 302 may generate metadata MT of the target data unit based on the index IDX of the target data unit, and may store the metadata MT in the metadata buffer 304. For example, the metadata MT of the target row data unit may include information about the target row data unit that can be identified in the read data RD output by the memory device 220.

[0089] Specifically, the metadata MT of the target row data unit may include the sequence number of the target row data unit, the number of logical addresses to which the target row data unit has been allocated, the starting offset of the target row data unit, and the last offset of the target row data unit. Therefore, as will be described later, the operator 306 may identify the data from the starting offset to the last offset corresponding to the number of logical addresses in the read data RD as the target row data unit based on the metadata MT of the target row data unit.

[0090] The index cache 303 may store and maintain the index IDX under the control of the index controller 302. The index IDX that has been stored in the index cache 303 may be reused in a computing operation according to another computing operation request.

[0091] The metadata buffer 304 may store metadata MT under the control of the index controller 302. According to an embodiment, the metadata MT that has been stored in the metadata buffer 304 may be removed whenever a calculation operation of a target data unit is completed.

[0092] The read data buffer 305 may store the read data RD output by the memory device 220 .

[0093] The operator 306 may read the selection data SD from the read data buffer 305 based on the operation information IF received from the operation information buffer 301 and the metadata MT received from the metadata buffer 304. The selection data SD may be part or all of the target data unit according to the type of the calculation operation. In addition, the operator 306 may perform a calculation operation on the selection data SD and output an operation result RS.

[0094] For example, the operator 306 may identify the target row data unit in the read data RD stored in the read data buffer 305 based on the metadata MT of the target row data unit. In addition, the operator 306 may perform a calculation operation on the target row data unit based on the operation information IF.

[0095] According to an embodiment, the computing function accelerator 212 may further include an output data buffer (not shown) for storing the operation result RS. The operator 306 may perform a computing operation and then control the data to be output as the operation result RS to be transferred from the read data buffer 305 to the output data buffer. The computing function accelerator 212 may output the operation result RS from the output data buffer.

[0096] The write data buffer 307 may receive and store another data from the host device 100. The write data buffer 307 may output the other data as write data WT without any change, or may output data modified under the control of the merge controller 308 as write data WD. The write data WT may be stored in the memory device 220 by the main controller 211.

[0097] The merge controller 308 may operate in a calculation operation including an operation of modifying the read data RD and storing the modified data as write data WD in the memory device 220. Specifically, the merge controller 308 may read the read data RD stored in the read data buffer 305 based on the operation information IF received from the operation information buffer 301 and the metadata MT received from the metadata buffer 304. In addition, the merge controller 308 may modify the read data RD based on another data ID stored in the write data buffer 307, and may control the write data buffer 307 to output the modified data as the write data WD. In this case, the index controller 302 may output the logical address to which the write data has been assigned as the output logical address OLBA based on the operation information IF. The main controller 211 may control the memory device 220 to store the write data in another memory area, and may map the output logical address OLBA to the physical address of another memory area.

[0098] According to an embodiment, at least some of the various memory components included in the computing function accelerator 212 may be included in one memory device. According to an embodiment, at least some of the various components included in the computing function accelerator 212 except the memory components may be operated by one processor.

[0099] Figure 4 The present invention is a diagram showing an embodiment of the present invention. Figure 2 DT and the operation information IF_RQ1 included in the first computing operation request RQ1.

[0100] Reference Figure 4 , the first computing operation request RQ1 can be used for a SELECT operation of selecting one or more row data units in the table DT and outputting the selected row data units to the host device 100, in each of the one or more row data units, the element of column 4 is greater than 100 and the element of column 6 is 2. In the first computing operation request RQ1, the condition of the first computing operation request RQ1 can be expressed in the form of a WHERE syntax. In order to process the first computing operation request RQ1, it is necessary to check each of all row data units R0 to R6 included in the table DT. Therefore, each of all row data units R0 to R6 can be a target row data unit of the first computing operation request RQ1.

[0101] The first computing operation request RQ1 may include operation information IF_RQ1. The operation information IF_RQ1 may include a starting logical address (start_addr) of the table DT, the number of row data units R0 to R6 included in the table DT (row_total), the number of columns included in the table DT (col_total), the size of each element of the table DT (val_size), a computing operation type (type), one or more target offsets (tar_offset), the number of target offsets (tar_offset) (tar_offset_total), one or more conditional operations (op), the number of conditional operations (op) (op_total), one or more constants (const), and the number of constants (const_total). The target offset (tar_offset) may indicate an element of the computing operation to be performed in each target row data unit. The conditional operation (op) may be an operation included in the WHERE syntax of the first computing operation request RQ1. The constant may be a constant included in the condition of the first computing operation request RQ1.

[0102] Figure 5A and Figure 5B is used to describe the processing of the computing function accelerator 212 according to an embodiment of the present disclosure. Figure 4 Schematic diagram of a method for a first computing operation request RQ1.

[0103] first, Figure 5A A method is shown in which the computing function accelerator 212 performs a SELECT operation requested by a first computing operation request RQ1 on a row data unit 0 ( R0 ).

[0104] Reference Figure 5A , the index controller 302 may operate based on the operation information IF_RQ1 of the first computing operation request RQ1 so that the read data RD0 and RD1 including the row data unit 0 ( R0 ) are output from the memory device 220 to the read data buffer 305 .

[0105] Specifically, the index controller 302 may generate an index IDX_R0 of the row data unit 0 (R0) based on equations 1 (F1) to 9 (F9). The index IDX_R0 of the row data unit 0 (R0) may include validity information (valid), a sequence number (row_num) of the row data unit 0 (R0), a starting logical address (start_lba) of the row data unit 0 (R0), a starting offset (start_offset) of the row data unit 0 (R0), a last logical address (last_lba) of the row data unit 0 (R0), and a last offset (last_offset) of the row data unit 0 (R0).

[0106] As described above, if the index IDX_R0 of the row data unit 0 ( R0 ) has been stored in the index cache 303 before receiving the first computing operation request RQ1 , the index controller 302 may not regenerate the index IDX_R0 of the row data unit 0 ( R0 ).

[0107] In addition, the index controller 302 may generate metadata MT_R0 of the row data unit 0 ( R0 ) and store the metadata MT_R0 in the metadata buffer 304 .

[0108] The index controller 302 may determine the starting logical address (start_lba) of the row data unit 0 (R0) as the logical address 0 (LBA0) and the last logical address (last_lba) of the row data unit 0 (R0) as the logical address 1 (LBA1). The index controller 302 may output the logical address 0 (LBA0) as the output logical address OLBA, thereby performing a read operation on the logical address 0 (LBA0). In addition, the index controller 302 may output the logical address 1 (LBA1) as the output logical address OLBA, thereby performing a read operation on the logical address 1 (LBA1). The main controller 211 may control the memory device 220 to output the read data RD0 corresponding to the logical address 0 (LBA0) and the read data RD1 corresponding to the logical address 1 (LBA1).

[0109] The read data buffer 305 may store read data RD0 corresponding to a logical address 0 ( LBA0 ) and read data RD1 corresponding to a logical address 1 ( LBA1 ).

[0110] The operator 306 can identify the row data unit 0 (R0) among the read data RD0 and RD1 based on the metadata MT_R0 of the row data unit 0 (R0). Specifically, since the number of logical addresses (lba_total) is 2, the operator 306 can determine that the row data unit 0 (R0) has been assigned to two logical addresses. In addition, the operator 306 can determine that the entire read data RD0 corresponding to the logical address 0 (LBA0) is the front part of the row data unit 0 (R0) based on the starting offset (start_offset). In addition, the operator 306 can identify that the first 48B of the read data RD1 corresponding to the logical address 1 (LBA1) is the remaining part of the row data unit 0 (R0) based on the last offset (last_offset).

[0111] In addition, the operator 306 can read the elements of column 4 (C4) and column 6 (C6) of the row data unit 0 (R0) from the read data buffer 305 based on the target offset (tar_offset) of the operation information IF_RQ1. In addition, the operator 306 can perform the conditional operation of the first computing operation request RQ1 on the read elements based on the conditional operation (op) and the constant (const) of the operation information IF_RQ1. Specifically, the operator 306 can determine that the elements of column 4 (C4) of the row data unit 0 (R0) do not meet the conditions of the first computing operation request RQ1 (i.e., fail). In addition, the operator 306 can determine that the elements of column 6 (C6) of the row data unit 0 (R0) meet the conditions of the first computing operation request RQ1 (i.e., pass). Therefore, the operator 306 can determine that the row data unit 0 (R0) does not meet the conditions of the first computing operation request RQ1 (i.e., fail). Therefore, the row data unit 0 (R0) may not be output to the host device 100.

[0112] Next, Figure 5B A method is shown in which the computing function accelerator 212 performs a SELECT operation requested by a first computing operation request RQ1 on a row data unit 1 ( R1 ).

[0113] Reference Figure 5B , the index controller 302 may generate the index IDX_R1 of the row data unit 1 (R1) based on equations 1 (F1) to 9 (F9). As described above, if the index IDX_R1 of the row data unit 1 (R1) has been stored in the index cache 303 before receiving the first computing operation request RQ1, the index controller 302 may not regenerate the index IDX_R1 of the row data unit 1 (R1). In addition, the index controller 302 may generate metadata MT_R1 of the row data unit 1 (R1) and store the metadata MT_R1 in the metadata buffer 304.

[0114] The index controller 302 may determine that the starting logical address (start_lba) of the row data unit 1 (R1) is the logical address 1 (LBA1) and the last logical address (last_lba) of the row data unit 1 (R1) is the logical address 2 (LBA2). In this case, for example, if the memory device 220 performs a read operation on the logical address 1 (LBA1) to perform a calculation operation on the row data unit 0 (R0), or the read data RD1 corresponding to the logical address 1 (LBA1) already exists in the read data buffer 305, the index controller 302 may determine that another read operation on the logical address 1 (LBA1) is unnecessary. Therefore, the index controller 302 may output only the logical address 2 (LBA2) as the output logical address OLBA, thereby performing a read operation on the logical address 2 (LBA2). The main controller 211 may control the memory device 220 to output the read data RD2 corresponding to the logical address 2 (LBA2).

[0115] The read data buffer 305 may store read data RD1 corresponding to a logical address 1 (LBA1) and read data RD2 corresponding to a logical address 2 (LBA2). The read data RD1 corresponding to the logical address 1 (LBA1) may be used in a calculation operation for row data unit 0 (R0) and may be reused in a calculation operation for row data unit 1 (R1).

[0116] The operator 306 can identify the row data unit 1 (R1) among the read data RD1 and RD2 based on the metadata MT_R1 of the row data unit 1 (R1). Specifically, since the number of logical addresses (lba_total) is 2, the operator 306 can determine that the row data unit 1 (R1) is assigned to two logical addresses. In addition, the operator 306 can determine that the remaining part of the read data RD1 corresponding to the logical address 1 (LBA1) except the first 48B of the read data RD1 is the front part of the row data unit 1 (R1) based on the starting offset (start_offset). In addition, the operator 306 can identify that the first 96B of the read data RD2 corresponding to the logical address 2 (LBA2) is the remaining part of the row data unit 1 (R1) based on the last offset (last_offset).

[0117] In addition, the operator 306 can read the elements of column 4 (C4) and column 6 (C6) of the row data unit 1 (R1) from the read data buffer 305 based on the target offset (tar_offset) of the operation information IF_RQ1. In addition, the operator 306 can perform the conditional operation of the first computing operation request RQ1 on the read elements based on the conditional operation (op) and the constant (const) of the operation information IF_RQ1. Specifically, the operator 306 can determine that the elements of column 4 (C4) of the row data unit 1 (R1) meet the conditions of the first computing operation request RQ1 (i.e., pass). In addition, the operator 306 can determine that the elements of column 6 (C6) of the row data unit 1 (R1) meet the conditions of the first computing operation request RQ1 (i.e., pass). Therefore, the operator 306 can determine that the row data unit 1 (R1) meets the conditions of the first computing operation request RQ1 (i.e., pass). Therefore, the operator 306 may control the row data unit 1 ( R1 ) to be output from the read data buffer 305 to the host device 100 .

[0118] Similar to the aforementioned method, the computing storage device 200 may perform the SELECT operation requested by the first computing operation request RQ1 on the row data unit 2 ( R2 ) to the row data unit 6 ( R6 ) of the table DT.

[0119] The computing storage device 200 can efficiently perform the computing operation requested by the computing operation request for another computing operation type other than the SELECT operation by identifying each row data unit and each column of the table DT according to the aforementioned method.

[0120] The table DT is stored in the memory device 220 in row-major order. According to an embodiment, the table may be stored in the memory device 220 in column-major order. The computing function accelerator 212 may operate on the table stored in column-major order similar to the aforementioned method. That is, the index controller 302 may calculate one or more logical addresses to which the target column data unit has been assigned, and may generate the index IDX and metadata MT in units of columns. Therefore, the computing function accelerator 212 may effectively obtain the target column data unit stored in column-major order in response to a computing operation request, and may perform a computing operation on the target column data unit.

[0121] Figure 6 is a diagram for describing a method in which the computing function accelerator 212 performs a MODIFY operation by outputting only a required logical address according to an embodiment of the present disclosure.

[0122] When receiving a computing operation request for a predetermined computing operation type (e.g., a MODIFY operation), the computing function accelerator 212 can output only a logical address selected from one or more logical addresses to which the target data unit has been allocated as the output logical address OLBA. Because unnecessary read operations are omitted, the computing storage device 200 can process computing operation requests more efficiently.

[0123] Reference Figure 6 For example, the computing function accelerator 212 may receive a computing operation request for modifying an element of column 3 (C3) of row data unit 2 (R2) of table DT. Therefore, the index controller 302 may generate an index IDX_R2 for row data unit 2 (R2). As described above, if the index IDX_R2 for row data unit 2 (R2) has been stored in the index cache 303, the index controller 302 may not need to regenerate the index IDX_R2 for row data unit 2 (R2), but may refer to the index IDX_R2 for row data unit 2 (R2) already stored in the index cache 303. The index controller 302 may also generate metadata MT_R2 for row data unit 2 (R2).

[0124] In addition, the index controller 302 can determine that column 3 (C3) of row data unit 2 (R2) is included in the read data RD2 corresponding to logical address 2 (LBA2) based on the starting offset (start_offset) of row data unit 2 (R2). Specifically, the index controller 302 can determine that 8B after the first 120B in the read data RD2 is column 3 (C3) of row data unit 2 (R2) in the read data RD2, and in the read data RD2, row data unit 2 (R2) corresponds to logical address 2 (LBA2). Therefore, although row data unit 2 (R2) is assigned to logical address 2 (LBA2) and logical address 3 (LBA3), the index controller 302 can only output logical address 2 (LBA2) as the output logical address OLBA.

[0125] The merge controller 308 can modify the element of column 3 (C3) of the row data unit 2 (R2) corresponding to the logical address 2 (LBA2) in the read data RD2 based on the operation information IF and metadata MT_R2 of the row data unit 2 (R2). As in the operation method described with respect to the operator 306, the merge controller 308 can identify the element of column 3 (C3) of the row data unit 2 (R2) in the read data RD2 based on the metadata MT_R2 of the row data unit 2 (R2). The modified data can be output as write data WD. Thereafter, the main controller 211 can store the write data WT corresponding to the logical address 2 (LBA2) in another memory area of ​​the memory device 220, and can map the logical address 2 (LBA2) to the physical address of another memory area.

[0126] If the read data RD2 corresponding to the logical address 2 (LBA2) has already been stored in the read data buffer 305, it is not necessary to perform a read operation on the logical address 2 (LBA2), and the MODIFY operation will be performed by using the read data RD2 already stored in the read data buffer 305.

[0127] Figure 7 is a diagram for describing a method in which the computing function accelerator 212 assigns another data ID to be added to the table DT to one or more logical addresses according to an embodiment of the present disclosure.

[0128] Reference Figure 7 For example, when receiving a computing operation request to add another data ID to table DT as another row data unit 1, the index controller 302 may increase the sequence number (row_num) of each of row data unit 1 (R1) to row data unit 6 (R6) in indexes IDX_R0 to IDX_R6 of table DT by 1.

[0129] In addition, the index controller 302 may assign another row data unit 1 to logical addresses LBA7 and LBA8, and may generate an index IDX_NR1 of another row data unit 1. The index IDX_NR1 of another row data unit 1 may include 1 as the serial number (row_num) of the row data unit. In addition, the index IDX_NR1 of another row data unit 1 may include logical address 7 (LBA7) as the starting logical address (start_lba) of another row data unit 1, and include logical address 8 (LBA8) as the last logical address (last_lba) of another row data unit 1. That is, the front part of another row data unit 1 may be assigned to logical address 7 (LBA7) after the rear part of row data unit 7 (i.e., previous row data unit 6). The rear part of another row data unit 1 may be assigned to logical address 8 (LBA8).

[0130] The merge controller 308 may merge the front portion of another row data unit 1 with the rear portion of the row data unit 7 (i.e., the previous row data unit 6). Specifically, the index controller 302 may operate so that the read data RD corresponding to the logical address 7 (LBA7) is output by the memory device 220. The merge controller 308 may generate the write data WT by merging the rear portion of the row data unit 7 (i.e., the previous row data unit 6) and the front portion of another row data unit 1 included in the read data RD corresponding to the logical address 7 (LBA7). The main controller 211 may store the write data WT corresponding to the logical address 7 (LBA7) in another memory area of ​​the memory device 220, and may map the logical address 7 (LBA7) to the physical address of another memory area.

[0131] According to an embodiment, the host device 100 may pre-specify a range of logical addresses to which the table DT may be allocated to the computing storage device 200. The computing function accelerator 212 may allocate another data ID added to the table DT to the logical addresses of the range specified by the host device. Therefore, since the host device 100 does not need to manage the logical addresses allocated by the table DT, the overhead of the host device 100 may be further reduced.

[0132] Figure 8 is a diagram for describing a method in which the computing function accelerator 212 invalidates the index IDX stored in the index cache 303 according to an embodiment of the present disclosure.

[0133] Reference Figure 8 For example, when receiving a calculation operation request to remove row data unit 1 (R1) from table DT, index controller 302 may reduce the sequence number (row_num) of each of row data unit 2 (R2) to row data unit 6 (R6) in indexes IDX_R0 to IDX_R6 of table DT by 1. In addition, index controller 302 may modify validity information (valid) of index IDX_R1 of row data unit 1 (R1) so that validity information (valid) indicates that index IDX_R1 of row data unit 1 (R1) is invalid. Thereafter, index controller 302 may modify the row data unit 1 (R1) by using the same reference number as row_num. Figure 8 The same method described allocates another data ID to the logical addresses LBA1 and LBA2 of the row data unit 1 (R1) to which invalidation has been allocated.

[0134] Reference Figures 2 to 8 The described processing method of the table DT can be similarly applied to the case of processing the data unit group 221 in which the size of each data unit is larger than the maximum size of data applicable to each logical address.

[0135] Fig. 9A and Fig. 9B is a diagram for describing the logical addresses of the allocation table ET according to an embodiment of the present disclosure. The table ET may be Figure 1 An example of data unit group 221 is shown.

[0136] Reference Fig. 9A , table ET may be an embedded table including a plurality of vector data units V0 to Vm. For example, the size of each element included in table ET may be 4B. The vector dimension of table ET may be 30 (i.e., each vector data unit includes thirty elements). Therefore, the size of each vector data unit may be 120B. For example, vector data unit 0 (V0) may include thirty elements A0 to A29. The size of each vector data unit may be less than the maximum data size that may be allocated to each logical address, for example, 512B.

[0137] Reference Fig. 9B , when the table ET is stored in the memory device 220 under the control of the host device 100, the main controller 211 may assign the sequentially listed vector data units V0 to Vm to the consecutive logical addresses LBA0 to LBAi in units of 512B. For example, the starting logical address of the table ET is the logical address 0 (LBA0) and 0x0. Each vector data unit may be assigned to one or two logical addresses. A vector data unit assigned to only one logical address may not be unaligned data, while a vector data unit assigned to two logical addresses may be unaligned data.

[0138] For example, all elements from vector data unit 0 (V0) to vector data unit 3 (V3) may be allocated to logical address 0 (LBA0). Therefore, vector data unit 0 (V0) to vector data unit 3 (V3) may not be unaligned data.

[0139] For example, the first 32B of vector data unit 4 (V4) can be assigned to logical address 0 (LBA0), and the last 88B of vector data unit 4 (V4) can be assigned to logical address 1 (LBA1). Therefore, vector data unit 4 (V4) can be unaligned data. Logical address 0 (LBA0) can be the starting logical address (or first logical address) of vector data unit 4 (V4). Logical address 1 (LBA1) can be the last logical address (or second logical address) of vector data unit 4 (V4).

[0140] The computing storage device 200 may receive a computing operation request for the table ET from the host device 100. The operation information IF included in the computing operation request may selectively include information about the starting logical address of the table ET, the size of the elements, the vector dimension, the computing operation type, and the respective sequence numbers of one or more target data units (i.e., target vector data units).

[0141] The computing function accelerator 212 can be similar to Figure 2 The processing method of table DT shown in the figure processes table ET. However, all row data units R0 to R6 of table DT may be unaligned data, but each vector data unit of table ET may be unaligned data or non-unaligned data. Therefore, the index controller 302 may determine whether each vector data unit is unaligned data by calculating an unaligned flag for each vector data unit.

[0142] Specifically, the index controller 302 may generate an index IDX of the target vector data unit based on the operation information IF. The index controller 302 may generate a plurality of indexes corresponding to a plurality of target vector data units, respectively, based on the operation information IF.

[0143] More specifically, the index IDX of each vector data unit may include information about the vector data unit, such as validity information, the sequence number of the vector data unit, the starting logical address of the vector data unit, the starting offset of the vector data unit, the last logical address of the vector data unit, and the last offset of the vector data unit.

[0144] According to an embodiment, the index controller 302 may calculate information to be included in the index IDX of each vector data unit based on equations F10 to F18. Equations F10 to F18 may be applied to a case where a data unit group or table ET is assigned to consecutive logical addresses and each size of the vector data unit is smaller than the data size that can be assigned to each logical address.

[0145] Equation 10 (F10): Size of vector data unit (vt_size) = vt_dim*val_size.

[0146] Equation 11 (F11): Starting address of vector data unit (vt_start_addr) = start_addr + (vt_size*vt_num).

[0147] Equation 12 (F12): The starting logical address of the vector data unit (start_lba) = (vt_start_addr>>9)<<9.

[0148] Equation 13 (F13): The starting offset of the vector data unit (start_offset) = vt_start_addr[8:0].

[0149] Equation 14 (F14): unaligned_flag = (start_offset == 0)? 0:

[0150] [(vt_start_addr+vt_size)>>9]! =start_lba? 1:0.

[0151] Equation 15 (F15): The last logical address of the vector data unit as non-unaligned data (last_lba)=start_lba.

[0152] Equation 16 (F16): Last offset of vector data unit as non-unaligned data (last_offset) = start_offset + vt_size.

[0153] Equation 17 (F17): Last logical address of unaligned data (last_lba)=start_lba+lba_size.

[0154] Equation 18 (F18): Last offset of unaligned data (last_offset) = vt_size - (last_lba - vt_start_addr).

[0155] In Equation 10 (F10), the size of the vector data unit (vt_size) may be the size of one vector data unit. The parameter "vt_dim" may be the vector dimension. The parameter "val_size" may be the size of one element.

[0156] In equation 11 (F11), the starting address (vt_start_addr) of the vector data unit may be the number of bytes from the first element of the table ET to the position where the vector data unit starts. The parameter "start_addr" may be the starting logical address of the table ET. The parameter "vt_num" may be the serial number of the vector data unit.

[0157] In Equation 12 (F12), the start logical address (start_lba) of the vector data unit may be a frontmost logical address to which the vector data unit is allocated among one or more logical addresses.

[0158] In Equation 13 (F13), the start offset (start_offset) of the vector data unit may be the number of bytes from the frontmost position of the start logical address (start_lba) corresponding to the vector data unit in the data to the position where the vector data unit starts.

[0159] In equation 14 (F14), the unaligned flag (unaligned_flag) may indicate whether the vector data unit is unaligned data. For example, the unaligned flag (unaligned_flag) of the vector data unit as non-unaligned data may be calculated as 0. The unaligned flag (unaligned_flag) of the unaligned data may be calculated as 1.

[0160] In Equation 15 (F15) and Equation 17 (F17), the last logical address (last_lba) of the vector data unit may be the last logical address to which the vector data unit is allocated among one or more logical addresses. As shown in Equation 15 (F15), the last logical address (last_lba) of the vector data unit as non-unaligned data may be the same as the starting logical address (start_lba). As shown in Equation 17 (F17), the last logical address (last_lba) of the unaligned data may be a logical address after the starting logical address (start_lba). lba_size may be a size corresponding to one logical address.

[0161] In Equation 16 (F16) and Equation 18 (F18), the last offset (last_offset) of the vector data unit may be the number of bytes from the frontmost position in the data corresponding to the last logical address (last_lba) of the vector data unit to the position where the vector data unit ends.

[0162] According to an embodiment, when the vector data unit is not unaligned data, the calculation of the last logical address (last_lba) according to equation 15 (F15) and the calculation of the last offset (last_offset) according to equation 16 (F16) can be omitted. In addition, the operator 306 can simply obtain data corresponding to the size (vt_size) of the vector data unit according to the starting offset (start_offset) of the vector data unit from the read data RD corresponding to the starting logical address (start_lba) of the vector data unit.

[0163] The index controller 302 may output one or two logical addresses of the target vector data unit as the output logical address OLBA based on the index IDX of the target vector data unit. If the required read data RD has been stored in the read data buffer 305, the index controller 302 may not output the logical address corresponding to the required read data RD as the output logical address OLBA.

[0164] In addition, the index controller 302 may store metadata MT of the target vector data unit in the metadata buffer 304 based on the index IDX of the target vector data unit. The metadata MT of the target vector data unit may include information that can identify the target vector data unit in the read data RD output by the memory device 220. Specifically, the metadata MT of the target vector data unit may include the sequence number of the target vector data unit, the number of logical addresses to which the target vector data unit is allocated, the starting offset of the target vector data unit, and the last offset of the target vector data unit. Therefore, the computing function accelerator 212 can effectively perform the computing operation requested by the computing operation request by identifying the target vector data unit of the table ET based on the metadata MT of the target vector data unit.

[0165] According to an embodiment, the metadata MT of the target vector data unit may include a misalignment flag instead of the number of logical addresses to which the target vector data unit has been allocated.

[0166] Fig. 10A and Fig. 10B is a diagram illustrating a process in which the computing function accelerator 212 acquires the vector data unit 3 ( V3 ) and the vector data unit 4 ( V4 ) of the table ET according to an embodiment of the present disclosure.

[0167] Reference Fig. 10A , the index controller 302 may generate the index IDX_V3 of the vector data unit 3 (V3) based on equations 10 (F10) to 18 (F18). As described above, if the index IDX_V3 of the vector data unit 3 (V3) has been stored in the index cache 303, the index controller 302 may not regenerate the index IDX_V3 of the vector data unit 3 (V3). In addition, the index controller 302 may generate metadata (MT_V3) of the vector data unit 3 (V3) and store the metadata (MT_V3) in the metadata buffer 304.

[0168] The index controller 302 can determine that the starting logical address (start_lba) of the vector data unit 3 (V3) is the logical address 0 (LBA0). Because the unaligned flag (unaligned_flag) of the vector data unit 3 (V3) is 0, the index controller 302 can determine that the vector data unit 3 (V3) is not unaligned data. Therefore, the index controller 302 can determine that the last logical address (last_lba) of the vector data unit 3 (V3) is the logical address 0 (LBA0). The index controller 302 can output the logical address 0 (LBA0) as the output logical address OLBA, thereby performing a read operation on the logical address 0 (LBA0). The main controller 211 can control the memory device 220 to output the read data RD0 corresponding to the logical address 0 (LBA0).

[0169] The operator 306 can identify the vector data unit 3 (V3) in the read data RD based on the metadata (MT_V3) of the vector data unit 3 (V3). Specifically, since the number of logical addresses (lba_total) is 1, the operator 306 can determine that the vector data unit 3 (V3) is assigned to one logical address. In addition, the operator 306 can identify the vector data unit 3 (V3) in the read data RD0 corresponding to the logical address 0 (LBA0) based on the starting offset (start_offset) and the last offset (last_offset) of the vector data unit 3 (V3). The operator 06 can perform a calculation operation on the identified vector data unit 3 (V3).

[0170] Reference Fig. 10B , the index controller 302 may generate an index (IDX_V4) of the vector data unit 4 (V4) based on equations 10 (F10) to 18 (F18). As described above, if the index (IDX_V4) of the vector data unit 4 (V4) has been stored in the index cache 303, the index controller 302 may not regenerate the index (IDX_V4) of the vector data unit 4 (V4). In addition, the index controller 302 may generate metadata (MT_V4) of the vector data unit 4 (V4) and store the metadata (MT_V4) in the metadata buffer 304.

[0171] The index controller 302 can determine that the starting logical address (start_lba) of the vector data unit 4 (V4) is the logical address 0 (LBA0). Because the unaligned flag (unaligned_flag) of the vector data unit 4 (V4) is 1, the index controller 302 can determine that the vector data unit 4 (V4) is unaligned data. Therefore, the index controller 302 can determine that the last logical address (last_lba) of the vector data unit 4 (V4) is the logical address 1 (LBA1). In this case, for example, if the memory device 220 performs a read operation on the logical address 0 (LBA0) to perform a calculation operation on the vector data unit 3 (V3), or the read data RD0 corresponding to the logical address 0 (LBA0) already exists in the read data buffer 305, the index controller 302 can determine that another read operation on the logical address 0 (LBA0) is unnecessary. Therefore, the index controller 302 can only output the logical address 1 (LBA1) as the output logical address OLBA, thereby performing a read operation on the logical address 1 (LBA1). The main controller 211 may control the memory device 220 to output read data RD1 corresponding to the logical address 1 ( LBA1 ).

[0172] The operator 306 can identify the vector data unit 4 (V4) among the read data RD0 and RD1 based on the metadata (MT_V4) of the vector data unit 4 (V4). Specifically, since the number of logical addresses (lba_total) is 2, the operator 306 can determine that the vector data unit 4 (V4) is assigned to two logical addresses. In addition, the operator 306 can determine that the remaining part of the read data RD corresponding to the logical address 0 (LBA0) except the first 480B is the front part of the vector data unit 4 (V4) based on the starting offset (start_offset). In addition, the operator 306 can identify that the first 88B of the read data RD1 corresponding to the logical address 1 (LBA1) is the remaining part of the vector data unit 4 (V4) based on the last offset (last_offset). The operator 306 can perform a calculation operation on the identified vector data unit 4 (V4).

[0173] Reference 9A to 10B The described processing method of the embedded table ET can be similarly applied when processing the data unit group 221, the size of each data unit being smaller than the maximum data size allocable to each logical address.

[0174] According to an embodiment, the computing storage device 200 can autonomously determine the one or more logical addresses to which the target data unit has been allocated, although one or more logical addresses of the target data unit allocated for the computing operation are not received from the host device 100. In addition, although the size of the target data unit is different from the size corresponding to the logical address, the computing storage device 200 can still identify the target data unit in the read data corresponding to the logical address. Therefore, the computing storage device 200 can effectively perform the computing operation requested by the host device 100, and the performance of the data processing system 10 can be improved.

[0175] The above description is merely a description of the technical spirit of the present technology, and those skilled in the art can change and modify the present technology in various ways without departing from the essential features of the present technology. Therefore, the disclosed embodiments should not be interpreted as limiting the technical spirit of the present technology, but should be interpreted as describing the technical spirit of the present technology. The technical spirit of the present technology is not limited by the embodiments. The protection scope of the present technology should be interpreted based on the attached claims, and all technical spirits within the equivalent scope of the present technology should be interpreted as included in the scope of rights of the present technology. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should include their equivalents.

[0176] In the above-described embodiments, all operations may be selectively performed or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the order described, but may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0177] The computational storage device according to the embodiment may efficiently perform computational operations.

[0178] Embodiments of the present disclosure are described in the drawings and the specification. Although specific terms are used herein, this is only for the purpose of describing embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, but many variations may exist within the scope of the present disclosure. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A computing storage device, comprising: a memory device storing a data unit group including a plurality of data units; as well as Controller: one or more logical addresses are calculated based on the computing operation request, target data units included in the data unit group are assigned to the one or more logical addresses, the target data units are targets of computing operations to be performed in response to the computing operation request, Calculate a starting logical address and a starting offset of the target data unit based on the information, wherein the starting logical address is included in the one or more logical addresses, reading data corresponding to the one or more logical addresses from the memory device, and identifying the target data unit in the read data, The computing operation request includes information about a starting logical address of the data unit group and a size of each data unit in the plurality of data units.

2. The computing storage device according to claim 1, wherein: The start offset corresponds to the number of bytes from the frontmost position corresponding to the start logical address of the target data unit in the read data to the start position of the target data unit.

3. The computing storage device according to claim 1, wherein: When the target data unit is unaligned data, the controller further calculates a final logical address and a final offset of the target data unit based on the information.

4. The computing storage device according to claim 3, wherein: The final offset corresponds to the number of bytes from the frontmost position corresponding to the final logical address in the read data to the end position of the target data unit.

5. The computing storage device according to claim 3, wherein: The controller further generates an index of the target data unit to store the index in an index cache, and The index includes a starting logical address, a starting offset, a last logical address and a last offset of the target data unit.

6. The computing storage device according to claim 3, wherein: The controller comprises: a metadata buffer storing metadata of the target data unit, the metadata including information of the number of the one or more logical addresses, the start offset, and the last offset; and Operator: identifying a target data unit in the read data based on the metadata, and A computation operation is performed on the target data unit.

7. The computing storage device according to claim 3, wherein: When the size of the target data unit is greater than a maximum data size that can be allocated to one logical address, the controller further determines that the target data unit is not aligned.

8. The computing storage device according to claim 3, wherein: The controller further: When the size of the target data unit is smaller than the maximum data size that can be allocated to a logical address, calculating an unaligned flag indicating whether the target data unit is unaligned data, and It is determined whether the target data unit is the misaligned data based on the misaligned flag.

9. The computing storage device according to claim 1, wherein: The controller: converting the logical address to a physical address, and The memory device is controlled to output read data from a memory area corresponding to the physical address to the controller.

10. The computing storage device according to claim 1, wherein: The controller includes an index cache storing an index of the plurality of data units, and When the index of the target data unit has been stored in the index cache, the controller further refers to the index of the target data unit that has been stored in the index cache to calculate the one or more logical addresses.

11. The computing storage device according to claim 1, wherein: The controller further: In response to a first subsequent computing operation request to remove the target data unit from the data unit group, modifying respective sequence numbers of data units following the target data unit among the plurality of data units and invalidating the target data unit, and In response to a second subsequent computing operation request to add another target data unit to the group of data units, the one or more logical addresses are assigned to the another target data unit.

12. A computing storage device, comprising: a memory device storing a data unit group including a plurality of data units; as well as Controller: calculating a first logical address to which a selected portion of a target data unit included in the data unit group has been allocated and a misalignment flag of the target data unit, When it is determined according to the misalignment flag that the target data unit is misaligned data, calculating a second logical address to which the remaining portion of the target data unit has been allocated, reading first read data corresponding to the first logical address and second read data corresponding to the second logical address from the memory device, and The target data unit is obtained from the first read data and the second read data.

13. The computing storage device according to claim 12, wherein: The controller further receives information of a start logical address of the data unit group, a sequence number of the target data unit, and a size of the target data unit from an external host device, and The controller calculates the first logical address and the misalignment flag based on the information.

14. The computing storage device according to claim 13, wherein: The controller calculates a starting address of the target data unit based on the information, The controller calculates the first logical address and the misalignment flag based on the start address, and The start address corresponds to the number of bytes from the start position of the data unit group to the start position of the target data unit.

15. The computing storage device according to claim 14, wherein: The controller further: Calculating the starting offset of the target data unit based on the starting address, and obtaining the selected portion from the first read data based on the starting offset, and The start offset corresponds to the number of bytes from the frontmost position of the first read data to the start position of the target data unit.

16. The computing storage device of claim 12, wherein: When it is determined based on the misalignment flag that the target data unit is not misaligned data, the controller obtains all target data units from the first read data.

17. The computing storage device of claim 12, wherein: The data unit group is an embedded table, and The target data unit is a vector data unit.

18. A data processing system comprising: A computing storage device that allocates consecutive logical addresses to the data unit groups when storing the data unit groups; as well as The host device sends a computing operation request for the data unit group to the computing storage device, The computing storage device performs a computing operation on the data unit group in response to the computing operation request.

19. The data processing system according to claim 18, wherein: The computing storage device further: determining a target data unit on which the computing operation is to be performed among a plurality of data units included in the data unit group, determining one or more logical addresses to which the target data unit has been allocated, and The target data unit is obtained by performing a read operation on one or more physical addresses mapped to the one or more logical addresses.

20. The data processing system according to claim 18, wherein: The host device further specifies a range of logical addresses that can be allocated to the computational storage device for the group of data units.

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