Interrupt controller, chip and electronic equipment

Abstract

The invention discloses an interrupt controller, a chip and electronic equipment. The interrupt controller comprises at least one interrupt domain module and an output module, each interrupt domain module is configured to receive a line interrupt request, obtain a target line interrupt request matched with the current interrupt domain module from the received line interrupt request, and generate a corresponding message interrupt request according to the target line interrupt request; and the output module is configured to receive the message interruption request sent by the at least one interruption domain module and control the output of the message interruption request. The interrupt controller processes a line interrupt request in an interrupt system based on message interrupt.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an interrupt controller, a chip, and an electronic device. Background Art

[0002] The interrupt system is an important part of the computer system. It is used in real-time control, fault handling, and handshakes with peripherals, which require the coordination of the system's response and processing of various internal and external events. It can improve the processor's multi-tasking capabilities and greatly improve the efficiency of the computer. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an interrupt controller, comprising at least one interrupt domain module and an output module, each of the interrupt domain modules being configured to receive a line interrupt request, obtain a target line interrupt request matching the current interrupt domain module from the received line interrupt request, and generate a corresponding message interrupt request according to the target line interrupt request; the output module being configured to receive the message interrupt request sent by the at least one interrupt domain module, and to control the output of the message interrupt request.

[0004] At least one embodiment of the present disclosure provides a chip, including the interrupt controller provided by any embodiment of the present disclosure.

[0005] At least one embodiment of the present disclosure provides an electronic device, including the chip provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0007] Figure 1 A schematic diagram of an interrupt controller provided by at least one embodiment of the present disclosure is shown;

[0008] Figure 2 A schematic diagram showing the state transition of an output module provided by at least one embodiment of the present disclosure is shown;

[0009] Figure 3 A schematic diagram of a second arbitration submodule provided by at least one embodiment of the present disclosure is shown;

[0010] Figure 4 A schematic diagram of an interrupt domain module provided by at least one embodiment of the present disclosure is shown;

[0011] Figure 5 A schematic diagram showing various input signals before and after adjustment provided by at least one embodiment of the present disclosure is shown;

[0012] Figure 6 A schematic diagram of generating a valid line interrupt request provided by at least one embodiment of the present disclosure is shown;

[0013] Figure 7 A schematic diagram of state transition of a first finite state machine provided by at least one embodiment of the present disclosure is shown;

[0014] Figure 8 A processing timing diagram provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0016] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0017] Different computer hardware structures can have different interrupt systems. The interrupts under the RISC-V architecture (a reduced instruction set computer architecture) are divided into external interrupts, software interrupts, and timer interrupts. For external interrupts, they can be divided into two types according to the way of initiating interrupts: wire interrupts (WSI) and message interrupts (MSI). Among them, wire interrupts are interrupt requests based on hardware interrupt line drivers, and message interrupts are interrupt requests based on message drivers. Message interrupts are interrupt standards defined by the PCI Express (Peripheral Component Interconnect Express, PCIE) protocol and other protocols. In modern large-scale integrated circuit design, the number of interrupts is often very large. Message interrupts (MSI) can greatly enrich the number of interrupts and reduce the number of hardware interrupt lines. At the same time, the information interrupt method can bring higher interrupt flexibility.

[0018] At present, the RISC-V architecture-based system on chip (SoC) uses a wire interrupt (WSI) interrupt system to manage external interrupts. It does not support a message interrupt (MSI)-based interrupt system and requires PCIE and other devices to use traditional wire interrupt methods, which limits the number of interrupts supported by the system, as well as its flexibility and complexity. The interrupt system is a processing system composed of multiple devices on the chip, including an interrupt controller, for processing interrupt requests.

[0019] At least one embodiment of the present disclosure provides an interrupt controller, a chip, and an electronic device. The interrupt controller includes at least one interrupt domain module and an output module, each interrupt domain module is configured to receive a line interrupt request, obtain a target line interrupt request matching the current interrupt domain module from the received line interrupt request, and generate a corresponding message interrupt request according to the target line interrupt request; the output module is configured to receive the message interrupt request sent by the at least one interrupt domain module, and control the output of the message interrupt request.

[0020] The interrupt controller can realize the conversion from line interrupt request to message interrupt request. In the processing program after the interrupt controller, only the message interrupt request needs to be processed without processing the line interrupt request. Therefore, the interrupt system based on message interrupt can be adopted in the architecture such as RISC-V. After adopting the interrupt controller of the embodiment of the present disclosure, the line interrupt request can be processed in the interrupt system based on message interrupt, so as to achieve the purpose of processing external line interrupts when the interrupt system based on message interrupt is adopted in the future under the architecture such as RISC-V, so that the architecture such as RISC-V can support more interrupts, reduce the number of interrupt lines, and improve flexibility.

[0021] Furthermore, in the interrupt controller provided in at least one embodiment of the present disclosure, at least one interrupt domain module is provided, and each interrupt domain module can process a line interrupt request that matches its type, so that the interrupt controller can process different types of line interrupt requests separately, and manage the output of message interrupt requests generated by each interrupt domain module through the output module, thereby realizing output management of different types of message interrupt requests, and the processing efficiency and output flexibility of the interrupt controller are improved through the at least one interrupt domain module and the output module.

[0022] Figure 1 A schematic diagram of an interrupt controller provided by at least one embodiment of the present disclosure is shown.

[0023] like Figure 1 As shown, the interrupt controller 10 includes at least one interrupt domain module 100 and an output module 200 .

[0024] Each interrupt domain module 100 is configured to receive a line interrupt request, obtain a target line interrupt request matching the current interrupt domain module from the received line interrupt request, and generate a corresponding message interrupt request according to the target line interrupt request.

[0025] The output module 200 is configured to receive a message interrupt request sent by at least one interrupt domain module 100 and control the output of the message interrupt request.

[0026] For example, the at least one interrupt domain module may include multiple interrupt domain modules 100, that is, the interrupt controller includes multiple interrupt domain modules 100. The interrupt controller 10 may be connected to at least one interrupt line, and the external device may send a line interrupt request to the interrupt controller 10 through the at least one interrupt line, and the interrupt controller 10 may assign the received line interrupt request to multiple interrupt domain modules 100 for processing. Each interrupt domain module 100 may filter out a line interrupt request that matches itself and is valid from the received line interrupt request as a target line interrupt request, and process the target line interrupt request. Each interrupt domain module may run independently, and multiple interrupt domain modules 100 may be processed in parallel to improve processing efficiency. For example, different line interrupt modules may correspond to different privilege levels, and the matching of the line interrupt request with the interrupt domain module may be understood as matching the privilege level setting of the interrupt domain module, that is, the line interrupt request belongs to the current interrupt domain module.

[0027] For example, multiple interrupt domain modules 100 can process multiple types of line interrupt requests, each interrupt domain module can correspond to one type of line interrupt request, or two or more interrupt domain modules 100 can correspond to one type of line interrupt request. The multiple types can be divided according to the privilege level of the computer architecture or the type of the interrupt request initiating device.

[0028] For example, each interruption domain module 100 may filter out valid line interruption requests that match its own type from the received line interruption requests, and generate a corresponding message interruption request according to each filtered line interruption request.

[0029] For example, each interrupt domain module 100 can send the generated message interrupt request (request MSI_1 and request MSI_2 as shown in the figure) to the output module 200. The output module 200 can arbitrate and select the message interrupt request for each output based on the time of receiving the message interrupt request and / or the type of the message interrupt request, thereby realizing the output management of the message interrupt request. The output module 200 can also be called an output selection module.

[0030] The embodiment of the present disclosure provides an architecture of an interrupt controller, which can realize the conversion of line interrupt requests to message interrupt requests. In the processing program after the interrupt controller, only the message interrupt request needs to be processed without processing the line interrupt request, so that the interrupt system based on message interrupt can be adopted in the architecture such as RISC-V. After adopting the interrupt controller of the embodiment of the present disclosure, the line interrupt request can be processed in the interrupt system based on message interrupt, and the purpose of processing external line interrupts when the interrupt system based on message interrupt is adopted in the future under the architecture such as RISC-V is achieved, so that the architecture such as RISC-V can support more interrupts, reduce the number of interrupt lines, and improve flexibility.

[0031] Furthermore, in the interrupt controller provided in at least one embodiment of the present disclosure, at least one interrupt domain module is provided, and each interrupt domain module can process a line interrupt request that matches its type, so that the interrupt controller can process different types of line interrupt requests separately, and manage the output of message interrupt requests generated by each interrupt domain module through the output module, thereby realizing output management of different types of interrupt requests, and the processing efficiency and output flexibility of the interrupt controller are improved through the at least one interrupt domain module and the output module.

[0032] For example, in the case where multiple interrupt domain modules are provided, the multiple interrupt domain modules correspond to multiple privilege levels respectively. Matching with the current interrupt domain module may include: matching with the privilege level corresponding to the current interrupt domain module.

[0033] For example, the interrupt controller includes a first interrupt domain module and a second interrupt domain module, the first interrupt domain module corresponds to a first privilege level and is used to process an interrupt request with the first privilege level, and the second interrupt domain module corresponds to a second privilege level and is used to process an interrupt request with the second privilege level. For example, the privilege level can be understood as an importance level.

[0034] For example, multiple interrupt domain modules correspond to multiple different privilege levels, so that interrupt requests of different privilege levels can be processed separately. Multiple interrupt domain modules can respectively generate message interrupt requests with multiple privilege levels, and the output module can perform output management according to the privilege level of the message interrupt request.

[0035] For example, the interrupt controller can be used for a reduced instruction set computer architecture, such as a fifth-generation reduced instruction set computer architecture (RISC-V architecture). Some embodiments of the present disclosure also provide a message interrupt transmission data protocol, and the message interrupt request generated by each interrupt domain complies with the provisions of the data protocol. The data protocol includes information such as a data frame format and a privilege level definition, and each data bit width also has a certain expansion space. It is not only suitable for converting line interrupt requests into message interrupt requests, but also can be used as a message interrupt transmission data protocol for SoC platforms that support message interrupt systems in the future. The data protocol will be described in detail in subsequent embodiments.

[0036] For example, multiple interrupt domain modules can correspond to multiple privilege levels of the computer architecture (such as RISC-V architecture) to which the interrupt controller is applied. Based on this approach, the conversion of line interrupt requests to message interrupt requests can be realized in architectures such as RISC-V, and then an interrupt system based on message interrupts can be adopted in architectures such as RISC-V.

[0037] For example, the RISC-V architecture has the following privilege levels: Machine Level, Supervisor Level, and User Level. For processors that support virtualization, the Supervisor Level privilege level interrupt domain can be further subdivided into Virtual Supervisor Level privilege levels based on configuration information. The interrupt controller can set the interrupt domain module based on the privilege level of the RISC-V architecture.

[0038] For example, the multiple interrupt domain modules include at least part of the following: a first interrupt domain module corresponding to a machine-level privilege level; a second interrupt domain module corresponding to a supervisor-level privilege level; a third interrupt domain module corresponding to a user-level privilege level; and a fourth interrupt domain module corresponding to a virtual supervisor-level privilege level.

[0039] For example, one (or more) interrupt domain modules may be set for each privilege level of the RISC-V architecture, and the interrupt controller may include the first interrupt domain module, the second interrupt domain module, the third interrupt domain module, and the fourth interrupt domain module. Based on this approach, interrupt requests for each privilege level under the RISC-V architecture may be processed and managed separately.

[0040] For example, in other embodiments, the second interrupt domain module and the fourth interrupt domain module may be implemented as one interrupt domain module, which determines whether the interrupt request corresponds to a supervisor privilege level or a virtual supervisor privilege level according to different configuration information.

[0041] For example, in some of the following embodiments, a line interrupt request may be referred to as a line interrupt, a message interrupt request may be referred to as a message interrupt, a line interrupt request or a message interrupt request may be referred to as an interrupt request or an interrupt, and an interrupt domain module may be referred to as an interrupt domain.

[0042] For example, the interrupt controller may further include a collection module 300, which is configured to receive a line interrupt request, perform clock domain synchronization processing on the received line interrupt request, and send the processed line interrupt request to the at least one interrupt domain module.

[0043] For example, the interrupt controller may have two levels: a top layer and a core layer. The top layer may be provided with the acquisition module 300, and the core layer is located within the top layer. The core layer may include all interrupt domain modules 100 and their related configuration modules and output modules, etc., and is the core module of the interrupt controller.

[0044] For example, the acquisition module 300 can be connected to the interrupt line to obtain a line interrupt request from the interrupt line. The acquisition module 300 can perform clock domain synchronization processing on the input line interrupt request signal. The clock domain synchronization processing can be, for example, secondary register synchronization, which is used to transfer a signal from one clock domain (source clock domain) to another clock domain (target clock domain). When the clock pulse of the source clock domain arrives, the source trigger locks the input signal in its own storage unit. When the clock pulse of the target clock domain arrives, the target trigger copies the data in the source trigger to its own storage unit, thus realizing signal synchronization between the two clock domains. By performing secondary register synchronization on the line interrupt request, the synchronization of the line interrupt request from one clock domain to another clock domain where the interrupt controller is located can be realized.

[0045] For example, in the case where the interrupt controller includes multiple interrupt domain modules, the multiple interrupt domain modules can be cascaded, and the privilege levels corresponding to the first-level interrupt domain modules to the last-level interrupt domain modules are successively reduced. Each interrupt domain module is further configured to: receive a line interrupt request sent by the acquisition module or the upper-level interrupt domain module, obtain a target line interrupt request that matches the current interrupt domain module from the received line interrupt request, generate a corresponding message interrupt request according to the target line interrupt request, and send a valid line interrupt request that does not match the current interrupt domain module to the next-level interrupt domain module.

[0046] For example, mismatch with the current interrupt domain module can be understood as mismatch with the privilege level setting of the current interrupt domain module, that is, it does not belong to the current interrupt domain module. The line interrupt request sent by the current interrupt domain module to the next-level interrupt domain module is in a valid state, that is, the line interrupt request is enabled. If a line interrupt request does not match the current interrupt domain module but is not enabled, the current interrupt domain module will not send the line interrupt request to the next-level interrupt domain module.

[0047] For example, if the interrupt controller includes N interrupt domain modules (N is an integer greater than or equal to 2), the first-level interrupt domain module to the Nth-level interrupt domain module are connected in sequence, and the first-level interrupt domain module can be connected to the acquisition module 300. The first-level interrupt domain module can also be called a root node interrupt domain module. The acquisition module 300 can send all line interrupt requests to the first-level interrupt domain module. The first-level interrupt domain module selects the line interrupt requests that match its own privilege level from the received line interrupt requests for processing, and sends the remaining line interrupt requests to the second-level interrupt domain module. The second-level interrupt domain module selects the line interrupt requests that match its own privilege level from the received line interrupt requests for processing, and sends the remaining line interrupt requests to the third-level interrupt domain module, and so on, until the last-level interrupt domain module. The configuration, identification, and arbitration of each interrupt request are completed in each level of the interrupt domain module, and converted into a message interrupt request. At least one embodiment of the present disclosure also defines an efficient data protocol for transmitting message interrupt requests in an interrupt system based on message interrupts, which will be described in detail in the following embodiments.

[0048] For example, the ranking of the machine level, supervisor level, and user level mentioned above may be that the machine level is higher than the supervisor level and the supervisor level is higher than the user level. Therefore, in some embodiments, if the interrupt controller is provided with a two-level interrupt domain module, the first-level interrupt domain module may be set to correspond to the machine-level privilege level, and the second-level interrupt domain module may be configured to correspond to the supervisor-level privilege level. Furthermore, in other embodiments, if the interrupt controller is provided with a three-level interrupt domain module, in addition to the first-level interrupt domain module and the second-level interrupt domain module, the third-level interrupt domain module may be configured to correspond to the user-level privilege level. By means of this cascading method, it can be ensured that interrupt requests with higher privilege levels among multiple interrupt requests arriving in the same time period are processed earlier in priority.

[0049] For example, in other embodiments, multiple interrupt domain modules may be in parallel, and the output of the acquisition module may be connected to the input of multiple interrupt domain modules. Alternatively, multiple interrupt domain modules other than the first-level interrupt domain module may be in parallel, and the output of the first-level interrupt domain module may be connected to the input of the remaining multiple interrupt domain modules.

[0050] For example, the output module includes a second finite state machine and a second arbitration submodule, the second finite state machine has a first state and a second state, in the first state, in response to receiving a message interrupt request sent by at least one interrupt domain module, the second finite state machine jumps to the second state; while the second finite state machine jumps from the first state to the second state, the second arbitrator selects the message interrupt request to be output from the received message interrupt request, outputs the message interrupt request to be output to the interrupt target module, and waits for the confirmation signal returned by the interrupt target module; in response to receiving the confirmation signal returned by the interrupt target module, the second finite state machine jumps back to the first state. The interrupt target module is the recipient of the interrupt request, and the interrupt target module can perform the corresponding interrupt operation after receiving the interrupt request.

[0051] For example, the output module may be a selector using a polling arbitration mechanism, including a polling arbitrator (ie, the second arbitration submodule) and a control state machine (ie, the second finite state machine).

[0052] Figure 2 A schematic diagram of state transition of an output module provided by at least one embodiment of the present disclosure is shown.

[0053] like Figure 2As shown, the second finite state machine has two states: the first state and the second state. The initial state is the first state. In the first state, if the output module does not receive a valid message interrupt request from multiple interrupt domain modules, it remains in the first state. For example, a multi-bit request control signal tvalid_req_use can be used to determine whether a valid message interrupt request is received. If the signal tvalid_req_use is invalid after bitwise OR (tvalid_req_use!=1), it means that a valid message interrupt request has not been received. If the signal tvalid_req_use is valid after bitwise OR (tvalid_req_use==1), it means that a valid message interrupt request has been received. After receiving a valid message interrupt request, the second finite state machine jumps from the first state to the second state. When the second finite state machine jumps from the first state to the second state (for example, within the same clock cycle), the second arbitration submodule arbitrates the current message interrupt request to be output from the valid message interrupt request that has been received, and samples and stores the arbitration result. Therefore, the first state can indicate that the arbitration result of the second arbitration submodule will be sampled and stored. When the arbitration result of the second arbitration submodule is sampled and stored, the first state ends. The second state can indicate that the stored message interrupt request is being sent. When the stored message interrupt request is successfully sent, the second state ends. Specifically, in the second state, it is determined whether the message interrupt request to be output has been issued and whether a confirmation signal (reply signal) returned by the interrupt target module has been received. The interrupt target module refers to the recipient of the message interrupt request, that is, the target party (or target end) that the message interrupt request wants to interrupt. The signal tvalid can be used to indicate whether the message interrupt request to be output has been issued, and the signal tready can be used to indicate the confirmation signal (handshake signal) returned by the target end after receiving the message interrupt request. If the signal tvalid or the signal tready is invalid (!(tvalid&tready)), it indicates that the message interrupt signal to be output has not been issued or the confirmation signal returned by the interrupt target module has not been received, then the second state is maintained; if the signal tvalid and the signal tready are both valid ((tvalid&tready)), it indicates that the message interrupt signal to be output has been issued and the confirmation signal returned by the interrupt target module has been received, then the second state is jumped back to the first state.

[0054] For example, the second arbitration submodule is configured to select the message interrupt request to be output according to the privilege level corresponding to the received message interrupt request and the clock cycle of the received message interrupt request. The second arbitration submodule can be further configured to: for multiple message interrupt requests received in the same clock cycle, give priority to the message interrupt request with a higher privilege level; for multiple message interrupt requests received in different clock cycles, give priority to the message interrupt request with an earlier clock cycle.

[0055] For example, in the first clock cycle, message interrupt requests M1 and M2 are received, and request M1 has a higher priority than request M2. In the second clock cycle, message interrupt request M3 is received. For these three message interrupt requests, the second arbitration submodule will respond to interrupt M1 first, then interrupt M2, and finally interrupt M3. Even if interrupt M3 has a higher priority than interrupt M2, interrupt M2 in the previous clock cycle will be processed first. Based on this method, it can ensure that high-priority message interrupt requests in the same period are responded to first, and it can also avoid the phenomenon that low-priority message interrupt requests are not responded to for a long time.

[0056] Figure 3 A schematic diagram of a second arbitration submodule provided by at least one embodiment of the present disclosure is shown.

[0057] like Figure 3 As shown, the second arbitration submodule may include a first arbitrator, a second arbitrator and a shielding signal generating module. The message interrupt request output by each interrupt domain module carries the index number of the interrupt domain module. The higher the privilege level of the interrupt domain module, the lower the index number corresponding to the interrupt domain module. For example, if the index number of the first-level interrupt domain module is 1, then the message interrupt request output by the first-level interrupt domain module carries the index number 1 of the first-level interrupt domain module. If the index number of the second-level interrupt domain module is 2, then the message interrupt request output by the second-level interrupt domain module carries the index number 2 of the second-level interrupt domain module. The second arbitration submodule may arbitrate according to the default priority rule that the lower the index number of the message interrupt request, the higher the priority. For example, the request corresponding to the index number 0 is always invalid. The first arbitrator and the second arbitrator are both low-priority ordinary arbitration selectors that comply with the above rules. The difference is that the input of the first arbitrator is a message interrupt request signal and a shielding signal, and the input of the second arbitrator is a message interrupt request signal without a shielding signal. In order to distinguish, in the following embodiments, the first arbitrator is also referred to as a masked input arbiter, and the second arbitrator is also referred to as a non-shielded input arbiter. The shielding signal generating module is used to generate a shielding signal.

[0058] For example, for message interrupt requests received in the same round (for example, the same clock cycle), high-priority requests are processed first. After the high-priority requests are processed, the processed high-priority requests can be shielded, and the remaining low-priority requests are in an unshielded state. In this way, low-priority requests in the current round can be processed without skipping low-priority requests in the current round to process high-priority requests in the next round, thereby avoiding the situation where low-priority requests are never processed.

[0059] For example, the result of the bitwise OR of the masked request can be determined to determine which normal arbiter to select from the masked input arbiter and the non-masked input arbiter. If the bitwise OR of the masked request is 0, there is no unmasked request in the current round (no unprocessed low-priority request), so the result of the non-masked input arbiter is selected; if the bitwise OR of the masked request is 1, there is still an unmasked interrupt request in the current round (there is still an unprocessed low-priority request), so the result of the masked input arbiter is selected to ensure that all requests in the current round are processed before processing the subsequent requests. The polling arbitration of a specified number of requests is realized by combining two low-priority normal arbiters. The polling arbitration output result signal is a one-hot code, and the mask signal generation module can use the progressive bitwise OR result of the one-hot code as the value of the next bit of the mask signal (mask) to generate each bit of the mask signal. After all the interrupt requests in the current round are output, the masking of each interrupt request can be released so that the interrupt request corresponding to the corresponding index number can continue to participate in the arbitration of the next round.

[0060] Figure 4 A schematic diagram of an interrupt domain module provided by at least one embodiment of the present disclosure is shown.

[0061] like Figure 1 and Figure 4 As shown, for example, each interrupt domain module may include a register control submodule 110, an input management submodule 120, a distribution submodule 130, and a processing submodule 140. The register control submodule 110 is configured to receive configuration information, configure the control and status registers of the interrupt domain module based on the configuration information, and control other submodules in the interrupt domain module based on the configured control and status registers, and record the execution status of the interrupt domain module. The input management submodule 120 is configured to obtain a target line interrupt request that matches the current interrupt domain module from the received multiple line interrupt requests. The distribution submodule 130 is configured to send the line interrupt request that does not match the current interrupt domain module among the received multiple line interrupt requests to the next-level interrupt domain module. The processing submodule 140 is configured to process the target line interrupt request sent by the input management submodule in sequence, generate a corresponding message interrupt request, and send the message interrupt request to the output module.

[0062] For example, Figure 1 As shown, the interrupt controller may further include a configuration module 400 , which is used to enable an interrupt domain module 100 corresponding to the address information among multiple interrupt domain modules 100 according to the address information, and send configuration information to the enabled interrupt domain module 100 .

[0063] For example, the configuration module 400 can be connected to the register control submodules 110 of multiple interrupt domain modules 100 via an Advanced Peripheral Bus (APB) configuration interface. The register control submodule 110 of each interrupt domain module 100 can include control and status registers, which can be configured via the configuration module 400.

[0064] For example, each interrupt domain module 100 may be configured by the configuration module 400 before the interrupt controller 10 starts to receive and process line interrupt requests. The configuration module 400 may enable one interrupt domain module 100 at a time to configure the enabled interrupt domain module 100 until all interrupt domain modules 100 are configured.

[0065] For example, the configuration module 400 can be a branch selection controller of the APB interface, which controls the corresponding bit of the multi-bit wide chip select signal (pselx signal) to be valid according to the address range to be accessed, and accesses the memory mapping register space of the corresponding interrupt domain module. Each bit of the chip select signal is connected to the APB interface of an interrupt domain module respectively, and the multi-bit signals of the chip select signal are arranged in order from low to high according to the index number. The smaller the index number, the higher the privilege level of the corresponding interrupt domain module. Other APB interfaces can be connected to all interrupt domain modules indiscriminately. For example, the first bit (bit0) of the chip select signal pselx[1:0] is valid, indicating that the control and status register access of the first-level interrupt domain module is valid, and the second bit (bit1) is valid, indicating that the control and status register access of the second-level interrupt domain module is valid.

[0066] For example, the configuration module can determine the interrupt domain module to be accessed by the starting address of the control and status register (CSR) space of each control domain module, but this method requires calculating the address of the control and status register and fixing the address in the design. If the number of interrupt domain modules changes or the space size of the control and status register changes, the address needs to be recalculated and fixed, which causes inconvenience. Therefore, the embodiment of the present disclosure provides another method for determining the register address. For example, the space capacity of the control and status register of each interrupt domain module is the same, and the configuration module 400 can determine the address information according to the base address, the space capacity of the control and status register and the index number of the interrupt domain.

[0067] For example, the space size of the command and status register (CSR) of each interrupt domain can be the same. The embodiment of the present disclosure adds an input signal to the configuration module: the space capacity signal (addr_range_s) is used to indicate the size of the register space capacity required by each interrupt domain module. The space capacity can be set to 15'h4000, for example, indicating 16KByte. In this way, only an overall register base address (BA) is required. The interrupt domain module to be accessed can be determined by adding the base address to the product of the space capacity of the control and status register (addr_range_s) and the index number of the interrupt domain module. Based on this method, it will become easier and more convenient to increase the number of interrupt domain modules or to change the size of the control and status register space in the interrupt domain.

[0068] For example, after the control and status registers of each interrupt domain module 100 are configured, each interrupt domain module 100 may start to receive and process line interrupt requests.

[0069] For example, each instantiated interrupt domain module is a multiple instantiation of the same module, and the hierarchical relationship and privilege level of the interrupt domain module can be identified and distinguished by the parameter SUBSYS_ID that is the same as the serial number of the instantiation name. Each interrupt domain module can also be called an interrupt controller subsystem, referred to as an interrupt domain subsystem. In the following embodiments, the processing flow of an interrupt domain module (e.g., a first-level interrupt domain module) is used as an example for explanation, and the processing flow of other interrupt domain modules can refer to the processing flow of the first-level interrupt domain module.

[0070] For example, the acquisition module 300 sends the line interrupt request to the first-level interrupt domain module 100, and the input management submodule 120 in the interrupt domain module 100 receives the line interrupt request sent by the acquisition module. For example, the input management submodule 120 can select the line interrupt request assigned to the current interrupt domain module (interrupt domain), obtain a unified high-effective input, control the change of the pending bit (pending bit), and generate a request signal for arbitration to send to the arbitration module.

[0071] For example, the input management submodule 120 can be configured as follows: filter out the line interruption requests that match the current interruption domain module from the multiple line interruption requests received; for the filtered line interruption requests, uniformly adjust the line interruption requests to be high level valid or uniformly adjust them to be low level valid (the following embodiments are explained using uniform high level valid as an example); when the valid edge of the line interruption request is identified, change the corresponding suspend signal from the initial value to the first value; obtain a valid line interruption request as the target line interruption request based on the suspend signal, global enable signal and interrupt enable signal corresponding to the line interruption request; when the message interruption request corresponding to the target line interruption request is output by the output module, change the corresponding suspend signal from the first value back to the initial value.

[0072] For example, the interrupt trigger modes of the line interrupt request signals sent by different peripheral components are different, some are low level valid (for example, represented by Level0), some are high level valid (for example, represented by Level1), some are rising edge valid (for example, represented by Edge1), some are falling edge valid (for example, represented by Edge0), etc. The input management submodule 120 can convert the input value according to different interrupt trigger mode configurations, and the converted input value is called the recognized input value (rectified input value). At this time, different types of interrupt trigger modes can be uniformly converted to high level or high pulse valid, which is convenient for subsequent processing.

[0073] For example, the following Table 1 shows the correspondence between conversion operations and interrupt trigger modes. The exclusive OR operation (XOR) indicates that an exclusive OR operation is performed on the input signal and the opposite operand at the source end in the third column of the table.

[0074] Table 1

[0075] Trigger mode configuration Trigger mode type The opposite operand of the source Recognized input value 0 Inactive \ 0 1 Detached \ 0 2-3 Reserved \ 0 4 Rising edge (Edge1) 0 XOR result 5 Falling edge (Edge0) 1 XOR result 6 High level (Level 1) 0 XOR result 7 Low level (Level 0) 1 XOR result

[0076] Figure 5 A schematic diagram showing various input signals before and after adjustment provided by at least one embodiment of the present disclosure is shown.

[0077] like Figure 5 As shown, the input signals S1~S4 correspond to the four effective trigger modes (Edge1, Edge0, Level1 and Level0) in Table 1 respectively. After the "XOR" operation, the input signals S1~S4 are uniformly high pulse or high level valid results, that is, the input value after recognition. According to this value, the rising edge or falling edge can be used to uniformly judge the interruption of the input signal.

[0078] For example, the input management submodule 120 can also implement the control of the suspend bit. When the rising edge of the identified input signal appears and meets the suspend position start condition, the suspend bit of the corresponding interrupt is set (for example, becomes 1). There may be multiple suspend positions at the same time. For example, as long as the rising edge of the identified input signal changes, it can be set. When the suspend bit release condition is met, the suspend bit of the corresponding interrupt request is released (becomes 0). For example, the corresponding suspend bit can be cleared after the corresponding message interrupt request is sent. The setting and release (assert / de-assert) conditions here are compatible with the provisions of the RISC-V AIA (Advanced Interrupt Architecture) standard.

[0079] Figure 6 A schematic diagram of generating a valid line interrupt request provided by at least one embodiment of the present disclosure is shown.

[0080] like Figure 6 As shown, the input management submodule 120 can also generate a valid line interrupt request. The input management submodule 120 can use the suspend bit to generate a valid line interrupt request. For example, the suspend bit can be first "logically ANDed" with the global enable bit (for example, represented by IE bit), and then "logically ANDed" with the corresponding interrupt enable bit (for example, represented by enable[i]). After that, the corresponding valid line interrupt request is obtained and sent to the first arbitration submodule in the processing submodule as the target line interrupt request. The first arbitration submodule selects an interrupt request that obtains the sending permission from multiple valid line interrupt requests to continue subsequent processing.

[0081] For example, only when both the global enable signal and the interrupt enable signal are valid can a valid line interrupt request be generated, so that the line interrupt request can continue subsequent processing. The global enable signal corresponds to the current interrupt domain module, and the global enable signal is valid, for example, indicating that the current interrupt domain module is allowed to process the received line interrupt request, or the global enable signal can correspond to the entire interrupt controller, and the global enable signal is valid, for example, indicating that the interrupt controller is allowed to process the received line interrupt request. The interrupt enable signal is the enable signal of the line interrupt request itself. Based on this method, the line interrupt request can be processed normally in some cases, and the entire interrupt controller or a certain interrupt domain module can be prevented from processing the line interrupt request in some cases, which increases the flexibility of processing.

[0082] For example, the distribution submodule 130 may send the line interruption request that does not match the current interruption domain module among the multiple line interruption requests received by the current interruption domain module to the next-level interruption domain module. For example, the distribution submodule 130 may be implemented by a "logical AND" operation, and all line interruptions of the interruption domain module are bit-wise "logically ANDed" with the configuration value of the distribution configuration register of the current interruption domain module and then sent out.

[0083] For example, after the input management submodule 120 obtains a valid line interruption request, it sends the valid line interruption request to the processing submodule 140 , which can perform arbitration, encoding conversion and other operations on the valid line interruption request and generate a corresponding message interruption request.

[0084] For example, the processing submodule 140 may include a first arbitration submodule 141, a coding conversion submodule 142 and a message interruption control submodule 143. The first arbitration submodule 141 is configured to perform arbitration selection processing on the target line interruption request sent by the input management submodule, select the target line interruption request to be processed, and represent the index information of the target line interruption request to be processed in a one-hot code encoding form; the coding conversion submodule 142 is configured to convert the index information in the one-hot code encoding form into the index information in the binary encoding form; the message interruption control submodule 143 is configured to generate a corresponding message interruption request according to the target line interruption request to be processed corresponding to the index information in the binary encoding form, and send the message interruption request to the output module.

[0085] For example, each interrupt domain module may include a first finite state machine, the first finite state machine having an initial state, a waiting state and a sending state. The first finite state machine may reflect the overall state of the interrupt domain module, and the first finite state machine may be set in the message interrupt control submodule.

[0086] Figure 7 A state transition diagram of a first finite state machine provided by at least one embodiment of the present disclosure is shown.

[0087] like Figure 4 and Figure 7 As shown, for example, in the initial state, in response to the first arbitration submodule 141 selecting a target line interrupt request to be processed, the first finite state machine jumps to a waiting state; in the waiting state, in response to the message interrupt control submodule 143 generating a message interrupt request, the first finite state machine jumps to a sending state; in the sending state, in response to the message interrupt request being sent by the output module 200 to the interrupt target module and receiving a confirmation signal returned by the interrupt target module, the first finite state machine jumps back to the initial state.

[0088] For example, the implementation of the first arbitration submodule 141 is similar to that of the second arbitration submodule in the aforementioned output module, and the composition of the first arbitration submodule 141 can be the same as that of the second arbitration submodule in the aforementioned output module. The first arbitration submodule 141 can complete the selection of the interrupt request by polling the arbitrator. Unlike the second arbitration submodule, the arbitrator of the first arbitration submodule 141 is controlled by the overall state machine (first finite state machine) of the interrupt domain module. The quantity parameter of the first arbitration submodule 141 is different from that of the second arbitration submodule. The quantity parameter represents the number of input interrupt requests. The input signal of the first arbitration submodule 141 is the interrupt request gated by the input management submodule 120, and the input signal of the second arbitration submodule is the interrupt request sent by the message control submodule 140 of each interrupt domain module. The second arbitration submodule can determine the arbitration priority according to the index number of the corresponding interrupt domain module carried by the message interrupt request, and the first arbitration submodule 141 can determine the arbitration priority according to the identification number of the line interrupt request, and the polling arbitration is performed according to the priority of the line interrupt request with a smaller identification number and a higher priority. For example, the interrupt controller supports 255 valid external line interrupts, which correspond to 255 numbers respectively, and the number corresponding to the interrupt request is used as the identification number of the interrupt request (or the index number of the line interrupt request).

[0089] For example, the arbitration operation of the first arbitration submodule 141 occurs in the initial state of the first finite state machine, obtains the result of one-hot index encoding, and clears the corresponding request signal to complete an arbitration process. The one-hot index encoding is used as the index information of the interrupt request to distinguish different interrupt requests. Then, the first finite state machine jumps to start the generation and sending control process of the message interrupt request. When the message interrupt request is successfully issued by the interrupt controller, its corresponding suspension bit can be cleared.

[0090] For example, the encoding conversion submodule can realize the conversion from one-hot encoding to binary encoding (binary index) for subsequent processing. The hardware parameter (WIRE_NUM) can be used to represent the number of line interrupt requests supported by the interrupt controller. The bit width required for binary encoding is obtained by performing logarithmic calculation on the hardware parameter: ceil[log2(WIRE_NUM)], where ceil represents rounding up, and WIRE_NUM is the number of line interrupt requests supported by the interrupt controller. Binary encoding can start from 0 and increase in sequence. The following table 2 shows the mapping relationship table from 6-bit one-hot encoding to 3-bit binary encoding. For example, the hardware parameter (WIRE_NUM) is 256, which means that 255 valid external line interrupt indexes are supported, and the required binary encoding bit width is 8 bits.

[0091] Table 2

[0092]

[0093] For example, the message interrupt control submodule 143 can also be controlled by the first finite state machine. When the first finite state machine is in the initial state, the first arbitration submodule 141 is allowed to arbitrate, grant sending permission to a certain interrupt request, and jump to the waiting state when a valid interrupt request is selected. Entering the waiting state means suspending and converting the line interrupt request to a message interrupt request. The message interrupt control submodule 143 can obtain or parse the information required for the message interrupt request from the configuration information of the interrupt domain module and the privilege level corresponding to the current interrupt domain module, generate a request control signal (such as the above-mentioned tvalid signal), and jump to the sending state. Entering the sending state means that the generated message interrupt request is being sent and waiting for the external return handshake signal (such as the above-mentioned tready signal). When the handshake signal is received, the sending of an interrupt request is completed, and then the process jumps back to the initial state.

[0094] For example, Figure 4 The components and structure of the interrupt domain module 100 shown are merely exemplary and non-limiting. The interrupt domain module 100 may also have other components and structures as required.

[0095] For example, each interrupt domain module 100 is further configured to generate and process an immediate interrupt signal and generate a corresponding immediate message interrupt request based on the immediate interrupt signal, wherein the immediate interrupt signal is generated by writing a first register in the register control submodule.

[0096] For example, the chip includes multiple processor cores, and the interrupt target module of the interrupt request can be, for example, one of the multiple processor cores. If the chip wants to run a certain processor core (for example, processor core C1) in low power mode, that is, the processor core C1 is offline, and the processor core C1 in low power mode no longer receives interrupt requests, then in this case, the control and status registers in the interrupt controller need to be reconfigured. If a message interrupt request is being sent to the processor core C1, and the processor core C1 enters a low power state, then the message interrupt request will not be responded to. In order to avoid this situation, an instant message interrupt processing flow is added. Before the processor core C1 goes offline (enters a low power state), the interrupt controller can be prevented from processing new line interrupt requests, and then an instant interrupt signal corresponding to the processor core C1 is generated by writing a register and a corresponding instant message interrupt request (extempore MSI) is generated based on the instant interrupt signal. Then, the instant message interrupt request is the last interrupt request sent to the processor core C1. When the processor core C1 receives the instant message interrupt request, it can be considered that all message interrupt requests sent to the processor core C1 have arrived, and the low power state can be entered.

[0097] For example, the register control submodule includes a specific register (first register), and the software can write to the specific register to generate an immediate interrupt signal. The information of the immediate message interrupt request can come from the configuration information of the bit field of the specific register, and the pending instant message interrupt request is sent from the interrupt controller with minimum delay. This message interrupt is used to synchronize the order of message interrupt requests between the interrupt controller and the processor core, so that the software can determine that when the instant message interrupt request is received, all the message interrupt requests previously sent to a processor core have arrived at the core. Therefore, the instant message interrupt request is used as the interrupt domain module's current or next interrupt request that is granted the right to send.

[0098] For example, the register control submodule is further configured as follows: if the immediate interrupt signal is generated during the period when the first finite state machine is in the initial state or before the initial state, the line interrupt request to be input to control the first arbitration submodule is invalidated, and the message interrupt control submodule is controlled to generate and output the corresponding immediate message interrupt request; if the immediate interrupt signal is generated during the period when the first finite state machine is in the waiting state, the line interrupt request to be input to control the first arbitration submodule is invalidated, the encoding conversion submodule and the message interrupt control submodule are controlled to process the target line interrupt request to be processed currently selected by the first arbitration submodule, and after obtaining the corresponding message interrupt request and sending it to the output module, the message interrupt control submodule is controlled to generate and output the corresponding immediate message interrupt request.

[0099] For example, with respect to the first finite state machine control, the immediate interrupt signal occurs before or after the initial state, and the interrupt controller has two different processing flows. The generation of the immediate interrupt signal (the immediate interrupt signal is pulled high) indicates that the software has written a specific register and wants to generate an immediate message interrupt request. After the immediate message interrupt request is issued, the immediate interrupt signal can be cleared.

[0100] For example, if an immediate interrupt signal is generated by writing a specific register during the initial state or before entering the initial state, the input signal (line interrupt request signal) of the first arbitration submodule is directly invalidated by negating the immediate interrupt signal and performing bitwise logical AND on the input request of the first arbitration submodule, thereby achieving the effect of shutting down the first arbitration submodule. The first arbitration submodule selects an invalid arbitration result (all results are 0), and the immediate interrupt signal causes the first finite state machine to jump to the waiting state. At this time, the message interrupt control submodule generates a corresponding immediate message interrupt request according to the immediate interrupt signal, and then the first finite state machine jumps to the sending state to send the immediate message interrupt request to the interrupt domain module and sends it to the output module. Since the target line interrupt requests that have been arbitrated in the interrupt domain module during the initial state or before entering the initial state have all generated corresponding message interrupt requests and have been issued, in this case, an immediate message interrupt request can be directly generated and issued, and it can be ensured that the immediate message interrupt request is the last message interrupt request sent to the corresponding interrupt target module.

[0101] For example, if an immediate interrupt signal (immediate interrupt signal is pulled high) is generated in the waiting state after the initial state, and the first arbitration submodule has arbitrated the target line interrupt request to be processed, the system can first perform a coding conversion operation on the target line interrupt request that has been arbitrated and generate a corresponding message interrupt request to be issued, and then invalidate the input signal (line interrupt request signal) of the first arbitration submodule to achieve the effect of shutting down the first arbitration submodule. At the same time, the immediate interrupt signal allows the first finite state machine to jump to the waiting state, and the message interrupt control submodule generates a corresponding instant message interrupt request according to the immediate interrupt signal. After that, the first finite state machine jumps to the sending state to send the instant message interrupt request to the interrupt domain module and sends it to the output module. Since the interrupt domain module has arbitrated the target line interrupt request to be processed in the waiting state, the interrupt request can be processed and issued first, and then the instant message interrupt request can be generated and issued to ensure that the instant message interrupt request is the last message interrupt request sent to the corresponding interrupt target module.

[0102] For example, the control and status registers are reconfigured in the following ways: turning off the global enable signal and the interrupt enable signal; generating an instant message interrupt by writing the first register in the register control submodule; and reconfiguring the control and status registers of the interrupt domain after the interrupt target module receives the instant message interrupt.

[0103] For example, before reconfiguring the control and status registers, the global enable signal and the interrupt enable signal of the interrupt domain module can be turned off first, for example, the global enable signal and the interrupt enable signal of the interrupt domain module can be written to 0, so that each interrupt domain module no longer generates a valid line interrupt request. Then, read the specified bit field of the specific register (the first register), and if its value is 0, proceed to the next step. The software writes the immediate specific register in the form of a software lock to generate an immediate interrupt signal. After the interrupt target module receives the immediate interrupt signal, the control and status register space of the interrupt domain module can be reconfigured. If the control and status registers of multiple interrupt domain modules need to be reconfigured, the above process can be repeated for each interrupt domain module. After completing the configuration operation, the global enable signal and the interrupt enable signal of each interrupt domain module can be reopened.

[0104] For example, at least one embodiment of the present disclosure provides an efficient data protocol for transmitting message interrupt information in an interrupt system of a message interrupt, and can convert an external line interrupt request into a message interrupt request that complies with the data protocol.

[0105] For example, the data protocol corresponding to the message interrupt request includes at least part of the following: a control signal regarding the message interrupt request sent to the interrupt target module; a confirmation signal returned by the interrupt target module after receiving the message interrupt request; data information, the data information including the identification number, interrupt type, privilege level information and target virtual machine number of the external line interrupt request corresponding to the message interrupt request; routing information of the interrupt target module; and information on the initiator of the interrupt request.

[0106] For example, the following Table 3 is an interrupt transmission data protocol provided by an embodiment of the present disclosure, which can adopt an AXI4-Stream interface, hereinafter referred to as an A4S interface. The prefix mas of the signal name in Table 3 refers to master, indicating the interface signal of the sender. Table 3 is, for example, defined based on supporting 2 chips (die), each chip including 4 cores (hart). In other embodiments, more or fewer chips or cores can be supported, and corresponding expansion can be performed according to the following description.

[0107] Table 3

[0108]

[0109] For example, the target end represents the target recipient of the interrupt request, the signal mas_tvalid and the signal mas_tvalid are the handshake information between the source end and the target end, the signal mas_tvalid indicates that the source end has sent a message interrupt request to the target end, and the mas_tready signal indicates the confirmation signal returned by the target end after receiving the message interrupt request sent by the source end. All cores (hart) on a chip (die) are divided into a group (group), and the group index number (group number) is used to determine whether it is a cross-chip (die) interrupt. The core index number (hart number) is the target core index number configured by the software in the control and status register space. The mas_tid signal can be used to distinguish whether the source end is an interrupt controller, a bus (PCIE) or other (such as a core hart), and can distinguish which interrupt domain module of the interrupt controller, or which PCIE bus, etc. the source end is.

[0110] For example, the data information may include multiple data segments, each data segment includes multiple bits of data. The data information includes, for example, 64 bits, one of which (for example, bits 0 to 10) represents the identification number of the external interrupt request (ExternalInterrupt Identifier). For example, the interrupt controller supports 255 valid external line interrupt indexes, each corresponding to 255 numbers, and the number corresponding to the interrupt request is used as the identification number of the interrupt request. Another data segment (for example, bits 16 to 18) represents the type of interrupt request (external interrupt, software interrupt, software external interrupt, etc.). Another data segment (for example, bits 48 to 49) represents the privilege level of the interrupt request (machine level, supervisor level, virtual supervisor level, etc.). Another data segment (e.g., bits 50 to 55) indicates the target virtual machine number (or guest number). When the system supports virtualization, each core may include interrupt file spaces corresponding to all supported virtual machine numbers. According to the software routing configuration, the interrupt request points to the physical core that the virtual machine can access, so that the interrupt request can be sent directly to the virtual machine on the hardware without going through the management of the software-level manager (Hypervisor). For example, the identification number of the interrupt request and the target virtual machine number are both configured in the control and status register space of the interrupt domain module.

[0111] For example, the process of interrupt processing in the interrupt controller can be described as follows: initially, all interrupts can be assumed to belong to the first-level interrupt domain module (root interrupt domain), until the system completes the initialization of the control and status registers of all interrupt domain modules of the interrupt controller; the interrupt configured to be activated in a certain interrupt domain module obtains the identified input value (rectified input) according to its triggering mode value), and then logically ANDs the global enable signal and the interrupt enable signal to generate a valid interrupt request and send it to the first arbitration submodule; the first arbitration submodule performs polling arbitration according to the priority of the line interrupt index number with a smaller priority, and obtains the selected line interrupt index number after conversion and sends it to the message interrupt control submodule; the message interrupt control submodule obtains the target core, external interrupt identification number and other required information according to the configuration information in the control and status register in the interrupt domain module, packages it into a defined message interrupt data format and sends it out; if the message interrupts sent by different interrupt domain modules are generated at the same time, they are sent out in sequence through the output module; after a round of message interrupts are sent out by the output module, the masking of the index numbers of these interrupts can be released, so that the interrupts corresponding to these index numbers can continue to participate in the next round of arbitration; for multiple interrupt domain modules, the interrupts in the output module are arranged on a first-come-first-out basis. In a polling process, high-level interrupts are placed at the low index number position of the polling request and are sent out first.

[0112] Figure 8 A processing timing diagram provided by at least one embodiment of the present disclosure is shown.

[0113] like Figure 8 As shown, taking signal S1 as an example, the interrupt trigger mode of signal S1 is rising edge valid (Edge1). Starting from the recognized input value (rectified input value) corresponding to signal S1 ("S1_recognized value" in the figure), the process from an ideal arbitration of the interrupt controller to sending a message interrupt is shown.

[0114] For example, the group of signals of the input management submodule can be the process of generating an interrupt suspend signal ("S1_suspend signal" in the figure) and a valid line interrupt request ("S1_valid signal" in the figure) from the identified input value ("S1_identified value" in the figure). The edge-triggered interrupt signal is maintained for no less than 2 module main working clock cycles, otherwise it will not be regarded as a valid interrupt signal. The identified input value of each interrupt source is detected to have a rising edge of 2 clock cycles before its suspend position is set. The suspend bit logic and the global enable signal and the interrupt enable signal are used as a valid line interrupt request for the subsequent arbitration logic.

[0115] For example, the next packet signal after the input management submodule is the process of processing and arbitrating the line interrupt request input to the first arbitration submodule. The rising edge of the line interrupt request ("S1_valid_rising edge" in the figure) generates a request signal ("S1_request signal" in the figure, i.e., the aforementioned tvalid_req_use signal), and the S1_request signal is used to determine whether the line interrupt request needs arbitration. The initial state of the first finite state machine enables the gating signal ("arbitration enable signal" in the figure), and the S1_request signal is logically ANDed to obtain a cycle of arbitration request information ("S1_arbitration" in the figure), and the result information of the one-hot code encoding is obtained through the first arbitration submodule, and then the request signal of the corresponding interrupt ("S1_request signal" in the figure) is cleared, indicating that the interrupt corresponding to the interrupt index number has been selected and is to be sent. The one-hot code result obtained by arbitration in the initial state of the first finite state machine is then converted into an interrupt number represented by binary code, ranging from 0 to 255, where 0 is an invalid interrupt number.

[0116] For example, after conversion to binary code, the preparation for sending data is completed in the waiting state of the first finite state machine. The target number of the corresponding interrupt is parsed from the interrupt domain and its configuration space, and the source number and data information are packaged. After the completion, the request control signal (such as the above-mentioned tvalid signal) is set, and the sending state is entered. Finally, after waiting for the interrupt target module to reply to the handshake signal (such as the above-mentioned tready signal) in the sending state, the transmission of a message interrupt is completed. The suspend bit of the corresponding interrupt source is also cleared after the message interrupt is sent from the interrupt controller.

[0117] For example, the current RISC-V architecture still uses an interrupt system based on line interrupts, and no interrupt system based on message interrupts has been implemented on the SoC chip. At least one embodiment of the present disclosure provides an interrupt controller for processing external line interrupts when an interrupt system based on message interrupts is adopted in the future under the RISC-V architecture, and designs a specific internal micro-architecture, control method, and implementation of each functional module.

[0118] For example, at least one embodiment of the present disclosure realizes the conversion of line interrupts into message interrupts containing the information required by the specification according to the AIA specification, has a complete micro-architecture design and functional implementation, and adopts many easily expandable implementation methods, providing an implementation basis for the future RISV-V architecture to adopt a message interrupt system to handle line interrupts.

[0119] For example, at least one embodiment of the present disclosure also defines a message interruption data transmission protocol, including a specific data frame format and privilege level definition, and each data bit width also has a certain expansion space. It is not only suitable for converting line interrupts into message interrupts, but can also be used as a message interruption transmission protocol for future SoC systems that adopt a message interruption architecture.

[0120] For example, the message interrupt transmission protocol defined in at least one embodiment of the present disclosure is efficient and scalable, defines detailed data content, and is also a feasible implementation method for message interrupt system platform transmission under the RISC-V architecture in the future.

[0121] For example, the implementation of the configuration module adds an input signal (space capacity signal addr_range_s) to indicate the size of the configuration space in the interrupt domain, to implement the method of configuring the interrupt domain selection. Based on the consistent size of the register configuration space of each interrupt domain, the interrupt domain sequence number and the fixed configuration space size are used to implement the selection of the configuration access interrupt domain without calculating the starting address of each interrupt domain configuration space. This implementation method greatly facilitates the expansion and increase of interrupt domains. When the overall register configuration space base address of the interrupt controller remains unchanged and there is enough space, it is only necessary to modify the interrupt domain quantity parameter and the register configuration space base address without calculating the addresses of each interrupt domain and modifying the design content to complete the expansion and modification; even if the size of the configuration space of a single interrupt domain changes, it can be completed by modifying the configuration space size signal without recalculating and modifying the internal design of the module.

[0122] At least one embodiment of the present disclosure further provides a chip, comprising the interrupt controller as described in any of the above embodiments.

[0123] For example, the chip may be a SoC chip or other chips. In addition to the interrupt controller, the chip may also include components such as an on-chip bus and a processor core.

[0124] At least one embodiment of the present disclosure further provides an electronic device, comprising the chip as described in any of the above embodiments.

[0125] For example, the electronic device may be a computer, a server, etc.

[0126] For example, the specific functions and technical effects of the chip and the electronic device can be referred to the above description of the interrupt controller, which will not be repeated here.

[0127] The drawings show an interrupt controller having various modules / sub-modules, but it should be understood that the interrupt controller is not required to have all the devices shown, and the interrupt controller may alternatively have more or fewer devices.

[0128] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0129] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0130] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

[0131] There are a few points to note about this disclosure:

[0132] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0133] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0134] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An interrupt controller, comprising: at least one interrupt domain module, wherein each of the interrupt domain modules is configured to receive a line interrupt request, obtain a target line interrupt request matching the current interrupt domain module from the received line interrupt request, and generate a corresponding message interrupt request according to the target line interrupt request; The output module is configured to receive the message interruption request sent by the at least one interruption domain module and control the output of the message interruption request.

2. The interrupt controller according to claim 1, wherein: The at least one interrupt domain module includes a plurality of interrupt domain modules, and the plurality of interrupt domain modules correspond to a plurality of privilege levels respectively; Matching with the current interrupt domain module includes: matching with the privilege level corresponding to the current interrupt domain module.

3. The interrupt controller according to claim 2, wherein: The plurality of interrupt domain modules respectively correspond to a plurality of privilege levels of a computer architecture to which the interrupt controller is applied.

4. The interrupt controller according to claim 3, wherein: The plurality of interrupt domain modules include at least part of the following: A first interrupt domain module corresponding to the machine-level privilege level; a second interrupt domain module corresponding to the supervisor privilege level; A third interrupt domain module corresponding to the user-level privilege level; A fourth interrupt domain module corresponding to the virtual supervisor privilege level.

5. The interrupt controller according to claim 1, further comprising: The acquisition module is configured to receive a line interrupt request, perform clock domain synchronization processing on the received line interrupt request, and send the processed line interrupt request to the at least one interrupt domain module.

6. The interrupt controller according to claim 5, wherein: The at least one interrupt domain module includes a plurality of interrupt domain modules, the plurality of interrupt domain modules are cascaded, Each of the interrupt domain modules is further configured to: receive a line interrupt request sent by the acquisition module or an upper-level interrupt domain module, obtain a target line interrupt request matching the current interrupt domain module from the received line interrupt request, generate a corresponding message interrupt request according to the target line interrupt request, and send a line interrupt request that does not match the current interrupt domain module to a lower-level interrupt domain module.

7. The interrupt controller according to claim 6, wherein: Each of the interrupt domain modules comprises: a register control submodule configured to receive configuration information, configure the control and status registers of the interrupt domain module based on the configuration information, control other submodules in the interrupt domain module based on the configured control and status registers, and record the execution status of the interrupt domain module; An input management submodule configured to obtain a target line interrupt request matching a current interrupt domain module from the received multiple line interrupt requests; A distribution submodule, configured to send the line interruption request that does not match the current interruption domain module among the received multiple line interruption requests to the next-level interruption domain module; The processing submodule is configured to process the target line interruption requests sent by the input management submodule in sequence, generate corresponding message interruption requests, and send the message interruption requests to the output module.

8. The interrupt controller according to claim 7, wherein: The processing submodule comprises: a first arbitration submodule, configured to perform arbitration selection processing on the target line interruption request sent by the input management submodule, select the target line interruption request to be processed, and represent the index information of the target line interruption request to be processed in a one-hot code encoding form; A code conversion submodule, configured to convert the index information in the one-hot code format into index information in the binary code format; The message interruption control submodule is configured to generate a corresponding message interruption request according to the to-be-processed target line interruption request corresponding to the index information in binary encoding form, and send the message interruption request to the output module.

9. The interrupt controller according to claim 7, wherein: The input management submodule is further configured as follows: Filtering out a line interrupt request matching a current interrupt domain module from the received multiple line interrupt requests; For the screened line interruption requests, uniformly adjusting the line interruption requests to be high level valid or uniformly adjusting them to be low level valid; When a valid edge of the line interrupt request is identified, changing the corresponding suspend signal from an initial value to a first value; Obtaining a valid line interrupt request as the target line interrupt request according to the suspend signal, the global enable signal and the interrupt enable signal corresponding to the line interrupt request; After the message interrupt request corresponding to the target line interrupt request is output by the output module, the corresponding suspend signal is changed from the first value back to the initial value.

10. The interrupt controller according to claim 8, wherein: Each of the interrupt domain modules includes a first finite state machine, wherein the first finite state machine has an initial state, a waiting state, and a sending state; In the initial state, in response to the first arbitration submodule selecting a target line interrupt request to be processed, the first finite state machine jumps to the waiting state; In the waiting state, in response to the message interruption control submodule generating the message interruption request, the first finite state machine jumps to the sending state; In the sending state, in response to the message interrupt request being sent by the output module to the interrupt target module and receiving a confirmation signal returned by the interrupt target module, the first finite state machine jumps back to the initial state.

11. The interrupt controller according to claim 7, wherein: The interrupt controller further includes a configuration module, which is configured to enable an interrupt domain module corresponding to the address information among the multiple interrupt domain modules according to the address information, and send the configuration information to the enabled interrupt domain module.

12. The interrupt controller according to claim 11, wherein: The control and status registers of each interrupt domain module have the same space capacity, The configuration module determines the address information according to the base address, the space capacity of the control and status register and the index number of the interrupt domain module.

13. The interrupt controller according to any one of claims 1 to 12, wherein: The output module includes a second finite state machine and a second arbitration submodule, wherein the second finite state machine has a first state and a second state. In the first state, in response to receiving a message interrupt request sent by at least one of the interrupt domain modules, the second finite state machine jumps to the second state; When the second finite state machine jumps from the first state to the second state, the second arbiter selects a message interrupt request to be output from the received message interrupt requests, outputs the message interrupt request to be output to the interrupt target module, and waits for a confirmation signal returned by the interrupt target module; In response to receiving a confirmation signal returned by the interrupt target module, the second finite state machine jumps back to the first state.

14. The interrupt controller according to claim 13, wherein: The second arbitration submodule is configured to select a message interrupt request to be output according to the privilege level corresponding to the received message interrupt request and the clock cycle of the received message interrupt request; The second arbitration submodule is further configured to: for multiple message interrupt requests received in the same clock cycle, give priority to message interrupt requests with higher privilege levels; for multiple message interrupt requests received in different clock cycles, give priority to message interrupt requests with earlier clock cycles.

15. The interrupt controller according to claim 10, wherein: Each of the interrupt domain modules is further configured to generate and process an immediate interrupt signal and generate a corresponding instant message interrupt request based on the immediate interrupt signal, wherein the immediate interrupt signal is generated by writing a first register in the register control submodule.

16. The interrupt controller according to claim 15, wherein: The register control submodule is also configured as: If the immediate interrupt signal is generated during the period when the first finite state machine is in the initial state or before the initial state, the line interrupt request to be input into the control first arbitration submodule is invalidated, and the message interrupt control submodule is controlled to generate and output a corresponding immediate message interrupt request; If the immediate interrupt signal is generated while the first finite state machine is in the waiting state, the line interrupt request to be input into the first arbitration submodule is invalidated, the encoding conversion submodule and the message interrupt control submodule are controlled to process the target line interrupt request to be processed that has been currently selected by the first arbitration submodule, and after the corresponding message interrupt request is obtained and sent to the output module, the message interrupt control submodule is controlled to generate and output the corresponding immediate message interrupt request.

17. The interrupt controller according to claim 9, wherein: The control and status registers are reconfigured in the following manner: Turning off the global enable signal and the interrupt enable signal; Generate an instant message interrupt by writing a first register in the register control submodule; After the interrupt target module receives the instant message interrupt, the control and status registers of the interrupt domain are reconfigured.

18. The interrupt controller according to any one of claims 1 to 12, wherein: The data protocol corresponding to the message interrupt request includes at least part of the following: A control signal regarding a message interrupt request sent to an interrupt target module; The interrupt target module returns a confirmation signal after receiving the message interrupt request; Data information, wherein the data information includes an identification number, an interrupt type, privilege level information, and a target virtual machine number of an external line interrupt request corresponding to the message interrupt request; Interrupt the routing information of the target module; Interrupt request initiator information.

19. A chip comprising the interrupt controller according to any one of claims 1 to 18.

20. An electronic device comprising the chip according to claim 19.

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