A circuit and a chip for enabling the CXL protocol to support a low-rate serial link

Abstract

The present invention discloses a circuit and a chip for enabling the CXL protocol to support a low-rate serial link. The circuit of the present invention includes a link management state machine including a "Transmit SDS" state, a 4-byte clock deviation compensation symbol SKP_4B generation circuit and parsing circuit, an encoder and decoder supporting a data stream start symbol SDS, a 128b / 130b encoder and decoder, a data stream start detection circuit, a 40:1 serial-to-parallel conversion circuit, a 32:1 serial-to-parallel conversion circuit, a multiplexer, a 1:40 parallel-to-serial conversion circuit, a 1:32 parallel-to-serial conversion circuit, and a demultiplexer. The output end of the multiplexer is connected to the input end of the demultiplexer through a serial link. The purpose of the present invention is to enable the CXL protocol to be extended to support PCIe Gen1 and Gen2 rates, so that FPGA chips can use the CXL protocol and ASIC chips can use the CXL protocol at low rates.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed interconnection interfaces between chiplets, and particularly relates to a circuit and a chip that enable the CXL protocol to support a low-rate serial link. Background Art

[0002] The CXL protocol standard is a protocol standard proposed by Intel for the interconnection of a new generation of chips, supporting two types of transactions: CXL.io and CXL.mc. Its main feature is based on traditional PCIe Gen3 and higher-rate (Gen4, Gen5, etc.) PCIe Serdes. On the basis of supporting traditional master-to-slave IO access between chips (implemented through CXL.io transactions), it extends to support master-to-slave storage and cache coherence access (implemented through CXL.mc transactions). The goal of the CXL protocol is to not only meet the access from the CPU to external IO peripherals, but also meet the efficient interconnection in various rich scenarios such as CPU to CPU, CPU to GPU, and CPU to memory. Intel intends to unify various communication requirements within and between cabinets in application scenarios such as data centers through the CXL protocol standard, establish standards, and build an ecosystem. Since the CXL protocol standard is compatible with PCIe Gen3 and higher-rate physical links, it has received support from a large number of chip and system development manufacturers and has broad application prospects.

[0003] The CXL protocol specifies that the physical link does not support low-rate (PCIe Gen1 and Gen2) serial links, which limits some application scenarios of the CXL protocol. One scenario is to use the CXL protocol in FPGA chips. As a prototype verification chip or a dedicated acceleration chip for high-performance chips, FPGAs need to integrate interconnect interfaces that support the CXL protocol. When the FPGA chip supports the CXL protocol, the physical link can use the standard PCIe PHY, but the digital circuits such as the MAC layer, data link layer, and protocol layer specified in the CXL protocol specification need to be implemented through the lookup table (LUT) in the FPGA. Due to the large scale of this part of the digital circuit, it is very difficult to achieve a higher main frequency. Usually, this part of the digital circuit can only achieve a frequency of more than 100 megahertz, which does not reach 200MHz. Taking the PCIe PHY supporting 16 lanes as an example, if the transmission rate of 8Gbps per lane specified by PCIe Gen3 is to be achieved, when the PIPE interface between the MAC layer and PHY in the CXL controller has a data width of 512 bits, the operating frequency of the MAC layer and the digital circuits above it needs to reach 16*8G / 512=250MHz to achieve bandwidth balance, and the operating frequency of 250MHz is difficult to achieve in FPGA. Therefore, in FPGA, when the PIPE interface between the MAC layer and PHY has a data width of 512 bits, the PCIe PHY must operate at the Gen1 or Gen2 rate. Taking the Gen2 rate as an example, at this time, the operating frequency of the MAC layer and the layers above the CXL controller only needs to reach 16*5G / 512=156.25Mhz; at the Gen1 rate, the operating frequency only needs to reach 16*2.5G / 512=78.125MHz. The above frequencies are feasible for the implementation of the CXL controller in FPGA. Another scenario is when the ASIC chip cannot reach Gen3 or higher speeds due to serial link reliability and other issues, and it is decelerated to work at Gen1 or Gen2 speeds. According to Intel's current CXL protocol specification, once the physical link works at a speed lower than Gen3, CXL.mc transactions are not supported, and the functions of accessing memory and other chips' caches through the CXL protocol interface will be invalid. In order to enable the ASIC chip to still use the full functionality of the CXL protocol when the physical link rate is Gen1 or Gen2, the CXL protocol specification must be optimized to support PCIe Gen1 and Gen2 rates.

[0004] In summary, due to the lack of support for low-rate serial links in the current CXL protocol specification, the application scenarios of FPGA chips and ASIC chips are restricted. Therefore, making the CXL protocol physical link support low-rate serial links has become a key technical issue that needs to be solved urgently. Summary of the invention

[0005] Technical problems to be solved by the present invention: In view of the above problems of the prior art, a circuit and a chip that enable the CXL protocol to support a low-speed serial link are provided. The present invention aims to enable the CXL protocol specification to be extended to support PCIe Gen1 and Gen2 rates, so that FPGA chips can use the CXL protocol and ASIC chips can still operate normally when the physical link is reduced to Gen1 and Gen2 rates at the CXL protocol interface.

[0006] To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0007] A circuit that enables the CXL protocol to support a low-speed serial link includes a sending end and a receiving end. The sending end includes a link management state machine including a "send SDS" state, a 4-byte clock deviation compensation symbol SKP_4B generation circuit, an encoder supporting a data stream start symbol SDS, a 128b / 130b encoder, a 40:1 serial-to-parallel conversion circuit, a 32:1 serial-to-parallel conversion circuit, and a multiplexer. The encoder supporting the data stream start symbol SDS is used to perform 8b / 10b encoding on the data of the PCIe physical link at Gen1 and Gen2 rates and insert the 4-byte clock deviation compensation symbol SKP_4B generated by the 4-byte clock deviation compensation symbol SKP_4B generation circuit into the message. The receiving end includes a data stream start detection circuit, a 4-byte clock deviation compensation symbol SKP_4B parsing circuit, a decoder supporting the data stream start symbol SDS, a 128b / 130b decoder, a 1:40 parallel-to-serial conversion circuit, a 1:32 parallel-to-serial conversion circuit, and a demultiplexer. The decoder supporting the data stream start symbol SDS is used to perform 10b / 8b decoding on the data of the PCIe physical link at Gen1 and Gen2 rates, and after decoding, send it to the 4-byte clock deviation compensation symbol SKP_4B parsing circuit to parse out the 4-byte clock deviation compensation symbol SKP_4B in the message. The input ends of the multiplexer are respectively connected to the output end of the encoder supporting the data stream start symbol SDS through the 40:1 serial-to-parallel conversion circuit and the output end of the 128b / 130b encoder through the 32:1 serial-to-parallel conversion circuit. The output end of the multiplexer is connected to the input end of the demultiplexer through a serial communication link. The output ends of the demultiplexer are respectively connected to the input end of the 128b / 130b decoder through the 1:32 parallel-to-serial conversion circuit and the input end of the decoder supporting the data stream start symbol SDS through the 1:40 parallel-to-serial conversion circuit.

[0008] Optionally, the encoder supporting the data stream start symbol SDS performs 8b / 10b encoding on the data of the PCIe physical link at Gen1 and Gen2 rates using the 8b / 10b encoding rule with the added SDS control character, and the SDS control character is the code group identifier K28.4 reserved in the 8b / 10b encoding table of the CXL protocol.

[0009] Optionally, the encoder supporting the data stream start symbol SDS includes:

[0010] A first judgment module, configured to judge whether the high 3 bits data_in[7:5] of the input 8-bit data to be encoded data_in is 3'd4 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal;

[0011] A first NOT gate, configured to generate the bitwise inversion value of the fixed encoding data_abcdei_sds, where the encoding value of the fixed encoding data_abcdei_sds is fixed to 6'b001101;

[0012] A first selector, configured to select and output between the fixed encoding data_abcdei_sds and the bitwise inversion value of the fixed encoding data_abcdei_sds generated by the first NOT gate according to the 1-bit polarity signal disp_in; where the 1-bit polarity signal disp_in being 1 indicates positive polarity RD+ in this clock cycle, and being 0 indicates negative polarity RD- in this clock cycle;

[0013] A second selector, configured to select and generate a 6-bit encoding value data_abcdei between the output value of the first selector and the 0 encoding value according to the selection signal generated by the first judgment module;

[0014] A second judgment module, configured to judge whether the low 5 bits data_in[4:0] of the input 8-bit data to be encoded data_in is 5'd28 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal;

[0015] A second NOT gate, configured to generate the bitwise inversion value of the fixed encoding data_fghj_sds, where the encoding value of the fixed encoding data_fghj_sds is fixed to 4'b1100;

[0016] A third selector, configured to select and output between the fixed encoding data_fghj_sds and the bitwise inversion value of the fixed encoding data_fghj_sds generated by the second NOT gate according to the 1-bit polarity signal disp_in;

[0017] A fourth selector, configured to generate a 4-bit encoded value data_fghj by selecting between the output value of a third selector and a 0 encoded value according to a selection signal generated by a second determination module, and form an encoded result data_out = {data_fghj, data_abcdei} together with a 6-bit encoded value data_abcdei for output;

[0018] A third determination module, configured to determine whether the encoded result data_out is equal to 10’h0, and use the determination result as a generated error signal sds_err. If the error signal sds_err is 1, it indicates that the SDS control character encoding is incorrect.

[0019] Optionally, the decoder supporting the data stream start symbol SDS performs 10b / 8b decoding on the data of the PCIe physical link at Gen1 and Gen2 rates using a 10b / 8b decoding rule with an added SDS control character. The SDS control character is a code group identifier K28.4 reserved in the 10b / 8b decoding table of the CXL protocol.

[0020] Optionally, the decoder supporting the data stream start symbol SDS includes:

[0021] A fourth determination module, configured to determine whether the high 4 bits data_in[9:6] of the input 10-bit data to be decoded data_in are 4’b1100 or 4’b0011, and use the determination result as a generated selection signal;

[0022] A fifth selector, configured to select a fixed encoding data_EDCBA _sds or 5’d0 as a 5-bit decoded value data_EDCBA according to the selection signal generated by the fourth determination module;

[0023] A fifth determination module, configured to determine whether the 1st, 3rd, and 4th bits of the input 10-bit data to be decoded data_in are all 1 at the same time, and use the determination result as an output signal;

[0024] A sixth determination module, configured to determine whether any one of the 1st, 3rd, and 4th bits of the input 10-bit data to be decoded data_in is 1, and use the determination result as an output signal;

[0025] An OR gate, configured to perform an OR operation on the signals output by the fifth determination module and the sixth determination module;

[0026] A sixth selector, configured to select a fixed code data_HGF_sds or 3'd0 as a 3-bit decoded value data_HGF according to the OR operation result of an OR gate, and the 3-bit decoded value data_HGF and the 5-bit decoded value data_EDCBA together form a decoded result data_out = {data_HGF, data_EDCBA}, where the code value of the fixed code data_HGF_sds is fixed to 3'd4;

[0027] A first AND gate, configured to perform an AND operation on the selection signal generated by the fourth determination module and the OR operation result of the OR gate to obtain a 1-bit K code k_out as an output, indicating whether the decoded result data_out is an SDS control character;

[0028] A seventh determination module, configured to determine whether the decoded result data_out is equal to 8'h0, and use the determination result as a generated error signal sds_err. If the error signal sds_err is 1, it indicates that the decoding of the SDS control character is incorrect.

[0029] Optionally, the encoder supporting the data stream start symbol SDS performs link management using a link management state machine with an added "send SDS" state. The link management state machine with the added "send SDS" state includes the following states: "reset / idle" state, which is the initial state of the link and enters this state after power-on; "link training" state, which is the state for initializing and training the link; "L0 / active" state, which is the normal working state. In this state, the link normally sends and receives messages and enters this state after link training is completed; "L0s" state, which is the first-level low-power state; "retraining" state, which is the state for re-initializing and training the link. After the link exits the "L1" state, it needs to go through this state for retraining and can enter the "L0 / active" state only after training is completed; "L1" state, which is the second-level low-power state; "L2" state, which is the third-level low-power state; "send SDS" state, which is the state for sending the SDS control character; exiting the "reset / idle" state enters the "link training" state; exiting the "link training" state enters the "send SDS" state; under the control of the "send SDS" state, the encoding circuit of the data stream start symbol SDS at the sending end starts to send the SDS control character. After the receiving end recognizes the SDS control character and detects the start of the data stream, the link management state machine jumps from the "send SDS" state to the "L0 / active" state; the "L0 / active" state and the "L0s" state can be switched with each other, and the "L0 / active" state can be unidirectionally switched to the "L1" state and the "L2" state; exiting the "L2" state enters the "reset / idle" state; exiting the "L1" state enters the "retraining" state; exiting the "retraining" state re-enters the "send SDS" state.

[0030] Optionally, when the PCIe physical link is at Gen1 and Gen2 rates, the clock skew compensator SKP_4B in the packets received by each link is {SKP_1B, SKP_1B, SKP_1B, COMMA_1B}, and when the PCIe physical link is at Gen3 and above rates, the clock skew compensator SKP_4B in the packets received by each link is {SKP_1B, SKP_1B, SKP_1B, SKP_1B}, where SKP_1B is a single-byte clock skew compensator and COMMA_1B is a single-byte synchronizer; the 4-byte clock skew compensator SKP_4B parsing circuit for parsing two types of 4-byte clock skew compensators SKP_4B in the packets includes:

[0031] An eighth determination module, configured to determine whether the logical AND operation result of the 4th bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the clock skew compensator SKP_1B;

[0032] A ninth determination module, configured to determine whether the logical AND operation result of the 3rd bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the clock skew compensator SKP_1B;

[0033] A tenth determination module, configured to determine whether the logical AND operation result of the 2nd bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the clock skew compensator SKP_1B;

[0034] An eleventh determination module, configured to determine whether the logical AND operation result of the 1st bit rx_datak[0] in the received K code rx_datak and the 1st to 8th bits rx_data[7:0] in the received data rx_data is equal to the clock skew compensator SKP_1B;

[0035] A twelfth determination module, configured to determine whether the logical AND operation result of the 1st bit rx_datak[0] in the received K code rx_datak and the 1st to 8th bits rx_data[7:0] in the received data rx_data is equal to the synchronizer COMMA_1B;

[0036] A seventh selector, configured to select the determination result of the twelfth determination module when the PCIe physical link is at Gen1 and Gen2 rates, and otherwise select the determination result of the eleventh determination module;

[0037] A second AND gate, configured to perform a logical AND operation on the output results of an eighth determination module, a ninth determination module, a tenth determination module, and an eleventh multiplexer to obtain a 4-byte clock deviation compensation symbol parsing result SKP_OUT;

[0038] A first counter, configured to output 1 for each received SKP_4B sequence {SKP_1B, SKP_1B, SKP_1B, SKP_1B} at Gen3 and higher rates;

[0039] A second counter, configured to output 3 for each received SKP sequence {SKP_1B, SKP_1B, SKP_1B, COMMA_1B} at Gen1 and Gen2 rates;

[0040] An eighth selector, configured to select and output the output result of the second counter at Gen1 and Gen2 rates, and otherwise select and output the output result of the first counter;

[0041] An SKP counter, configured to accumulate the output result of the eighth selector to obtain a clock deviation compensation symbol count value SKP_COUNT.

[0042] Optionally, the data stream start detection circuit is configured to generate a data stream start flag for both Gen1 and Gen2 rates and Gen3 and higher rates, and use the Gen1 / Gen2 signal representing Gen1 and Gen2 rates as a decoding enable signal to implement alternative enabling of a decoder supporting a data stream start symbol SDS and a 128b / 130b decoder. The data stream start detection circuit includes a Gen3 and higher rates SDS detection circuit, a Gen1 / Gen2 rates SDS detection circuit, and a ninth selector. The Gen3 and higher rates SDS detection circuit is configured to perform data stream start flag detection on the decoding result of the 128b / 130b decoder to obtain an output result SDS_OUT_GEN3. The Gen1 / Gen2 rates SDS detection circuit is configured to perform data stream start flag detection on the decoding result of the decoder supporting the data stream start symbol SDS to obtain an output result SDS_OUT_GEN1. The ninth selector is configured to select one path from the output result SDS_OUT_GEN3 and the output result SDS_OUT_GEN1 based on the control of the Gen1 / Gen2 signal as the finally generated data stream start flag.

[0043] Optionally, the Gen1 / Gen2 rates SDS detection circuit includes:

[0044] The thirteenth judgment module is used to judge whether the result of the AND operation between the 4th bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the SDS control character SDS_1B;

[0045] The fourteenth judgment module is used to judge whether the result of the AND operation between the 3rd bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the SDS control character SDS_1B;

[0046] The fifteenth judgment module is used to judge whether the result of the AND operation between the 2nd bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the SDS control character SDS_1B;

[0047] The sixteenth judgment module is used to judge whether the result of the AND operation between the 1st bit rx_datak[0] in the received K code rx_datak and the 1st to 8th bits rx_data[7:0] in the received data rx_data is equal to the SDS control character SDS_1B;

[0048] The third AND gate is used to perform a logical AND operation on the output results of the thirteenth judgment module, the fourteenth judgment module, the fifteenth judgment module, and the sixteenth judgment module to obtain the result SDS_OUT_GEN1 of whether the received data is an SDS control character.

[0049] In addition, the present invention also provides a chip, including a plurality of die interconnected through a high-speed interconnect interface, and the high-speed interconnect interface includes a circuit that enables the CXL protocol to support a low-rate serial link.

[0050] Compared with the prior art, the present invention can mainly achieve the following beneficial effects:

[0051] 1. The present invention solves the problem that the CXL protocol specification does not support PCIe Gen1 and Gen2 rates. Currently, neither the CXL protocol specification nor the commercial CXL protocol controller can support the CXL protocol interface circuit to access memory and the Cache in other chips when the physical link operates at Gen1 and Gen2 rates. The present invention can enable the CXL controller to still support the normal access of CXL.mc transactions when the physical link operates at PCIe Gen1 and Gen2 rates, ensuring the integrity and correctness of the CXL protocol function.

[0052] 2. By supporting PCIe Gen1 and Gen2 rates, the present invention achieves the independence of the CXL controller from the physical layer serial link rate, further realizes the "decoupling" of the CXL controller from the physical layer link, supports the adaptation of the CXL controller to a richer variety of physical link types, greatly improves the practicality of the CXL protocol in chip and die interconnection, and is of great significance for expanding the CXL ecosystem. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a schematic diagram of the circuit structure in an embodiment of the present invention.

[0054] Figure 2 It is a circuit schematic diagram of the 8b / 10b encoder for SDS control characters in an embodiment of the present invention.

[0055] Figure 3 It is a circuit schematic diagram of the 8b / 10b decoder for SDS control characters in an embodiment of the present invention.

[0056] Figure 4 It is an improved schematic diagram of the link management state machine in an embodiment of the present invention, where (a) is the original link management state machine, and (b) is the link management state machine with the "SDS state" added in the embodiment of the present invention.

[0057] Figure 5 It is a circuit schematic diagram of the SKP_4B parsing circuit for 4-byte clock deviation compensation characters in an embodiment of the present invention.

[0058] Figure 6 It is a circuit schematic diagram of the data stream start detection circuit in an embodiment of the present invention.

[0059] Figure 7 It is a circuit schematic diagram of the Gen1 / Gen2 SDS detection circuit in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0060] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0061] As Figure 1As shown, the circuit in this embodiment that enables the CXL protocol to support a low-speed serial link includes a transmitter and a receiver. The transmitter includes a link management state machine containing the "Transmit SDS" state, a 4-byte clock skew compensation symbol SKP_4B generation circuit, an encoder that supports the data stream start symbol SDS, a 128b / 130b encoder, a 40:1 serial-to-parallel conversion circuit, a 32:1 serial-to-parallel conversion circuit, and a multiplexer. The encoder that supports the data stream start symbol SDS is used to perform 8b / 10b encoding on the data of the PCIe physical link at Gen1 and Gen2 rates and insert the 4-byte clock skew compensation symbol SKP_4B generated by the 4-byte clock skew compensation symbol SKP_4B generation circuit at a fixed time into the message. The receiver includes a data stream start detection circuit, a 4-byte clock skew compensation symbol SKP_4B parsing circuit, a decoder that supports the data stream start symbol SDS, a 128b / 130b decoder, a 1:40 parallel-to-serial conversion circuit, a 1:32 parallel-to-serial conversion circuit, and a demultiplexer. The decoder that supports the data stream start symbol SDS is used to perform 10b / 8b decoding on the data of the PCIe physical link at Gen1 and Gen2 rates, and after decoding, send it to the 4-byte clock skew compensation symbol SKP_4B parsing circuit to parse out the 4-byte clock skew compensation symbol SKP_4B in the message. The input terminals of the multiplexer are respectively connected to the output terminal of the encoder that supports the data stream start symbol SDS through the 40:1 serial-to-parallel conversion circuit and to the output terminal of the 128b / 130b encoder through the 32:1 serial-to-parallel conversion circuit. The output terminal of the multiplexer is connected to the input terminal of the demultiplexer through a serial communication link. The output terminals of the demultiplexer are respectively connected to the input terminal of the 128b / 130b decoder through the 1:32 parallel-to-serial conversion circuit and to the input terminal of the decoder that supports the data stream start symbol SDS through the 1:40 parallel-to-serial conversion circuit. The 128b / 130b encoder, the 128b / 130b decoder, and the 4-byte clock skew compensation symbol SKP_4B generation circuit are circuits that are well-known in the art.

[0062] See Figure 1, when the link is at Gen1 / Gen2 rate, if the link management state machine is in the "transmit SDS" state, the encoder that supports the start-of-data symbol (SDS) of the sender transmits the SDS control character, and through 8b / 10b encoding, 8 bits are encoded into 10 bits, and 512-bit data (interface width is 512 bits) is encoded into 640-bit data and output to the electrical physical layer; after the receiver receives 640-bit data from the electrical physical layer, the decoder that supports the start-of-data symbol (SDS) decodes the data into 512 bits while parsing out the SDS control character, and the data stream start detection circuit determines the start of the data stream based on the SDS control character and outputs this information. When the link is at Gen3 and above rates, if the link management state machine is in the "transmit SDS" state, the 128b130b encoder of the sender transmits the SDS control character and outputs 512-bit data to the electrical physical layer; after the receiver receives 512-bit data from the electrical physical layer, the 128b / 130b decoder parses out the SDS control character, and the data stream start detection circuit determines the start of the data stream based on the SDS control character and outputs this information.

[0063] Based on the requirement of increasing bandwidth, PCIe Gen3 and above versions replace 8b / 10b encoding with 128b / 130b encoding. The CXL protocol requires the start-of-data symbol (SDS) in 128b / 130b encoding to identify the start of the data stream, so as to correctly parse the position of the first protocol ID (PID). Since the physical link of PCIe does not support 128 / 130b encoding at Gen1 and Gen2 rates, only 8b / 10b encoding is supported, and there is no SDS required by the CXL protocol in 8b / 10b encoding. Therefore, the CXL protocol cannot determine the start of the data stream at Gen1 and Gen2 rates, thus unable to parse the PID, and further causing the CXL.mc protocol not to work properly. To address the above issues, this embodiment extends the 8b / 10b encoding rule in the CXL protocol and adds an SDS control character. Table 1 shows the 8b / 10b encoding table of the CXL protocol, where two groups of encodings K28.4 and K28.6 are reserved in the control character part and do not represent any control characters; based on the 8b / 10b encoding rule of the CXL protocol, this embodiment defines the original reserved encoding K28.4 as the SDS control character, and the encoding and meaning of other control characters remain unchanged; Table 2 and Table 3 are the 8b / 10b encoding and 10b / 8b decoding comparison tables of the SDS control character respectively.

[0064] Table 1: Extend the SDS control character in the 8b / 10b encoding table of the CXL protocol

[0065]

[0066] Table 2: 8b / 10b Coding Lookup Table for SDS Control Characters

[0067]

[0068] Table 3: 10b / 8b Decoding Lookup Table for SDS Control Characters

[0069]

[0070] Among them, 8’h9C is an 8-bit hexadecimal number, and its hexadecimal value is 9C.

[0071] Therefore, the encoder that supports the data stream start symbol SDS in this embodiment uses the 8b / 10b coding rule with the added SDS control character to perform 8b / 10b coding on the data of the PCIe physical link at Gen1 and Gen2 rates. The SDS control character is the code group identifier K28.4 reserved in the 8b / 10b coding table of the CXL protocol. The decoder that supports the data stream start symbol SDS in this embodiment uses the 10b / 8b decoding rule with the added SDS control character to perform 10b / 8b decoding on the data of the PCIe physical link at Gen1 and Gen2 rates. The SDS control character is the code group identifier K28.4 reserved in the 10b / 8b decoding table of the CXL protocol.

[0072] The 8b / 10b coding circuit and decoding circuit corresponding to the 8b / 10b coding table are well-known circuits, so their detailed implementations will not be elaborated here. As Figure 2 shown, in order to perform 8b / 10b coding on the SDS control character, the encoder that supports the data stream start symbol SDS in this embodiment includes:

[0073] A first judgment module, used to judge whether the high 3 bits data_in[7:5] of the input 8-bit data to be encoded data_in is 3’d4 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal; where 3’d4 represents a 3-bit binary number, and its value is 4 (binary value is 100);

[0074] A first NOT gate, used to generate the bitwise inversion value of the fixed coding data_abcdei_sds, where the coding value of the fixed coding data_abcdei_sds is fixed at 6’b001101; where 6’b001101 represents a 6-bit binary number, and its binary value is 001101;

[0075] A first selector for selecting an output between a fixed code data_abcdei_sds and the bitwise inversion value of the fixed code data_abcdei_sds generated by a first NOT gate according to a 1-bit polarity signal disp_in; where the 1-bit polarity signal disp_in being 1 indicates a positive polarity RD+ in the current clock cycle, and being 0 indicates a negative polarity RD- in the current clock cycle;

[0076] A second selector for generating a 6-bit coded value data_abcdei by selecting between the output value of the first selector and a 0 coded value according to a selection signal generated by a first determination module;

[0077] A second determination module for determining whether the lower 5 bits data_in[4:0] of the input 8-bit data to be coded data_in and the input 1-bit K code k_in being 1 hold simultaneously, and using the determination result as the generated selection signal;

[0078] A second NOT gate for generating the bitwise inversion value of a fixed code data_fghj_sds, where the coded value of the fixed code data_fghj_sds is fixed as 4’b1100;

[0079] A third selector for selecting an output between a fixed code data_fghj_sds and the bitwise inversion value of the fixed code data_fghj_sds generated by the second NOT gate according to a 1-bit polarity signal disp_in;

[0080] A fourth selector for generating a 4-bit coded value data_fghj by selecting between the output value of the third selector and a 0 coded value according to a selection signal generated by the second determination module, and forming a coded result data_out={data_fghj, data_abcdei} for output together with the 6-bit coded value data_abcdei;

[0081] A third determination module for determining whether the coded result data_out is equal to 10’h0, and using the determination result as the generated error signal sds_err. If the error signal sds_err is 1, it indicates that the SDS control character coding is incorrect. Here, 10’h0 represents 10 hexadecimal codes and the value is 0;

[0082] See Figure 2 , the input signals of the encoder supporting the data stream start symbol SDS in this embodiment are:

[0083] 1) 8-bit data to be coded (data_in);

[0084] 2) 1-bit K code (k_in). When k_in is 1, it indicates that data_in in this clock cycle is a control character; when it is 0, it indicates that data_in in this clock cycle is data.

[0085] 3) 1-bit polarity signal (disp_in). When disp_in is 1, it indicates positive polarity (RD+) within this clock cycle; when it is 0, it indicates negative polarity (RD-) within this clock cycle.

[0086] See Figure 2 , the output signals of the encoder that supports the data stream start symbol SDS in this embodiment are:

[0087] 1) 10-bit encoded data (data_out);

[0088] 2) 1-bit error signal (sds_err). When sds_err is 1, it indicates an error in the encoding of the SDS control character; when it is 0, it indicates that the encoding of the SDS control character is correct.

[0089] See Figure 2 , the intermediate signals other than the input and output signals of the encoder that supports the data stream start symbol (SDS) in this embodiment are:

[0090] 1) data_abcdei_sds, with a fixed value of 6'b001101;

[0091] 2) data_fghj_sds, with a fixed value of 4'b1100;

[0092] 3) data_abcdei, which is a 6-bit encoded value;

[0093] 4) data_fghj, which is a 4-bit encoded value.

[0094] According to the encoding rule of the SDS control character in Table 2, the encoder proposed in this embodiment divides data_in into the upper 3 bits (data_in[7:5]) and the lower 5 bits (data_in[4:0]) for encoding. For the SDS control character, the encoding under positive and negative polarities is an inversion relationship. Therefore, two NOT gates in the circuit are used to generate the bitwise inversion values of data_abcdei_sds and data_fghj_sds, and the disp_in signal is used to select whether to output the original value or the bitwise inversion value. If data_in[7:5] is 3’d4 and the corresponding k_in of data_in is 1, it means that the code group identifier of data_in[7:5] is Kxx.4 (where xx represents an unknown value); at the same time, if disp_in = 1 (positive polarity), data_abcdei_sds (6’b001101) is selected, otherwise the bitwise inversion value 6’b0110010 of data_abcdei_sds is selected and assigned to data_abcdei. The encoding logic of data_in[4:0] is the same. If data_in[4:0] is 5’d28 and the corresponding k_in of data_in is 1, it means that the code group identifier of data_in[4:0] is K28.x (where x represents an unknown value); combined with the code group identifier of data_in[7:5] being Kxx.4 mentioned above, the code group identifier of data_in can be obtained as K28.4, that is, the SDS control character. At the same time, if disp_in = 1, data_fghj_sds (4’b1100) is selected, otherwise the bitwise inversion value 4’b0011 of data_fghj_sds is selected and assigned to data_fghj. data_fghj and data_abcdei are combined into the output signal data_out, data_out = {data_fghj, data_abcdei}, that is, 10’b001111 0010 or 10’b 110000 1101. If data_out is 0, the error signal sds_err is 1, indicating that the encoding of the SDS control character is incorrect.

[0095] As Figure 3 shown, to perform 8b / 10b encoding on the SDS control character, the decoder for the data stream start symbol SDS supported by this embodiment includes:

[0096] A fourth determination module, configured to determine whether the upper 4 bits data_in[9:6] of the input 10-bit data to be decoded data_in is 4’b1100 or 4’b0011, and use the determination result as the generated selection signal;

[0097] A fifth selector for selecting a fixed code data_EDCBA _sds or 5’d0 as a 5-bit decoded value data_EDCBA according to a selection signal generated by a fourth determination module;

[0098] A fifth determination module for determining whether the 1st, 3rd, and 4th bits of an input 10-bit data to be decoded data_in are all 1, and using the determination result as an output signal;

[0099] A sixth determination module for determining whether any one of the 1st, 3rd, and 4th bits of an input 10-bit data to be decoded data_in is 1, and using the determination result as an output signal;

[0100] An OR gate for performing an OR operation on the signals output by the fifth determination module and the sixth determination module;

[0101] A sixth selector for selecting a fixed code data_HGF_sds or 3’d0 as a 3-bit decoded value data_HGF according to the OR operation result of the OR gate, and the 3-bit decoded value data_HGF and the 5-bit decoded value data_EDCBA together form a decoded result data_out={data_HGF, data_EDCBA}, where the coding value of the fixed code data_HGF_sds is fixed at 3’d4;

[0102] A first AND gate for performing an AND operation on the selection signal generated by the fourth determination module and the OR operation result of the OR gate to obtain an output 1-bit K code k_out to indicate whether the decoded result data_out is an SDS control character;

[0103] A seventh determination module for determining whether the decoded result data_out is equal to 8’h0, and using the determination result as a generated error signal sds_err. If the error signal sds_err is 1, it indicates that the decoding of the SDS control character is incorrect.

[0104] 10b / 8b decoding is the inverse process of 8b / 10b encoding. Refer to Figure 3 , the input signal of the decoder supporting the data stream start symbol (SDS) in this embodiment is: 10-bit data to be decoded (data_in).

[0105] Refer to Figure 3 , the input signal of the decoder supporting the data stream start symbol (SDS) in this embodiment is:

[0106] 1) 8-bit decoded data (data_out);

[0107] 2) 1-bit K code (k_out). When k_out is 1, it indicates that the decoded data data_out in this clock cycle is a control character; when it is 0, it indicates that data_out is data.

[0108] 3) 1-bit error signal (sds_err). When sds_err is 1, it indicates that the decoding of the SDS control character is incorrect; when it is 0, it indicates that the decoding of the SDS control character is correct.

[0109] See Figure 3 , the intermediate signals supported by this embodiment other than the input and output signals of the decoder for the data stream start symbol (SDS) are:

[0110] 1) data_EDCBA _sds, with a fixed value of 5'd28;

[0111] 2) data_HGF_sds, with a fixed value of 3'd4;

[0112] 3) data_EDCBA, which is a 5-bit decoded value;

[0113] 4) data_HGF, which is a 3-bit decoded value.

[0114] According to the decoding rule of the SDS control characters in Table 3, data_in is divided into the upper 4 bits (data_in[9:6]) and the lower 6 bits (data_in[5:0]) for decoding. Among them, for the lower 6 bits, only the rules of bits 0 / 2 / 3 are needed to decode data_HGF. If data_in[9:6] is 4’b1100 or 4’b0011, it means that the decoded code group identifier is K28.x (where x represents an unknown value). Therefore, the selector selects data_EDCBA _sds (5’d28), otherwise it selects 5’d0; the selected value is assigned to data_EDCBA. The decoding logic of data_in[5:0] is the same. If data_in[3]&data_in[2]&data_in[0] = 1 or data_in[3]| data_in[2] | data_in[0]= 0, it means that the decoded code group identifier is Kxx.4 (where xx represents an unknown value). Combining with the code group identifier K28.x decoded from data_in[9:6] above, the code group identifier of data_out can be obtained as K28.4, which is the SDS control character. Therefore, the selector selects data_HGF_sds (3’d4), otherwise it selects 3’d0; the selected value is assigned to data_HGF. data_HGF and data_EDCBA are combined into the output signal data_out, data_out ={data_HGF, data_EDCBA}, that is, 8’h9C. If the decoding result of data_in[9:6] is K28.x and the decoding result of data_in[5:0] is Kxx.4, it means that the decoding result is a control character, and k_out = 1, otherwise k_out = 0. If data_out is 0, the output signal sds_err is 1, indicating that the decoding of the SDS control character is incorrect.

[0115] See Figure 4 the improved schematic diagram of the link management state machine shown in Figure 4 In which, (a) is the traditional link management state machine. The traditional link management state machine includes the following states:

[0116] 1) The "Reset / Idle" state, which is the initial state of the link. After power-on, it enters this state;

[0117] 2) The "Link Training" state, which is the state for the link to initialize and train;

[0118] 3) The "L0 / Active" state, which is the normal working state. The link normally sends and receives messages in this state. After the link training is completed, it enters this state;

[0119] 4) The "L0s" state, which is the first-level low-power state;

[0120] 5) "Retraining" state, which is the state for re - initializing and training the link. After the link exits the "L1" state, it needs to go through this state for retraining and can enter the "L0 / Active" state only after the training is completed.

[0121] 6) "L1" state, which is the secondary low - power state.

[0122] 7) "L2" state, which is the tertiary low - power state.

[0123] As Figure 4 shown in (b) of

[0124] Refer to Figure 4 In the link management state machine that supports the encoder of the data stream start symbol SDS by adding the "Send SDS" state as shown in (b) of , the link management state machine with the added "Send SDS" state includes the following states: "Reset / Idle" state, which is the initial state of the link and enters this state after power - on; "Link Training" state, which is the state for initializing and training the link; "L0 / Active" state, which is the normal working state. In this state, the link normally sends and receives packets and enters this state after the link training is completed; "L0s" state, which is the primary low - power state; "Retraining" state, which is the state for re - initializing and training the link. After the link exits the "L1" state, it needs to go through this state for retraining and can enter the "L0 / Active" state only after the training is completed; "L1" state, which is the secondary low - power state; "L2" state, which is the tertiary low - power state; "Send SDS" state, which is the state for sending the SDS control character. Exiting the "Reset / Idle" state enters the "Link Training" state; exiting the "Link Training" state enters the "Send SDS" state. Under the control of the "Send SDS" state, the encoding circuit of the data stream start symbol SDS at the sending end starts to send the SDS control character. After the receiving end recognizes the SDS control character and detects the start of the data stream, the link management state machine jumps from the "Send SDS" state to the "L0 / Active" state. The "L0 / Active" state and the "L0s" state can be switched mutually, and the "L0s" state can be switched unidirectionally to the "L1" state and the "L2" state. Exiting the "L2" state enters the "Reset / Idle" state; exiting the "L1" state enters the "Retraining" state; exiting the "Retraining" state re - enters the "Send SDS" state.

[0124] Refer to Figure 4In (b) of this embodiment, based on the traditional link management state machine, a "transmit SDS" state is added, and the state transition directions and conditions of other states are modified. First, when the link exits the "link training" state, it does not directly enter the "L0 / active" state, but enters the "transmit SDS" state. Under the control of the "transmit SDS" state, the encoder at the transmitting end that supports the data stream start delimiter SDS starts to transmit the SDS control character. After the receiving end recognizes the SDS control character and detects the start of the data stream, the state machine jumps from the "transmit SDS" state to the "L0 / active" state. Second, when the traditional link management state machine exits the "L1" state, it first enters the "retraining" state; after the retraining is completed, it directly enters the "L0 / active" state. After the retraining of the state machine proposed in this embodiment is completed, it needs to first enter the "transmit SDS" state ( Figure 4 the bold state transition arrow in the right figure), and after repeating and completing the above process of transmitting the SDS control character, it can jump from the "transmit SDS" state to the "L0 / active" state. Since the "L1" state is a low-power state and no packets are transmitted or received on the link in this state, after exiting the "L1" state, it is necessary to re-locate the start of the data stream (i.e., the packet). However, the "retraining" state only trains parameters such as the lane number and rate of the link and does not locate the start of the data stream. Therefore, before entering the "L0 / active" state, it is necessary to first go through the "transmit SDS" state. Finally, during the process of the state machine proposed in this embodiment exiting the "L2" state and entering the "L0 / active" state again, in addition to going through the "reset / idle" state and the "link training" state, it also needs to go through the "transmit SDS" state. After repeating and completing the above process of transmitting the SDS control character, it jumps from the "transmit SDS" state to the "L0 / active" state.

[0125] Since the CXL protocol stipulates that the micropacket from the data link layer is 512 bits wide, and each link in the physical layer under x16 uses a 32:1 parallel-to-serial conversion circuit, the control character must use a 4-byte (32-bit) mode, that is, the clock deviation compensation symbol is in a 4-byte format (SKP_4B). According to the PCIe protocol, when the PCIe physical link works in Gen1 and Gen2 modes, the clock deviation compensation symbol is specified as a single-byte format (SKP_1B), and the clock deviation compensation symbol is followed by the synchronization symbol (COMMA), where the synchronization symbol is also in a single-byte format (COMMA_1B). Therefore, in this embodiment, when the PCIe physical link is at the rate of Gen1 and Gen2, the clock deviation compensation symbol SKP_4B in the message received by each link is {SKP_1B, SKP_1B, SKP_1B, COMMA_1B}, and when the PCIe physical link is at the rate of Gen3 and above, the clock deviation compensation symbol SKP_4B in the message received by each link is {SKP_1B, SKP_1B, SKP_1B, SKP_1B}, where SKP_1B is a single-byte clock deviation compensation symbol, and COMMA_1B is a single-byte synchronization symbol; Figure 5 As shown, the 4-byte clock deviation compensation symbol SKP_4B parsing circuit for parsing two types of 4-byte clock deviation compensation symbols SKP_4B in the message in this embodiment includes:

[0126] An eighth judgment module is used to judge whether the result of an AND operation of the fourth bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B;

[0127] A ninth judgment module, used to judge whether the result of an AND operation of the third bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B;

[0128] A tenth judgment module is used to judge whether the result of the AND operation of the second bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B;

[0129] An eleventh judgment module is used to judge whether the result of an AND operation of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B;

[0130] The twelfth judgment module is used to judge whether the result of the AND operation between the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the synchronization symbol COMMA_1B;

[0131] The seventh selector is used to select the judgment result of the twelfth judgment module when the PCIe physical link is at Gen1 and Gen2 rates, otherwise select the judgment result of the eleventh judgment module;

[0132] The second AND gate is used to perform a logical AND operation on the output results of the eighth judgment module, the ninth judgment module, the tenth judgment module, and the eleventh multiplexer to obtain the 4-byte clock deviation compensation symbol parsing result SKP_OUT;

[0133] The first counter is used to output 1 for each received SKP_4B sequence {SKP_1B, SKP_1B, SKP_1B, SKP_1B} at Gen3 and higher rates;

[0134] The second counter is used to output 3 for each received SKP sequence {SKP_1B, SKP_1B, SKP_1B, COMMA_1B} at Gen1 and Gen2 rates;

[0135] The eighth selector is used to select and output the output result of the second counter at Gen1 and Gen2 rates, otherwise select and output the output result of the first counter;

[0136] The SKP counter is used to accumulate the output result of the eighth selector to obtain the clock deviation compensation symbol count value SKP_COUNT.

[0137] See Figure 5, in this embodiment, the logic for the 4-byte clock skew compensation symbol SKP_4B parsing circuit to determine whether it is SKP_1B is: (rx_datak[i] & (rx_data[(i + 1) * 8 - 1:i * 8] == SKP_1B)), where i ranges from 0 to 3. The logic for determining whether it is COMMA_1B is: (rx_datak[0] & (rx_data[7:0] == COMMA_1B)). When the physical link operates in the Gen1 / Gen2 rate mode, the multiplexer selects the result of "determining whether it is COMMA_1B"; when the physical link operates in the Gen3 and above rate modes, the multiplexer selects the result of "determining whether it is SKP_1B". Finally, the determination results for each byte of the received data are obtained through logical AND (&) to get the 4-byte clock skew compensation symbol parsing result SKP_OUT. When calculating the cumulative SKP, in the Gen3 and above rate modes, for each received SKP_4B sequence {SKP_1B, SKP_1B, SKP_1B, SKP_1B}, the cumulative SKP counter is incremented by 1; in the Gen1 / 2 mode, for each received SKP sequence {SKP_1B, SKP_1B, SKP_1B, COMMA_1B}, the cumulative SKP counter is incremented by 3, indicating that 3 SKP_1B are received. The multiplexer is used to select whether to increment the value of the SKP counter by 1 or 3.

[0138] Such as Figure 1 And Figure 6As shown, in this embodiment, the data stream start detection circuit generates data stream start markers for both Gen1 and Gen2 rates and Gen3 and above rates simultaneously. The Gen1 / Gen2 signal representing Gen1 and Gen2 rates is used as the decoding enable signal to achieve alternative enabling of both the decoder supporting the data stream start delimiter (SDS) and the 128b / 130b decoder. The data stream start detection circuit includes an SDS detection circuit for Gen3 and above rates, an SDS detection circuit for Gen1 / Gen2 rates, and a ninth selector. The SDS detection circuit for Gen3 and above rates is used to detect the data stream start marker for the decoding result of the 128b / 130b decoder to obtain the output result SDS_OUT_GEN3. The SDS detection circuit for Gen1 / Gen2 rates is used to detect the data stream start marker for the decoding result of the decoder supporting the data stream start delimiter (SDS) to obtain the output result SDS_OUT_GEN1. The ninth selector is used to select one path from the output results SDS_OUT_GEN3 and SDS_OUT_GEN1 based on the control of the Gen1 / Gen2 signal as the finally generated data stream start marker. The 40-bit or 32-bit data obtained from the data link serial-to-parallel conversion circuit is sent to the 128b / 130b decoder and the 8b / 10b decoder. The Gen1 / Gen2 signal is used to control the decoding enable of the two decoders. When Gen1 / Gen2 is valid, the 8b / 10b decoder is enabled. When Gen1 / Gen2 is invalid, the 128b / 130b decoder is enabled. When Gen1 / Gen2 is valid, the output result SDS_OUT_GEN3 of the Gen1 / Gen2 SDS detection logic is selected to generate the data stream start marker. When Gen1 / Gen2 is invalid, the output result SDS_OUT_GEN1 of the Gen3 rate SDS detection logic is selected to generate the data stream start marker. Among them, the 128b130b decoder and the SDS detection circuit for Gen3 and above rates are existing well-known circuits, so their detailed implementations will not be elaborated here.

[0139] As Figure 7 shown, the Gen1 / Gen2 rate SDS detection circuit in this embodiment includes:

[0140] A thirteenth determination module, configured to determine whether the logical AND result of the 4th bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the SDS control character SDS_1B;

[0141] The fourteenth judgment module is used to judge whether the result of the AND operation between the 3rd bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the SDS control character SDS_1B;

[0142] The fifteenth judgment module is used to judge whether the result of the AND operation between the 2nd bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the SDS control character SDS_1B;

[0143] The sixteenth judgment module is used to judge whether the result of the AND operation between the 1st bit rx_datak[0] in the received K code rx_datak and the 1st to 8th bits rx_data[7:0] in the received data rx_data is equal to the SDS control character SDS_1B;

[0144] The third AND gate is used to perform a logical AND operation on the output results of the thirteenth judgment module, the fourteenth judgment module, the fifteenth judgment module, and the sixteenth judgment module to obtain the result SDS_OUT_GEN1 of whether the received data is the SDS control character. The logic for the Gen1 / Gen2 rate SDS detection circuit to judge whether it is SDS_1B is: (rx_datak[i] & (rx_data[(i + 1)*8 - 1:i*8] == SDS_1B)), where i is 0 to 3. The judgment results for each byte of the received data are obtained through the logical AND (&) logic to obtain the result SDS_OUT_GEN1 of whether the received data is the SDS control character. The valid signal of SDS_OUT_GEN1 will be used as the data stream start marker.

[0145] In summary, a significant difference between the Gen1 / Gen2 rate versions and the Gen3 and higher rate versions of the PCIe physical link is that the physical layer uses 8b / 10b encoding at Gen1 / Gen2 rates, while the physical layer uses 128b / 130b encoding at Gen3 and higher rates. There are differences in the types of control characters and even the encoding of the same control character between the two encodings. Since the CXL protocol only supports Gen3 and higher rates, its data stream start detection, clock skew compensation, and other logics are only based on the 128b / 130b encoding mechanism. When supporting Gen1 / Gen2 rates, due to the use of 8b / 10b encoding, some logics of the CXL protocol cannot work properly, which in turn causes the CXL protocol to not support Gen1 / Gen2 rates. If you want the CXL protocol to support Gen1 / Gen2 rates, it is necessary to unify the data stream start symbol (Start of Data Stream, SDS) generation and parsing logics and the 4-byte clock skew compensation symbol SKP_4B parsing logic under 8b / 10b encoding and 128b / 130b encoding. Therefore, the circuit that enables the CXL protocol to support low-speed serial links in this embodiment mainly includes four parts: The first part is an encoder and decoder that support the data stream start symbol (Start of Data Stream, SDS); the second part is a link management state machine circuit at the protocol sender end that includes a "send SDS" state; the third part is a 4-byte clock skew compensation symbol SKP_4B parsing circuit at the protocol receiver end; the fourth part is a data stream start detection circuit at the protocol receiver end. The circuit that enables the CXL protocol to support low-speed serial links in this embodiment can enable the CXL protocol specification to be extended to support PCIe Gen1 and Gen2 rates, enabling FPGA chips to use the CXL protocol and ASIC chips to still work properly when the physical link speed is reduced to Gen1 and Gen2.

[0146] In addition, this embodiment also provides a chip, including multiple die interconnected through a high-speed interconnect interface, and the high-speed interconnect interface includes the circuit that enables the CXL protocol to support low-speed serial links.

[0147] The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, several improvements and refinements made without departing from the principle of the present invention should also be regarded as within the protection scope of the present invention.

Claims

1. A circuit for enabling the CXL protocol to support a low-rate serial link, characterized in that: The invention comprises a transmitting end and a receiving end, wherein the transmitting end comprises a link management state machine including a "sending SDS" state, a 4-byte clock deviation compensation symbol SKP_4B generating circuit, an encoder supporting a data stream start symbol SDS, a 128b / 130b encoder, a 40:1 parallel-to-serial conversion circuit, a 32:1 parallel-to-serial conversion circuit and a multiplexer, wherein the encoder supporting the data stream start symbol SDS is used to perform 8b / 10b encoding on data of a PCIe physical link at Gen1 and Gen2 rates, and convert the 4-byte clock deviation compensation symbol The 4-byte clock deviation compensation symbol SKP_4B generated by the SKP_4B generating circuit is inserted into the message, and the receiving end includes a data stream start detection circuit, a 4-byte clock deviation compensation symbol SKP_4B parsing circuit, a decoder supporting the data stream start symbol SDS, a 128b / 130b decoder, a 1:40 serial-to-parallel conversion circuit, a 1:32 serial-to-parallel conversion circuit and a demultiplexer. The decoder supporting the data stream start symbol SDS is used to perform 10b / 8 on the data of the PCIe physical link at the Gen1 and Gen2 rates. b decoding, and after decoding, sending it to a 4-byte clock deviation compensation symbol SKP_4B parsing circuit to parse the 4-byte clock deviation compensation symbol SKP_4B in the message, the input end of the multiplexer is connected to the output end of the encoder supporting the data stream start symbol SDS through a 40:1 parallel-serial conversion circuit, and is connected to the output end of the 128b / 130b encoder through a 32:1 parallel-serial conversion circuit, the output end of the multiplexer is connected to the input end of the demultiplexer through a serial communication link, and the output end of the demultiplexer is connected to the input end of the demultiplexer through a 1:32 serial-parallel conversion circuit. The conversion circuit is connected to the input end of the 128b / 130b decoder and is connected to the input end of the decoder supporting the data stream start symbol SDS through a 1:40 serial-to-parallel conversion circuit. The data stream start detection circuit is used to generate a data stream start mark for Gen1 and Gen2 rates, and Gen3 and above rates at the same time, and uses the Gen1 / Gen2 signal representing the Gen1 and Gen2 rates as a decoding enable signal to realize the selective enablement of the decoder supporting the data stream start symbol SDS and the 128b / 130b decoder. The encoder supporting the data stream start character SDS adopts the 8b / 10b encoding rule with an added SDS control character to perform 8b / 10b encoding on the data of the PCIe physical link at the Gen1 and Gen2 rates, wherein the SDS control character is a code group identifier K28.4 reserved in the 8b / 10b encoding table of the CXL protocol; The decoder supporting the data stream start character SDS uses a 10b / 8b decoding rule with an added SDS control character to perform 10b / 8b decoding on data of the PCIe physical link at Gen1 and Gen2 rates. The SDS control character is a code group identifier K28.4 reserved in a 10b / 8b decoding table of the CXL protocol.

2. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 1, characterized in that: The encoder supporting the data stream start symbol SDS comprises: The first judgment module is used to judge whether the high 3 bits data_in[7:5] of the input 8-bit to-be-encoded data data_in are 3'd4 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal; The first NOT gate is used to generate a bitwise inverted value of the fixed code data_abcdei_sds, wherein the code value of the fixed code data_abcdei_sds is fixed to 6'b001101; The first selector is used to select and output between the fixed code data_abcdei_sds and the bitwise inverted value of the fixed code data_abcdei_sds generated by the first NOT gate according to the 1-bit polarity signal disp_in; wherein the 1-bit polarity signal disp_in is 1, indicating that the current clock cycle is positive polarity RD+, and is 0, indicating that the current clock cycle is negative polarity RD-; A second selector, used for selecting and generating a 6-bit code value data_abcdei between the output value of the first selector and the 0 code value according to the selection signal generated by the first judgment module; The second judgment module is used to judge whether the lower 5 bits data_in[4:0] of the input 8-bit to-be-encoded data data_in are 5'd28 and the input 1-bit K code k_in is 1 at the same time, and use the judgment result as the generated selection signal; The second NOT gate is used to generate a bitwise inverted value of the fixed code data_fghj_sds, wherein the code value of the fixed code data_fghj_sds is fixed to 4'b1100; A third selector is used to select and output between the fixed code data_fghj_sds and the bitwise inverted value of the fixed code data_fghj_sds generated by the second NOT gate according to the 1-bit polarity signal disp_in; A fourth selector is used to select between the output value of the third selector and the 0 encoding value to generate a 4-bit encoding value data_fghj according to the selection signal generated by the second judgment module, and together with the 6-bit encoding value data_abcdei, form an encoding result data_out={data_fghj, data_abcdei} output; The third judgment module is used to judge whether the encoding result data_out is equal to 10'h0, and use the judgment result as the generated error signal sds_err. If the error signal sds_err is 1, it means that the SDS control character encoding is incorrect.

3. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 2, characterized in that: The decoder supporting the data stream start symbol SDS comprises: A fourth judgment module is used to judge whether the upper 4 bits data_in[9:6] of the input 10-bit to-be-decoded data data_in are 4'b1100 or 4'b0011, and use the judgment result as the generated selection signal; a fifth selector, configured to select the fixed code data_EDCBA_sds or 5'd0 as the 5-bit decoded value data_EDCBA according to the selection signal generated by the fourth determination module; A fifth judgment module, used for judging whether the first, third and fourth bits of the 10-bit input data to be decoded data_in are all 1 at the same time, and outputting the judgment result as a signal; A sixth judgment module, used to judge whether any one of the 1st, 3rd and 4th bits of the 10-bit input data to be decoded data_in is 1, and output the judgment result as a signal; An OR gate, used for performing an OR operation on the signals output by the fifth judgment module and the sixth judgment module; a sixth selector, for selecting the fixed code data_HGF_sds or 3'd0 as the 3-bit decoding value data_HGF according to the OR operation result of the OR gate, and the 3-bit decoding value data_HGF and the 5-bit decoding value data_EDCBA together constitute the decoding result data_out={data_HGF, data_EDCBA}, wherein the code value of the fixed code data_HGF_sds is fixed to 3'd4; A first AND gate, used for performing an AND operation on the selection signal generated by the fourth judgment module and the OR operation result of the OR gate to output a 1-bit K code k_out to indicate whether the decoding result data_out is an SDS control character; The seventh judgment module is used to judge whether the decoding result data_out is equal to 8'h0, and use the judgment result as the generated error signal sds_err. If the error signal sds_err is 1, it means that the SDS control character decoding is wrong.

4. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 1, characterized in that: The encoder supporting the data stream start character SDS adopts a link management state machine with an added "send SDS" state to perform link management. The link management state machine with an added "send SDS" state includes the following states: "reset / idle" state, which is the initial state of the link and is entered after power-on; "link training" state, which is the state in which the link is initialized and trained; "L0 / active" state, which is a normal working state, in which the link normally sends and receives messages, and enters this state after the link training is completed; "L0s" state, which is a first-level low-power state; "retraining" state, which is a state in which the link is reinitialized and trained, and the link needs to be retrained in this state after exiting from the "L1" state, and can enter the "L0 / active" state after the training is completed; "L1" state, which is a second-level low-power state; "L2" state, which is a third-level low-power state state; "send SDS" state is the state of sending SDS control characters; exiting the "reset / idle" state enters the "link training" state; exiting the "link training" state enters the "send SDS" state; under the control of the "send SDS" state, the encoding circuit that supports the data stream start character SDS on the sending end starts to send SDS control characters. After the receiving end recognizes the SDS control characters and detects the start of the data stream, the link management state machine jumps from the "send SDS" state to the "L0 / active" state; the "L0 / active" state and the "L0s" state can switch to each other, and the "L0 / active" state can switch unidirectionally to the "L1" state and the "L2" state; exiting the "L2" state enters the "reset / idle" state; exiting the "L1" state enters the "retraining" state; exiting the "retraining" state re-enters the "send SDS" state.

5. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 1, characterized in that: When the PCIe physical link is at the rate of Gen1 and Gen2, the clock deviation compensation symbol SKP_4B in the message received by each link is {SKP_1B, SKP_1B, SKP_1B, COMMA_1B}; when the PCIe physical link is at the rate of Gen3 and above, the clock deviation compensation symbol SKP_4B in the message received by each link is {SKP_1B, SKP_1B, SKP_1B, SKP_1B}, wherein SKP_1B is a single-byte clock deviation compensation symbol, and COMMA_1B is a single-byte synchronization symbol; the 4-byte clock deviation compensation symbol SKP_4B parsing circuit includes: An eighth judgment module is used to judge whether the result of an AND operation of the fourth bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A ninth judgment module, used to judge whether the result of an AND operation of the third bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A tenth judgment module is used to judge whether the result of the AND operation of the second bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; An eleventh judgment module is used to judge whether the result of an AND operation of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the clock deviation compensation symbol SKP_1B; A twelfth judgment module is used to judge whether the AND operation result of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the synchronization symbol COMMA_1B; a seventh selector, configured to select the judgment result of the twelfth judgment module when the PCIe physical link is at the rate of Gen1 and Gen2, and to select the judgment result of the eleventh judgment module otherwise; The second AND gate is used to perform a logic AND operation on the output results of the eighth judgment module, the ninth judgment module, the tenth judgment module and the seventh selector to obtain a 4-byte clock deviation compensation symbol parsing result SKP_OUT; The first counter is used to output 1 every time a SKP_4B sequence {SKP_1B, SKP_1B, SKP_1B, SKP_1B} is received at the rate of Gen3 and above; The second counter is used to output 3 for each SKP sequence {SKP_1B, SKP_1B, SKP_1B, COMMA_1B} received at the Gen1 and Gen2 rates; an eighth selector, for selecting to output the output result of the second counter at the Gen1 and Gen2 rates, and otherwise selecting to output the output result of the first counter; The SKP counter is used to accumulate the output result of the eighth selector to obtain the clock deviation compensation symbol count value SKP_COUNT.

6. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 1, characterized in that: The data stream start detection circuit includes a Gen3 and above rate SDS detection circuit, a Gen1 / Gen2 rate SDS detection circuit and a ninth selector. The Gen3 and above rate SDS detection circuit is used to perform data stream start mark detection on the decoding result of the 128b / 130b decoder to obtain an output result SDS_OUT_GEN3. The Gen1 / Gen2 rate SDS detection circuit is used to perform data stream start mark detection on the decoding result of the decoder supporting the data stream start symbol SDS to obtain an output result SDS_OUT_GEN1. The ninth selector is used to select one from the output results SDS_OUT_GEN3 and the output results SDS_OUT_GEN1 as the final data stream start mark based on the control of the Gen1 / Gen2 signal.

7. The circuit for enabling the CXL protocol to support a low-rate serial link according to claim 6, characterized in that: The Gen1 / Gen2 rate SDS detection circuit comprises: The thirteenth judgment module is used to judge whether the result of the AND operation of the fourth bit rx_datak[3] in the received K code rx_datak and the 25th to 32nd bits rx_data[31:24] in the received data rx_data is equal to the SDS control character SDS_1B; A fourteenth judgment module is used to judge whether the result of the AND operation of the third bit rx_datak[2] in the received K code rx_datak and the 17th to 24th bits rx_data[23:16] in the received data rx_data is equal to the SDS control character SDS_1B; The fifteenth judgment module is used to judge whether the result of the AND operation of the second bit rx_datak[1] in the received K code rx_datak and the 9th to 16th bits rx_data[15:8] in the received data rx_data is equal to the SDS control character SDS_1B; A sixteenth judgment module is used to judge whether the result of the AND operation of the first bit rx_datak[0] in the received K code rx_datak and the first to eighth bits rx_data[7:0] in the received data rx_data is equal to the SDS control character SDS_1B; The third AND gate is used for performing a logic AND operation on the output results of the thirteenth judgment module, the fourteenth judgment module, the fifteenth judgment module and the sixteenth judgment module to obtain a result SDS_OUT_GEN1 of whether the received data is an SDS control character.

8. A chip comprising a plurality of core particles interconnected by a high-speed interconnect interface, characterized in that: The high-speed interconnect interface includes the circuit described in any one of claims 1 to 7 for enabling the CXL protocol to support a low-rate serial link.

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