Data transmission method, data transmission device, system on chip and storage medium

Abstract

The invention relates to the technical field of on-chip interconnection, and discloses a data transmission method, a data transmission device, a system on chip and a storage medium. Wherein the data transmission request sent by the host carries the current data packet and the bypass signal in order to prompt the redundant data volume needing to be optimized on the on-chip bus in the data transmission process of the current data packet. The bypass signal serves as additional information, transmission logic of original transmission protocol standard signals is not affected, the follow-up process of transmitting a current data packet to the slave is dynamically controlled through the bypass signal on the premise of being compatible with an original transmission protocol, and under the condition that it is detected that the transmitted data size reaches the optimized data size, the data packet is transmitted to the slave through the bypass signal. Transmission of the current data packet is terminated in time in advance, transmission of invalid data forcibly filled in an original transmission protocol is reduced, and the technical effects of reducing downstream bandwidth consumption and remarkably improving the bandwidth utilization rate are achieved.

Description

Technical Field

[0001] The present application relates to the field of on-chip interconnection technology, and in particular to a data transmission method, a data transmission device, an on-chip system and a storage medium. Background Art

[0002] In AI computing scenarios, computing power is huge. As the data channel between processors, memory, and accelerators, the on-chip bus needs to make full use of bandwidth with limited design resources.

[0003] In the related art, when the total amount of data transmission cannot completely fill the integer multiple of the bus data bit width, invalid data is usually used to fill the remaining part.

[0004] However, this method of filling invalid data will lead to bandwidth waste. Therefore, a new data transmission method is urgently needed to optimize this problem. Summary of the invention

[0005] The present application provides a data transmission method, a data transmission device, a system on chip and a storage medium, which solve the technical problem of bandwidth waste caused by filling invalid data, and achieve the technical effect of reducing bandwidth consumption by reducing the transmission of invalid data amount.

[0006] In order to achieve the above objectives, the main technical solutions adopted in this application include: The present application provides a data transmission method, the method comprising: Receive a data transmission request sent by a host; wherein the data transmission request carries a current data packet and a bypass signal, and the bypass signal is used to prompt the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission process of the current data packet; The current data packet is transmitted to the slave machine, and if it is detected that the amount of transmitted data reaches the optimized data amount, the transmission of the current data packet is terminated; wherein the optimized data amount is calculated based on the protocol description data amount corresponding to the current data packet and the redundant data amount.

[0007] The data transmission method proposed in the embodiment of the present application is that in order to prompt the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission of the current data packet, the data transmission request sent by the host carries the current data packet and the bypass signal. The bypass signal, as additional information, does not affect the transmission logic of the original transmission protocol standard signal, and realizes the subsequent process of transmitting the current data packet to the slave by dynamically controlling the bypass signal under the premise of compatibility with the original transmission protocol, and when it is detected that the amount of transmitted data reaches the optimized data amount, the transmission of the current data packet is terminated in advance in time, reducing the transmission of invalid data that is forcibly filled by the original transmission protocol, so as to achieve the purpose of reducing downstream bandwidth consumption and significantly improving bandwidth utilization.

[0008] Optionally, the optimized data amount is determined based on a difference between the protocol description data amount and the redundant data amount.

[0009] Optionally, the method further includes determining whether to generate the bypass signal in the following manner: determining the actual required data volume, base address offset and bus data bit width of the on-chip bus corresponding to the current data packet; if it is determined that the protocol description data volume contains the redundant data volume that needs to be marked according to the actual required data volume, the base address offset and the bus data bit width, generating the bypass signal. Information transmission between the host address calculation module and the host bus interface module is realized through the bypass signal, providing preparation conditions for accurately transmitting the redundant data volume to the host bus interface module.

[0010] Optionally, judging whether the amount of redundant data that needs to be marked exists in the amount of data described in the protocol based on the amount of data actually required, the base address offset and the bus data bit width includes: determining a first multiple between the amount of data actually required and a preset data granularity, a second multiple between the base address offset and the preset data granularity, and a third multiple between the bus data bit width of the on-chip bus and the preset data granularity; judging whether the amount of redundant data exists in the amount of data described in the protocol based on the arithmetic operation result of the first multiple, the second multiple and the third multiple. This embodiment proposes a judgment mechanism for whether to trigger a bypass signal, which is conducive to reducing unnecessary data transmission.

[0011] Optionally, judging whether the redundant data amount exists in the protocol description data amount according to the arithmetic operation results of the first multiple, the second multiple and the third multiple includes: obtaining the sum operation result of the first multiple and the second multiple; taking the modulus of the third multiple according to the sum operation result to obtain a first modulus operation result; if the first modulus operation result is not equal to zero, judging that the redundant data amount exists in the protocol description data amount.

[0012] Optionally, judging whether the redundant data amount exists in the protocol description data amount according to the arithmetic operation result of the first multiple, the second multiple and the third multiple includes: determining the difference between the third multiple and the second multiple, performing a difference operation using the first multiple and the difference to obtain a difference operation result; performing modulo operation on the third multiple according to the difference operation result to obtain a second modulo operation result; if the second modulo operation result is not equal to zero, judging that the redundant data amount exists in the protocol description data amount.

[0013] Optionally, the second multiple is a positive integer smaller than the third multiple; and the first multiple is greater than a difference between the third multiple and the second multiple.

[0014] Optionally, the preset data granularity is X times the basic data granularity; the basic data granularity is related to the data bit width of the slave, and X is a positive integer less than the third multiple. By adjusting the preset data granularity, the interface bit width of different slaves can be flexibly adapted while maintaining efficient use of the bus.

[0015] Optionally, the optimized data volume is determined in the following manner: parsing the bypass signal to obtain the redundant data volume; parsing the burst parameters in the current data packet to calculate the amount of data to be transmitted that complies with the transmission protocol to obtain the protocol description data volume; subtracting the redundant data volume from the protocol description data volume to obtain the optimized data volume. In this embodiment, the bypass signal and the current data packet are parsed by the host bus interface module to determine the optimized data volume to guide the physical layer to transmit on demand, thereby reducing the transmission of redundant data volume and improving bandwidth utilization.

[0016] Optionally, the transmission of the current data packet to the slave machine, if it is detected that the amount of data transmitted has reached the optimized data amount, the transmission of the current data packet is terminated, including: splitting the current data packet according to a preset data granularity to obtain multiple sub-data packets; sending the sub-data packets to the slave machine via the on-chip bus, and counting the amount of data transmitted in real time; if the counting result shows that the amount of data transmitted has reached the optimized data amount, the transmission of the current data packet is terminated. In this embodiment, by comparing the amount of data transmitted and the amount of data after optimization, a basis for determination is provided for early termination of transmission. When the amount of data transmitted reaches the optimized data amount, the transmission of the current data packet is terminated to avoid redundant data occupying bandwidth.

[0017] Optionally, if the counting result indicates that the amount of data transmitted has reached the optimized amount of data, terminating the transmission of the current data packet includes: if the counting result indicates that the amount of data transmitted has reached the optimized amount of data, sending a packet end signal to the slave in advance. This embodiment can maintain AXI protocol compatibility without modifying the slave hardware logic.

[0018] An embodiment of the present application provides a data transmission device, which includes a host bus interface module, and is configured to receive a data transmission request sent by a host, transmit a current data packet carried by the data transmission request to a slave, and terminate the transmission of the current data packet if it is detected that the amount of transmitted data reaches the optimized data amount; wherein the data transmission request also carries a bypass signal, and the bypass signal is used to prompt the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission of the current data packet, and the optimized data amount is calculated based on the protocol description data amount corresponding to the current data packet and the redundant data amount.

[0019] Optionally, the device also includes a host address calculation module connected to the host bus interface module; the host address calculation module is configured to generate the bypass signal when it is determined that there is redundant data that needs to be marked in the protocol description data based on the actual required data amount corresponding to the current data packet, the base address offset and the bus data bit width of the on-chip bus.

[0020] An embodiment of the present application provides an on-chip system, including a host, an on-chip bus and a slave; the host is connected to the slave via the on-chip bus; the on-chip bus is used to implement the data transmission method as described in any one of the above embodiments.

[0021] An embodiment of the present application provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to enable a computer to execute the data transmission method as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1a A schematic diagram of data transmission in the related art using invalid data blocks to fill the bus data bit width; Figure 1b A schematic diagram of data transmission using a narrowband transmission method in the related art; Figure 1c A schematic diagram of a data transmission architecture provided in a scenario example of this specification; Figure 1d A schematic diagram of data splitting provided in a scenario example of this specification; Figure 1eThis is an interactive schematic diagram of a data transmission method provided in a scenario example of this specification; Figure 1f This is another schematic diagram of data splitting provided in the scenario example of this specification; Figure 2 This is a flow chart of a data transmission method provided in one embodiment of the present application; Figure 3 A flowchart of generating a bypass signal provided in an embodiment of the present application; Figure 4 A flowchart for determining whether there is redundant data in the protocol description data provided in an embodiment of the present application; Figure 5 A flowchart of a data transmission method provided in another embodiment of the present application; Figure 6 A schematic diagram of a data transmission device provided in an embodiment of the present application; Figure 7 A schematic diagram of a data transmission device provided in another embodiment of the present application; Figure 8 A schematic diagram of a system on chip provided in an embodiment of the present application; Fig. 9 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0025] In the related technologies, bus protocols for high-performance, low-latency data transmission have emerged. Such bus protocols are suitable for high-bandwidth and low-latency systems and can be widely used in SoC design, communication equipment, storage systems and other fields. However, there is a technical problem of bandwidth waste in data packet transmission scenarios based on such bus protocols. Taking the AXI protocol as an example, the Advanced eXtensible Interface (AXI) is a high-performance system bus suitable for high-speed deep submicron integrated circuit interconnection. The AXI bus is designed for high performance, high bandwidth and low latency, and is widely used for data transmission of high-performance processors and other on-chip system components.

[0026] In the AXI system architecture, there are hosts (Master), buses and slaves (S1ave). Among them, the bus includes the host bus interface module (Internface), the bus matrix (Bus Matrix) and the slave bus interface module. The host bus interface module is located between the host and the bus matrix. The slave bus interface module is located between the slave and the bus matrix. The bus matrix can provide a multi-channel communication mechanism and support multiple master devices to access multiple slave devices concurrently. The bus matrix plays a role in routing and management during the data transmission process, ensuring that data flows to the target device along the correct path, and performs corresponding control and scheduling. The bus matrix is ​​also called AXI Interconnect. The AXI protocol architecture is based on five main transmission channels. From the perspective of the upper-layer protocol, AXI divides the transmission into five signals according to the direction: The read address signal (AR, Address Read) of the read operation is sent from the master to the slave (S1ave) to request a read operation. The read data signal (R, Read) of the read operation is returned from the slave to the master, carrying the read data.

[0027] The write address signal (AW, Address Write) of the write operation is sent from the Master to the Slave to request the write operation. The write data signal (W, Write) of the write operation carries the data to be written. The write response signal (B, Back) of the write operation is returned by the Slave to the Master, indicating that the write operation is completed.

[0028] In an AXI transaction, data is organized in the form of bursts. A burst can contain one or more data units, each of which is called a beat. An AXI transaction includes all interactions between the Master and the Slave to transfer a set of data. For example, a read transaction includes the Master sending an AR signal and the Slave responding to an R signal; a write transaction includes the Master sending an AW and W signal and the Slave responding to a B signal. The type of burst (such as fixed burst, incremental burst, etc.) can be selected according to specific needs to optimize data transmission efficiency.

[0029] The following also takes the AXI protocol as an example to introduce two typical scenarios in related technologies. The on-chip interconnect solution is implemented based on the AXI protocol, and the data packet transmission volume is described by a combination of base address, burst length, and burst size. However, when the total transmission volume does not fill an integer multiple of the bus data width (BusWidth), the transmission data volume defined by the protocol layer will significantly exceed the actual demand, resulting in redundant transmission of invalid data. Figure 1a Invalid data block 102 is shown. Such redundant transmission not only wastes bandwidth resources, but also increases transmission delay and dynamic power consumption. In order to alleviate this problem, related technologies use narrowband transmission (Narrow Transfer), such as Figure 1b As shown, the host's wide data is split into multiple narrow transmissions, but this will introduce additional protocol overhead.

[0030] Therefore, in order to effectively improve bandwidth utilization under limited resources, the scenario example of this specification provides a data transmission architecture. Under this data transmission architecture, a bypass signal is generated to guide transmission truncation through the difference between the theoretical calculation data volume and the actual transmission data volume specified by the protocol. While maintaining the integrity of the AXI protocol, invalid data transmission is reduced or eliminated, providing a low-overhead, highly flexible bandwidth optimization path for high-density computing scenarios.

[0031] In this scenario example, Figure 1c As shown, the data transmission architecture includes a host, a bus and a slave. The bus includes a host bus interface module, a bus matrix and a slave bus interface module. The host bus interface module is located between the bus matrix and the host, the slave bus interface module is located between the bus matrix and the slave, and a host address calculation module is provided in the host.

[0032] In this scenario example, the host address calculation module generates a data transmission request that complies with the AXI protocol by calculating the address and the actual required data volume. If it is detected that the actual required data volume is less than the theoretical transmission data volume (or the protocol description data volume) specified by the original AXI that does not use the narrowband transmission method, it is necessary to inform the subsequent bus of the redundant data volume through the bypass signal. The redundant data volume is the invalid data volume that can be optimized in the protocol description data volume. The host sends the protocol request transmission information (or the current data packet) and the bypass signal to the host bus interface module. The host bus interface module obtains the redundant data volume that needs to be reduced by parsing the bypass signal and performs the optimized data transmission, so that the subsequent bus transmits the optimized data volume to the slave bus interface module and transmits it to the slave. The slave receives the data transmitted by the bus and caches it.

[0033] It should be noted that the host sends the current data packet, caches and parses the current data packet in the host bus interface module, and sends the sub-data packet to the bus downstream according to the data granularity N, and counts the amount of transmitted data through the counter. The host bus interface module ends the transmission of the current data packet until the amount of transmitted data reaches the optimized data amount.

[0034] like Figure 1d and 1e As shown, the data transmission method provided by this scenario example is exemplarily described. The host address calculation module generates transmission data that conforms to the AXI protocol, including a first data block 1 with a data bit width equal to 2N, a second data block 2 with a data bit width equal to N, and a third data block 3 with a data bit width equal to N. Among them, the third data block 3 is the amount of data transmission that can be optimized. The host sends the current data packet and the bypass signal to the host bus interface module. The host bus interface module obtains the amount of redundant data that needs to be reduced by parsing the bypass signal, determines the amount of data after optimization, and performs optimized data transmission. Specifically, according to the data granularity N, the first data block 1 with a data bit width equal to 2N is packaged, and the fourth data block 4 with a data bit width equal to N and the fifth data block 5 with a data bit width equal to N are split. The fourth data block 4, the fifth data block 5, and the second data block 2 with data bit widths equal to N are sent to the bus in sequence. Counting is performed while sending. When the count reaches the optimized data amount, the host bus interface module ends the sending of the current data packet and adjusts the packet end signal. The slave receives the data blocks transmitted by the bus and caches them. When the slave receives the packet end signal, the slave returns a completion signal to the bus, and the bus returns the completion signal to the host.

[0035] In another example, Figure 1f , the host address calculation module generates transmission data that conforms to the AXI protocol, including the base address offset 104, the actual required data volume 106 and the redundant data volume 108. Among them, the transmission data that conforms to the AXI protocol is an integer multiple of the bus data bit width M×N, and its data length is recorded as Length. The base address offset 104 is expressed as a×N, which is the offset of the base address of the transmission data relative to the bus data bit width. The actual required data volume 106 is expressed as b×N, and the redundant data volume 108 is expressed as k×N, which is the optimized transmission data volume. Among them, a is a positive integer less than M, b is a positive integer greater than (Ma), and k is a positive integer less than M.

[0036] Pack the data downstream according to the data granularity N and send it to the bus. The amount of redundant data k×N transmitted by the bypass signal can determine the optimized data volume. Pack the optimized data volume according to the data granularity N, split the optimized data volume into multiple data blocks with a data bit width equal to N, and dynamically send the data blocks with a data bit width equal to N to the bus in sequence. Count while sending, and when the counter reaches the optimized data volume, the host bus interface module ends the transmission of the current data packet and adjusts the packet end signal. In this scenario example, not only can the transmission of invalid data be effectively reduced, but also narrowband transmission is not introduced, the bandwidth of large bit width upstream transmission is maintained, and no additional narrowband transmission overhead is introduced on the host side, and there is no additional delay overhead compared to narrowband transmission.

[0037] It should be noted that, in some cases, the bus data bit width may be referred to as the bus bit width or the bus interface bit width. In this specification, for example, the above scenario examples are described using the widely used AXI protocol as an example, and the data transmission method and data transmission architecture mentioned can also be applied to data packet transmission scenarios with similar mechanisms. The protocol used in the data packet transmission scenario may be other self-defined similar protocols, or a protocol that adds some custom behaviors based on the AXI protocol, or a protocol described in a manner similar to the AXI protocol.

[0038] According to an embodiment of the present application, an embodiment of a data transmission method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0039] Figure 2 is a flow chart of a data transmission method according to an embodiment of the present application. Figure 2 As shown, the data transmission method includes the following steps: S210, receiving a data transmission request sent by a host, where the data transmission request carries a current data packet and a bypass signal.

[0040] In this embodiment, the bypass signal (Sideband Signals) is used to prompt the amount of redundant data 108 that needs to be optimized on the on-chip bus during the data transmission process of the current data packet. The data transmission request is a transmission request sent by the host to the host bus interface module and complies with the provisions of the transmission protocol. The transmission protocol is explained by taking the AXI protocol as an example. The current data packet is used as the main data transmission signal, and the bypass signal can be regarded as an auxiliary signal or an extended signal transmitted in parallel with the main data transmission signal, and the bypass signal is transmitted synchronously with the current data packet. The bypass signal allows the user to add custom information according to specific needs to achieve specific system functions such as notifying the amount of redundant data 108. The bypass signal can express the amount of redundant data 108 indirectly or directly. A direct method can be used to indicate how many bytes the amount of data to be transmitted needs to be reduced, and an indirect method can be used to equivalently indicate the amount of data to be transmitted. For example, for multi-beat transmission, how much each beat can be identified.

[0041] It should be noted that, taking the AXI protocol as an example, the bypass signal transmits additional optimization information without interfering with the original AXI protocol signal. The AXI protocol adopts a reserved extension mechanism. The USER signal defined by the AXI protocol is a user-defined signal reserved by the protocol. The bit width and function are not mandatory in the protocol. This design allows developers to implement the bypass signal in this embodiment through the USER signal without violating the protocol specification to transmit control information outside the protocol. That is, the amount of redundant data 108 that needs to be optimized on the on-chip bus is transmitted through the bypass signal to guide the host bus interface module to terminate the invalid transmission amount of redundant transmission in advance.

[0042] As mentioned in the background technology, when the total amount of data transmission cannot completely fill the integer multiple of the bus data bit width, invalid data is usually used to fill the remaining part. The redundant data amount 108 can be at least part of the invalid data block used to make the total amount of data transmission completely fill the integer multiple of the bus data bit width. Taking the AXI protocol as an example, when the host interface bit width is large and the slave interface bit width is small, the redundant data amount 108 can be determined according to the difference between the transmission data amount specified in the AXI protocol and the actual transmission data amount without using narrowband transmission.

[0043] Since invalid data transmitted on the on-chip bus leads to waste of bus bandwidth, in order to reduce unnecessary data transmission, the amount of redundant data that can be optimized on the subsequent bus is notified by a bypass signal 108. Specifically, the host can determine the amount of transmission data specified by the protocol when narrowband transmission is not used by calculating the address and the actual amount of data required in the host address calculation module. If it is further detected that the actual amount of transmission data is less than the amount of transmission data specified by the protocol, the host generates a bypass signal. The host sends the current data packet and the bypass signal to the host bus interface module synchronously, so as to inform the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission of the current data packet through the bypass signal 108. The host bus interface module receives the data transmission request.

[0044] S220, transmitting the current data packet to the slave device, and if it is detected that the amount of transmitted data reaches the optimized amount of data, terminating the transmission of the current data packet.

[0045] In this embodiment, the optimized data volume is calculated based on the protocol description data volume and redundant data volume 108 corresponding to the current data packet. The protocol description data volume can be understood as the transmission data volume that complies with the AXI protocol regulations when narrowband transmission is not used. The transmission data volume that complies with the AXI protocol regulations can be calculated based on AXI protocol parameters (such as burst length and burst size). In other words, the protocol description data volume refers to the theoretical total transmission data volume calculated based on the AXI protocol parameters, which may contain redundant invalid data that fills blanks. Further, in order to reduce the bandwidth waste caused by invalid data, the redundant data volume 108 is used to optimize and adjust the protocol description data volume to obtain the optimized data volume. For example, the redundant ratio is determined based on the redundant data volume 108, and the protocol description data volume is optimized and adjusted using the redundant ratio to obtain the optimized data volume. For another example, a dynamic adjustment factor matching the actual transmission situation is determined, and the redundant data volume 108 is adjusted according to the dynamic adjustment factor to obtain the adjusted redundant data volume, and the difference between the protocol description data volume and the adjusted redundant data volume is calculated to obtain the optimized data volume.

[0046] Specifically, after acquiring the current data packet and the bypass signal, the host bus interface module parses and executes the current data packet and the bypass signal. Since the bypass signal has been used to mark the existence of an optimizable transmission data volume, after parsing the bypass signal and the current data packet, the host bus interface module can clearly determine the optimizable redundant data volume 108, thereby calculating the optimized data volume. Based on the parsing result, the host bus interface module sends the current data packet to the slave. During the data transmission process, the host bus interface module counts the amount of data that has been transmitted, and compares the amount of data that has been transmitted obtained by statistics with the optimized data volume. If it is detected that the amount of data that has been transmitted reaches the optimized data volume, it indicates that the subsequent amount of data to be transmitted is the redundant data volume 108, and the transmission of the current data packet can be dynamically truncated, that is, the transmission of the current data packet is terminated in advance, reducing the transmission of subsequent redundant invalid data. It can be understood that the optimized data volume is equal to the actual transmission data volume before truncating at least part of the redundant data volume.

[0047] The data transmission method provided in this embodiment, in order to prompt the redundant data volume 108 that needs to be optimized on the on-chip bus during the data transmission process of the current data packet, the data transmission request sent by the host carries the current data packet and the bypass signal. The bypass signal, as additional information, does not affect the transmission logic of the original transmission protocol standard signal, and realizes the subsequent process of transmitting the current data packet to the slave by dynamically controlling the bypass signal under the premise of compatibility with the original transmission protocol, and timely terminates the transmission of the current data packet in advance when it is detected that the amount of transmitted data has reached the optimized data amount, reducing the transmission of invalid data that is forcibly filled by the original transmission protocol, so as to achieve the purpose of reducing downstream bandwidth consumption and significantly improving bandwidth utilization.

[0048] In some embodiments, the optimized data amount is determined based on the difference between the protocol description data amount and the redundant data amount.

[0049] In this embodiment, since the redundant data volume 108 can be transmitted through the bypass signal, and the redundant data volume 108 is the invalid data volume used to fill the blank, the actual transmission data volume corresponding to the current data packet is obtained by subtracting the redundant data volume 108 transmitted by the bypass signal from the protocol description data volume corresponding to the current data packet, as the optimized data volume. Specifically, after the host bus interface module obtains the current data packet and the bypass signal sent by the host, in the subsequent data transmission process, the host bus interface module counts the amount of data that has been transmitted, and compares the amount of data that has been transmitted obtained by counting with the optimized data volume. If it is detected that the amount of data that has been transmitted reaches the optimized data volume, it indicates that the subsequent amount of data to be transmitted is invalid data that is forcibly filled by the protocol, and it is no longer necessary to transmit the invalid data that is forcibly filled by the protocol, thereby triggering the dynamic truncation of the current data packet transmission process.

[0050] In the above embodiment, the redundant data volume 108 is transmitted through the bypass signal, which is an extra-protocol signal, so that when it is determined that the amount of data transmitted meets the actual needs of data transmission, the transmission process of the current data packet can be stopped in time, thereby avoiding invalid transmission while maintaining the compatibility of the original transmission protocol.

[0051] In some embodiments, Figure 3 As shown, the method also includes the step of determining whether to generate a bypass signal in the following manner: S310, determining the actual required data amount, base address offset and bus data bit width of the on-chip bus corresponding to the current data packet.

[0052] S320: If it is determined based on the actual required data volume, the base address offset and the bus data bit width that there is redundant data volume that needs to be marked in the protocol description data volume, a bypass signal is generated.

[0053] In this embodiment, the current data packet may be an original transmission request data packet generated based on a transmission protocol such as the AXI protocol, which may include protocol parameters and data payload required for transmission. The current data packet is generated by the host and is used to describe a complete data transmission task. The current data packet has a base address (Base Address), a burst length (BurstLength), a burst size (Burst Size) and the data content to be transmitted.

[0054] In this embodiment, the actual required data amount can be the amount of valid data that the application layer actually needs to transmit, excluding invalid data filled due to protocol alignment rules. The actual required data amount can be directly determined by the application task requirements. It is understandable that the actual required data amount can be passed to the host address calculation module through the application layer logic or hardware configuration interface.

[0055] In this embodiment, the base address offset may be the offset of the data start address or the base address of the transmission relative to the bus data bit width alignment boundary. The bus data bit width may be the data capacity of a single transmission of the intra-chip bus. The protocol description data volume may be the theoretical transmission data volume calculated based on the AXI protocol parameters (such as burst length, burst size). The protocol description data volume may include redundant data or invalid data filled because the total amount of data is not aligned with the bus data bit width.

[0056] Under the AXI protocol framework, the protocol description data volume of data transmission must be strictly aligned with the bus data width. When the total amount of data is not aligned with the bus data width, the protocol layer will force invalid data to be filled to meet the alignment rules, and the invalid data will occupy limited bus resources. Furthermore, although narrowband transmission is used in the related art to improve the forced filling mechanism under the AXI protocol, the narrowband transmission control logic will cause additional overhead, increase transmission delay and power consumption. Therefore, in this embodiment, the host address calculation module is responsible for calculating the redundant data volume 108, and a bypass signal is introduced to transfer the redundant data volume 108 to the host bus interface module.

[0057] Specifically, the host address calculation module obtains the actual required data amount, the base address offset and the bus data bit width of the on-chip bus. Redundancy judgment is performed based on the actual required data amount, the base address offset and the bus data bit width to determine whether there is redundant data amount 108 that needs to be marked in the protocol description data amount. For example, the size relationship between the protocol description data amount and the actual transmission data amount is determined by the redundancy judgment result. If the protocol description data amount is greater than the actual transmission data amount, there is redundant invalid data and a bypass signal needs to be generated. If there is no redundant data amount 108 in the protocol description data amount, there is no need to generate a bypass signal. Exemplarily, it is determined whether the actual required data amount and the base address offset can fill an integer multiple of the bus data bit width. If the integer multiple of the bus data bit width can be filled, there is no redundant invalid data. If the integer multiple of the bus data bit width cannot be filled, there is redundant invalid data.

[0058] In the above embodiment, the bypass signal is generated by the host address calculation module, and the information transmission between the host address calculation module and the host bus interface module is realized through the bypass signal, so as to provide preparation conditions for accurately transmitting the redundant data volume 108 to the host bus interface module. It not only avoids the separation of the protocol layer and the physical layer, but also effectively solves the bandwidth waste problem caused by the protocol alignment rules in the related technology; it also avoids the use of narrowband transmission, and does not introduce additional narrowband transmission overhead on the host side.

[0059] The embodiment of the present application also provides a method for determining whether there is redundant data 108 in the protocol description data. Figure 4 As shown, the determination method includes the following steps: S410, determining a first multiple of the actual required data amount and the preset data granularity, a second multiple of the base address offset and the preset data granularity, and a third multiple of the bus data bit width of the on-chip bus and the preset data granularity.

[0060] S420. Determine whether there is redundant data in the protocol description data according to the arithmetic operation results of the first multiple, the second multiple, and the third multiple.

[0061] In this embodiment, the preset data granularity may be the smallest logical unit of data transmission, which is used to quantify the actual effective data volume, base address offset, and bus data bit width, and is defined as the net data volume excluding protocol control signals (such as address and status bits). The preset data granularity may be denoted as N. It should be noted that the preset data granularity may be expanded to x×N according to hardware design requirements. x is a positive integer less than the third multiple.

[0062] In this embodiment, the first multiple may be the total amount of valid data actually required to be transmitted converted into an integer multiple value in units of preset data granularity N. The second multiple may be the offset of the data start address relative to the alignment boundary of the bus data bit width, which is an integer multiple value in units of preset data granularity N. The third multiple may be an integer multiple value of the physical transmission capacity of the on-chip bus in units of preset data granularity N. Among them, the first multiple may be recorded as b, the second multiple may be recorded as a, and the third multiple may be recorded as M. Since the offset does not exceed the bus data bit width, the second multiple a is a positive integer less than the third multiple M. Since the actual required data volume needs to be greater than the remaining capacity between the bus data bit width and the base address offset, the first multiple b is greater than the difference (Ma) between the third multiple and the second multiple. It can be understood that the bus data bit width is expressed as M×N, the actual required data volume is expressed as b×N, and the base address offset is expressed as a×N.

[0063] In some cases, in order to simplify the judgment logic of whether there is redundant data volume 108, the actual required data volume, base address offset and bus data bit width are uniformly dimensioned according to the preset data granularity, and the unit difference is eliminated by multiple conversion to avoid introducing floating point operations. All parameters are positive integers, which are suitable for low-complexity implementation of hardware logic.

[0064] Specifically, a first multiple of the actual required data volume and the preset data granularity is calculated, a second multiple of the base address offset and the preset data granularity is calculated, and a third multiple of the bus data bit width of the on-chip bus and the preset data granularity is calculated. Arithmetic operations are performed using the first multiple, the second multiple, and the third multiple, and it is determined whether there is redundant data in the protocol description data volume according to the arithmetic operation result 108.

[0065] In one embodiment, judging whether there is redundant data 108 in the protocol description data volume based on the arithmetic operation results of the first multiple, the second multiple and the third multiple includes: obtaining the sum operation result of the first multiple and the second multiple; performing modulo operation on the third multiple according to the sum operation result to obtain a first modulo operation result; if the first modulo operation result is not equal to zero, judging that there is redundant data 108 in the protocol description data volume.

[0066] Specifically, whether there is redundant data 108 in the protocol description data is determined by the following formula: y1=(a+b)%M; Among them, y1 is used to represent the first modulo operation result, a is used to represent the second multiple, b is used to represent the first multiple, and M is used to represent the third multiple.

[0067] If the first modulo operation result y1 is not equal to 0, it is determined that there is redundant data 108 in the protocol description data. If the first modulo operation result y1 is equal to 0, it is determined that there is no redundant data 108 in the protocol description data. Further, when y1 is not equal to 0, it indicates that the amount of invalid data in the last beat of data is equal to (M-y1)×N. Wherein, if (M-y1) is denoted as k, then k=[M-(a+b)%M]. The redundant data amount 108 is marked by the bypass signal, and the redundant data amount 108 is equal to k×N.

[0068] Exemplarily, N is equal to 64 bits, and if the bus data bit width is 256 bits, the third multiple M is equal to 4. If the actual amount of data to be transmitted is 320 bits, the first multiple b is equal to 5. If the base address offset is equal to 64 bits, the second multiple a is equal to 1.

[0069] y1=(1+5)%4=2; k=4-2=2; In this example, y1 is not equal to 0, indicating that the total span of the actual required data amount and the base address offset is not aligned with the bus data bit width, and it is determined that there is redundant data 108 in the protocol description data amount, and the amount of invalid data in the last beat of data is equal to 2N. A bypass signal needs to be generated to optimize transmission, and the redundant data amount 108 is marked by the bypass signal, and the redundant data amount 108 is equal to 2N.

[0070] In another embodiment, based on the arithmetic operation results of the first multiple, the second multiple and the third multiple, it is determined whether there is redundant data in the protocol description data volume, including: determining the difference between the third multiple and the second multiple, performing a difference operation using the first multiple and the difference to obtain a difference operation result; performing a modulo operation on the third multiple according to the difference operation result to obtain a second modulo operation result; if the second modulo operation result is not equal to zero, it is determined that there is redundant data in the protocol description data volume.

[0071] Specifically, the following formula is used to determine whether there is redundant data in the protocol description data: y2=[b-(Ma)]%M; Among them, y2 is used to represent the second modulo operation result, a is used to represent the second multiple, b is used to represent the first multiple, and M is used to represent the third multiple.

[0072] If the second modulo operation result y2 is not equal to 0, it is determined that there is redundant data in the data volume described by the protocol. If the second modulo operation result y2 is equal to 0, it is determined that there is no redundant data in the data volume described by the protocol. Further, when y2 is not equal to 0, it indicates that the amount of invalid data in the last beat of data is equal to (M-y2)×N. Wherein, if (M-y2) is denoted as k, then k={M-[b-(Ma)]%M}. The redundant data volume 108 is marked by the bypass signal, and the redundant data volume 108 is equal to k×N.

[0073] Exemplarily, N is equal to 64 bits, and if the bus data bit width is 256 bits, the third multiple M is equal to 4. If the actual amount of data to be transmitted is 320 bits, the first multiple b is equal to 5. If the base address offset is equal to 64 bits, the second multiple a is equal to 1.

[0074] y2=[5-(4-1)]%4=2; k=4-2=2; In this example, y2 is not equal to 0, indicating that the total span of the actual required data amount and the base address offset is not aligned with the bus data bit width, and it is determined that there is redundant data in the protocol description data amount, and the amount of invalid data in the last beat of data is equal to 2N. A bypass signal needs to be generated to optimize transmission, and the redundant data amount 108 is marked by the bypass signal, and the redundant data amount 108 is equal to 2N.

[0075] In some embodiments, the preset data granularity is X times the basic data granularity; the basic data granularity is related to the interface bit width of the slave, and X is a positive integer less than the third multiple.

[0076] Among them, the preset data granularity can be the smallest logical unit of data transmission, which is used to quantify the actual effective data volume, base address offset and bus data bit width. The basic data granularity can be a reference data unit directly related to the slave bit width, which is used to define the expansion basis of the preset data granularity. The basic data granularity needs to be strictly aligned with the physical design parameters of the slave to ensure the compatibility of data reception and processing. X refers to the expansion multiple between the preset data granularity and the basic data granularity, and its value range is a positive integer less than the third multiple M. Exemplarily, if the third multiple M is equal to 4 (the bus data bit width is 4N), X can be set to 1, 2 or 3. For example, when the basic data granularity is 64 bits and X=2, the preset data granularity N=128 bits.

[0077] In the above embodiment, the preset data granularity is dynamically adjusted according to the slave bit width to adapt to different hardware scenarios. X must be less than the third multiple to ensure that the expansion of the preset data granularity is within the controllable range of the bus data bit width. By adjusting the preset data granularity, the interface bit width of different slaves can be flexibly adapted while maintaining efficient use of the bus.

[0078] It should be noted that the basic data granularity is recorded as n. If the preset data granularity adopts the basic data granularity n, the calculation formula in the above embodiment can remain unchanged. If the preset data granularity is expanded to X×n, a in the calculation formula in the above embodiment can be replaced by a / X, b can be replaced by b / X, k can be replaced by k / X, and M can be replaced by M / X, where a / X, b / X, k / X and M / X are positive integers.

[0079] In some embodiments, the optimized data volume is determined by: parsing the bypass signal to obtain the redundant data volume; parsing the burst parameters in the current data packet, calculating the amount of data to be transmitted in accordance with the transmission protocol, and obtaining the protocol description data volume; subtracting the redundant data volume from the protocol description data volume to obtain the optimized data volume.

[0080] In this embodiment, the transmission protocol is described by taking the AXI protocol as an example, and the bypass signal may be an out-of-protocol signal generated by the host address calculation module, which is used to transmit the amount of redundant data that needs to be reduced to the subsequent host bus interface module 108. The burst parameter may be a transmission control parameter defined in the AXI protocol, including a burst length and a burst size. It should be noted that the burst parameter determines the calculation rule of the protocol description data amount.

[0081] Specifically, by parsing the bypass signal, the optimizable redundant data volume 108 calculated by the host address calculation module is extracted to provide a basis for the control of the subsequent transmission process. By parsing the burst parameters in the current data packet, the complete transmission volume specified by the protocol is obtained as the basis for optimization calculation, which can ensure protocol compatibility and avoid modifying the AXI standard parameters. The optimized data volume is obtained by calculating the difference between the protocol description data volume and the redundant data volume 108.

[0082] In the above embodiment, the bypass signal and the current data packet are parsed by the host bus interface module to determine the optimized data volume to guide the physical layer to transmit on demand, thereby reducing the transmission of redundant data volume 108 and improving bandwidth utilization.

[0083] In some embodiments, Figure 5 As shown, transmitting the current data packet to the slave, if it is detected that the amount of transmitted data reaches the optimized amount of data, terminating the transmission of the current data packet, may include the following steps: S510: Split the current data packet according to a preset data granularity to obtain multiple sub-data packets.

[0084] S520, sending sub-data packets to the slave device via the on-chip bus, and counting the amount of transmitted data in real time.

[0085] S530: If the counting result shows that the amount of transmitted data reaches the optimized amount of data, the transmission of the current data packet is terminated.

[0086] In this embodiment, the preset data granularity is recorded as N. The preset data granularity can be the smallest logical unit of data transmission, which is used to quantify the benchmark value of data splitting, transmission and measurement, and is defined as the net data volume excluding the protocol control signal. The on-chip bus can be a physical data transmission channel connecting the host and the slave inside the system-on-chip (SoC), and its bit width is determined by the hardware design parameters. The on-chip bus follows the AXI protocol standard and supports burst transmission mode. It should be noted that the on-chip bus only carries valid data, that is, the optimized data volume during the transmission process, and the redundant data volume 108 indicated by the bypass signal has been dynamically truncated.

[0087] Specifically, the host bus interface module serves as the middle between the on-chip bus and the host, receives the current data packet and caches it internally. The current data packet is parsed, split according to the preset data granularity N, and the data is packaged and sent to the on-chip bus. The sub-data packets are dynamically sent to the slave through the on-chip bus and counted in real time to determine the amount of data transmitted, providing a basis for early termination of transmission. When the amount of data transmitted reaches the optimized data amount, the transmission of the current data packet is terminated to avoid redundant data occupying bandwidth.

[0088] In one embodiment, if the counting result shows that the amount of transmitted data reaches the optimized data amount, a packet end signal is sent to the slave in advance. Specifically, the bus host interface module counts the number of sub-packets that have been sent in real time and converts it into a cumulative value in units of preset data granularity N. When the value is equal to the optimized data amount, the termination condition is triggered. When the bus host interface module detects that the termination condition is met, it immediately sets the packet end signal defined by the transmission protocol to notify the slave that the current data packet transmission is over. For example, the LAST signal defined by the AXI protocol is set, and the packet end signal is set in the transmission of the last valid sub-packet. This embodiment can maintain AXI protocol compatibility without modifying the slave hardware logic. In other words, by setting the last beat data signal representing the current data packet in the protocol, the remaining data of the same data packet is not transmitted to the downstream at the same time, thereby achieving the purpose of stopping data transmission.

[0089] Furthermore, the slave receives the sub-data packet transmitted by the on-chip bus and caches it until the packet end signal is obtained. The slave returns a confirmation signal to the on-chip bus. The on-chip bus returns the confirmation signal to the host. The host receives the confirmation signal sent by the slave and ends the transmission of the current data packet. Specifically, after detecting the packet end signal, the slave returns a confirmation signal (such as the BVALID or RVALID signal of AXI) to the host through the on-chip bus. The confirmation signal is returned through the on-chip bus and forwarded to the host to inform the slave that the optimized data volume has been successfully received and cached. The handshake signal confirms that the transmission is complete, and the status synchronization of the host and the slave is achieved. By terminating the transmission task, the bus resources are released and the counter is reset to prepare for the next transmission task. It can be understood that the interaction between the packet end signal and the confirmation signal complies with the AXI standard, and the optimization logic is transparent to the downstream slave and does not need to be perceived.

[0090] According to an embodiment of the present application, a data transmission device embodiment is also provided, such as Figure 6 As shown, the data transmission device 600 includes a host bus interface module 610. The host bus interface module 610 is configured to receive a data transmission request sent by the host, transmit the current data packet carried by the data transmission request to the slave, and terminate the transmission of the current data packet if it is detected that the amount of transmitted data reaches the optimized data amount; wherein the data transmission request also carries a bypass signal, and the bypass signal is used to prompt the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission process of the current data packet, and the optimized data amount is calculated based on the protocol description data amount and the redundant data amount corresponding to the current data packet.

[0091] In some embodiments, Figure 7 As shown, the data transmission device 600 further includes a host address calculation module 710 connected to the host bus interface module 610. The host address calculation module is configured to generate a bypass signal when determining that there is redundant data that needs to be marked in the protocol description data according to the actual required data amount corresponding to the current data packet, the base address offset and the bus data bit width of the intra-chip bus.

[0092] The further functional description of each of the above modules is the same as that of the above corresponding embodiments and will not be repeated here.

[0093] The data transmission device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0094] According to an embodiment of the present application, a system on a chip is also provided. Figure 8As shown, the on-chip system includes a host 810, an on-chip bus 820 and a slave 830. The host 810 is connected to the slave 830 via the on-chip bus 820. The host 810 is coupled to the host bus interface of the on-chip bus 820, and the slave 830 is coupled to the slave bus interface of the on-chip bus 820. The on-chip bus 820 is used to implement the data transmission method as described in any one of the above embodiments.

[0095] According to an embodiment of the present application, a computing device is also provided. The computing device includes a processor and a memory. The memory stores computer executable instructions. When these computer executable instructions are executed by the processor, they implement the data transmission method provided by at least one embodiment of the present disclosure. Fig. 9 The figure shows a schematic block diagram of an electronic device. Fig. 9 As shown, the electronic device 900 includes a processor 910 and a memory 920. The memory 920 is used to store computer executable instructions (e.g., one or more computer program modules). The processor 910 is used to run the computer executable instructions, and when the computer executable instructions are run by the processor 910, one or more steps in the method described above can be executed. The memory 920 and the processor 910 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0096] For example, the processor 910 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be a CISC or RISC structure, such as an X86 or ARM architecture. The processor 910 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 900 to perform desired functions.

[0097] For example, the memory 920 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 910 may run one or more computer program modules to implement various functions of the electronic device 900. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0098] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0099] The embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method of any embodiment of the present application.

[0100] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

[0101] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. For the convenience of description, the above devices are described separately by functions in various units. Of course, when implementing the present application, the functions of each unit may be implemented in the same or multiple software and / or hardware.

[0102] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0103] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate a device for implementing the functions specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0104] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0105] These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0106] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0107] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0108] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0109] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A data transmission method, characterized in that: The method comprises: Receive a data transmission request sent by a host; wherein the data transmission request carries a current data packet and a bypass signal, and the bypass signal is used to prompt the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission process of the current data packet; The current data packet is transmitted to the slave machine, and if it is detected that the amount of transmitted data reaches the optimized data amount, the transmission of the current data packet is terminated; wherein the optimized data amount is calculated based on the protocol description data amount corresponding to the current data packet and the redundant data amount.

2. The method according to claim 1, characterized in that: The optimized data amount is determined based on the difference between the protocol description data amount and the redundant data amount.

3. The method according to claim 1, characterized in that The method further comprises, Whether the bypass signal is generated is determined by: Determine the actual required data amount, base address offset and bus data bit width of the on-chip bus corresponding to the current data packet; If it is determined according to the actually required data amount, the base address offset and the bus data bit width that there is the redundant data amount that needs to be marked in the protocol description data amount, the bypass signal is generated.

4. The method according to claim 3, characterized in that The determining, according to the actually required data amount, the base address offset and the bus data bit width, that there is the redundant data amount that needs to be marked in the protocol description data amount comprises: Determine a first multiple of the actually required data amount and a preset data granularity, a second multiple of the base address offset and the preset data granularity, and a third multiple of the bus data bit width of the on-chip bus and the preset data granularity; According to the arithmetic operation result of the first multiple, the second multiple and the third multiple, it is determined whether the redundant data amount exists in the protocol description data amount.

5. The method according to claim 4, characterized in that The step of judging whether the redundant data amount exists in the protocol description data amount according to the arithmetic operation result of the first multiple, the second multiple and the third multiple includes: Obtaining a summation result of the first multiple and the second multiple; Performing modulo operation on the third multiple according to the sum operation result to obtain a first modulo operation result; If the first modulo operation result is not equal to zero, it is determined that the redundant data amount exists in the protocol description data amount.

6. The method according to claim 4, characterized in that The step of judging whether the redundant data amount exists in the protocol description data amount according to the arithmetic operation result of the first multiple, the second multiple and the third multiple includes: determining a difference between the third multiple and the second multiple; Performing a difference operation using the first multiple and the difference value to obtain a difference operation result; Performing modulo operation on the third multiple according to the difference operation result to obtain a second modulo operation result; If the second modulo operation result is not equal to zero, it is determined that the redundant data amount exists in the protocol description data amount.

7. The method according to claim 4, characterized in that The second multiple is a positive integer smaller than the third multiple; The first multiple is greater than a difference between the third multiple and the second multiple.

8. The method according to claim 4, characterized in that The preset data granularity is X times the basic data granularity; The basic data granularity is related to the interface bit width of the slave, and X is a positive integer less than the third multiple.

9. The method according to any one of claims 1 to 8, characterized in that: The optimized data volume is determined by: parsing the bypass signal to obtain the redundant data amount; Parsing the burst parameters in the current data packet, calculating the amount of data to be transmitted in accordance with the transmission protocol, and obtaining the protocol description data amount; The optimized data volume is obtained by subtracting the redundant data volume from the protocol description data volume.

10. The method according to any one of claims 1 to 8, characterized in that: The transmitting of the current data packet to the slave device, and terminating the transmission of the current data packet if it is detected that the amount of transmitted data reaches the optimized amount of data, comprises: Splitting the current data packet according to a preset data granularity to obtain multiple sub-data packets; Sending the sub-data packet to the slave via the on-chip bus, and counting the amount of transmitted data in real time; If the counting result indicates that the amount of transmitted data reaches the optimized amount of data, the transmission of the current data packet is terminated.

11. The method according to claim 10, characterized in that If the counting result indicates that the amount of transmitted data reaches the optimized amount of data, terminating the transmission of the current data packet includes: If the counting result indicates that the amount of transmitted data reaches the optimized amount of data, a packet end signal is sent to the slave.

12. A data transmission device, characterized in that: The device comprises: A host bus interface module is configured to receive a data transmission request sent by a host, transmit a current data packet carried by the data transmission request to a slave, and terminate the transmission of the current data packet if it is detected that the amount of transmitted data reaches the optimized data amount; wherein the data transmission request also carries a bypass signal, and the bypass signal is used to prompt the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission of the current data packet, and the optimized data amount is calculated based on the protocol description data amount corresponding to the current data packet and the redundant data amount.

13. The device according to claim 12, characterized in that The device also includes a host address calculation module connected to the host bus interface module; The host address calculation module is configured to generate the bypass signal when it is determined that there is redundant data that needs to be marked in the protocol description data based on the actual required data amount corresponding to the current data packet, the base address offset and the bus data bit width of the on-chip bus.

14. A system on chip, characterized in that: It includes a host, an on-chip bus and a slave; the host is connected to the slave via the on-chip bus; The on-chip bus is used to implement the data transmission method according to any one of claims 1 to 11.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the data transmission method according to any one of claims 1 to 11.

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