Data Transmission Method, Data Transmission Device, System on Chip, and Storage Medium

Abstract

The present application relates to the field of on-chip interconnection technology, and discloses a data transmission method, a data transmission device, a system on a chip, and a storage medium. Among them, in order to prompt the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission of the current data packet, the data transmission request sent by the host carries the current data packet and a bypass signal. The bypass signal, as additional information, does not affect the transmission logic of the original transmission protocol standard signal, realizes dynamically controlling the subsequent process of transmitting the current data packet to the slave through the bypass signal on the premise of being compatible with the original transmission protocol, and terminates the transmission of the current data packet in advance in a timely manner when it is detected that the amount of transmitted data reaches the optimized data amount, reducing the transmission of invalid data forcibly filled by the original transmission protocol, and achieving the technical effects of reducing downstream bandwidth consumption and significantly improving bandwidth utilization.

Description

Technical Field

[0001] This application relates to the field of on-chip interconnection technology, and particularly to a data transmission method, a data transmission device, a system on a chip, and a storage medium. Background Art

[0002] In the artificial intelligence computing scenario, the computing power demand is huge. As the data channel between the processor, the memory, and the accelerator, the on-chip bus needs to make full use of the bandwidth under limited design resources.

[0003] In the related art, when the total amount of data to be transmitted cannot completely fill an integer multiple of the bus data width, invalid data is usually used to fill the remaining part.

[0004] However, this method of filling invalid data will cause bandwidth waste. Therefore, there is an urgent need for a new data transmission method to optimize this problem. Summary of the Invention

[0005] This application provides a data transmission method, a data transmission device, a system on a chip, and a storage medium, which solve the technical problem of bandwidth waste caused by the method of filling invalid data, and achieve the technical effect of reducing bandwidth consumption by reducing the transmission of invalid data volume.

[0006] To achieve the above object, the main technical solutions adopted in this application include:

[0007] An embodiment of this application provides a data transmission method, and the method includes:

[0008] Receiving a data transmission request sent by a host; wherein, the data transmission request carries a current data packet and a bypass signal, and the bypass signal is used to indicate the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission process of the current data packet;

[0009] Transmitting the current data packet to a slave device, and terminating the transmission of the current data packet if it is detected that the amount of data already transmitted reaches the optimized data volume; wherein, the optimized data volume is calculated according to the protocol description data volume corresponding to the current data packet and the redundant data volume.

[0010] In the data transmission method provided by the embodiment of the present application, in order to prompt the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission of the current data packet, the data transmission request sent by the host carries the current data packet and a bypass signal. As additional information, the bypass signal does not affect the transmission logic of the original transmission protocol standard signal, realizes dynamically controlling the subsequent process of transmitting the current data packet to the slave through the bypass signal on the premise of being compatible with the original transmission protocol, and terminates the transmission of the current data packet in advance in a timely manner when it is detected that the amount of transmitted data reaches the optimized amount of data, reducing the transmission of invalid data forcibly filled in the original transmission protocol, so as to achieve the purpose of reducing downstream bandwidth consumption and significantly improving bandwidth utilization.

[0011] Optionally, the optimized amount of data is determined based on the difference between the protocol-described amount of data and the amount of redundant data.

[0012] Optionally, the method further includes determining whether to generate the bypass signal in the following manner: determining the actually required amount of data, the base address offset, and the bus data bit width of the on-chip bus corresponding to the current data packet; if it is determined that there is redundant data that needs to be marked in the protocol-described amount of data according to the actually required amount of data, the base address offset, and the bus data bit width, generating the bypass signal. The information transfer between the host address calculation module and the host bus interface module is realized through the bypass signal, providing a preparation condition for accurately transmitting the amount of redundant data to the host bus interface module.

[0013] Optionally, determining that there is redundant data that needs to be marked in the protocol-described amount of data according to the actually required amount of data, the base address offset, and the bus data bit width includes: determining a first multiple between the actually required amount of data and a preset data granularity, a second multiple between the base address offset and the preset data granularity, and a third multiple between the bus data bit width of the on-chip bus and the preset data granularity; judging whether there is redundant data in the protocol-described amount of data according to the arithmetic operation result of the first multiple, the second multiple, and the third multiple. This embodiment proposes a judgment mechanism for whether to trigger a bypass signal, which is beneficial to reducing unnecessary data transmission.

[0014] Optionally, judging whether there is redundant data in the protocol-described amount of data according to the arithmetic operation result of the first multiple, the second multiple, and the third multiple includes: obtaining the summation operation result of the first multiple and the second multiple; taking the modulo of the third multiple according to the summation operation result to obtain a first modulo operation result; if the first modulo operation result is not equal to zero, determining that there is redundant data in the protocol-described amount of data.

[0015] Optionally, determining whether there is redundant data volume in the protocol description data volume according to the arithmetic operation result of the first multiple, the second multiple, and the third multiple includes: determining the difference between the third multiple and the second multiple, performing a subtraction operation using the first multiple and the difference to obtain a subtraction operation result; taking the modulus of the third multiple according to the subtraction operation result to obtain a second modulus operation result; if the second modulus operation result is not equal to zero, determining that there is redundant data volume in the protocol description data volume.

[0016] Optionally, the second multiple is a positive integer less than the third multiple; the first multiple is greater than the difference between the third multiple and the second multiple.

[0017] Optionally, the preset data granularity is X times the basic data granularity; the basic data granularity is related to the data bit width of the slave device, and X is a positive integer less than the third multiple. By adjusting the preset data granularity, different slave device interface bit widths can be flexibly adapted while maintaining the efficient utilization of the bus.

[0018] Optionally, the optimized data volume is determined in the following manner: parsing the bypass signal to obtain the redundant data volume; parsing the burst parameters in the current data packet to calculate the data volume to be transmitted that conforms to the transmission protocol regulations to obtain the protocol description data volume; subtracting the redundant data volume from the protocol description data volume to obtain the optimized data volume. In this embodiment, the bypass signal and the current data packet are parsed by the host bus interface module to determine the optimized data volume, so as to guide the physical layer to transmit on demand, thereby reducing the transmission of redundant data volume and improving the bandwidth utilization rate.

[0019] Optionally, when transmitting the current data packet to the slave device, if it is detected that the transmitted data volume reaches the optimized data volume, terminating the transmission of the current data packet includes: splitting the current data packet according to the preset data granularity to obtain a plurality of sub - data packets; sending the sub - data packets to the slave device through the on - chip bus and counting the transmitted data volume in real time; if the counting result indicates that the transmitted data volume reaches the optimized data volume, terminating the transmission of the current data packet. In this embodiment, by comparing the transmitted data volume and the optimized data volume, a determination basis for early termination of transmission is provided. When the transmitted data volume reaches the optimized data volume, the transmission of the current data packet is ended to avoid redundant data occupying the bandwidth.

[0020] Optionally, when the counting result indicates that the amount of transmitted data has reached the optimized data amount, terminating the transmission of the current data packet includes: when the counting result indicates that the amount of transmitted data has reached the optimized data amount, sending a packet end signal to the slave in advance. This embodiment can maintain the AXI protocol compatibility without modifying the slave hardware logic.

[0021] An embodiment of the present application provides a data transmission device, which includes a host bus interface module configured to receive a data transmission request sent by a host, transmit the current data packet carried in the data transmission request to a slave, and terminate the transmission of the current data packet if it is detected that the amount of transmitted data has reached the optimized data amount; wherein, the data transmission request further carries a bypass signal, and the bypass signal is used to indicate the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission process of the current data packet, and the optimized data amount is calculated according to the protocol description data amount corresponding to the current data packet and the redundant data amount.

[0022] Optionally, the device further includes a host address calculation module connected to the host bus interface module; the host address calculation module is configured to generate the bypass signal when it is determined that there is redundant data amount to be marked in the protocol description data amount according to the actually required data amount corresponding to the current data packet, the base address offset, and the bus data width of the on-chip bus.

[0023] An embodiment of the present application provides a system on a chip, including a host, an on-chip bus, and a slave; the host is connected to the slave through the on-chip bus; the on-chip bus is used to implement the data transmission method described in any one of the above embodiments.

[0024] An embodiment of the present application provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to execute the data transmission method described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1a It is a schematic diagram of transmitting data by filling the bus data width with invalid data blocks in the related art;

[0027] Figure 1bSchematic diagram of data transmission using narrowband transmission mode in related technologies;

[0028] Figure 1c Schematic diagram of the data transmission architecture provided in the scenario example of this specification;

[0029] Figure 1d Schematic diagram of a data splitting provided in the scenario example of this specification;

[0030] Figure 1e Interaction schematic diagram of the data transmission method provided in the scenario example of this specification;

[0031] Figure 1f Schematic diagram of another data splitting provided in the scenario example of this specification;

[0032] Figure 2 Flowchart of the data transmission method provided in an embodiment of this application;

[0033] Figure 3 Flowchart of generating a bypass signal provided in an embodiment of this application;

[0034] Figure 4 Flowchart of determining whether there is redundant data volume in protocol description data volume provided in an embodiment of this application;

[0035] Figure 5 Flowchart of the data transmission method provided in another embodiment of this application;

[0036] Figure 6 Schematic diagram of the data transmission device provided in an embodiment of this application;

[0037] Figure 7 Schematic diagram of the data transmission device provided in another embodiment of this application;

[0038] Figure 8 Schematic diagram of the system on chip provided in an embodiment of this application;

[0039] Figure 9 Schematic diagram of the electronic device provided in an embodiment of this application. Detailed implementation manners

[0040] To make the objectives, technical solutions and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Apparently, the described embodiments are some but not all of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the protection scope of this application.

[0041] In related technologies, bus protocols for high-performance and low-latency data transmission have emerged. Such bus protocols are suitable for high-bandwidth and low-latency systems and can be widely applied in fields such as SoC design, communication devices, and storage systems. However, there are technical problems of bandwidth waste in the packet transmission scenarios based on such bus protocols. Taking the AXI protocol as an example of the scenario for illustration, the Advanced eXtensible Interface (AXI) is a high-performance system bus suitable for the interconnection of high-speed deep sub-micron integrated circuits. The AXI bus is designed for high performance, high bandwidth, and low latency and is widely used in the data transmission of high-performance processors and other on-chip system components.

[0042] In the AXI system architecture, it includes a Master, a bus, and a Slave. Among them, the bus includes a Master bus interface module (Internface), a Bus Matrix, and a Slave bus interface module. The Master bus interface module is located between the Master and the Bus Matrix. The Slave bus interface module is located between the Slave and the Bus Matrix. The Bus Matrix can provide a multi-channel communication mechanism and support multiple master devices to concurrently access multiple slave devices. The Bus Matrix plays a role of routing and management during the data transmission process, ensuring that the data flows to the target device along the correct path and performing corresponding control and scheduling. The Bus Matrix is also called AXI Interconnect. The AXI protocol architecture is based on five main transmission channels. From the perspective of the upper-layer protocol, AXI divides the transmission into five signals according to the direction:

[0043] The read address signal (AR, Address Read) for the read operation is sent from the Master to the Slave to request a read operation. The read data signal (R, Read) for the read operation is returned from the Slave to the Master, carrying the read data.

[0044] The write address signal (AW, Address Write) for the write operation is sent from the Master to the Slave to request a write operation. The write data signal (W, Write) for the write operation carries the data to be written. The write response signal (B, Back) for the write operation is returned from the Slave to the Master, indicating that the write operation is completed.

[0045] In an AXI transfer transaction, data is organized in the form of a burst transfer. A single burst transfer can contain one or more data units, and each data unit is called a beat. An AXI transfer transaction includes all the interactions between the Master and the Slave for transferring a set of data. For example, a read transaction includes the Master sending an AR signal and the Slave responding with an R signal; a write transaction includes the Master sending AW and W signals and the Slave responding with a B signal. The type of burst transfer (such as fixed burst, incremental burst, etc.) can be selected according to specific requirements to optimize the data transfer efficiency.

[0046] Taking the AXI protocol as an example below, two typical scenarios in the related technology are introduced. The on-chip interconnection solution is implemented based on the AXI protocol, and the amount of data packet transmission is described by the combination of the base address, burst length, and burst size. However, when the total transmission amount does not fill an integer multiple of the bus data width (BusWidth), the amount of transmitted data defined by the protocol layer will significantly exceed the actual requirement, resulting in redundant transmission of invalid data. As Figure 1a shown by the invalid data block 102, such redundant transmission not only wastes bandwidth resources but also increases the transmission delay and dynamic power consumption. To alleviate this problem, the related technology adopts narrow transfer, as Figure 1b shown, splitting the wide data of the host into multiple narrow transfers, but this will introduce additional protocol overhead.

[0047] Therefore, in order to effectively improve the bandwidth utilization under limited resources, the scenario example in this specification provides a data transmission architecture. Under this data transmission architecture, the difference data amount between the theoretically calculated data amount and the actual transmitted data amount stipulated by the protocol is used to generate a bypass signal to guide the transmission truncation. While maintaining the integrity of the AXI protocol, it reduces or eliminates invalid data transmission, providing a low-overhead and highly flexible bandwidth optimization path for high-density computing scenarios.

[0048] In this scenario example, as Figure 1c shown, the data transmission architecture includes a host, a bus, and a slave. Among them, the bus includes a host bus interface module, a bus matrix, and a slave bus interface module. The host bus interface module is located between the bus matrix and the host, the slave bus interface module is located between the bus matrix and the slave, and a host address calculation module is set in the host.

[0049] In this scenario example, the host address calculation module generates a data transmission request that complies with the AXI protocol by calculating the address and the actual required data volume. If it is detected that the actual required data volume is less than the theoretical transmission data volume (or the protocol description data volume) specified by the original AXI that does not use the narrowband transmission method, it is necessary to inform the subsequent bus of the redundant data volume through the bypass signal. The redundant data volume is the invalid data volume that can be optimized in the protocol description data volume. The host sends the protocol request transmission information (or the current data packet) and the bypass signal to the host bus interface module. The host bus interface module obtains the redundant data volume that needs to be reduced by parsing the bypass signal and performs the optimized data transmission, so that the subsequent bus transmits the optimized data volume to the slave bus interface module and transmits it to the slave. The slave receives the data transmitted by the bus and caches it.

[0050] It should be noted that the host sends the current data packet, caches and parses the current data packet in the host bus interface module, and sends the sub-data packet to the bus downstream according to the data granularity N, and counts the amount of transmitted data through the counter. The host bus interface module ends the transmission of the current data packet until the amount of transmitted data reaches the optimized data amount.

[0051] like Figure 1d and 1e As shown, the data transmission method provided by this scenario example is exemplarily described. The host address calculation module generates transmission data that conforms to the AXI protocol, including a first data block 1 with a data bit width equal to 2N, a second data block 2 with a data bit width equal to N, and a third data block 3 with a data bit width equal to N. Among them, the third data block 3 is the amount of data transmission that can be optimized. The host sends the current data packet and the bypass signal to the host bus interface module. The host bus interface module obtains the amount of redundant data that needs to be reduced by parsing the bypass signal, determines the amount of data after optimization, and performs optimized data transmission. Specifically, according to the data granularity N, the first data block 1 with a data bit width equal to 2N is packaged, and the fourth data block 4 with a data bit width equal to N and the fifth data block 5 with a data bit width equal to N are split. The fourth data block 4, the fifth data block 5, and the second data block 2 with data bit widths equal to N are sent to the bus in sequence. Counting is performed while sending. When the count reaches the optimized data amount, the host bus interface module ends the sending of the current data packet and adjusts the packet end signal. The slave receives the data blocks transmitted by the bus and caches them. When the slave receives the packet end signal, the slave returns a completion signal to the bus, and the bus returns the completion signal to the host.

[0052] In another example, Figure 1f, the host address calculation module generates transmission data conforming to the AXI protocol, including a base address offset 104, an actual required data volume 106, and a redundant data volume 108. Among them, the transmission data conforming to the AXI protocol is an integer multiple of the bus data bit width M×N, and its data length is denoted as Length. The base address offset 104 is expressed as a×N, which is the offset of the base address of the transmission data relative to the bus data bit width. The actual required data volume 106 is expressed as b×N, and the redundant data volume 108 is expressed as k×N, which is the optimizable transmission data volume. Among them, a is a positive integer less than M, b is a positive integer greater than (M - a), and k is a positive integer less than M.

[0053] Pack and send data to the bus downstream according to the data granularity N. The redundant data volume k×N transmitted through the bypass signal can determine the optimized data volume. Pack according to the data granularity N, split the optimized data volume into multiple data blocks with a data bit width equal to N, and sequentially send the data blocks with a data bit width equal to N to the bus dynamically. While sending, perform counting. When the counter reaches the optimized data volume, the host bus interface module ends the transmission of the current data packet and adjusts the packet end signal. In this scenario example, not only can the transmission of invalid data be effectively reduced, but also no narrow-band transmission is introduced, maintaining the bandwidth during upstream transmission with a large bit width, without introducing additional overhead for narrow-band transmission at the host end, and there is no additional delay overhead compared to narrow-band transmission.

[0054] It should be noted that in some cases, the bus data bit width can be referred to as the bus bit width or the bus interface bit width. In this specification, for example, the above scenario example is described with the widely used AXI protocol as an example, and the mentioned data transmission method and data transmission architecture can also be applied to packet transmission scenarios with similar mechanisms. The protocol adopted by the packet transmission scenario can be other self-defined similar protocols, or a protocol with some custom behaviors added on the basis of the AXI protocol, or a protocol described in a manner similar to the AXI protocol.

[0055] According to an embodiment of the present application, an embodiment of a data transmission method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0056] Figure 2 is a flowchart of the data transmission method according to an embodiment of the present application, as Figure 2 shown, the data transmission method includes the following steps:

[0057] S210. Receive a data transmission request sent by the host, where the data transmission request carries a current data packet and a bypass signal.

[0058] In this embodiment, sideband signals are used to indicate the amount of redundant data 108 that needs to be optimized on the on-chip bus during the data transmission of the current data packet. The data transmission request is a transmission request sent by the host to the host bus interface module and compliant with the transmission protocol. Taking the AXI protocol as an example to illustrate the transmission protocol, the current data packet is used as the main data transmission signal, and the sideband signal can be regarded as an auxiliary signal or an extended signal transmitted in parallel with the main data transmission signal, and the sideband signal is transmitted synchronously with the current data packet. The sideband signal is custom information that allows users to add according to specific requirements to achieve specific system functions such as informing the amount of redundant data 108. The sideband signal can express the amount of redundant data 108 in an indirect manner or a direct manner. The direct way can be used to indicate how many bytes of data need to be reduced for transmission, and the indirect way can be used to equivalently indicate the amount of data that needs to be reduced for transmission. For example, in the case of multi-beat transmission, how much can be reduced can be identified for each beat.

[0059] It should be noted that taking the AXI protocol as an example, the sideband signal transmits additional optimization information without interfering with the original AXI protocol signals. The AXI protocol adopts a reserved extension mechanism. The USER signal defined by the AXI protocol is a user-defined signal reserved by the protocol, and neither the bit width nor the function is forcibly specified in the protocol. This design allows developers, without violating the protocol specifications, the sideband signal in this embodiment can be implemented through the USER signal to transmit control information outside the protocol. That is, the amount of redundant data 108 that needs to be optimized on the on-chip bus is transmitted through the sideband signal to guide the host bus interface module to terminate the invalid transmission amount of the redundant transmission in advance.

[0060] As mentioned in the background art, when the total amount of data transmission cannot completely fill an integer multiple of the bus data bit width, invalid data is usually used to fill the remaining part. The redundant data amount 108 can be at least part of the invalid data block used to make the total amount of data transmission completely fill an integer multiple of the bus data bit width. Taking the AXI protocol as an example, in the case where the host-side interface bit width is large and the slave-side interface bit width is small, the redundant data amount 108 can be determined according to the difference data amount between the transmission data amount specified by the AXI protocol and the actual transmission data amount without using narrow-band transmission.

[0061] Since the invalid data transmitted on the on-chip bus causes waste of bus bandwidth, in order to reduce unnecessary data transmission, a bypass signal is used to inform the subsequent bus of the redundant data volume 108 that can be optimized. Specifically, the host can calculate the amount of data to be transmitted as specified by the protocol when not using narrowband transmission by calculating the address and the actual required data volume in the host address calculation module. If it is further detected that the actual transmitted data volume is less than the data volume specified by the protocol, the host generates a bypass signal. The host synchronously sends the current data packet and the bypass signal to the host bus interface module to inform, through the bypass signal, of the redundant data volume 108 that needs to be optimized on the on-chip bus during the data transmission of the current data packet. The host bus interface module receives the data transmission request.

[0062] S220. Transmit the current data packet to the slave. If it is detected that the amount of data already transmitted has reached the optimized data volume, terminate the transmission of the current data packet.

[0063] In this embodiment, the optimized data volume is calculated based on the protocol description data volume corresponding to the current data packet and the redundant data volume 108. The protocol description data volume can be understood as the amount of data to be transmitted that conforms to the AXI protocol when not using narrowband transmission. The amount of data to be transmitted that conforms to the AXI protocol can be calculated based on AXI protocol parameters (such as burst length and burst size). Or rather, the protocol description data volume refers to the total theoretical data volume calculated according to the AXI protocol parameters, which may include redundant invalid data for filling blanks. Further, in order to reduce the bandwidth waste caused by invalid data, the redundant data volume 108 is used to optimize and adjust the protocol description data volume to obtain the optimized data volume. For example, a redundancy ratio is determined based on the redundant data volume 108, and the protocol description data volume is optimized and adjusted using the redundancy ratio to obtain the optimized data volume. Another example is to determine a dynamic adjustment factor that matches the actual transmission situation, adjust the redundant data volume 108 according to the dynamic adjustment factor to obtain an adjusted redundant data volume, and calculate the difference between the protocol description data volume and the adjusted redundant data volume to obtain the optimized data volume.

[0064] Specifically, after obtaining the current data packet and the bypass signal, the host bus interface module parses and executes the current data packet and the bypass signal. Since there is an amount of transferable data that can be optimized marked by the bypass signal, after parsing the bypass signal and the current data packet, the host bus interface module can determine the redundant data amount 108 that can be optimized, and thus calculate the optimized data amount. Based on the parsing result, the host bus interface module sends the current data packet to the slave. During the data transfer process, the host bus interface module counts the amount of data that has been transferred, and compares the counted transferred data amount with the optimized data amount. If it is detected that the transferred data amount reaches the optimized data amount, it indicates that the subsequent data amount to be transferred is the redundant data amount 108, and the transmission of the current data packet can be dynamically truncated, that is, the transmission of the current data packet can be terminated in advance, reducing the transmission of subsequent redundant and invalid data. It can be understood that the optimized data amount is equal to the actual transferred data amount before truncating at least part of the redundant data amount.

[0065] In the data transfer method provided in this embodiment, in order to indicate the redundant data amount 108 that needs to be optimized on the on-chip bus during the data transfer process of the current data packet, the data transfer request sent by the host carries the current data packet and the bypass signal. As additional information, the bypass signal does not affect the transmission logic of the original transmission protocol standard signal, realizing that on the premise of being compatible with the original transmission protocol, the subsequent process of transmitting the current data packet to the slave is dynamically controlled through the bypass signal, and when it is detected that the transferred data amount reaches the optimized data amount, the transmission of the current data packet is terminated in time in advance, reducing the transmission of invalid data forcibly filled by the original transmission protocol, achieving the purpose of reducing downstream bandwidth consumption and significantly improving bandwidth utilization.

[0066] In some embodiments, the optimized data amount is determined based on the difference between the protocol-described data amount and the redundant data amount.

[0067] In this embodiment, since the redundant data amount 108 can be transmitted through the bypass signal, and the redundant data amount 108 is the invalid data amount used to fill the blank, therefore, the actual transferred data amount corresponding to the current data packet is obtained by subtracting the redundant data amount 108 transmitted by the bypass signal from the protocol-described data amount corresponding to the current data packet, and used as the optimized data amount. Specifically, after the host bus interface module obtains the current data packet and the bypass signal sent by the host, during the subsequent data transfer process, the host bus interface module counts the amount of data that has been transferred, and compares the counted transferred data amount with the optimized data amount. If it is detected that the transferred data amount reaches the optimized data amount, it indicates that the subsequent data amount to be transferred is the invalid data forcibly filled by the protocol, and the invalid data forcibly filled by the protocol is no longer needed, so the dynamic truncation of the current data packet transmission process is triggered.

[0068] In the above embodiments, redundant data volume 108 is transmitted through a bypass signal, which is a signal outside the protocol, so that when it is determined that the transmitted data volume meets the actual requirements of data transmission, the transmission process of the current data packet can be stopped in time, thereby avoiding invalid transmission while maintaining the compatibility of the original transmission protocol.

[0069] In some embodiments, as Figure 3 shown, the method further includes steps of determining whether to generate a bypass signal by the following means:

[0070] S310. Determine the actually required data volume, base address offset, and bus data bit width of the on-chip bus corresponding to the current data packet.

[0071] S320. If it is determined that there is redundant data volume to be marked in the protocol description data volume according to the actually required data volume, base address offset, and bus data bit width, generate a bypass signal.

[0072] In this embodiment, the current data packet may be an original transmission request data packet generated based on a transmission protocol such as the AXI protocol, which may include protocol parameters and data payloads required for transmission. The current data packet is generated by the host and is used to describe a complete data transmission task. The current data packet has a base address, burst length, burst size, and data content to be transmitted.

[0073] In this embodiment, the actually required data volume may be the effective data volume actually required to be transmitted at the application layer, excluding invalid data filled due to protocol alignment rules. The actually required data volume can be directly determined by the application task requirements. It can be understood that the actually required data volume can be transmitted to the host address calculation module through the application layer logic or the hardware configuration interface.

[0074] In this embodiment, the base address offset may be the offset of the data start address or the transmission base address relative to the alignment boundary of the bus data bit width. The bus data bit width may be the data capacity transmitted by the on-chip bus at a single time. The protocol description data volume may be the theoretical transmission data volume calculated according to AXI protocol parameters (such as burst length, burst size). The protocol description data volume may include redundant data or invalid data filled due to the misalignment of the total data volume with the bus data bit width.

[0075] Under the AXI protocol framework, the protocol for data transmission describes that the data volume needs to be strictly aligned with the bus data width. When the total data volume is not aligned with the bus data width, the protocol layer will forcibly fill in invalid data to meet the alignment rules, and the invalid data will occupy limited bus resources. Further, although narrowband transmission is adopted in related technologies to improve the forced filling mechanism under the AXI protocol, the narrowband transmission control logic will cause additional overhead, increasing the transmission delay and power consumption. Therefore, in this embodiment, the host address calculation module is responsible for calculating the redundant data volume 108, and a bypass signal is introduced to transmit the redundant data volume 108 to the host bus interface module.

[0076] Specifically, the host address calculation module obtains the actually required data volume, the base address offset, and the bus data width of the on-chip bus. Based on the actually required data volume, the base address offset, and the bus data width, a redundancy judgment is performed to determine whether there is a redundant data volume 108 that needs to be marked in the protocol description data volume. For example, the size relationship between the protocol description data volume and the actually transmitted data volume is determined through the redundancy judgment result. If the protocol description data volume is greater than the actually transmitted data volume, there are redundant invalid data, and a bypass signal needs to be generated. If there is no redundant data volume 108 in the protocol description data volume, there is no need to generate a bypass signal. Exemplarily, it is judged whether the actually required data volume and the base address offset can fill an integer multiple of the bus data width. If they can fill an integer multiple of the bus data width, there are no redundant invalid data. If they cannot fill an integer multiple of the bus data width, there are redundant invalid data.

[0077] In the above embodiment, a bypass signal is generated by the host address calculation module, and the information transfer between the host address calculation module and the host bus interface module is realized through the bypass signal, providing a preparation condition for accurately transmitting the redundant data volume 108 to the host bus interface module. It not only avoids the separation between the protocol layer and the physical layer, and can effectively solve the problem of bandwidth waste caused by the protocol alignment rules in related technologies; but also avoids adopting narrowband transmission and does not introduce additional overhead of narrowband transmission at the host end.

[0078] The embodiment of the present application also provides a method for judging whether there is a redundant data volume 108 in the protocol description data volume. As Figure 4 shown, the judgment method includes the following steps:

[0079] S410. Determine the first multiple between the actually required data volume and the preset data granularity, the second multiple between the base address offset and the preset data granularity, and the third multiple between the bus data width of the on-chip bus and the preset data granularity.

[0080] S420. According to the arithmetic operation results of the first multiple, the second multiple, and the third multiple, judge whether there is a redundant data volume in the protocol description data volume.

[0081] In this embodiment, the preset data granularity may be the minimum logical unit of data transmission, which is used to quantify the actual effective data volume, the base address offset, and the bus data width. It is defined as the net data volume without protocol control signals (such as addresses and status bits). The preset data granularity may be denoted as N. It should be noted that the preset data granularity may be extended to x×N according to the hardware design requirements. x is a positive integer less than the third multiple.

[0082] In this embodiment, the first multiple may be an integer multiple value obtained by converting the total amount of effective data to be actually transmitted into a unit of the preset data granularity N. The second multiple may be the offset of the data start address relative to the alignment boundary of the bus data width, which is an integer multiple value in units of the preset data granularity N. The third multiple may be the physical transmission capacity of the on-chip bus in integer multiples of the preset data granularity N. Among them, the first multiple may be denoted as b, the second multiple may be denoted as a, and the third multiple may be denoted as M. Since the offset does not exceed the bus data width, the second multiple a is a positive integer less than the third multiple M. Since the actually required data volume needs to be greater than the remaining capacity between the bus data width and the base address offset, the first multiple b is greater than the difference between the third multiple and the second multiple (M - a). It can be understood that the bus data width is expressed as M×N, the actually required data volume is expressed as b×N, and the base address offset is expressed as a×N.

[0083] In some cases, in order to simplify the judgment logic of whether there is redundant data volume 108, the actually required data volume, the base address offset, and the bus data width are uniformly dimensioned according to the preset data granularity. The unit difference is eliminated through multiple conversion, and floating-point operations are avoided. All parameters are positive integers, which are adapted to the low-complexity implementation of the hardware logic.

[0084] Specifically, calculate the first multiple between the actually required data volume and the preset data granularity, calculate the second multiple between the base address offset and the preset data granularity, and calculate the third multiple between the bus data width of the on-chip bus and the preset data granularity. Use the first multiple, the second multiple, and the third multiple for arithmetic operations, and judge whether there is redundant data volume 108 in the protocol description data volume according to the arithmetic operation result.

[0085] In one embodiment, judging whether there is redundant data volume 108 in the protocol description data volume according to the arithmetic operation results of the first multiple, the second multiple, and the third multiple includes: obtaining the summation operation result of the first multiple and the second multiple; taking the modulo of the third multiple according to the summation operation result to obtain the first modulo operation result; if the first modulo operation result is not equal to zero, it is determined that there is redundant data volume 108 in the protocol description data volume.

[0086] Specifically, the following formula is used to determine whether there is redundant data volume 108 in the protocol description data volume:

[0087] y1 = (a + b) % M;

[0088] Among them, y1 is used to represent the result of the first modulo operation, a is used to represent the second multiple, b is used to represent the first multiple, and M is used to represent the third multiple.

[0089] If the result of the first modulo operation y1 is not equal to 0, it is determined that there is redundant data volume 108 in the protocol description data volume. If the result of the first modulo operation y1 is equal to 0, it is determined that there is no redundant data volume 108 in the protocol description data volume. Further, when y1 is not equal to 0, it indicates that the invalid data volume in the last beat of data is equal to (M - y1) × N. Among them, if (M - y1) is denoted as k, then k = [M - (a + b) % M]. The redundant data volume 108 is marked by a bypass signal, and the redundant data volume 108 is equal to k × N.

[0090] Exemplarily, N is equal to 64 bits. If the bus data bit width is 256 bits, then the third multiple M is equal to 4. If the actual data volume to be transmitted is 320 bits, then the first multiple b is equal to 5. If the base address offset is equal to 64 bits, then the second multiple a is equal to 1.

[0091] y1 = (1 + 5) % 4 = 2;

[0092] k = 4 - 2 = 2;

[0093] In this example, y1 is not equal to 0, indicating that the total span of the actual required data volume and the base address offset is not aligned with the bus data bit width. It is determined that there is redundant data volume 108 in the protocol description data volume, and the invalid data volume in the last beat of data is equal to 2N. A bypass signal needs to be generated to optimize the transmission. The redundant data volume 108 is marked by the bypass signal, and the redundant data volume 108 is equal to 2N.

[0094] In another embodiment, according to the arithmetic operation results of the first multiple, the second multiple, and the third multiple, to determine whether there is redundant data volume in the protocol description data volume, including: determining the difference between the third multiple and the second multiple, using the first multiple and this difference for a subtraction operation to obtain the subtraction operation result; taking the modulo of the third multiple according to the subtraction operation result to obtain the second modulo operation result; if the second modulo operation result is not equal to zero, it is determined that there is redundant data volume in the protocol description data volume.

[0095] Specifically, the following formula is used to determine whether there is redundant data volume in the protocol description data volume:

[0096] y2 = [b - (M - a)] % M;

[0097] Among them, y2 is used to represent the result of the second modulo operation, a is used to represent the second multiple, b is used to represent the first multiple, and M is used to represent the third multiple.

[0098] If the result of the second modulo operation y2 is not equal to 0, it is determined that there is redundant data volume in the protocol description data volume. If the result of the second modulo operation y2 is equal to 0, it is determined that there is no redundant data volume in the protocol description data volume. Further, when y2 is not equal to 0, it indicates that the invalid data volume in the last beat of data is equal to (M - y2) × N. Among them, if (M - y2) is denoted as k, then k = {M - [b - (M - a)] % M}. The redundant data volume 108 is marked by a bypass signal, and the redundant data volume 108 is equal to k × N.

[0099] Exemplarily, N is equal to 64 bits. If the bus data bit width is 256 bits, then the third multiple M is equal to 4. If the actual data volume to be transmitted is 320 bits, then the first multiple b is equal to 5. If the base address offset is equal to 64 bits, then the second multiple a is equal to 1.

[0100] y2 = [5 - (4 - 1)] % 4 = 2;

[0101] k = 4 - 2 = 2;

[0102] In this example, y2 is not equal to 0, indicating that the total span of the actual required data volume and the base address offset is not aligned with the bus data bit width. It is determined that there is redundant data volume in the protocol description data volume, and the invalid data volume in the last beat of data is equal to 2N. A bypass signal needs to be generated to optimize the transmission. The redundant data volume 108 is marked by the bypass signal, and the redundant data volume 108 is equal to 2N.

[0103] In some embodiments, the preset data granularity is X times the basic data granularity; the basic data granularity is related to the interface bit width of the slave device, and X is a positive integer less than the third multiple.

[0104] Among them, the preset data granularity can be the smallest logical unit of data transmission, used to quantify the actual effective data volume, the base address offset, and the bus data bit width. The basic data granularity can be a reference data unit directly related to the slave device bit width, used to define the extended basis of the preset data granularity. The basic data granularity needs to be strictly aligned with the physical design parameters of the slave device to ensure the compatibility of data reception and processing. X refers to the expansion multiple between the preset data granularity and the basic data granularity, and its value range is a positive integer less than the third multiple M. Exemplarily, if the third multiple M is equal to 4 (the bus data bit width is 4N), then X can be set to 1, 2, or 3. For example, when the basic data granularity is 64 bits and X = 2, the preset data granularity N = 128 bits.

[0105] In the above embodiments, the preset data granularity is dynamically adjusted according to the slave bit width to adapt to different hardware scenarios. X must be less than the third multiple to ensure that the expansion of the preset data granularity is within the controllable range of the bus data bit width. By adjusting the preset data granularity, different slave interface bit widths can be flexibly adapted while maintaining the efficient utilization of the bus.

[0106] It should be noted that the basic data granularity is denoted as n. When the preset data granularity adopts the basic data granularity n, the calculation formulas in the above embodiments can remain unchanged. If the preset data granularity is expanded to X×n, a in the calculation formulas in the above embodiments can be correspondingly replaced by a / X, b can be correspondingly replaced by b / X, k can be correspondingly replaced by k / X, and M can be correspondingly replaced by M / X, where a / X, b / X, k / X, and M / X are positive integers.

[0107] In some embodiments, the optimized data volume is determined in the following manner: the bypass signal is parsed to obtain the redundant data volume; the burst parameters in the current data packet are parsed to calculate the data volume to be transmitted that conforms to the transmission protocol regulations, and the protocol description data volume is obtained; the redundant data volume is subtracted from the protocol description data volume to obtain the optimized data volume.

[0108] In this embodiment, the transmission protocol is described by taking the AXI protocol as an example. The bypass signal can be a signal outside the protocol generated by the host address calculation module for transmitting the redundant data volume 108 that needs to be reduced to the subsequent host bus interface module. The burst parameters can be the transmission control parameters defined in the AXI protocol, including the burst length and the burst size. It should be noted that the burst parameters determine the calculation rule of the protocol description data volume.

[0109] Specifically, by parsing the bypass signal, the optimizable redundant data volume 108 calculated by the host address calculation module is extracted, providing a basis for the control of the subsequent transmission process. By parsing the burst parameters in the current data packet, the complete transmission volume specified by the protocol is obtained as the basis for the optimization calculation, which can ensure protocol compatibility and avoid modifying the AXI standard parameters. The optimized data volume is obtained through the difference calculation between the protocol description data volume and the redundant data volume 108.

[0110] In the above embodiments, the host bus interface module parses the bypass signal and the current data packet to determine the optimized data volume to guide the physical layer to transmit on demand, thereby reducing the transmission of the redundant data volume 108 and improving the bandwidth utilization rate.

[0111] In some embodiments, as Figure 5 shown, when transmitting the current data packet to the slave, if it is detected that the transmitted data volume reaches the optimized data volume, terminating the transmission of the current data packet may include the following steps:

[0112] S510. Split the current data packet according to a preset data granularity to obtain multiple sub - data packets.

[0113] S520. Send the sub - data packets to the slave through the on - chip bus and count the amount of data transmitted in real time.

[0114] S530. If the counting result indicates that the amount of data transmitted has reached the optimized amount of data, terminate the transmission of the current data packet.

[0115] In this embodiment, the preset data granularity is denoted as N. The preset data granularity can be the minimum logical unit of data transmission, which is used as a reference value for quantifying data splitting, transmission, and measurement. It is defined as the net data volume without protocol control signals. The on - chip bus can be the physical data transmission channel connecting the host and the slave inside the system - on - a - chip (SoC). Its bit width is determined by the hardware design parameters. The on - chip bus follows the AXI protocol standard and supports the burst transmission mode. It should be noted that the on - chip bus only carries valid data, that is, the optimized amount of data, during the transmission process, and the redundant data volume indicated by the bypass signal 108 has been dynamically truncated.

[0116] Specifically, the host bus interface module, as the middle between the on - chip bus and the host, receives the current data packet and caches it internally. Parse the current data packet, split the current data packet according to the preset data granularity N, package and send the data to the on - chip bus. Dynamically send sub - data packets to the slave through the on - chip bus and count in real time to determine the amount of data transmitted, providing a basis for early termination of transmission. When the amount of data transmitted reaches the optimized amount of data, end the transmission of the current data packet to avoid redundant data occupying the bandwidth.

[0117] In one embodiment, if the counting result indicates that the amount of data transmitted has reached the optimized amount of data, send a packet end signal to the slave in advance. Specifically, the bus host interface module statistically counts the number of sub - data packets sent in real time and converts it into an accumulated value in units of the preset data granularity N. When this value is equal to the optimized amount of data, the termination condition is triggered. When the bus host interface module detects that the termination condition is met, it immediately sets the packet end signal defined by the transmission protocol to notify the slave that the transmission of the current data packet has ended. For example, set the LAST signal defined by the AXI protocol. The packet end signal is set during the transmission of the last valid sub - data packet. This embodiment can maintain AXI protocol compatibility without modifying the slave hardware logic. Or rather, by setting the signal representing the last beat of data of the current data packet in the protocol and not transmitting the remaining data of the same data packet to the downstream, the purpose of stopping data transmission is achieved.

[0118] Further, the slave receives the sub-packet transmitted on the on-chip bus and caches it until the end-of-packet signal is obtained. The slave returns an acknowledgement signal to the on-chip bus. The on-chip bus returns this acknowledgement signal to the host. The host receives the acknowledgement signal sent by the slave and ends the transmission of the current data packet. Specifically, after detecting the end-of-packet signal, the slave returns an acknowledgement signal (such as the BVALID or RVALID signal of AXI) to the host through the on-chip bus. The acknowledgement signal is returned through the on-chip bus and forwarded to the host to inform that the slave has successfully received and cached the optimized data volume. The completion of the transmission is confirmed through the handshake signal to synchronize the states of the host and the slave. The bus resources are released and the counter is reset by terminating the transmission task to prepare for the next transmission task. It can be understood that the interaction between the end-of-packet signal and the acknowledgement signal conforms to the AXI standard, and the optimization logic is transparent to the downstream slaves and does not need to be perceived.

[0119] According to an embodiment of the present application, there is also provided an embodiment of a data transmission device, as Figure 6 shown. The data transmission device 600 includes a host bus interface module 610. The host bus interface module 610 is configured to receive a data transmission request sent by the host, transmit the current data packet carried in the data transmission request to the slave, and terminate the transmission of the current data packet if it is detected that the amount of data already transmitted reaches the optimized data volume; wherein, the data transmission request also carries a bypass signal, and the bypass signal is used to indicate the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission process of the current data packet, and the optimized data volume is calculated based on the protocol description data volume and the redundant data volume corresponding to the current data packet.

[0120] In some embodiments, as Figure 7 shown, the data transmission device 600 further includes a host address calculation module 710 connected to the host bus interface module 610. The host address calculation module is configured to generate a bypass signal when it is determined that there is redundant data volume that needs to be marked in the protocol description data volume according to the actually required data volume, base address offset, and bus data width of the on-chip bus corresponding to the current data packet.

[0121] The further functional descriptions of the above respective modules are the same as those in the corresponding above embodiments and will not be elaborated herein.

[0122] The data transmission device in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0123] According to an embodiment of the present application, there is also provided a system-on-chip. As Figure 8As shown in the figure, the system-on-chip includes a host 810, an on-chip bus 820, and a slave 830. The host 810 is connected to the slave 830 through the on-chip bus 820. The host 810 is coupled to the host bus interface of the on-chip bus 820, and the slave 830 is coupled to the slave bus interface of the on-chip bus 820. The on-chip bus 820 is used to implement the data transmission method in any one of the above embodiments.

[0124] According to an embodiment of the present application, there is also provided a computing device, which includes a processor and a memory. Computer-executable instructions are stored in the memory, and when these computer-executable instructions are executed by the processor, the data transmission method provided in at least one embodiment of the present disclosure is implemented. Figure 9 The following is a schematic block diagram of an electronic device. As Figure 9 shown, the electronic device 900 includes a processor 910 and a memory 920. The memory 920 is used to store computer-executable instructions (such as one or more computer program modules). The processor 910 is used to run the computer-executable instructions, and when the computer-executable instructions are run by the processor 910, one or more steps in the method described above can be executed. The memory 920 and the processor 910 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0125] For example, the processor 910 can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) can be of CISC or RISC architecture, such as X86 or ARM architecture, etc. The processor 910 can be a general-purpose processor or a special-purpose processor, and can control other components in the electronic device 900 to perform desired functions.

[0126] For example, the memory 920 can include any combination of one or more computer program products. The computer program products can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory can include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules can be stored on the computer-readable storage media, and the processor 910 can run one or more computer program modules to implement various functions of the electronic device 900. Various application programs and various data, as well as various data used and / or generated by the application programs, can also be stored in the computer-readable storage media.

[0127] The embodiments of the present application also provide a computer-readable storage medium. The methods according to the embodiments of the present application can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the methods described herein can be stored in such software processes on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0128] The embodiments of the present application provide a computer program product. The computer program product includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods of any embodiment of the present application.

[0129] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations all fall within the scope defined by the appended claims.

[0130] The systems, devices, modules, or units illustrated in the above embodiments can be specifically implemented by a computer chip or an entity, or by a product with a certain function. For the convenience of description, when describing the above devices, they are described as various units according to functions. Of course, when implementing the present application, the functions of each unit can be implemented in one or more software and / or hardware.

[0131] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0132] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing devices to generate a machine, such that the instructions executed by the processors of the computer or other programmable data processing devices produce means for implementing the functions specified in a flow or flows in the flowchart and / or one or more blocks in the block diagram.

[0133] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufacture including instruction means for implementing the functions specified in a flow or flows in the flowchart and / or one or more blocks in the block diagram.

[0134] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in a flow or flows in the flowchart and / or one or more blocks in the block diagram.

[0135] It should also be noted that the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, commodity, or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, commodity, or device including the said element.

[0136] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, they are described relatively simply, and the relevant parts can be referred to the description of the method embodiments.

[0137] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and variations can be made to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

[0138] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A data transmission method, characterized in that, The method includes: Receiving a data transmission request sent by a host; wherein, the data transmission request carries a current data packet and a bypass signal, and the bypass signal is used to prompt the amount of redundant data that needs to be optimized on the on-chip bus during the data transmission process of the current data packet; the amount of redundant data is at least part of the invalid data block utilized to make the total data transmission amount completely fill an integer multiple of the bus data width; Transmitting the current data packet to a slave, and terminating the transmission of the current data packet if it is detected that the amount of transmitted data reaches the optimized data amount; wherein, the optimized data amount is calculated based on the protocol description data amount corresponding to the current data packet and the amount of redundant data.

2. The method according to claim 1, characterized in that The optimized data amount is determined based on the difference between the protocol description data amount and the amount of redundant data.

3. The method according to claim 1, wherein The method further includes Judging whether to generate the bypass signal in the following manner: Determining the actually required data amount, base address offset corresponding to the current data packet, and the bus data width of the on-chip bus; If it is determined that there is the amount of redundant data to be marked in the protocol description data amount according to the actually required data amount, the base address offset, and the bus data width, generating the bypass signal.

4. The method according to claim 3, wherein The determining that there is the amount of redundant data to be marked in the protocol description data amount according to the actually required data amount, the base address offset, and the bus data width includes: Determining a first multiple between the actually required data amount and a preset data granularity, a second multiple between the base address offset and the preset data granularity, and a third multiple between the bus data width of the on-chip bus and the preset data granularity; Judging whether there is the amount of redundant data in the protocol description data amount according to the arithmetic operation result of the first multiple, the second multiple, and the third multiple.

5. The method according to claim 4, wherein The judging whether there is the amount of redundant data in the protocol description data amount according to the arithmetic operation result of the first multiple, the second multiple, and the third multiple includes: Obtaining the summation operation result of the first multiple and the second multiple; Taking the modulo of the third multiple according to the summation operation result to obtain a first modulo operation result; If the first modulo operation result is not equal to zero, determining that there is the amount of redundant data in the protocol description data amount.

6. The method according to claim 4, characterized in that The judging whether there is the amount of redundant data in the protocol description data amount according to the arithmetic operation result of the first multiple, the second multiple, and the third multiple includes: Determining the difference between the third multiple and the second multiple; Performing a subtraction operation using the first multiple and the difference to obtain a subtraction operation result; Taking the modulo of the third multiple according to the subtraction operation result to obtain a second modulo operation result; If the second modulo operation result is not equal to zero, determining that there is the amount of redundant data in the protocol description data amount.

7. The method according to claim 4, wherein The second multiple is a positive integer less than the third multiple; The first multiple is greater than the difference between the third multiple and the second multiple.

8. The method according to claim 4, wherein The preset data granularity is X times the basic data granularity; The basic data granularity is related to the interface bit width of the slave device, and X is a positive integer less than the third multiple.

9. The method according to any one of claims 1 to 8, characterized in that, The optimized data volume is determined by the following method: Analyze the bypass signal to obtain the redundant data volume; Analyze the burst parameters in the current data packet, calculate the data volume to be transmitted that complies with the transmission protocol regulations, and obtain the protocol description data volume; Subtract the redundant data volume from the protocol description data volume to obtain the optimized data volume.

10. The method according to any one of claims 1 to 8, characterized in that, When transmitting the current data packet to the slave device, if it is detected that the transmitted data volume reaches the optimized data volume, terminate the transmission of the current data packet, including: Split the current data packet according to a preset data granularity to obtain a plurality of sub-data packets; Send the sub-data packets to the slave device through the on-chip bus and count the transmitted data volume in real time; If the counting result indicates that the transmitted data volume reaches the optimized data volume, terminate the transmission of the current data packet.

11. The method according to claim 10, wherein When the counting result indicates that the transmitted data volume reaches the optimized data volume, terminate the transmission of the current data packet, including: If the counting result indicates that the transmitted data volume reaches the optimized data volume, send an end-of-packet signal to the slave device.

12. A data transmission device, characterized in that, The device includes: A host bus interface module, configured to receive a data transmission request sent by a host, transmit the current data packet carried by the data transmission request to a slave device, and terminate the transmission of the current data packet if it is detected that the transmitted data volume reaches the optimized data volume; wherein, the data transmission request also carries a bypass signal, and the bypass signal is used to prompt the redundant data volume that needs to be optimized on the on-chip bus during the data transmission process of the current data packet. The redundant data volume is at least part of the invalid data block used to make the total data transmission volume completely fill an integer multiple of the bus data bit width. The optimized data volume is calculated based on the protocol description data volume corresponding to the current data packet and the redundant data volume.

13. The device according to claim 12, wherein The device further includes a host address calculation module connected to the host bus interface module; The host address calculation module is configured to generate the bypass signal when it is determined that there is redundant data volume to be marked in the protocol description data volume according to the actually required data volume, base address offset corresponding to the current data packet, and the bus data bit width of the on-chip bus.

14. A system on a chip, characterized in that, It includes a host, an on-chip bus, and a slave device; the host is connected to the slave device through the on-chip bus; The on-chip bus is used to implement the data transmission method according to any one of claims 1 to 11.

15. A computer-readable storage medium, characterized in that, A computer-readable storage medium stores computer instructions, and the computer instructions are used to cause a computer to execute the data transmission method according to any one of claims 1 to 11.

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