Pulse coding method for calculation in SRAM (Static Random Access Memory) memory
Through Poisson encoding and random abandonment algorithms to process pulse signals, the problems of crosstalk, reduced accuracy and high power consumption in traditional SRAM in-memory computing are solved, and more stable and efficient in-memory computing is achieved.
Patent Information
- Application Number
- CN202411947364.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-18
AI Technical Summary
In traditional SRAM in-memory computing, multiple pulse inputs act on the SRAM array at the same time, crosstalk, reduced calculation accuracy, noise influence and excessive power consumption are caused.
The original input data is encoded by the Poisson encoding method, and the pulse signal is repeated by randomly discarding the algorithm to ensure that at most one pulse signal is input to the SRAM memory unit at each moment.
It effectively reduces noise interference and power consumption, improves the stability and calculation accuracy of SRAM in-memory computing, and avoids crosstalk.
Smart Images
Figure CN119847981A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a pulse encoding method for improving the calculation stability in a SRAM memory. Background Art
[0002] With the development of artificial intelligence and machine learning, computing demands are growing in computing-intensive tasks such as deep neural networks. In-memory computing combines data storage and computing in the same storage unit, effectively reducing the latency and energy consumption of data transmission, and is particularly suitable for neural network computing tasks. Among the many storage media, SRAM (static random access memory) has become a common choice in in-memory computing due to its high-speed access and low power consumption.
[0003] Traditional SRAM cells usually store information through binary coding and use bit-level operations for calculations. Traditional encoding methods may generate multiple pulse inputs at the same time, which usually causes multiple rows of the SRAM array to be turned on at the same time, thereby causing mutual crosstalk between different storage cells or arrays. This crosstalk phenomenon may not only cause the data values stored in the SRAM to be overwritten or destroyed, but may also cause deviations in the calculation results, affecting the calculation accuracy and stability. In addition, when multiple pulse inputs act on the SRAM array at the same time, a low-resistance path may be formed in the array, resulting in unnecessary current flow. The existence of a low-resistance path not only increases power consumption, but may also cause heat accumulation, affecting the thermal stability of the system and the reliability of long-term operation. Traditional encoding methods. The problems of reduced calculation accuracy, noise influence, hardware instability, etc. in traditional SRAM encoding methods limit its performance and application scope. Summary of the invention
[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a pulse encoding method for SRAM in-memory calculation, which solves the problems of insufficient stability and excessive power consumption of SRAM in-memory calculation.
[0005] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is:
[0006] The present invention provides a pulse encoding method for SRAM in-memory calculation, comprising the following steps:
[0007] S1, perform Poisson coding on the original input data to obtain pulse coding;
[0008] S2, according to the random discard algorithm, based on the pulse code, the pulse signal at each moment is deduplicated to obtain a deduplicated pulse code;
[0009] S3. Input the de-duplicated pulse code into the LIF neuron for calculation and processing, and obtain the calculation result in the SRAM memory.
[0010] Furthermore, the S1 comprises the following steps:
[0011] S11, obtaining original input data;
[0012] S12, normalize the original input data to obtain normalized data:
[0013]
[0014] Among them, X norm represents normalized data, x represents the original input data, min(x) represents the minimum value of the original input data, and max(x) represents the maximum value of the original input data;
[0015] S13. Based on the normalized data, generate the corresponding Poisson distribution event probability:
[0016] λ=k·X norm ,
[0017] Among them, λ represents the event probability of Poisson distribution, and k represents the amplification factor;
[0018] S14, according to the event probability of Poisson distribution, based on the probability mass model of Poisson distribution, a pulse event is generated in each clock cycle t;
[0019] S15. According to the generated pulse event, the corresponding pulse signal is converted into a binary code sequence to obtain a pulse code, wherein if a pulse event occurs at a certain moment in the clock cycle, the pulse signal at that moment is 1, otherwise the pulse signal at that moment is 0.
[0020] Furthermore, the calculation expression of the probability mass model of the Poisson distribution in S14 is as follows:
[0021]
[0022] Where P(k;λ) represents the probability of k events occurring within a clock cycle, e represents the exponential base constant, and k! represents the factorial of the amplification factor.
[0023] Furthermore, the S2 comprises the following steps:
[0024] S21, according to the pulse coding, construct the pulse signal input set {s 1 ,s 2 ,...,s n}, where s 1 Indicates the first pulse signal, s 2 Indicates the second pulse signal, s n represents the nth pulse signal, where n is a positive integer;
[0025] S22, determining whether the number of pulse signals in the pulse signal input set is greater than 1, if so, using a random number generator rand(1,n) to select any integer between 1 and n, generating a random index i, and deleting the remaining pulse signals in the pulse signal input set except the i-th pulse signal;
[0026] S23, executing S22 in sequence on the pulse signal input sets at each time corresponding to the pulse code, until the pulse signal input sets at all times are executed, thereby obtaining a de-duplicated pulse code.
[0027] Furthermore, S3 comprises the following steps:
[0028] S31, inputting the pulse sequence signal corresponding to the de-repeated pulse code into the SRAM storage unit through N word lines, wherein each word line is an independent input channel;
[0029] S32, if the pulse train signal reaches the SRAM storage unit through the word line, then the synaptic weight value of the corresponding input channel stored in the SRAM storage unit is multiplied with the pulse train signal, and the operation result is output to the LIF neuron in the form of current;
[0030] S33, using LIF neurons to receive the current output by all SRAM storage cells, and performing time integration on the received current to obtain an accumulated current value;
[0031] S34, if the accumulated current value is less than the preset current threshold, the LIF neuron is not activated, so that the LIF neuron remains in a resting state;
[0032] S35. If the accumulated current value is greater than or equal to the preset current threshold, the LIF neuron is activated, so that the LIF neuron enters an excited state and generates an output pulse signal as a calculation result stored in the SRAM.
[0033] The beneficial effects of the present invention are as follows: a pulse encoding method for SRAM in-memory calculation provided by the present invention, according to the characteristics of Poisson distribution, represents the information in the original input data by encoding the probability of pulses, effectively reduces noise interference, thereby providing a basis for reducing interference and power consumption when the SRAM in-memory medium performs in-memory calculation; the present invention also introduces a random discard algorithm to process the situation of multiple pulses at the same time, and only retains one pulse signal among multiple pulse signals, thereby ensuring that at most only one pulse signal is retained at the same time, effectively improving the stability of in-memory calculation, and further reducing the interference and power consumption of SRAM in-memory calculation; based on the encoding method provided by the method of the present invention, there will be no mutual crosstalk between SRAM storage units, effectively improving the stability of SRAM in-memory calculation, ensuring that at most only one SRAM corresponding to a word line is turned on at each moment, and effectively reducing the overall power consumption of the SRAM in-memory calculation system.
[0034] Other advantages of the present invention will be analyzed in more detail in subsequent embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0036] Figure 1 The present invention is a flowchart of a pulse encoding method for SRAM memory calculation in an embodiment of the present invention.
[0037] Figure 2 Schematic diagram of SRAM in-memory calculation in an embodiment of the present invention.
[0038] Figure 3 This is a waveform comparison diagram corresponding to the encoding method in the embodiment of the present invention. DETAILED DESCRIPTION
[0039] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.
[0040] like Figure 1 As shown, in one embodiment of the present invention, the present invention provides a pulse encoding method for SRAM in-memory calculation, comprising the following steps:
[0041] S1, perform Poisson coding on the original input data to obtain pulse coding;
[0042] The S1 comprises the following steps:
[0043] S11, obtaining original input data;
[0044] S12, normalize the original input data to obtain normalized data:
[0045]
[0046] Among them, X norm represents normalized data, x represents the original input data, min(x) represents the minimum value of the original input data, and max(x) represents the maximum value of the original input data;
[0047] S13. Based on the normalized data, generate the corresponding Poisson distribution event probability:
[0048] λ=k·X norm ,
[0049] Wherein, λ represents the event probability of Poisson distribution, and k represents the amplification factor; in this scheme, the amplification factor k is used to adjust the dynamic range of Poisson distribution.
[0050] S14, according to the event probability of Poisson distribution, based on the probability mass model of Poisson distribution, a pulse event is generated in each clock cycle t;
[0051] The calculation expression of the probability mass model of the Poisson distribution in S14 is as follows:
[0052]
[0053] Where P(k;λ) represents the probability of k events occurring within a clock cycle, e represents the exponential base constant, and k! represents the factorial of the amplification factor.
[0054] S15. According to the generated pulse event, the corresponding pulse signal is converted into a binary code sequence to obtain a pulse code, wherein if a pulse event occurs at a certain moment in the clock cycle, the pulse signal at that moment is 1, otherwise the pulse signal at that moment is 0.
[0055] S2, according to the random discard algorithm, based on the pulse code, the pulse signal at each moment is deduplicated to obtain a deduplicated pulse code;
[0056] The S2 comprises the following steps:
[0057] S21, according to the pulse coding, construct the pulse signal input set {s 1 ,s 2 ,...,s n}, where s 1 Indicates the first pulse signal, s 2 Indicates the second pulse signal, s n represents the nth pulse signal, where n is a positive integer;
[0058] S22, determining whether the number of pulse signals in the pulse signal input set is greater than 1, if so, using a random number generator rand(1,n) to select any integer between 1 and n, generating a random index i, and deleting the remaining pulse signals in the pulse signal input set except the i-th pulse signal;
[0059] S23, executing S22 in sequence on the pulse signal input sets at each time corresponding to the pulse code, until the pulse signal input sets at all times are executed, thereby obtaining a de-duplicated pulse code.
[0060] S3. Input the de-duplicated pulse code into the LIF neuron for calculation and processing, and obtain the calculation result in the SRAM memory.
[0061] like Figure 2 As shown, the pulse neural network with in-memory computing architecture provided by this embodiment has N word lines, and each word line is connected in parallel with a corresponding SRAM storage unit, which is finally merged into the LIF element. After the pulse sequence signal corresponding to the de-duplicated pulse is input into the pulse neural network, the LIF element outputs the SRAM in-memory calculation result.
[0062] The S3 comprises the following steps:
[0063] S31, inputting the pulse sequence signal corresponding to the de-repeated pulse code into the SRAM storage unit through N word lines, wherein each word line is an independent input channel;
[0064] S32, if the pulse train signal reaches the SRAM storage unit through the word line, then the synaptic weight value of the corresponding input channel stored in the SRAM storage unit is multiplied with the pulse train signal, and the operation result is output to the LIF neuron in the form of current;
[0065] S33, using LIF neurons to receive the current output by all SRAM storage cells, and performing time integration on the received current to obtain an accumulated current value;
[0066] S34, if the accumulated current value is less than the preset current threshold, the LIF neuron is not activated, so that the LIF neuron remains in a resting state;
[0067] S35. If the accumulated current value is greater than or equal to the preset current threshold, the LIF neuron is activated, so that the LIF neuron enters an excited state and generates an output pulse signal as a calculation result stored in the SRAM.
[0068] In the traditional SRAM in-memory calculation process, the simultaneous conduction of multiple rows of word lines will cause current crosstalk between the rows, resulting in a decrease in calculation accuracy. At the same time, the simultaneous conduction of multiple rows will also cause large static power consumption, and as the number of rows turned on at the same time increases, the power consumption problem becomes more significant. This crosstalk and power consumption problem limits the practicality and reliability of in-memory calculations in large-scale neural network applications. Through the present invention, after Poisson encoding and deduplication processing of the original input data, it is ensured that at most only one pulse signal is retained at the same time. Based on this mechanism, the stability of in-memory calculations is effectively improved, and interference and power consumption are further reduced.
[0069] like Figure 3As shown, the waveforms of the traditional encoding method for SRAM in-memory calculation and the encoding method of the present invention are compared, wherein the synaptic weight values corresponding to the input X0 of the 0th in-memory calculation and the input X1 of the 1st in-memory calculation are both 1, and the synaptic weight value corresponding to the input XN of the Nth in-memory calculation is 0. It can be found that at the moment P1, the input X1 of the 1st in-memory calculation and the input XN of the Nth in-memory calculation have pulse signals at the same time, that is, there are multiple pulse signals at the same time. For the traditional encoding method, the presence of multiple pulse signals at the same time may cause the 1st word line WL1 and the Nth word line WLN to be turned on at the same time, that is, multiple rows of word lines are turned on at the same time at P1, and the in-memory calculation is a sum of one positive and one negative, which leads to crosstalk between the SRAM in-memory units, the SRAM value is overwritten, and the bit line BL signal is interfered. At moment P2, the input X0 of the 0th in-memory calculation and the input X1 of the 1st in-memory calculation simultaneously have pulse signals. For the traditional encoding method, there are multiple pulse signals at the same time, and the in-memory calculation is the sum of two positives, which will cause a low-resistance path between the SRAM memory cells. Because the bit line BL signal drop rate is proportional to the number of pulse signals, it will cause a significant increase in system power consumption. Different from the traditional encoding method, the encoding method provided by the present invention ensures that there is at most one pulse signal at each moment after Poisson coding and de-duplication coding processing, which prevents mutual crosstalk between SRAM memory cells and improves the stability of SRAM memory calculation.
[0070] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.
Claims
1. A pulse encoding method for SRAM in-memory calculation, characterized in that: The steps include: S1, perform Poisson coding on the original input data to obtain pulse coding; S2, according to the random discard algorithm, based on the pulse code, the pulse signal at each moment is deduplicated to obtain a deduplicated pulse code; S3. Input the de-duplicated pulse code into the LIF neuron for calculation and processing, and obtain the calculation result in the SRAM memory.
2. The pulse encoding method for SRAM in-memory calculation according to claim 1, characterized in that: The S1 comprises the following steps: S11, obtaining original input data; S12, normalize the original input data to obtain normalized data: Among them, X norm represents normalized data, x represents the original input data, min(x) represents the minimum value of the original input data, and max(x) represents the maximum value of the original input data; S13. Based on the normalized data, generate the corresponding Poisson distribution event probability: λ=k·X norm , Among them, λ represents the event probability of Poisson distribution, and k represents the amplification factor; S14, according to the event probability of Poisson distribution, based on the probability mass model of Poisson distribution, a pulse event is generated in each clock cycle t; S15. According to the generated pulse event, the corresponding pulse signal is converted into a binary code sequence to obtain a pulse code, wherein if a pulse event occurs at a certain moment in the clock cycle, the pulse signal at that moment is 1, otherwise the pulse signal at that moment is 0.
3. The pulse encoding method for SRAM in-memory calculation according to claim 2, characterized in that: The calculation expression of the probability mass model of the Poisson distribution in S14 is as follows: Where P(k;λ) represents the probability of k events occurring within a clock cycle, e represents the exponential base constant, and k! represents the factorial of the amplification factor.
4. The pulse encoding method for SRAM in-memory calculation according to claim 2, characterized in that: The S2 comprises the following steps: S21, according to the pulse coding, construct the pulse signal input sets {s1, s2, ..., s n }, where s1 represents the first pulse signal, s2 represents the second pulse signal, and s n represents the nth pulse signal, where n is a positive integer; S22, determining whether the number of pulse signals in the pulse signal input set is greater than 1, if so, using a random number generator rand(1,n) to select any integer between 1 and n, generating a random index i, and deleting the remaining pulse signals in the pulse signal input set except the i-th pulse signal; S23, executing S22 in sequence on the pulse signal input sets at each time corresponding to the pulse code, until the pulse signal input sets at all times are executed, thereby obtaining a de-duplicated pulse code.
5. The pulse encoding method for SRAM in-memory calculation according to claim 4, characterized in that: The S3 comprises the following steps: S31, inputting the pulse sequence signal corresponding to the de-repeated pulse code into the SRAM storage unit through N word lines, wherein each word line is an independent input channel; S32, if the pulse train signal reaches the SRAM storage unit through the word line, then the synaptic weight value of the corresponding input channel stored in the SRAM storage unit is multiplied with the pulse train signal, and the operation result is output to the LIF neuron in the form of current; S33, using LIF neurons to receive the current output by all SRAM storage cells, and performing time integration on the received current to obtain an accumulated current value; S34, if the accumulated current value is less than the preset current threshold, the LIF neuron is not activated, so that the LIF neuron remains in a resting state; S35. If the accumulated current value is greater than or equal to the preset current threshold, the LIF neuron is activated, so that the LIF neuron enters an excited state and generates an output pulse signal as a calculation result stored in the SRAM.