In-memory computing architecture and operating policy thereof

Abstract

The present disclosure relates to an in-memory computing architecture and an operation strategy thereof, the in-memory computing architecture comprising: a memory array comprising a memory string, a source line, a word line, and a bit line; the storage string comprises a plurality of storage units which are connected in series along a first direction, each storage unit comprises a storage transistor and a bypass resistor which are connected in parallel, the storage string is connected with a source line through a lower gate tube and is connected with a bit line through an upper gate tube, and a control end of each storage unit is connected with a word line; the driving and detecting circuit is connected with the source line, and the driving and detecting circuit is configured to inject reading current into the source line and detect and output a voltage signal of the source line; and a peripheral circuit connected to the word line and the bit line, the peripheral circuit configured to control voltages of the word line and the bit line. According to the technical scheme, the framework of the storage array can be used for executing the calculation task, the multiple storage strings can be operated in parallel, the voltage change of the source line corresponding to each storage unit is detected, the calculation result is read out from the source line, and high calculation efficiency is achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to an in-memory computing architecture and its operation strategy. Background Art

[0002] NAND Flash (‌Not AND Flash, NAND) is a non-volatile memory. NAND Flash memory has the advantages of high storage density, low cost, long life and low power consumption. It is widely used in solid-state drives, mobile flash drives (USB flashdisk), memory cards and embedded systems.

[0003] Currently, NAND Flash memory improves storage density by vertically stacking and connecting storage cells in series using a vertical method, thereby achieving higher storage density and lower cost. However, the computational parallelism and computational efficiency of NAND Flash memory are very low. How to effectively improve the computational efficiency of NAND Flash is an urgent problem to be solved. Summary of the invention

[0004] Based on this, it is necessary to provide an in-memory computing architecture and its operation strategy to address the problems in the prior art.

[0005] In order to achieve the above objectives, in a first aspect, the present disclosure provides an in-memory computing architecture, including:

[0006] A memory array, the memory array comprising a memory string, a source line, a word line and a bit line; the memory string comprises a plurality of memory cells connected in series along a first direction, the memory cell comprises a memory transistor and a bypass resistor connected in parallel, the memory string is connected to the source line through a lower gate tube, is connected to the bit line through an upper gate tube, and a control end of the memory cell is connected to the word line;

[0007] A driving and detecting circuit connected to the source line, wherein the driving and detecting circuit is configured to inject a read current into the source line, detect and output a voltage signal of the source line;

[0008] The peripheral circuit is connected to the word line and the bit line, and is configured to control the voltages of the word line and the bit line.

[0009] Optionally, the source line is disposed below the storage string, the source line is arranged along a second direction and a third direction perpendicular to the first direction, and the source line is connected to a first end of the lower gate tube of the storage string;

[0010] The word lines are arranged along the first direction, and the word lines are connected to the control terminals of the storage units in the same layer;

[0011] The bit line is disposed above the memory string, the bit line extends along the second direction and is arranged along the third direction, and the bit line is connected to the second end of the upper selection tube of the memory string arranged along the second direction;

[0012] Wherein, the plurality of storage strings arranged along the second direction are respectively connected to the plurality of source lines arranged along the second direction.

[0013] Optionally, a resistance value of the bypass resistor is greater than a channel equivalent resistance when the storage transistor is turned on, and is less than a channel equivalent resistance when the storage transistor is turned off.

[0014] Optionally, along the first direction, the driving and detecting circuit is integrated below the source line, and the peripheral circuit is integrated above the bit line; wherein the driving and detecting circuit includes:

[0015] A current generating circuit, used for generating a reading current;

[0016] a current mirror for replicating the read current and injecting the read current into the source line;

[0017] A source follower, configured to read the voltage signal of the source line;

[0018] The analog-to-digital converter is used for converting the voltage signal into a digital signal and then outputting it.

[0019] Optionally, it also includes:

[0020] A control logic circuit, wherein the control logic circuit is connected to the driving and detecting circuits and the peripheral circuits respectively;

[0021] The control logic circuit is configured to: deploy the weight information to the storage unit according to the weight writing strategy, and represent the weight information with the threshold voltage of the storage unit;

[0022] Applying a read voltage or a turn-on voltage to the word line and inputting a read current to the source line;

[0023] The number of the memory transistors turned off in the memory string is calculated according to the voltage drop generated by the source line, and the calculation result is output.

[0024] In a second aspect, the present disclosure provides an operation strategy of an in-memory computing architecture, including:

[0025] Deploy the weight information to a storage unit according to a weight writing strategy, and represent the weight information with a threshold voltage of the storage unit;

[0026] Applying a read voltage or a turn-on voltage to the word line and inputting a read current to the source line;

[0027] The number of memory transistors turned off in the memory string is calculated according to the voltage drop generated by the source line, and the calculation result is output.

[0028] Optionally, deploying the weight information to a storage unit according to a weight writing strategy, and representing the weight information with a threshold voltage of the storage unit, includes:

[0029] Encode each element of the weight matrix as a binary value weight "1" or weight "0";

[0030] According to the mapping relationship between the weight matrix and the storage cell, a programming voltage or an erasing voltage is applied to the storage cell corresponding to the weight element to adjust the threshold voltage of the storage cell to a high threshold voltage or a low threshold voltage, wherein the high threshold voltage corresponds to a weight of "1" and the low threshold voltage corresponds to a weight of "0".

[0031] Optionally, applying a read voltage or a turn-on voltage to the word line comprises:

[0032] Encode each element of the activation vector as a binary value;

[0033] According to the mapping relationship between the activation vector and the word line, the read voltage is applied to the word line corresponding to the encoded activation value "1", and the turn-on voltage is applied to the word line corresponding to the encoded activation value "0", and the turn-on voltage is greater than the read voltage.

[0034] Optionally, applying a read voltage or a turn-on voltage to the word line and inputting a read current to the source line further comprises:

[0035] The voltage of the word line and the read current are adjusted so that when the storage transistor is turned on, the current of the storage cell flows through the storage transistor, and when the storage transistor is turned off, the current of the storage cell flows through the bypass resistor, generating a voltage drop on both sides of the storage cell.

[0036] Optionally, the calculating the number of the storage transistors turned off in the storage string according to the voltage drop generated by the source line, and outputting the calculation result, comprises:

[0037] Performing a multiplication operation on the weight of the memory cell and the activation value of the word line connected to the memory cell, so that the voltage drop of the memory cell is 1 or 0;

[0038] An addition operation is performed on the voltage drops of the storage cells of the storage string to obtain the number of the storage transistors in the storage string that are turned off.

[0039] The in-memory computing architecture and its operation strategy disclosed in the present invention have the following beneficial effects:

[0040] The in-memory computing architecture disclosed in the present invention integrates a storage array, a driving and detection circuit, and a peripheral circuit, thereby achieving a high degree of integration of data storage and computing. It can process data directly inside the storage array without having to read the data out to an external processor for computing, thereby avoiding delays and energy consumption caused by external data transmission. The in-memory computing architecture of this embodiment can utilize the architecture of the storage array to perform computing tasks, and can perform operations on multiple storage strings in parallel. By detecting the voltage change of the source line corresponding to each storage unit and reading the computing results from the source line, high computing efficiency is achieved.

[0041] The operating strategy of the in-memory computing architecture disclosed in the present invention utilizes the in-memory computing architecture to implement an in-memory computing strategy based on a voltage domain, characterizes weight information by controlling the threshold voltage of the storage unit, and quickly calculates the number of storage transistors that are turned off in the storage string by detecting the voltage drop on the source line. This not only improves computing parallelism and computing efficiency, but also reduces power consumption of data transmission, providing support for computing-intensive applications such as neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 is an architectural diagram of an in-memory computing architecture provided in one embodiment;

[0044] Figure 2 is a circuit diagram of a storage array provided in an embodiment;

[0045] Figure 3 A circuit schematic diagram of a storage array provided in an embodiment;

[0046] Figure 4 is a circuit diagram of a driving and detecting circuit provided in one embodiment;

[0047] Figure 5 A schematic diagram of a process of an operation strategy of an internal computing architecture of a memory provided in an embodiment;

[0048] Figure 6 A circuit diagram of an operation strategy of an in-memory computing architecture provided in one embodiment;

[0049] Figure 7 A schematic diagram of weight coding provided in an embodiment;

[0050] Figure 8The figure is a diagram of the internal structure of an electronic device provided in one embodiment. DETAILED DESCRIPTION

[0051] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0053] Modern computers usually use the von Neumann architecture that separates computing and storage, and data needs to be transferred between the processor and the memory. In recent years, with the rapid development of artificial intelligence, the scale of neural network models has continued to expand. Among them, the large language model (LLM) based on the attention mechanism-based neural network structure (Transformer) often has billions to trillions of parameters, so the computing requirements and data handling needs in the reasoning process have also increased dramatically. At the same time, the demand for deploying large models on end-side devices such as the Artificial Intelligence of Things (AIoT), smartphones, and autonomous driving systems has also continued to grow. Under the conditions of limited end-side storage and computing resources, prominent power consumption constraints, and strict latency requirements, the von Neumann architecture that requires frequent data transmission is inefficient. Existing in-memory computing solutions mostly use storage media such as Resistive Random Access Memory (RRAM) and Static Random-Access Memory (SRAM), but these media have low storage density, limited array size, and high manufacturing costs, which are not suitable for the potential computing needs of large model reasoning on the end side.

[0054] NAND Flash memory has great potential in storing model parameters, providing cheap computing power and saving chip area due to its high storage density, low cost, ultra-large array scale and multi-layer stacking structure. In NAND Flash in-memory computing, the current domain operation strategy is currently mainly used.

[0055] The calculation method of the current domain operation strategy is similar to the operation of NAND Flash in the memory scenario, where the weights are stored in the array, the activation value is input in the form of voltage amplitude, and the multiplication and accumulation result is output in the form of the sum of currents. However, the current domain operation strategy can only open one layer of storage cells at a time for the read operation of NAND Flash, and the massive storage cells cannot be effectively parallelized when performing in-memory calculations. The current mainstream storage and calculation strategy can only use 0.14% to 0.43% of the total number of cells in the array for a single calculation, and the calculation parallelism and efficiency are very low.

[0056] According to an exemplary embodiment, the present disclosure provides an in-memory computing architecture, such as Figure 1 As shown, the in-memory computing architecture includes a storage array 100 , a driving and detecting circuit 200 , and a peripheral circuit 300 .

[0057] like Figure 2 As shown, the memory array 100 includes a memory string Str, a source line SL, a word line WL and a bit line BL; the memory string Str includes a plurality of memory cells TR connected in series along a first direction Y, the memory cell TR includes a memory transistor T and a bypass resistor R connected in parallel, the memory string Str is connected to the source line SL via a lower gate tube BM, the memory string Str is connected to the bit line BL via an upper gate tube TM, each memory string Str can be independently controlled and accessed via the source line SL and the bit line BL, the control end of the memory cell TR (the gate of the memory transistor T) is connected to the word line WL, the switching state of the memory transistor T in the memory cell TR can be controlled by controlling the voltage change of the word line WL, thereby realizing the reading and writing operations of data.

[0058] In this embodiment, each storage string Str includes n storage cells TR (n≥1) vertically stacked along a first direction Z. Along the first direction Z, the storage transistors T of the plurality of storage cells TR are sequentially connected in series along the first direction Z, and the bypass resistors R of the plurality of storage cells TR are sequentially connected in series along the first direction Z. Along a plane perpendicular to the first direction Z, the storage transistor T includes a channel layer, a tunneling layer, a charge trapping layer, a gate dielectric layer, and a control gate that sequentially surround and cover the peripheral surface of the bypass resistor R.

[0059] Along the first direction Z, n word lines WL1-WL n They are arranged at intervals and are respectively connected to the control gates of the n storage transistors T of the storage string Str.

[0060] The driving and detecting circuit 200 is connected to the source line SL, and the driving and detecting circuit 200 is configured to inject a read current I into the source line SL. ref , detect the voltage signal of the source line SL, and convert the output voltage signal into a digital signal before outputting it, thereby improving the efficiency and speed of data processing.

[0061] The peripheral circuit 300 is connected to the word line WL and the bit line BL respectively, and is configured to control the voltage of the word line WL and the bit line BL. The peripheral circuit 300 is used to implement the read and write operations of the memory cell TR and cooperate with the driving and detecting circuit 200 to realize data transmission.

[0062] The in-memory computing architecture of the present embodiment integrates the storage array 100, the driving and detection circuit 200 and the peripheral circuit 300, thereby achieving a high degree of integration of data storage and computing, and can process data directly inside the storage array 100 without reading the data out to an external processor for computing, thereby avoiding delays and energy consumption caused by external data transmission; the in-memory computing architecture of the present embodiment can utilize the architecture of the storage array 100 to perform computing tasks, and can perform operations on multiple storage strings Str in parallel. By detecting the voltage change of the source line SL corresponding to each storage cell TR, the calculation result can be read from the source line, thereby achieving high computing efficiency.

[0063] In some embodiments, Figure 2 , Figure 3 As shown, the source line SL is arranged below the storage string Str, and the source line SL is arranged along the second direction Y and the third direction X which are perpendicular to the first direction Z. The source line SL is connected to the first end of the lower gate tube BM of the storage string Str; in this embodiment, the first end of the lower gate tube BM is the source end of the lower gate tube BM. The second direction Y and the third direction X are located in a plane perpendicular to the first direction Z, and the second direction Y intersects with the third direction X. In this embodiment, the second direction Y is perpendicular to the third direction X. For example, the source line SL is connected to the storage string Str one by one through the lower gate tube BM; or, multiple adjacent storage strings Str are connected to the same source line SL.

[0064] Word lines WL1-WL n They are arranged along a first direction Z, wherein each word line WL is connected to a control terminal of a storage unit TR in the same layer.

[0065] The bit line BL is disposed above the storage string Str, and the bit line BL extends along the second direction Y and is arranged along the third direction X. The bit line BL is connected to the second end of the upper selection tube TM of the storage string Str arranged along the second direction Y; in this embodiment, the second end of the upper selection tube TM is the drain end of the upper selection tube TM.

[0066] In this embodiment, Figure 2 , Figure 3 As shown, the memory array 100 further includes a lower gate line SSL and an upper gate line DSL. The lower gate line SSL is provided on the word lines WL1-WL2. n Below, the lower gate line SSL is connected to the control end of the lower gate tube BM; the upper gate line DSL is set on the word lines WL1-WL nAt the top, the upper gate line DSL is connected to the control terminal of the upper gate transistor TM.

[0067] Among them, Figure 2 , Figure 3 As shown, a plurality of storage strings Str arranged along the second direction Y are respectively connected to a plurality of source lines SL arranged along the second direction Y. In this way, on the one hand, the number of storage strings Str processed by each source line SL can be reduced, and on the other hand, each bit line BL can be connected to a plurality of storage strings Str, and a column of storage strings Str connected to the same bit line BL can be connected to a plurality of source lines SL, and a column of storage strings Str connected to the same bit line BL can be read in parallel, thereby improving the read bandwidth.

[0068] The in-memory computing architecture of the present embodiment arranges the source lines SL along the second direction Y and the third direction X, so that the source lines SL of each storage string Str can be led out separately, so that the in-memory computing architecture supports reading storage information through the source lines SL. Since the source lines SL of each storage block are independent of each other, the storage strings Str in the same column in the storage plane (Plane) have hundreds or thousands of lead-out ports, thereby improving the parallel reading potential.

[0069] In some embodiments, the resistance value R of the bypass resistor R is greater than the channel equivalent resistance R when the storage transistor T is turned on. on , is smaller than the channel equivalent resistance R when the storage transistor T is turned off off .

[0070] The in-memory computing architecture of this embodiment controls the word line voltage V WL and the threshold voltage V of the storage transistor T T The size of the word line voltage V WL >V T When the storage transistor T is turned on, the equivalent resistance of the storage unit TR is approximately equal to the channel equivalent resistance R when the storage transistor T is turned on. on , the current mainly flows through the storage transistor T; when V WL <V T When the storage transistor T is turned off, the equivalent resistance of the storage cell TR is close to the resistance value R of the bypass resistor R, and the current mainly passes through the bypass resistor R. Therefore, whether the storage transistor T is turned on or off, the storage string Str where the storage cell TR is located can always form a current path, so that when a read operation is performed on the storage cell TR of the storage string Str, the number of turned-off transistors in the storage string Str can be calculated according to the voltage drop of the storage string Str.

[0071] In some embodiments, Figure 1 As shown, along the first direction Z, the driving and detecting circuit 200 is integrated below the source line SL, and the peripheral circuit 300 is integrated above the bit line BL.

[0072] In this embodiment, the CUA technology can be used to integrate the driving and detecting circuit 200 under the memory array 100. Vias can be used to achieve electrical connection between the memory array 100 and the driving and detecting circuit 200, ensuring stable transmission of current and voltage signals while maintaining the overall structural compactness and reliability of the in-memory computing architecture.

[0073] In this embodiment, the peripheral circuit 300 can be integrated above the memory array 100 using hybrid bonding technology. The hybrid bonding technology ensures high-precision, high-strength electrical and mechanical connection between the peripheral circuit 300 and the memory array 100, and ensures stable interconnection between the peripheral circuit 300 and the memory array 100.

[0074] The peripheral circuit 300 may include a page buffer, a row decoder, a column decoder, a data write circuit, a read-sensitive amplifier circuit, and a read-write control circuit, etc. The data write circuit is used to implement the writing of weights and the input of activation vectors to the storage array 100 to meet the needs of in-memory computing.

[0075] It should be noted that CUA technology, namely complementary metal oxide semiconductor set under the memory array (CMOS Under Array), is a design method that places most of the peripheral circuits of NAND chips (such as page buffers, read amplifiers, charge pumps, etc.) under the vertical stack of memory cells. This layout greatly saves integration space, allowing more area to be used for the memory cell array, thereby improving storage density and performance.

[0076] In the in-memory computing architecture of this embodiment, the driving and detecting circuit 200 is integrated below the source line SL, and the peripheral circuit 300 is integrated above the bit line BL. The entire architecture is highly integrated, which can improve the performance of the memory, reduce its power consumption and cost, reduce the delay and interference of signal transmission, and improve the read and write speed and reliability of the memory. The peripheral circuit 300 is integrated above the bit line BL, and the peripheral circuit 300 has expansion space, so the memory can flexibly adapt to different application scenarios and performance requirements, such as in-memory computing, high-speed storage, etc.

[0077] In some embodiments, Figure 4 As shown, the driving and detecting circuit 200 includes:

[0078] The current generating circuit 210 is used to generate a read current I ref The current generating circuit 210 generates a constant read current I ref , read the current I ref The stability and accuracy of the sensor are critical to subsequent current replication and voltage reading.

[0079] Current mirror 220, current mirror 220 is used to copy the read current I ref And inject a read current I into the source line SL ref The current mirror 220 in this embodiment is a common-source common-gate current mirror, and the current mirror 220 copies the read current I generated by the current generating circuit 210. ref In this embodiment, in order to save the area and power consumption cost of the driving and detecting circuit 200, the current mirror 220 copies the read current I ref After that, it is injected into multiple source lines SL. On the one hand, the common source and common gate current mirror ensures that the read current I ref The high-precision replication reduces the mismatch error of the current mirror, thereby ensuring that a stable current can be obtained on each source line SL. On the other hand, the output impedance of the common source and common gate current mirror is large, and the driving ability is strong, which can ensure the stable transmission of the current, so that the output read current I ref With high stability and high precision.

[0080] Source follower 230, source follower 230 is used to read the voltage signal of source line SL; source follower 230 is used as a voltage buffer to read the voltage value at the output end of source line SL. Source follower 230 is also used to isolate memory array 100 from analog-to-digital converter 240 to prevent the high impedance inside memory array 100 from interfering with voltage reading.

[0081] It should be noted that the voltage range of the source follower 230 input should match the memory array 100 to avoid a wide range of changes in the source line SL output voltage caused by multiple word lines WL to ensure that the voltage reading is not distorted or saturated. In this embodiment, the source follower 230 uses a rail-to-rail operational amplifier.

[0082] The analog-to-digital converter 240 is used to convert the voltage signal into a digital signal and then output it. The analog-to-digital converter 240 converts the analog voltage signal output by the source follower 230 into a digital signal for subsequent digital signal processing.

[0083] In some embodiments, in order to save area and power consumption of the driving and detecting circuit 200, the source follower 230 and the analog-to-digital converter 240 can be shared by multiple source lines SL. The driving and detecting circuit 200 also includes: a multiplexer MUX, which is used to select the source line SL that needs to be voltage detected to achieve effective resource reuse.

[0084] For example, the analog-to-digital converter 240 is a successive approximation register analog-to-digital converter (SAR ADC).

[0085] The in-memory computing architecture of this embodiment optimizes the driving and detecting circuit 200 so that the driving and detecting circuit 200 can inject a constant read current I into the source line SL. ref And accurately read its voltage, providing a reliable foundation for the voltage domain in-memory computing operations of the in-memory computing architecture, ensuring its effectiveness and reliability in in-memory computing applications.

[0086] In some embodiments, the in-memory computing architecture further includes: Figure 1 As shown, the control logic circuit 400 is connected to the driving and detecting circuit 200 and the peripheral circuit 300 respectively. The control logic circuit 400 is connected to the driving and detecting circuit 200 to receive the digital signal from the driving and detecting circuit 200, and the digital signal reflects the state of the storage cell TR in the storage array 100. The control logic circuit 400 is connected to the peripheral circuit 300, and the control logic circuit 400 controls the voltage of the word line WL and the bit line BL through the peripheral circuit 300, thereby realizing the read and write operation of the storage cell TR.

[0087] The control logic circuit 400 is configured to: deploy the weight information to the storage cell TR according to the weight writing strategy, and represent the weight information with the threshold voltage of the storage cell TR. For example, different threshold voltages can correspond to different weight values ​​to achieve writing data to the storage cell TR; apply a read voltage V to the word line WL. read Or the on-state voltage V pass , and read the current I to the source line input ref ; According to the voltage drop ΔV generated by the source line SL, the number of storage transistors T turned off in the storage string Str is calculated, and the calculation result is output. When the reading current I ref When the storage string Str is passed, due to the different switching states of the storage transistors T (i.e., different threshold voltages), a corresponding voltage drop will be generated on the source line SL, and the control logic circuit 400 detects the voltage drop ΔV, and calculates the number of storage transistors T turned off in the storage string Str according to the voltage drop ΔV. The control logic circuit 400 outputs the calculation result for subsequent processing or application.

[0088] The control logic circuit 400 uses ONFI 5.0 protocol to realize data transmission between the driving and detecting circuit 200 and the peripheral circuit 300. The control logic circuit 400 uses PCIe 5.0 protocol to communicate with the terminal.

[0089] The in-memory computing architecture of this embodiment deploys the weight information and the calculation and output of the voltage drop ΔV by controlling the logic circuit 400, using the word line WL as the input port and the source line SL as the output port, and applying different read voltages V to each word line WL. readand the on-state voltage V pass , injects a read current I into the source line SL ref , which enables the architecture to directly execute computing tasks inside the storage unit TR, realize parallel computing of data in the storage unit TR, and process multiple data values ​​at the same time, further improving computing efficiency.

[0090] According to an exemplary embodiment, the present disclosure provides an operation strategy of an in-memory computing architecture, and the operation strategy of this embodiment is executed based on the in-memory computing architecture of the above embodiment. Figure 5 As shown, the operation strategy of the in-memory computing architecture includes the following steps S101 to S103. Among them:

[0091] Step S101: deploying weight information to a storage unit according to a weight writing strategy, and representing the weight information with a threshold voltage of the storage unit;

[0092] In this embodiment, refer to Figure 6 , Figure 7 , and combined with reference Figure 1-4 , the control logic circuit 400 deploys the weight information to the storage unit according to the weight writing strategy. The weight information can be generated by a terminal (such as a neural network processor, a central processing unit, etc.) and transmitted to the control logic circuit 400, or the weight information can be stored in an external database, and the control logic circuit 400 obtains the weight information by accessing the database.

[0093] The weight writing strategy may also be stored in a database, and the weight writing strategy defines how to map the weight information to the threshold voltage of the storage unit TR. The control logic circuit 400 obtains the weight writing strategy by accessing the database.

[0094] The control logic circuit 400 adjusts the voltages of the bit line BL and the word line WL through the peripheral circuit 300 according to the weight write strategy to set the threshold voltage of the storage cell TR, thereby characterizing the weight information, and deploys the weight information accordingly to the storage cell TR of the storage array 100, and sets the threshold voltage of the storage transistor T of the storage cell TR to a value corresponding to the weight information.

[0095] Step S102: applying a read voltage or a turn-on voltage to the word line, and inputting a read current to the source line;

[0096] In this embodiment, refer to Figure 6 , Figure 7 , and combined with reference Figure 1-4 , the control logic circuit 400 controls the peripheral circuit 300 to apply a read voltage V to the word line WL read Or the on-state voltage V pass ; Read voltage V readIt is used to read the state of the memory cell TR, and the conduction voltage V pass The control logic circuit 400 controls the driving and detecting circuit 200 to input a read current I to the source line SL to be detected. ref . Read the current I ref It is used to generate a voltage drop ΔV in the memory string Str, thereby reflecting the state of the memory cell TR.

[0097] In this embodiment, the control logic circuit 400 can input the activation vector corresponding to each word line WL to the peripheral circuit 300. The activation vector determines the word line WL receiving the read voltage and the word line receiving the conduction voltage V pass The word line WL.

[0098] Step S103: Calculate the number of storage transistors that are turned off in the storage string according to the voltage drop generated by the source line, and output the calculation result.

[0099] In this embodiment, refer to Figure 6 , Figure 7 , and combined with reference Figure 1-4 The driving and detecting circuit 200 calculates the number of storage transistors T turned off in the storage string Str according to the voltage drop ΔV generated on the source line SL, and the magnitude of the voltage drop ΔV is directly related to the number of storage transistors T turned off in the storage string Str. The driving and detecting circuit 200 calculates the number of storage transistors T turned off in the storage string Str according to the voltage drop ΔV generated on the source line SL, and outputs the calculation result to the control logic circuit 400. The control logic circuit 400 can further process the calculation result and transmit it to the terminal or other processing unit for subsequent use. Among them, the terminal can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, Internet of Things devices and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car devices, projection devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0100] The operation strategy of the in-memory computing architecture of this embodiment utilizes the in-memory computing architecture to implement an in-memory computing strategy based on a voltage domain, characterizes weight information by controlling the threshold voltage of the storage cell TR, and quickly calculates the number of storage transistors T turned off in the storage string Str by detecting the voltage drop ΔV on the source line SL, which not only improves the computing parallelism and computing efficiency, but also reduces the power consumption of data transmission, providing support for computing-intensive applications such as neural networks.

[0101] In some embodiments, step S101 deploys weight information to a storage unit according to a weight writing strategy, and represents the weight information with a threshold voltage of the storage unit, including steps S101-1 to S101-2:

[0102] Step S101 - 1 : Encode each element of the weight matrix as a binary value weight “1” or weight “0”;

[0103] In this embodiment, refer to Figure 7 The weight matrix can be generated by the terminal or stored in an external database. The terminal encodes each element of the weight matrix as a binary value weight "1" or weight "0". For each element in the weight matrix, the terminal encodes it into a binary form according to its value, for example, it can be obtained through neural network training.

[0104] In this embodiment, the weight matrix is ​​a floating-point weight matrix, and the weights in the weight matrix are represented by floating-point numbers. Through neural network training, quantization (selection of quantization range, determination of quantization bit number), scaling and rounding operations, the continuous floating-point weights are converted into discrete binary values.

[0105] Step S101-2: According to the mapping relationship between the weight matrix and the storage cell, a programming voltage or an erasing voltage is applied to the storage cell corresponding to the weight element to adjust the threshold voltage of the storage cell to a high threshold voltage or a low threshold voltage, where the high threshold voltage corresponds to a weight of "1" and the low threshold voltage corresponds to a weight of "0".

[0106] In this embodiment, refer to Figure 7 The mapping relationship between the weight matrix and the storage unit is an address mapping mechanism between each element of the weight matrix and the storage unit TR of the storage array 100, to ensure that each weight element can uniquely correspond to a storage unit TR. The mapping relationship between the weight matrix and the storage unit can be generated by the terminal or stored in a database.

[0107] The control logic circuit 400 controls the peripheral circuit 300 to apply a programming voltage or an erasing voltage to the storage cell TR according to the weights after the weight matrix is ​​encoded as binary values ​​and the mapping relationship between the weight matrix and the storage cell TR. The storage transistor T of the storage cell TR will enter the corresponding programming state or erasing state, thereby storing the weight information in the form of a threshold voltage.

[0108] In this embodiment, an erase voltage is applied to each word line WL of the memory array 100. Then, for the memory cell TR corresponding to the weight "1", the control logic circuit 400 controls the peripheral circuit 300 to apply a programming voltage to the corresponding word line WL to adjust its threshold voltage to the high threshold voltage V T,H . So that the threshold voltage of the storage cell TR corresponding to the weight "1" is the high threshold voltage V T,H , the threshold voltage of the storage cell TR corresponding to the weight "0" is the low threshold voltage V T,L .

[0109] In this embodiment, before the calculation starts, all elements of the weight matrix are encoded bit by bit and deployed to the corresponding positions in the storage array 100. In this way, each storage unit TR stores 1 bit of information of the corresponding weight element through the storage transistor T. The information of the weight element is expressed as two threshold voltage states of the storage transistor T, where the high threshold voltage V T,H Corresponding weight "1" and low threshold voltage V T,L The corresponding weight "0" provides a basis for subsequent in-memory calculations, so that the weight information can be directly involved in the calculation in the storage unit TR, thereby improving the calculation efficiency and reducing power consumption.

[0110] In some embodiments, step S102 applies a read voltage or a turn-on voltage to the word line, including steps S102-1 to S102-2:

[0111] Step S102-1: Encode each element of the activation vector into a binary value;

[0112] In this embodiment, the activation vector can be generated by the terminal, or the activation vector can be stored in a database, and the terminal accesses the database to obtain the activation vector. The terminal encodes each element of the activation vector into a binary value activation value "1" or an activation value "0". Similarly, the encoding process of the activation vector can be obtained through neural network training.

[0113] In this embodiment, the activation vector is a floating-point activation value matrix. The activation values ​​in the activation vector are represented by floating-point numbers. They are input from the outside or generated by the previous layer of the neural network. After quantization (selection of the quantization range, determination of the number of quantization bits), scaling and rounding operations, the continuous floating-point activation values ​​are converted into discrete binary values.

[0114] Step S102-2: According to the mapping relationship between the activation vector and the word line, a read voltage is applied to the word line corresponding to the encoded activation value "1", and a conduction voltage V is applied to the word line corresponding to the encoded activation value "0". pass , on-state voltage V pass Greater than the read voltage V read .

[0115] In this embodiment, the mapping relationship between the activation vector and the word line is an address mapping mechanism between each element of the activation vector and each word line WL to ensure that each activation vector can uniquely correspond to a word line WL. The mapping relationship between the activation vector and the word line WL can be generated by the terminal or stored in a database.

[0116] The control logic circuit 400 controls the peripheral circuit 300 to input a read voltage V to the corresponding word line WL according to the activation value encoded by the activation vector and the mapping relationship between the activation vector and the word line. read Or the on-state voltage Vpass .

[0117] For the encoded activation value “1”, the control logic circuit 400 controls the peripheral circuit 300 to apply a read voltage V to the corresponding word line WL. read . Read the voltage V read The storage transistor T connected to the word line WL and having a low threshold voltage (ie, storing weight "0") can be kept on, but the storage transistor T having a high threshold voltage (ie, storing weight "1") can be turned off.

[0118] For the encoded activation value "0", the control logic circuit 400 controls the peripheral circuit 300 to apply a higher voltage, namely, the conduction voltage V pass . On-state voltage V pass It is ensured that the storage transistor T can maintain the on state regardless of whether the threshold voltage of the storage transistor T is high or low.

[0119] It should be noted that the on-state voltage V pass Greater than the read voltage V read To ensure that the storage transistor T can be successfully turned on when the activation value is "0".

[0120] In this embodiment, V T,L <V read <V T,H <V pass If and only if the threshold voltage of the storage transistor T is equal to V T,H And the word line voltage is equal to V read When the storage transistor T in the storage unit TR is in the off state and generates a voltage drop across the storage unit TR, the storage transistor T is turned on in other cases.

[0121] This embodiment maps the activation vector information to the voltage of the word line WL, providing a basis for subsequent in-memory calculations, so that the activation value can be directly involved in the calculation in the storage unit TR, thereby improving the calculation efficiency and reducing power consumption.

[0122] In some embodiments, a read voltage V is applied to the word line WL. read Or the on-state voltage V pass , input the read current I to the source line SL ref , further comprising: adjusting the voltage of the word line WL and the read current I ref , so that when the storage transistor T is turned on, the current of the storage cell TR flows through the storage transistor T, and when the storage transistor T is turned off, the current of the storage cell TR flows through the bypass resistor R, generating a voltage drop ΔV on both sides of the storage cell TR.

[0123] The voltage drop ΔV generated by turning off the storage transistor T is accumulated along the storage string Str, and finally forms an output voltage V on the source line SL. SL , output voltage V SL The size of is proportional to the number of storage transistors T turned off in the storage string Str. The number of storage transistors T turned off in the storage string Str is equal to the sum of the storage cells TR of the storage string Str and the WL input information after multiplication.

[0124] In some embodiments, step S103 calculates the number of storage transistors T turned off in the storage string Str according to the voltage drop ΔV generated by the source line SL, and outputs the calculation result, including steps S103-1 to S103-2:

[0125] Step S103 - 1 : performing a multiplication operation on the weight of the memory cell and the activation value of the word line connected to the memory cell, and obtaining a voltage drop of the memory cell as 1 or 0;

[0126] In this embodiment, the control logic circuit 400 performs a multiplication operation on the weight of the storage cell TR and the activation value of the word line WL connected to the storage cell TR. The weight of the storage cell TR is "1" (that is, when the storage transistor T of the storage cell TR is turned off), and the activation value of the word line WL connected to the storage cell TR is "1" (the word line WL is applied with a read voltage V read ), the voltage drop of the storage unit TR is obtained to be 1.

[0127] The weight of the memory cell TR is "0" (that is, when the memory transistor T of the memory cell TR is turned on) and / or the activation value of the word line WL connected to the memory cell TR is "0" (the word line WL is applied with the turn-on voltage V pass ), the voltage drop of the storage unit TR is obtained to be 0.

[0128] Step S103 - 2 : performing an addition operation on the voltage drops of the memory cells of the memory string to obtain the number of memory transistors that are turned off in the memory string.

[0129] In this embodiment, based on the architecture of the memory array 100, the voltage drops of all memory cells TR in the memory string Str are accumulated for addition. Since each memory cell TR with a memory transistor T turned off will generate a voltage drop in the memory string Str, the result of the addition operation can represent the number of memory transistors T turned off in the memory string Str.

[0130] For example, there are n storage cells TR in the storage string Str, among which the storage transistors T of m storage cells TR are turned off, then these m turned-off storage transistors T will generate m voltage drops, which will be accumulated together to obtain the total voltage drop value of the storage string Str. According to the total voltage drop value, the number m of the turned-off storage transistors T in the storage string Str can be obtained.

[0131] The operation strategy of the in-memory computing architecture of this embodiment is to inject a constant read current I into the storage string Str. ref , all the bit lines BL are grounded, and by detecting the voltage of the source line SL, the calculation results of the Vector Matrix Multiplication (VMM) expressed in the form of voltage are obtained, which improves the accuracy of detection and provides strong support for the further application and development of VMM technology.

[0132] In order to further understand the solution of the present disclosure, refer to Figure 1-Figure 7 , an exemplary in-memory computing architecture and its operation strategy of the present disclosure are as follows:

[0133] In the in-memory computing architecture of this embodiment, the stacked storage N of the memory array 100 is 232, that is, each memory string Str includes 232 vertically stacked memory cells TR, and the memory array 100 includes 232 word lines WL1-WL 232 .

[0134] Each storage string Str is connected to a source line SL through a lower selection tube BM, and the storage string Str is connected to the source line SL in a one-to-one correspondence. In this embodiment, the source lines SL corresponding to the storage cells Str of the same storage page are independently led out, and each storage page has m storage strings Str, which are connected to m source lines SL1-SLm. For example, each storage page contains 128k storage strings Str, and the 128k storage strings Str of each storage page are respectively connected to 128k source lines, that is, the total number of output ports m=128k.

[0135] In other embodiments, 3 to 4 storage strings Str arranged in sequence with the storage page may share one output port, which reduces the difficulty of the manufacturing process and reduces the manufacturing cost.

[0136] Each memory cell TR includes a memory transistor T and a bypass resistor R connected in parallel with the memory transistor T. Along the first direction Z, the memory transistors T of the memory string Str are sequentially connected in series, and the bypass resistors R are sequentially connected in series.

[0137] The resistance value R of the bypass resistor R is much larger than the channel equivalent resistance R when the storage transistor T is turned on. on , which is much smaller than the channel equivalent resistance R when the storage transistor T is turned off off.

[0138] The channel equivalent resistance R of the storage transistor T when it is turned off off Approximately infinite, in this embodiment, the resistance value R of the bypass resistor R of the storage unit TR satisfies R on < <R<<R off requirements.

[0139] When the operation strategy is executed on the in-memory computing architecture of this embodiment, the word line WL is used as the input port and the source line SL is used as the output port.

[0140] According to the weight writing strategy, the weight information is deployed to the storage unit TR, and the weight information is represented by the threshold voltage of the storage transistor T of the storage unit TR.

[0141] According to the corresponding relationship between the activation vector and the word line WL, the activation value is input to the word line WL, and a read voltage V is applied to the word line WL. read Or the on-state voltage V pass ; and input the read current I to the source line SL ref .

[0142] When the storage transistor T of a certain layer of storage unit TR is turned off, a voltage drop ΔV=I is generated across the storage unit TR. ref ·R. These voltage drops are accumulated along the storage string Str, and finally output voltage V through the source line SL SL , output voltage V SL The size of is proportional to the number of storage transistors T that are turned off in the storage string Str.

[0143] In the operation strategy of this embodiment, the number of storage cells TR that can participate in parallel calculation at one time is the product of the total number of word lines WL and the total number of source lines SL, that is, n×m. Combined with the expansion of the storage array 100 in the horizontal direction, the total number of storage cells TR that can actually participate in parallel is equal to the number of all storage cells TR of the storage array 100. For example, for a four-level storage array (Quad-Level Cell, QLC) with a storage capacity of 1Tb, the total number of cells that can be parallelized can reach 256M, and the upper limit of the parallelism of the storage and calculation strategy is greatly improved. The voltage domain-based in-memory calculation strategy of this embodiment increases the parallel potential to several times the original.

[0144] In some embodiments, an electronic device is provided, such as Figure 8 As shown, the electronic device may be a terminal, and the electronic device includes a controller and a processor. The controller stores a computer program, and when the processor executes the computer program, the steps of the operation strategy of the in-memory computing architecture in the above embodiment are implemented.

[0145] The internal structure diagram of the electronic device can be Figure 8As shown. The electronic device includes a processor, a controller, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the controller and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the electronic device is used to provide computing and control capabilities. The controller of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the electronic device is used to exchange information between the processor and an external device. The communication interface of the electronic device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an operation strategy of an in-memory computing architecture is implemented.

[0146] Those skilled in the art will understand that Figure 8 The structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0147] It should be noted that the information (including but not limited to electronic device information) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data permitted by the user or with full permission from all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0148] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the controller, database or other media used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, etc., but are not limited to this.

[0149] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0150] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. An in-memory computing architecture, characterized in that: include: A memory array, the memory array comprising a memory string, a source line, a word line and a bit line; the memory string comprises a plurality of memory cells connected in series along a first direction, the memory cell comprises a memory transistor and a bypass resistor connected in parallel, the memory string is connected to the source line through a lower gate tube, is connected to the bit line through an upper gate tube, and a control end of the memory cell is connected to the word line; A driving and detecting circuit connected to the source line, wherein the driving and detecting circuit is configured to inject a read current into the source line, detect and output a voltage signal of the source line; The peripheral circuit is connected to the word line and the bit line, and is configured to control the voltages of the word line and the bit line.

2. The in-memory computing architecture according to claim 1, characterized in that: The source line is disposed below the storage string, the source line is arranged along a second direction and a third direction perpendicular to the first direction, and the source line is connected to a first end of the lower gate tube of the storage string; The word lines are arranged along the first direction, and the word lines are connected to the control terminals of the storage units in the same layer; The bit line is disposed above the memory string, the bit line extends along the second direction and is arranged along the third direction, and the bit line is connected to the second end of the upper selection tube of the memory string arranged along the second direction; Wherein, the plurality of storage strings arranged along the second direction are respectively connected to the plurality of source lines arranged along the second direction.

3. The in-memory computing architecture according to claim 1, characterized in that: The resistance value of the bypass resistor is greater than the channel equivalent resistance when the storage transistor is turned on, and is less than the channel equivalent resistance when the storage transistor is turned off.

4. The in-memory computing architecture according to claim 3, characterized in that: Along the first direction, the driving and detecting circuit is integrated below the source line, and the peripheral circuit is integrated above the bit line; wherein the driving and detecting circuit includes: A current generating circuit, used for generating a reading current; a current mirror for replicating the read current and injecting the read current into the source line; A source follower, configured to read the voltage signal of the source line; The analog-to-digital converter is used for converting the voltage signal into a digital signal and then outputting it.

5. The in-memory computing architecture according to claim 1, characterized in that: Also includes: A control logic circuit, wherein the control logic circuit is connected to the driving and detecting circuits and the peripheral circuits respectively; The control logic circuit is configured to: deploy the weight information to the storage unit according to the weight writing strategy, and represent the weight information with the threshold voltage of the storage unit; Applying a read voltage or a turn-on voltage to the word line and inputting a read current to the source line; The number of the memory transistors turned off in the memory string is calculated according to the voltage drop generated by the source line, and the calculation result is output.

6. An operation strategy for an in-memory computing architecture, characterized in that: include: Deploy the weight information to a storage unit according to a weight writing strategy, and represent the weight information with a threshold voltage of the storage unit; Applying a read voltage or a turn-on voltage to the word line and inputting a read current to the source line; The number of memory transistors turned off in the memory string is calculated according to the voltage drop generated by the source line, and the calculation result is output.

7. The operation strategy of the in-memory computing architecture according to claim 6, characterized in that: The step of deploying the weight information to a storage unit according to the weight writing strategy and representing the weight information with a threshold voltage of the storage unit includes: Encode each element of the weight matrix as a binary value weight "1" or weight "0"; According to the mapping relationship between the weight matrix and the storage cell, a programming voltage or an erasing voltage is applied to the storage cell corresponding to the weight element to adjust the threshold voltage of the storage cell to a high threshold voltage or a low threshold voltage, wherein the high threshold voltage corresponds to a weight of "1" and the low threshold voltage corresponds to a weight of "0".

8. The operation strategy of the in-memory computing architecture according to claim 7, characterized in that: The applying a read voltage or a turn-on voltage to the word line comprises: Encode each element of the activation vector as a binary value; According to the mapping relationship between the activation vector and the word line, the read voltage is applied to the word line corresponding to the encoded activation value "1", and the turn-on voltage is applied to the word line corresponding to the encoded activation value "0", and the turn-on voltage is greater than the read voltage.

9. The operation strategy of the in-memory computing architecture according to claim 6, characterized in that: The step of applying a read voltage or a turn-on voltage to the word line and inputting a read current to the source line also includes: The voltage of the word line and the read current are adjusted so that when the storage transistor is turned on, the current of the storage cell flows through the storage transistor, and when the storage transistor is turned off, the current of the storage cell flows through the bypass resistor, generating a voltage drop on both sides of the storage cell.

10. The operation strategy of the in-memory computing architecture according to claim 9, characterized in that: The step of calculating the number of the storage transistors turned off in the storage string according to the voltage drop generated by the source line and outputting the calculation result comprises: Performing a multiplication operation on the weight of the memory cell and the activation value of the word line connected to the memory cell, so that the voltage drop of the memory cell is 1 or 0; An addition operation is performed on the voltage drops of the storage cells of the storage string to obtain the number of the storage transistors in the storage string that are turned off.

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