Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises the following steps: executing erasing operation on at least one of a plurality of entity units; in response to the erase operation, updating time information which reflects the average execution time of the erase operation for the plurality of entity units; executing partial information extraction on the time information to obtain small digital information of the time information; generating password information according to the small digital information; segmenting the first data to generate a plurality of second data; according to the password information, encrypting the plurality of second data to generate third data, the third data including encrypted data corresponding to the first data; and storing the third data to the first entity unit. Therefore, the data encryption efficiency of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] With the rapid development of informatization today, information security has been paid more and more attention by countries and industries. Modern cryptographic technology has made rapid progress in the development of application technologies such as online shopping, financial securities, government, and military confrontation. Modern cryptographic technology is mostly based on keys to implement different encryption and decryption algorithms, and the generation of keys comes from random number generators.

[0003] Random number generators are generally divided into two categories: Pseudo Random Number Generator (PRNG) and True Random Number Generator (TRNG). Pseudo random number generators are usually implemented based on a given algorithm and initialization random seed. When the random seeds are different, the generated random numbers are different. Its disadvantage is that when the random seeds used are the same, the generated random numbers are the same. True random number generators usually use the uncertainty of certain physical properties to generate random numbers, such as thermal noise of circuits, environmental noise, radioactive decay, oscillation method and other technologies.

[0004] In addition, the true random number generator generally uses an oscillator-type true random number generator based on digital logic, which includes a high-frequency oscillation clock, a low-frequency sampling clock, and a digital post-processing unit. However, the high-frequency oscillation clock in the true random number generator will produce a certain amount of crosstalk during implementation, resulting in the randomness of the generated random number being insufficient.

[0005] Therefore, how to solve the above problems has become the focus of attention of people in this field. Summary of the invention

[0006] The present invention provides a memory management method and a storage device, which can improve the above-mentioned problem and enhance the data encryption efficiency of the storage device.

[0007] An embodiment of the present invention provides a memory management method, which is used for a storage device, wherein the storage device includes a memory module, the memory module includes multiple physical units, and the memory management method includes: performing an erase operation on at least one of the multiple physical units; updating time information in response to the erase operation, wherein the time information reflects the average execution time of the erase operation on the multiple physical units; performing partial information extraction on the time information to obtain small-digit information of the time information; generating password information based on the small-digit information; dividing first data to generate multiple second data, wherein the data length of each second data is shorter than the total data length of the first data; encrypting the multiple second data based on the password information to generate third data, wherein the third data includes encrypted data corresponding to the first data; and storing the third data in the first physical unit among the multiple physical units.

[0008] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is used to: perform an erase operation on at least one of the plurality of physical units; update time information in response to the erase operation, wherein the time information reflects the average execution time of the erase operation for the plurality of physical units; perform partial information extraction on the time information to obtain small digit information of the time information; generate password information based on the small digit information; divide the first data to generate a plurality of second data, wherein the data length of each second data is shorter than the total data length of the first data; encrypt the plurality of second data according to the password information to generate third data, wherein the third data includes encrypted data corresponding to the first data; and store the third data in the first physical unit among the plurality of physical units.

[0009] Based on the above, after performing an erase operation on at least one of the multiple entity units, in response to the erase operation, the time information can be updated. In particular, the time information can reflect the average execution time of the erase operation on the multiple entity units. After performing partial information extraction on the time information, the small digit information of the time information can be obtained. According to the small digit information, password information can be generated. On the other hand, after the first data is segmented, a plurality of second data can be generated, wherein the data length of each second data is shorter than the total data length of the first data. According to the password information, the plurality of second data can be encrypted to generate third data, wherein the third data includes encrypted data corresponding to the first data. Thereafter, the third data can be stored in the first entity unit among the multiple entity units. Thus, the problem that the random numbers traditionally used to encrypt data are not random enough can be effectively improved, thereby improving the data encryption efficiency of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0011] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0012] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0013] Figure 4 is a schematic diagram of generating password information according to an embodiment of the present invention;

[0014] Figure 5 is a schematic diagram of dividing first data into a plurality of second data and encrypting the second data according to an embodiment of the present invention;

[0015] Figure 6 is a schematic diagram of storing third data, password information and error correction data in a first physical subunit according to an embodiment of the present invention;

[0016] Figure 7 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0018] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0019] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (embedded Multi-Media Card, eMMC), a universal flash storage (Universal Flash Storage, UFS), a fast peripheral component interconnect (Peripheral Component Interconnect Express, PCIExpress), a fast non-volatile memory (Non-Volatile Memory Express, NVM express), a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), a universal serial bus (Universal Serial Bus, USB) or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (for example, exchange signals, instructions and / or data).

[0020] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0021] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0022] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0023] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0026] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc.

[0027] In one embodiment, the memory controller 123 may further include an encryption circuit 26. The encryption circuit 26 is connected to the memory control circuit 23 and is used to perform encryption and decryption on data to ensure the confidentiality of the data. For example, after a certain data (also referred to as the first data) is encrypted by the encryption circuit 26, a ciphertext corresponding to the first data may be formed. After the ciphertext is decrypted by the encryption circuit 26, a plaintext corresponding to the ciphertext (i.e., the first data) may be restored.

[0028] In one embodiment, the encryption circuit 26 may support a symmetric encryption algorithm, an asymmetric encryption algorithm, or other types of encryption / decryption algorithms. For example, the symmetric encryption algorithm may include AES (Advanced Encryption Standard)-256, etc., and the asymmetric encryption algorithm may include RSA (Rivest-Shamir-Adleman), etc., and the present invention is not limited thereto. In one embodiment, the memory controller 123 may also include other types of various circuit modules (such as a power management circuit, etc.), and the present invention is not limited thereto.

[0029] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile storage of data.

[0030] In one embodiment, a physical unit may include one or more physical erasing units. In addition, a physical unit may include multiple physical sub-units. For example, a physical sub-unit may include one or more physical programming units.

[0031] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0032] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0033] In one embodiment, a physical erase unit may include a plurality of physical programming units. The plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the plurality of physical programming units in the physical erase unit to change the threshold voltage of at least some of the storage cells in the physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared.

[0034] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0035] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0036] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0037] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0038] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0039] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0040] In one embodiment, the memory control circuit 23 may perform an erase operation on at least one of the plurality of physical units in the memory module 122. Figure 3 In an erase operation performed on the physical unit 301(i), the memory module 122 may apply an erase voltage to each memory cell (or physical sub-unit) in the physical unit 301(i). The erase operation (or the applied erase voltage) may be used to clear the data stored in the physical unit 301(i).

[0041] In one embodiment, in response to the erase operation performed, the memory control circuit 23 may update the time information. The time information may reflect the average execution time of the erase operation for the plurality of physical units. For example, the execution time of the erase operation performed for a physical unit refers to the time from the start of the erase operation for the physical unit until the erase operation ends or is completed.

[0042] In one embodiment, the memory control circuit 23 may continuously monitor the usage status of the memory module 122 to obtain the total execution time of the erase operation executed on each physical unit in the memory module 122. Then, the memory control circuit 23 may obtain (or update) the time information according to the total number of physical units in the memory module 122 and the total execution time. Thus, the obtained or updated time information may reflect the average execution time of the erase operation on the plurality of physical units in real time.

[0043] In one embodiment, it is assumed that at a certain time point, the total execution time of the erase operation performed on each physical unit in the memory module 122 is "22451 microseconds (micro second, us)", and the total number of physical units in the memory module 122 is "1727". The memory control circuit 23 can obtain (or update) the time information according to the total execution time (i.e., "22451 microseconds") and the total number of physical units (i.e., "1727"). For example, the obtained or updated time information can reflect that the average execution time of the erase operation for the plurality of physical units is "374.18333333333333333333 seconds".

[0044] In one embodiment, after obtaining the time information, the memory control circuit 23 may perform partial information extraction on the time information to obtain decimal information of the time information. For example, the decimal information includes at least a portion of data information after the decimal point in the time information. For example, assuming that the time information is "374.1833333333333333333 seconds", by performing partial information extraction on the time information, the decimal information of the time information (i.e., "18333333333333333333") can be obtained.

[0045] In one embodiment, the data format (e.g., data length) of the small digital information matches the encryption algorithm used by the encryption circuit 26 to encrypt the data (e.g., the first data). For example, assuming that the encryption algorithm used by the encryption circuit 26 is a certain encryption algorithm (also referred to as the first encryption algorithm), the small digital information may conform to a certain data format (also referred to as the first data format). Alternatively, assuming that the encryption algorithm used by the encryption circuit 26 is another encryption algorithm (also referred to as the second encryption algorithm), the small digital information may conform to another data format (also referred to as the second data format). The first encryption algorithm is different from the second encryption algorithm. The first data format is different from the second data format.

[0046] In one embodiment, the small digital information conforming to the first data format may have a certain data length (also referred to as the first data length), and the small digital information conforming to the second data format may have another data length (also referred to as the second data length), and the first data length is different from the second data length. For example, the first data format (or the first data length) may match the first encryption algorithm, and the second data format (or the second data length) may match the second encryption algorithm.

[0047] In one embodiment, after obtaining the small number information, the memory control circuit 23 may generate password information according to the small number information. Taking the AES-256 encryption algorithm as an example, the password information may include private-key information and initialization sequence information. The key information may carry information about the key used to perform encryption in the AES-256 encryption algorithm. The initialization sequence information may carry information about the initialization sequence (also called initialization vector) used to perform encryption in the AES-256 encryption algorithm. It should be noted that the information content of the password information may be different according to different encryption algorithms, and the present invention is not limited thereto.

[0048] In one embodiment, the data format (e.g., data length) of the key information may be different from the data format (e.g., data length) of the initialization sequence information. For example, taking the AES-256 encryption algorithm as an example, the data lengths of the key information and the initialization sequence information used in the AES-256 encryption algorithm may be "256" bits and "128" bits, respectively. However, the data format of the key information and / or the initialization sequence information may be adjusted according to practical needs, and the present invention is not limited thereto.

[0049] Figure 4 is a schematic diagram of generating password information according to an embodiment of the present invention. Figure 4 , the memory control circuit 23 may obtain the time information 41 according to the erase operation executed in the past on at least one of the multiple physical units in the memory module 122. The time information 41 may reflect the average execution time of the erase operation on the multiple physical units. For example, the average execution time may be obtained according to the total execution time of at least one erase operation executed in the past on the multiple physical units and the total number of the multiple physical units (for example, the total execution time is divided by the total number to obtain).

[0050] After obtaining the time information 41, the memory control circuit 23 may perform partial information extraction 401 on the time information 41 to obtain the small number information 42. For example, assuming that the time information 41 is "374.18333333333333333333 seconds", the small number information 42 may be "183333333333333333333" (i.e., at least a portion of the data information after the decimal point in "374.1833333333333333333 seconds"). Then, the memory control circuit 23 may generate the password information 43 according to the small number information 42. For example, taking the AES-256 encryption algorithm as an example, the password information 43 may include the key information 431 and the initialization sequence information 432.

[0051] In one embodiment, the memory control circuit 23 may perform a data conversion (also referred to as a first data conversion) 411 on the small digital information 42 to obtain key information 431. For example, the key information 431 may carry information about a key used to perform encryption in the encryption algorithm used by the encryption circuit 26. In addition, the memory control circuit 23 may perform another data conversion (also referred to as a second data conversion) 412 on the small digital information 42 to obtain initialization sequence information 432. For example, the initialization sequence information 432 may carry information about an initialization sequence (or initialization vector) used to perform encryption in the encryption algorithm used by the encryption circuit 26.

[0052] It should be noted that in Figure 4In the embodiment of the present invention, the partial information extraction 401, the first data conversion 411 and the second data conversion 412 can be set or configured according to the encryption algorithm used by the encryption circuit 26. Therefore, the partial information extraction 401, the first data conversion 411 and the second data conversion 412 can be used to generate the small digital information 42, the password information 431 and the initialization sequence information 432 that match the encryption algorithm used by the encryption circuit 26, respectively.

[0053] Generally speaking, the efficiency of an encryption algorithm in encrypting data can be determined by the cryptographic information used by the encryption algorithm (e.g. Figure 4 The randomness of the key information 431 and / or the initialization sequence 432) of the encryption algorithm is used for evaluation. For example, if the randomness of the password information used by the encryption algorithm is higher (i.e., the repetitiveness of the password information used by the encryption algorithm each time is lower), it means that the encryption efficiency of the encryption algorithm for data is higher, and it is less likely for an attacker or hacker to decrypt the encrypted data. Conversely, if the randomness of the password information used by the encryption algorithm is lower (i.e., the repetitiveness of the password information used by the encryption algorithm each time is higher), it means that the encryption efficiency of the encryption algorithm for data is lower, and it is easier for an attacker or hacker to decrypt the encrypted data.

[0054] In one embodiment, by performing partial information extraction on the time information to obtain the small digit information and generating the password information based on the small digit information, the randomness of the generated password information can be effectively improved. In particular, compared with the conventional pseudo-random number generator (PRNG) and true random number generator (TRNG), the generated random numbers may not be random enough due to various factors. In the embodiment of the present invention, as long as there is continuous data writing, erasure of physical units and / or rotation of physical units inside the memory module 122, the small digit information of the time information will continue to change unexpectedly. Similarly, the password information generated based on the small digit information of the time information will also continue to change unexpectedly. As a result, the randomness of the generated password information and the efficiency of the subsequent encryption operations performed using the password information can be effectively improved.

[0055] In one embodiment, the memory control circuit 23 may divide the data to be encrypted (i.e., the first data) to generate a plurality of sub-data (also referred to as second data). The data length of each second data is shorter than the total data length of the first data. For example, the total data length of the first data is 4 kilobytes (KB), and the data length of each second data may be 16 bytes (B) (i.e., 128 bits), and the present invention is not limited thereto. In addition, the first data may be data obtained from the host system 11 or read from the memory module 122, and the present invention is not limited thereto.

[0056] In one embodiment, the memory control circuit 23 may encrypt the plurality of second data according to the password information to generate another data (also referred to as third data). In particular, the third data includes encrypted data corresponding to the first data. Figure 4 The key information 431 and the initialization sequence information 432 are used to encrypt the plurality of second data to generate third data.

[0057] In one embodiment, the plurality of second data includes first sub-data and second sub-data. In particular, during the encryption of the plurality of second data, the second sub-data is encrypted based on the encryption result of the first sub-data. In one embodiment, the encryption circuit 26 performs encryption of the plurality of second data based on a cipher block chaining method. However, in one embodiment, the encryption circuit 26 may also perform encryption of the plurality of second data based on other methods other than cipher block chaining, which is not limited by the present invention.

[0058] Figure 5 is a schematic diagram of dividing first data into a plurality of second data and encrypting the second data according to an embodiment of the present invention. Figure 5 , assuming that the first data includes data 51. The memory control circuit 23 may divide the data 51 to generate a plurality of sub-data D(1) to D(n) (i.e., second data). For example, the total data length of the data 51 may be 4KB, and the data length of the sub-data D(j) may be 16 B, and the present invention is not limited thereto. j is between 1 and n. In addition, the total data length of the sub-data D(1) to D(n) may be equal to the data length of the data 51.

[0059] In one embodiment, the encryption circuit 26 may be based on a ciphertext grouping chaining method, according to Figure 4The encryption circuit 26 may encrypt the sub-data D(1) to D(n) in sequence according to the password information 431 and the initialization sequence information 432. For example, the encryption circuit 26 may first encrypt the sub-data D(1) according to the password information 431 and the initialization sequence information 432 to generate the sub-data D(1)'. For example, the sub-data D(1)' may reflect the encryption result of the sub-data D(1). After generating the sub-data D(1)', the encryption circuit 26 may encrypt the sub-data D(2) based on the sub-data D(1)' to generate the sub-data D(2)'. For example, the sub-data D(2)' may reflect the encryption result of the sub-data D(2). Similarly, after encrypting the sub-data D(n-1) to generate the sub-data D(n-1)', the encryption circuit 26 may encrypt the sub-data D(n) based on the sub-data D(n-1)' to generate the sub-data D(n)'. For example, sub-data D(n-1)' and sub-data D(n)' can respectively reflect the encryption results of sub-data D(n-1) and D(n). Thus, the memory control circuit 23 can obtain data 52 (i.e., third data). For example, data 52 can include sub-data D(1)'~D(n)'.

[0060] In one embodiment, after obtaining the third data (eg Figure 5 After the data 52 is stored, the memory control circuit 23 may store the third data in at least one physical unit (also referred to as a first physical unit) in the memory module 122. For example, the first physical unit may include Figure 3 At least one entity unit extracted from the idle area 32.

[0061] In one embodiment, before storing the third data in the first physical unit, the memory control circuit 23 may encode the third data with an error correction code (ECC) to generate error correction data. Then, the memory control circuit 23 may store the third data in a data area in a physical subunit (also referred to as the first physical subunit) in the first physical unit. For example, the first physical subunit may include at least one physical programming unit in the first physical unit. In addition, the memory control circuit 23 may store the password information and the error correction data in a spare area in the first physical subunit.

[0062] Figure 6 is a schematic diagram showing the storage of third data, password information and error correction data in the first entity subunit according to an embodiment of the present invention. Figure 6Assuming that the first physical unit is physical unit 610, physical unit 610 includes physical subunits 601(1)-601(D), and the first physical subunit is physical subunit 601(1). The memory control circuit 23 can instruct the memory module 122 to store data 52 (i.e., the third data) into the data area of ​​the physical subunit 601(1).

[0063] In one embodiment, the decoding circuit 25 may perform an error correction code encoding on the data 52 to generate error correction data 61. The error correction data 61 may be used to correct errors (i.e., error bits) in the data 52. For example, the error correction data 61 may carry error correction information corresponding to the data 52. The memory control circuit 23 may instruct the memory module 122 to store the password information 43 and the error correction data 61 in an idle area in the physical subunit 601(1).

[0064] In one embodiment, the memory controller 123 may read the third data from the data area in the first physical subunit. The memory controller 123 may read the error correction data and the password information from the idle area in the first physical subunit. Then, the memory controller 123 may restore the third data to the first data according to the error correction data and the password information.

[0065] by Figure 6 For example, after storing data 52 (i.e., third data), password information 43, and error correction data 61 in physical subunit 601(1), memory controller 123 may instruct memory module 122 to read data 52 from the data area in physical subunit 601(1) and to read password information 43 and error correction data 61 from the idle area in physical subunit 601(1). Decoding circuit 25 may decode data 52 according to error correction data 61 to try to correct errors in data 52. Then, encryption circuit 26 may decode data 52 according to password information 43 (e.g., Figure 4 The key information 431 and the initialization sequence information 432) are used to decrypt the corrected data 52 to restore the data 52 to Figure 5 For example, the encryption circuit 26 may decrypt the data based on ciphertext group concatenation or other methods, which is not limited in the present invention.

[0066] Figure 7 FIG. 1 is a flowchart of a memory management method according to an embodiment of the present invention. Figure 7, in step S701, an erase operation is performed on at least one of the multiple entity units. In step S702, in response to the erase operation, time information is updated, wherein the time information reflects the average execution time of the erase operation on the multiple entity units. In step S703, partial information extraction is performed on the time information to obtain small digit information of the time information. In step S704, password information is generated based on the small digit information. In step S705, the first data is divided to generate a plurality of second data, wherein the data length of each second data is shorter than the total data length of the first data. In step S706, the plurality of second data is encrypted according to the password information to generate third data, wherein the third data includes encrypted data corresponding to the first data. In step S707, the third data is stored in the first entity unit among the multiple entity units.

[0067] However, Figure 7 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 7 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 7 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0068] In summary, the memory management method and storage device proposed in the embodiment of the present invention can extract small digital information from the average execution time of erase operations executed on multiple physical units in the memory module in the past, and then obtain the password information used for encryption based on the small digital information. Therefore, the randomness of the generated password information and the efficiency of the subsequent encryption operation performed using the password information can be effectively improved.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For use in a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of entity units, and the memory management method comprises: performing an erase operation on at least one of the plurality of physical units; In response to the erase operation, updating time information, wherein the time information reflects an average execution time of the erase operation on the plurality of physical units; Performing partial information extraction on the time information to obtain small digital information of the time information; Generate password information according to the small digital information; Slicing the first data to generate a plurality of second data, wherein the data length of each second data is shorter than the total data length of the first data; encrypting the plurality of second data according to the password information to generate third data, wherein the third data includes the encrypted data corresponding to the first data; and The third data is stored in a first physical unit among the plurality of physical units. 2 . The memory management method according to claim 1 , wherein the decimal information includes at least a portion of data information after a decimal point in the time information. 3 . The memory management method according to claim 1 , wherein a data format of the small digital information matches an encryption algorithm used to encrypt the first data.

4. The memory management method according to claim 3, wherein if the encryption algorithm is a first encryption algorithm, the small digital information conforms to a first data format, and If the encryption algorithm is a second encryption algorithm, the small digital information conforms to a second data format, wherein the first encryption algorithm is different from the second encryption algorithm, and the first data format is different from the second data format.

5. The memory management method according to claim 1, wherein the password information includes key information and initialization sequence information, and the step of generating the password information according to the small digital information includes: Performing a first data conversion on the small digital information to obtain the key information; as well as A second data conversion is performed on the small digital information to obtain the initialization sequence information, wherein a data format of the key information is different from a data format of the initialization sequence information.

6. The memory management method according to claim 5, wherein the step of encrypting the plurality of second data according to the password information comprises: The plurality of second data are encrypted according to the key information and the initialization sequence information. 7 . The memory management method according to claim 5 , wherein the plurality of second data comprises first sub-data and second sub-data, and the second sub-data is encrypted based on an encryption result of the first sub-data.

8. The memory management method according to claim 7, wherein the encryption is performed based on a ciphertext group concatenation method.

9. The memory management method according to claim 1, wherein the step of storing the third data in the first physical unit among the plurality of physical units comprises: encoding the third data with an error correction code to generate error-corrected data; storing the third data in a data area in a first physical subunit in the first physical unit; as well as The password information and the error correction data are stored in an idle area in the first physical subunit.

10. The memory management method according to claim 9, further comprising: Read the third data from the data area in the first entity subunit; Reading the error correction data and the password information from the idle area in the first physical subunit; as well as The third data is restored to the first data according to the error correction data and the password information.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: performing an erase operation on at least one of the plurality of physical units; In response to the erase operation, updating time information, wherein the time information reflects an average execution time of the erase operation on the plurality of physical units; Performing partial information extraction on the time information to obtain small digital information of the time information; Generate password information according to the small digital information; Slicing the first data to generate a plurality of second data, wherein the data length of each second data is shorter than the total data length of the first data; encrypting the plurality of second data according to the password information to generate third data, wherein the third data includes the encrypted data corresponding to the first data; as well as The third data is stored in a first physical unit among the plurality of physical units. 12 . The storage device according to claim 11 , wherein the decimal information includes at least a portion of data information after a decimal point in the time information.

13. The storage device according to claim 11, wherein a data format of the small digital information matches an encryption algorithm used to encrypt the first data.

14. The storage device according to claim 13, wherein if the encryption algorithm is a first encryption algorithm, the small digital information conforms to a first data format, and If the encryption algorithm is a second encryption algorithm, the small digital information conforms to a second data format, wherein the first encryption algorithm is different from the second encryption algorithm, and the first data format is different from the second data format.

15. The storage device according to claim 11, wherein the password information includes key information and initialization sequence information, and the operation of the memory controller generating the password information according to the small digital information includes: Performing a first data conversion on the small digital information to obtain the key information; as well as A second data conversion is performed on the small digital information to obtain the initialization sequence information, wherein a data format of the key information is different from a data format of the initialization sequence information.

16. The storage device according to claim 15, wherein the memory controller encrypts the plurality of second data according to the password information, comprising: The plurality of second data are encrypted according to the key information and the initialization sequence information. 17 . The storage device according to claim 15 , wherein the plurality of second data include first sub-data and second sub-data, and the second sub-data is encrypted based on an encryption result of the first sub-data.

18. The storage device according to claim 17, wherein the encryption is performed based on a ciphertext block concatenation method.

19. The storage device according to claim 11, wherein the operation of the memory controller storing the third data in the first physical unit among the plurality of physical units comprises: encoding the third data with an error correction code to generate error-corrected data; storing the third data in a data area in a first physical subunit in the first physical unit; as well as The password information and the error correction data are stored in an idle area in the first physical subunit.

20. The storage device according to claim 19, wherein the memory controller is further configured to: Read the third data from the data area in the first entity subunit; Reading the error correction data and the password information from the idle area in the first physical subunit; and The third data is restored to the first data according to the error correction data and the password information.

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