General multi-bias noise model parameter extraction method for microwave compound transistor

Abstract

The invention discloses a general multi-bias noise model parameter extraction method for a microwave compound transistor, and relates to the technical field of semiconductor device modeling, the transistor is tested, and static direct current IV, S parameters and noise parameter actual measurement data under different biases are obtained; establishing a large signal model, and performing nonlinear model parameter extraction in combination with multi-bias static direct current IV and S parameters to obtain nonlinear model parameters; carrying out noise characteristic modeling under different biases, and extracting noise model parameters under different biases in combination with actually measured data and nonlinear model parameters; fitting a noise model parameter through a piecewise function to obtain a bias correlation function of the noise model parameter; and establishing a multi-bias noise model according to the nonlinear model parameters of the device, the noise model parameters and the bias correlation function, and verifying by combining actual measurement data of static direct current IV, S parameters and noise parameters. According to the invention, multi-bias noise modeling can be carried out based on a general noise model parameter bias correlation function equation.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor device modeling, and more particularly to a method for extracting parameters of a universal multi-bias noise model of a microwave compound transistor. Background Art

[0002] The low noise amplifier is a core component of the RF front-end system, and its performance has a significant impact on the overall system performance. The microwave transistor noise equivalent circuit model is an important bridge between device preparation and circuit design, and is also the key to achieving high-precision low noise amplifier design. Common microwave transistor noise equivalent circuit models mainly include empirical / semi-empirical models such as the Pucel model, Pospieszalski model, and Van der Ziel model, as well as physical models. Among them, the Pucel model is widely used in microwave transistor noise modeling due to its simple model equations and easy integration into commercial SPICE simulation software. However, the traditional Pucel model is mainly based on the transistor small signal equivalent circuit model. Therefore, it is only applicable to a single transistor operating bias point and does not have the ability to characterize multi-bias noise characteristics.

[0003] At present, domestic and foreign scholars have carried out a series of research work on transistor multi-bias noise models and their parameter extraction. In 2008, Matthias Rudolph et al. from Brandenburg University of Technology in Germany proposed a noise modeling method based on the HBT large signal compact model. The author introduced two non-correlated noise current sources between the base-emitter and collector-emitter nodes in the HBT device model, and its noise power spectrum density equation was associated with the base current and collector current respectively through linear functions. At the same time, the noise source correlation of the model was associated with the bias through the time constant and the collector current, thereby realizing noise modeling under multi-bias. However, the extraction process of the time constant in the model is complicated, and the noise power spectrum density equation only realizes the bias correlation through a simple linear function, which cannot be applied to application scenarios with more complex bias correlation. On this basis, in 2013, Matthias Rudolph et al. proposed a multi-bias noise source equation for HEMT devices based on the Pucel model. The model constructs a hyperbolic tangent function to associate the drain channel noise fitting parameters and gate induced noise fitting parameters in the Pucel model with the bias-related charge source and current source, thereby achieving multi-bias noise characteristic characterization. However, the model does not consider the bias correlation of the noise correlation coefficient and cannot accurately characterize the changes in the correlation of the two noise sources under different biases. In 2014, Dasgupta et al. from the Indian Institute of Technology Kanpur realized bias-related noise modeling based on the surface potential modeling method. The gate and drain noise power spectrum density model was associated with the multi-bias gate charge, drain charge and drain-source current model, and the model accuracy was corrected by combining the empirical fitting function. However, due to the multi-bias characterization capability of the nonlinear model, the three empirical parameters in the model still have certain limitations in their ability to correct the bias correlation of the noise power spectrum density. In 2017, Chen Yongbo et al. proposed a multi-bias transistor noise modeling method, in which the drain noise power spectrum and the gate noise power spectrum are characterized by the bias-related surface potential equation combined with a polynomial empirical function. However, a large number of physical parameters in the model need to be obtained in combination with a specific transistor test structure, and parameter extraction is complex. In 2022, Felix Heinz and others from the Fraunhofer Institute for Applied Solid State Physics in Germany extended the Pospeiszalski model, introduced a shot noise source, and proposed a bias-dependent HEMT device noise model. Among them, the functional relationship between the gate noise model and the gate voltage and drain current is characterized by a three-variable Taylor polynomial; the bias-dependent equivalent noise temperature corresponding to the channel noise is obtained by fitting a two-variable Taylor polynomial. However, for devices with different processes / materials, the degree of bias correlation of their noise model parameters is different. Therefore, if this method is used, the number of terms in the Taylor polynomial needs to be re-determined, and the versatility is poor.

[0004] The above models all realize multi-bias noise modeling of transistors to a certain extent. However, due to the limitations of the functions used in the model equations, their multi-bias characterization accuracy is difficult to apply to different types of devices. As a result, when performing multi-bias noise modeling for devices of different processes, it is still necessary to reselect functions to adapt the bias correlation of model parameters, which brings great challenges to the extraction of multi-bias noise model parameters.

[0005] Therefore, how to perform multi-bias noise modeling based on a universal bias correlation function of noise model parameters and extract its model parameters is a problem that those skilled in the art need to solve urgently. Summary of the invention

[0006] In view of this, the present invention provides a method for extracting parameters of a universal multi-bias noise model of a microwave compound transistor, so as to solve the problems existing in the above-mentioned background technology.

[0007] In order to achieve the above object, the present invention adopts the following technical solution: A method for extracting parameters of a universal multi-bias noise model of a microwave compound transistor, comprising: Step 1, performing a multi-bias static DC IV test, an S parameter test, and a noise parameter test on the transistor to obtain measured data of the multi-bias static DC IV, S parameter, and noise parameter; Step 2, establishing a large signal model of the transistor, and extracting large signal model parameters of the large signal model in combination with the multi-bias static DC IV and S parameters in step 1 to obtain device current and capacitance model parameters; Step 3, modeling the noise characteristics of the device under different biases through the PUCEL model, combining the noise parameter measured data in step 1 with the large signal model parameters in step 2, and extracting the PUCEL noise model parameters of the device under different biases; Step 4, fitting the PUCEL noise model parameters described in step 3 by a two-dimensional canonical piecewise function to obtain a bias correlation function; Step 5: Establish a multi-bias noise model based on the large signal model parameters and the bias correlation function, and verify it in combination with multi-bias static DC IV, S parameters and noise parameter measured data.

[0008] Preferably, in step 1, the static DC IV test, the gate-source bias voltage range is V gs =-1.6~1V, the drain-source bias voltage range is V ds =0~6V; S parameter test, bias is the same as static DC IV test, S parameter frequency range is 10-30 GHz at each bias point; noise parameter test, frequency and bias conditions are the same as S parameter test; get each gate-source bias voltageV gs and drain-source bias voltage V ds Drain-source current under I ds Characteristic curves and different gate-source bias voltages V gs and drain-source bias voltage V ds The S parameters and noise parameters under the test include the minimum noise figure NF min , Noise resistance R n , optimal source reflection coefficient S opt Amplitude and phase.

[0009] Preferably, the large signal model of the transistor established in step 2 specifically includes a parasitic part equivalent circuit, an intrinsic part equivalent circuit and a noise source part equivalent circuit: In the parasitic part equivalent circuit, the parasitic inductance and the parasitic resistance are connected as follows: L g and R g Connected in series between the external gate input and the intrinsic gate port, L d and R d Connected in series between the external drain output terminal and the intrinsic part drain port, L s and R s Connected in series between the external source port and the intrinsic part source port; the parasitic capacitor connection method is as follows: C pgi Connect across the parasitic resistance R g and R s between, C pdi Connect across the parasitic resistance R d and R s between, C gdi Connect across the parasitic resistance R g and R d between; Pad Contact capacitance C pga Connected between the external gate and source, C pdaConnected between the external drain and source, C gda Connected between the external gate and drain; In the intrinsic part equivalent circuit, the intrinsic capacitor connection method is as follows: C gs Connect between the intrinsic gate and source terminals, C gd Connect between the intrinsic gate and drain terminals, C ds Connected between the intrinsic drain and source terminals; the remaining intrinsic components are connected as follows: channel resistance R i Connected between intrinsic source and drain terminals; gate-drain resistance R gd connected between the intrinsic gate and drain terminals; In the noise source equivalent circuit, the intrinsic gate induced noise current source Connected between the gate and source of the intrinsic part; intrinsic drain channel noise current source Connected between the drain and source of the intrinsic part; parasitic noise current source , , Parallel to the parasitic resistance R g , R d , R s .

[0010] Preferably, in step 2, large signal model parameters are extracted to obtain device current and capacitance model parameters, specifically as follows: ; ; ; in, is the internal intrinsic gate-source voltage, is the internal intrinsic drain-source voltage, is the maximum current model of the device under the applied gate bias voltage, β is the order of the electric field-electron velocity relationship, , and are the gate length and the length of the source access region and the drain access region, respectively. is the critical electric field model when the electron velocity is saturated, C gdp ，C gd0 ，C gsp，C gs0 and These are all fitting parameters of the nonlinear capacitance model.

[0011] Preferably, in step 3, the PUCEL noise model parameters of the device under different biases are extracted, and the noise model equation used is as follows: ; ; ; ; in, T is the Kelvin temperature, k is the Boltzmann constant, Represents the gate parasitic resistance R g , Drain parasitic resistance R d and source parasitic resistance R s The size of P is the drain channel noise fitting parameter, R is the gate induced noise fitting parameter, C is the correlation noise factor, is the noise bandwidth, is the transconductance, C gs is the gate-source capacitance, is the angular frequency, i g is the gate noise current, i d is the noise current of the drain, H Denotes conjugate transpose.

[0012] Preferably, extracting the noise model parameters under different biases in step 3 specifically includes: ; ; ; in, T is the Kelvin temperature, k is the Boltzmann constant, is the angular frequency, is the noise admittance matrix of the intrinsic part The first item, is the noise admittance matrix of the intrinsic part The second item, is the noise admittance matrix of the intrinsic part The fourth item; Repeat the above calculation process to obtain the P , R and C Noise model parameters.

[0013] Preferably, obtaining the bias correlation function in step 4 specifically includes: ; in, Drain-source voltage v ds The partition threshold, Drain-source current i ds The partition threshold, A 1 ~ I 1 is the fitting constant.

[0014] It can be seen from the above technical solution that, compared with the prior art, the present invention discloses a method for extracting parameters of a universal multi-bias noise model for microwave compound transistors, covering the complete process from basic transistor characteristic testing to complex multi-bias noise model establishment, forming a systematic parameter extraction and model establishment method, and comprehensively considering static DC IV characteristics, S parameters and noise parameters, providing a comprehensive data basis and parameter support for accurate noise modeling. The bias-related function has the advantages of reusability and easy parameter extraction, which helps to deeply understand and accurately describe the changes in noise characteristics of transistors under different bias conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0016] Figure 1 A diagram of the method steps provided by the present invention; Figure 2 The equivalent circuit topology diagram of the noise model provided by the present invention; FIG. 3( a ) is a diagram of the present invention. V gs =-0.3V when the noise parameters of the present invention and the traditional model NF min Comparison chart between simulation and measured results; FIG. 3( b ) is a diagram of the present invention. V gs=-0.3V when the noise parameters of the present invention and the traditional model R n Comparison chart between simulation and measured results; FIG. 3( c ) is a diagram of the present invention. V gs =-0.3V when the noise parameters of the present invention and the traditional model S opt Comparison chart between simulation and measured results; FIG. 4( a ) is a diagram of the present invention. V gs =-0.4V Noise parameters of the present invention and the traditional model NF min Comparison chart between simulation and measured results; FIG. 4( b ) is a diagram of the present invention. V gs =-0.4V Noise parameters of the present invention and the traditional model R n Comparison chart between simulation and measured results; FIG. 4( c ) is a diagram of the present invention. V gs =-0.4V Noise parameters of the present invention and the traditional model S opt Comparison chart of simulation and measured results. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] The embodiment of the present invention discloses a method for extracting parameters of a universal multi-bias noise model of a microwave compound transistor, such as Figure 1 As shown, including: Step 1, performing a multi-bias static DC IV test, an S parameter test, and a noise parameter test on the transistor to obtain measured data of the multi-bias static DC IV, S parameter, and noise parameter; Step 2, establish a large signal model of the transistor, and extract large signal model parameters of the large signal model by combining the multi-bias static DC IV and S parameters in step 1 to obtain device current and capacitance model parameters; Step 3, modeling the noise characteristics of the device under different biases through the PUCEL model, combining the noise parameter measured data in step 1 with the large signal model parameters in step 2, and extracting the PUCEL noise model parameters of the device under different biases; Step 4, fitting the PUCEL noise model parameters in step 3 by a two-dimensional canonical piecewise function to obtain a bias correlation function; Step 5: Establish a multi-bias noise model based on the large signal model parameters and the bias correlation function, and verify it by combining the multi-bias static DC IV, S parameters and noise parameter measured data.

[0019] In a specific embodiment, for a device whose parameters need to be extracted (a GaAspHEMT device with a size of 2×25 μm is used as an example in the present invention), a static DC IV test is performed, and the gate-source bias voltage range is V gs =-1.6~1V, the drain-source bias voltage range is V ds =0~6V; S parameter test, bias is the same as static DC IV test, S parameter frequency range is 10-30 GHz at each bias point; noise parameter test, frequency and bias conditions are the same as S parameter test; get each gate-source bias voltage V gs and drain-source bias voltage V ds Drain-source current under I ds Characteristic curves and different gate-source bias voltages V gs and drain-source bias voltage V ds The S parameters and noise parameters under the test include the minimum noise figure NF min , Noise resistance R n , optimal source reflection coefficient S opt Amplitude and phase.

[0020] In a specific embodiment, a large signal model of a transistor is first established. The large signal model consists of parasitic elements introduced by external electrodes and internal intrinsic elements. The parasitic elements include inter-electrode capacitance and air bridge capacitance ( C pgi and C pdi and C gdi ); Pad The contact capacitance ( C pga , C pda and C gda ); parasitic inductance and parasitic resistance ( L g , Ld , L s and R g , R d , R s ); gate-source capacitance, gate-drain capacitance and drain-source capacitance ( C gs , C gd and C ds ); R i is the channel resistance, R gd is the gate-drain resistance, G m is the transconductance, τ is the time delay. The connection relationship of each component is as follows Figure 2 As shown. The established transistor large signal model specifically includes the parasitic part equivalent circuit, the intrinsic part equivalent circuit and the noise source part equivalent circuit: In the parasitic part equivalent circuit, the parasitic inductance and parasitic resistance are connected as follows: L g and R g Connected in series between the external gate input and the intrinsic gate port, L d and R d Connected in series between the external drain output terminal and the intrinsic part drain port, L s and R s Connected in series between the external source port and the intrinsic part source port; the parasitic capacitor connection method is as follows: C pgi Connect across the parasitic resistance R g and R s between, C pdi Connect across the parasitic resistance R d and R s between, C gdi Connect across the parasitic resistance R g and R d between; Pad Contact capacitance C pgaConnected between the external gate input and the source terminal, C pda Connected between the external drain output terminal and the source terminal. C gda Connected between the external gate and drain; In the equivalent circuit of the intrinsic part, the intrinsic capacitor is connected as follows: C gs Connect between the intrinsic gate and source terminals, C gd Connect between the intrinsic gate and drain terminals, C ds Connected between the intrinsic drain and source terminals; the remaining intrinsic components are connected as follows: channel resistance R i Connected between intrinsic source and drain terminals; gate-drain resistance R gd connected between the intrinsic gate and drain terminals; In the equivalent circuit of the noise source part, the intrinsic gate induced noise current source Connected between the gate and source of the intrinsic part; intrinsic drain channel noise current source Connected between the drain and source of the intrinsic part; parasitic noise current source , , Parallel to the parasitic resistance R g , R d , R s .

[0021] In a specific embodiment, the S parameters and static DC measured in step 1 are IV The measured characteristic data are used to extract the nonlinear model parameters of the selected GaAs pHEMT transistor with a size of 2×25μm. The nonlinear current of the transistor in the present invention adopts the quasi-physical zone division (QPZD) model, and the nonlinear capacitance model adopts the Angelov model. The large signal model parameters are extracted in step 2 to obtain the device current and capacitance model parameters, as follows: ; ; ; in, is the internal intrinsic gate-source voltage, is the internal intrinsic drain-source voltage, is the maximum current model of the device under the applied gate bias voltage, β is the order of the electric field-electron velocity relationship, , and are the gate length and the length of the source access region and the drain access region, respectively. is the critical electric field model when the electron velocity is saturated, C gdp ，C gd0 ，C gsp ，C gs0 and These are all fitting parameters of the nonlinear capacitance model.

[0022] In a specific embodiment, the present invention uses the PUCEL model to achieve noise characteristic modeling of the device under different biases. In the model, the noise of the parasitic parameter part is mainly contributed by the parasitic resistance, and is represented by an equivalent noise voltage source connected in parallel with it. For the noise of the intrinsic part of the device, the gate induced noise is represented by an equivalent noise current source connected in parallel with the gate terminal. The drain channel noise is represented by the equivalent noise current source connected in parallel to the drain terminal. In addition, gate induced noise is generated by channel thermal noise coupled through gate capacitance, so the correlation between gate and drain noise also needs to be considered. The power spectral density corresponding to each noise source and the correlation between gate and drain noise sources are calculated using the following expressions: ; ; ; ; in, T is the Kelvin temperature, k is the Boltzmann constant, Represents the gate parasitic resistance R g , Drain parasitic resistance R d and source parasitic resistance R s The size of P is the drain channel noise fitting parameter, R is the gate induced noise fitting parameter, C is the correlation noise factor, is the noise bandwidth, is the transconductance, C gs is the gate-source capacitance, is the angular frequency, i g is the gate noise current, i dis the noise current of the drain. H Denotes conjugate transpose.

[0023] In a specific embodiment, according to the measured noise parameter data of the device under different biases in step 1, combined with the device nonlinear model parameters extracted in step 2, the influence of parasitic parameters on noise characteristics is first stripped away, and the stripping method is the prior art, and the obtained Figure 2 The noise characteristics of the intrinsic part of the noise admittance matrix are: Furthermore, the noise model parameters P , R and C It can be combined by the following expression Calculated. Extracting noise model parameters under different biases specifically includes: ; ; ; in, T is the Kelvin temperature, k is the Boltzmann constant, is the angular frequency, is the noise admittance matrix of the intrinsic part The first item, is the noise admittance matrix of the intrinsic part The second item, is the noise admittance matrix of the intrinsic part The fourth item; Repeat the above calculation process to obtain the P , R and C Noise model parameters.

[0024] In a specific embodiment, considering the lack of a unified and universal bias correlation function in traditional noise modeling, however, the polynomial or hyperbolic tangent function used in traditional multi-bias noise modeling has the problems of low universality, complex model parameters and difficulty in extraction. To this end, the present invention characterizes the bias correlation of noise parameters based on the canonical piecewise linear function (CSWPL). The canonical piecewise linear function (CSWPL) theory is a method of approximating complex nonlinear systems with piecewise linear functions. The core idea is to divide the nonlinear function into several sub-intervals within the definition domain, approximate each interval with a linear equation, and smoothly transition between segments according to certain rules, so as to have the ability to characterize complex nonlinear mapping relationships. The basic equation is shown below, where represents the linear part, b is the proportional factor of linear change, a is the constant term; the nonlinear part is obtained by summing Indicates that c k is the weight coefficient, β k For independent variables x Set the partition threshold to capture input x The nonlinear behavior of the independent variable x and the dependent variable y can be accurately established by the following formula. However, the traditional CSWPL model theory only supports the nonlinear function representation of a single independent variable. V ds , drain-source current I ds ) does not apply; ; The present invention fits the three noise model parameters P, R and C discrete values ​​corresponding to the different biases obtained in step 3 by means of a two-dimensional canonical piecewise function, and respectively fits the bias correlation functions of the three noise parameters. The two-dimensional canonical piecewise function expression used in the present invention is shown in the following formula: ; in, Drain-source voltage v ds The partition threshold, Drain-source current i ds The partition threshold, A 1 ~ I 1 is the fitting constant. and is the preset value. A 1 ~ I 1 are the parameters to be extracted; fitting parameters A 1 ~ I 1 The least square method can be combined with P, R and C as the dependent variables of the function, and each dependent variable is V ds 、I ds As the independent variable of the function, discrete data points are fitted. After substituting the extracted fitting parameters into the above formula, the bias-related P, R and C noise sub-models can be obtained, which are used to calculate the device noise characteristics under corresponding conditions.

[0025] In a specific embodiment, the accuracy of the noise model established based on the general multi-bias noise model parameter extraction method proposed by the present invention is verified. The present invention builds a commercial SPICE simulation software such as Figure 2 The noise model topology shown in the figure includes the inter-electrode capacitance and the air bridge capacitance ( C pgi and C pdi and C gdi ); Pad The contact capacitance ( C pga , C pda and C gda ); parasitic inductance and parasitic resistance ( L g , L d , L s and R g , R d , R s ); gate-source capacitance, gate-drain capacitance and drain-source capacitance ( C gs , C gd and C ds ); R i is the channel resistance, R gd is the gate-drain resistance, G m is the transconductance, τ is the time delay. The intrinsic gate induced noise current source and drain channel noise current source Two noise current sources are used to simulate the noise characteristics of transistors. The external RF excitation signal can be added to the topology in combination with commercial Spice simulation software, and then the port characteristics of each port in the topology can be simulated and calculated. After substituting the model parameter values ​​extracted in the above steps, the noise characteristics under different biases are measured and simulated for comparison and verification. Among them, the gate-source bias voltage range is V gs =-0.4~-0.3V (step: 0.1V), the drain-source bias voltage range is V ds=2~4V (step: 1 V), frequency range (Frequency) is 10~30GHz (step: 0.1GHz). In order to compare the noise model of the present invention with the traditional multi-bias noise model, Figure 3(a)-Figure 3(c) , Figure 4(a)-Figure 4(c) The results of the traditional multi-bias noise model are also included.

[0026] In order to evaluate the accuracy of the multi-bias noise model proposed in this invention, the accuracy of each noise parameter in four groups of bias conditions is calculated in the range of 10~30 GHz. The results are shown in Table 1, where bias A: V gs = -0.3 V, V ds =2 V; Bias B: V gs = -0.3 V, V ds =3 V; bias C: V gs =-0.4V, V ds =2 V and bias D: V gs = -0.4 V, V ds =3 V. Figure 3(a)-Figure 3(c) , Figure 4(a)-Figure 4(c) The results in Table 1 show that the established transistor multi-bias noise model can accurately simulate the transistor noise characteristics under different biases compared with the traditional model.

[0027] ; Table 1 Noise model accuracy It can be seen from the above table that the noise model established by the present invention has good accuracy under different bias conditions. Among them, under bias A, the simulation accuracy of the model for the four noise parameters is higher than 89.91%; under bias B, the simulation accuracy of the model for the four noise parameters is higher than 90.86%; under bias C, the simulation accuracy of the model for the four noise parameters is higher than 88.07%; under bias D, the simulation accuracy of the model for the four noise parameters is higher than 86.65%; compared with the traditional noise modeling and parameter extraction method, the noise model established based on the method of the present invention has a maximum accuracy improvement of 42.04%. The accuracy and effectiveness of the general multi-bias noise model parameter extraction method proposed in the present invention are verified.

[0028] In view of the lack of a unified and universal bias correlation equation for noise model parameters in traditional microwave compound transistor noise modeling, it is difficult to extract multi-bias noise model parameters and the model accuracy is difficult to meet the requirements of engineering applications. The present invention proposes a multi-bias noise modeling method based on the canonical piecewise linear function (CSWPL). Relying on CSWPL to use different linear expressions in different intervals to approximate nonlinear relationships, thereby achieving the advantages of complex nonlinear fitting, it can effectively solve the problem of poor model accuracy caused by the lack of versatility of traditional modeling methods based on a single polynomial or hyperbolic tangent function in complex bias correlation modeling applications. The verification case of the present invention shows that the accuracy of the multi-bias noise model is improved by up to 42.04%, which effectively improves the accuracy of the multi-bias noise model.

[0029] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0030] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for extracting parameters of a universal multi-bias noise model for microwave compound transistors, characterized in that: include: Step 1, performing a multi-bias static DC IV test, an S parameter test, and a noise parameter test on the transistor to obtain measured data of the multi-bias static DC IV, S parameter, and noise parameter; Step 2, establishing a large signal model of the transistor, and extracting large signal model parameters of the large signal model in combination with the multi-bias static DC IV and S parameters in step 1 to obtain device current and capacitance model parameters; Step 3, modeling the noise characteristics of the device under different biases through the PUCEL model, combining the noise parameter measured data in step 1 with the large signal model parameters in step 2, and extracting the PUCEL noise model parameters of the device under different biases; Step 4, fitting the PUCEL noise model parameters described in step 3 by a two-dimensional canonical piecewise function to obtain a bias correlation function; Step 5: Establish a multi-bias noise model based on the large signal model parameters and the bias correlation function, and verify it in combination with multi-bias static DC IV, S parameters and noise parameter measured data.

2. The method for extracting parameters of a universal multi-bias noise model for a microwave compound transistor according to claim 1, characterized in that: In step 1, the static DC IV test, the gate-source bias voltage range is V gs =-1.6~1V, the drain-source bias voltage range is V ds =0~6V; S parameter test, bias is the same as static DC IV test, S parameter frequency range at each bias point is 10-30 GHz; Noise parameter test, frequency and bias conditions are the same as S parameter test; get each gate-source bias voltage respectively V gs and drain-source bias voltage V ds Drain-source current under I ds Characteristic curves and different gate-source bias voltages V gs and drain-source bias voltage V ds The S parameters and noise parameters under the test include the minimum noise figure NF min , Noise resistance R n , optimal source reflection coefficient S opt The amplitude and phase of .

3. The method for extracting parameters of a universal multi-bias noise model for a microwave compound transistor according to claim 2, characterized in that: The large signal model of the transistor established in step 2 specifically includes a parasitic part equivalent circuit, an intrinsic part equivalent circuit and a noise source part equivalent circuit: In the parasitic part equivalent circuit, the parasitic inductance and the parasitic resistance are connected as follows: L g and R g Connected in series between the external gate input and the intrinsic gate port, L d and R d Connected in series between the external drain output terminal and the intrinsic part drain port, L s and R s Connected in series between the external source port and the intrinsic source port; parasitic The capacitor connections are as follows: C pgi Connect across the parasitic resistance R g and R s between, C pdi Connect across the parasitic resistance R d and R s between, C gdi Connect across the parasitic resistance R g and R d between; Pad Contact capacitance C pga Connected between the external gate and source, C pda Connected between the external drain and source, C gda Connected between the external gate and drain; In the intrinsic part equivalent circuit, the intrinsic capacitor connection method is as follows: C gs Connect between the intrinsic gate and source terminals, C gd Connect between the intrinsic gate and drain terminals, C ds Connected between the intrinsic drain and source terminals; the remaining intrinsic components are connected as follows: channel resistance R i Connected between intrinsic source and drain terminals; gate-drain resistance R gd connected between the intrinsic gate and drain terminals; In the noise source partial equivalent circuit, the intrinsic gate induced noise current source Connected between the gate and source of the intrinsic part; intrinsic drain channel noise current source Connected between the drain and source of the intrinsic part; parasitic noise current source , , Parallel to the parasitic resistance R g , R d , R s .

4. The method for extracting parameters of a universal multi-bias noise model for a microwave compound transistor according to claim 3, characterized in that: In step 2, large signal model parameters are extracted to obtain device current and capacitance model parameters, as follows: ； ； ； in, is the internal intrinsic gate-source voltage, is the internal intrinsic drain-source voltage, is the maximum current model of the device under the applied gate bias voltage, β is the order of the electric field-electron velocity relationship, , and are the gate length and the length of the source access region and the drain access region, respectively. is the critical electric field model when the electron velocity is saturated, C gdp ，C gd0 ，C gsp ，C gs0 and These are all fitting parameters of the nonlinear capacitance model.

5. The method for extracting parameters of a universal multi-bias noise model for a microwave compound transistor according to claim 4, characterized in that: In step 3, the PUCEL noise model parameters of the device under different biases are extracted, and the noise model equation used is as follows: ； ； ； ； in, T is the Kelvin temperature, k is the Boltzmann constant, Represents the gate parasitic resistance R g , Drain parasitic resistance R d and source parasitic resistance R s The size of P is the drain channel noise fitting parameter, R is the gate induced noise fitting parameter, C is the correlation noise factor, is the noise bandwidth, is the transconductance, C gs is the gate-source capacitance, is the angular frequency, i g is the gate noise current, i d is the noise current of the drain, H Denotes conjugate transpose.

6. The method for extracting parameters of a universal multi-bias noise model for a microwave compound transistor according to claim 5, characterized in that: Extracting the noise model parameters under different biases in step 3 specifically includes: ； ； ； in, T is the Kelvin temperature, k is the Boltzmann constant, is the angular frequency, is the noise admittance matrix of the intrinsic part The first item, is the noise admittance matrix of the intrinsic part The second item, is the noise admittance matrix of the intrinsic part The fourth item; Repeat the above calculation process to obtain the P , R and C Noise model parameters.

7. The method for extracting parameters of a universal multi-bias noise model for a microwave compound transistor according to claim 1, characterized in that: Obtaining the bias correlation function in step 4 specifically includes: ； in, Drain-source voltage v ds The partition threshold, Drain-source current i ds The partition threshold, A 1~ I 1 is the fitting constant.

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